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8#include <linux/bitfield.h>
9#include <linux/init.h>
10#include <linux/export.h>
11#include <linux/module.h>
12#include <linux/device.h>
13#include <linux/platform_device.h>
14#include <linux/ioport.h>
15#include <linux/io.h>
16#include <linux/dma-mapping.h>
17#include <linux/compiler.h>
18#include <linux/stddef.h>
19#include <linux/bitops.h>
20#include <linux/types.h>
21#include <linux/err.h>
22#include <linux/interrupt.h>
23#include <linux/acpi.h>
24#include <linux/pm.h>
25#include <linux/pm_runtime.h>
26#include <linux/delay.h>
27#include <linux/dmi.h>
28
29#include <linux/mmc/host.h>
30#include <linux/mmc/pm.h>
31#include <linux/mmc/slot-gpio.h>
32
33#ifdef CONFIG_X86
34#include <asm/cpu_device_id.h>
35#include <asm/intel-family.h>
36#include <asm/iosf_mbi.h>
37#include <linux/pci.h>
38#endif
39
40#include "sdhci.h"
41
42enum {
43 SDHCI_ACPI_SD_CD = BIT(0),
44 SDHCI_ACPI_RUNTIME_PM = BIT(1),
45 SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
46};
47
48struct sdhci_acpi_chip {
49 const struct sdhci_ops *ops;
50 unsigned int quirks;
51 unsigned int quirks2;
52 unsigned long caps;
53 unsigned int caps2;
54 mmc_pm_flag_t pm_caps;
55};
56
57struct sdhci_acpi_slot {
58 const struct sdhci_acpi_chip *chip;
59 unsigned int quirks;
60 unsigned int quirks2;
61 unsigned long caps;
62 unsigned int caps2;
63 mmc_pm_flag_t pm_caps;
64 unsigned int flags;
65 size_t priv_size;
66 int (*probe_slot)(struct platform_device *, struct acpi_device *);
67 int (*remove_slot)(struct platform_device *);
68 int (*free_slot)(struct platform_device *pdev);
69 int (*setup_host)(struct platform_device *pdev);
70};
71
72struct sdhci_acpi_host {
73 struct sdhci_host *host;
74 const struct sdhci_acpi_slot *slot;
75 struct platform_device *pdev;
76 bool use_runtime_pm;
77 bool is_intel;
78 bool reset_signal_volt_on_suspend;
79 unsigned long private[] ____cacheline_aligned;
80};
81
82enum {
83 DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP = BIT(0),
84 DMI_QUIRK_SD_NO_WRITE_PROTECT = BIT(1),
85};
86
87static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
88{
89 return (void *)c->private;
90}
91
92static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
93{
94 return c->slot && (c->slot->flags & flag);
95}
96
97#define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
98#define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
99#define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
100#define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
101
102enum {
103 INTEL_DSM_FNS = 0,
104 INTEL_DSM_V18_SWITCH = 3,
105 INTEL_DSM_V33_SWITCH = 4,
106 INTEL_DSM_HS_CAPS = 8,
107};
108
109struct intel_host {
110 u32 dsm_fns;
111 u32 hs_caps;
112};
113
114static const guid_t intel_dsm_guid =
115 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
116 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
117
118static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
119 unsigned int fn, u32 *result)
120{
121 union acpi_object *obj;
122 int err = 0;
123
124 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
125 if (!obj)
126 return -EOPNOTSUPP;
127
128 if (obj->type == ACPI_TYPE_INTEGER) {
129 *result = obj->integer.value;
130 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
131 size_t len = min_t(size_t, obj->buffer.length, 4);
132
133 *result = 0;
134 memcpy(result, obj->buffer.pointer, len);
135 } else {
136 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
137 __func__, fn, obj->type, obj->buffer.length);
138 err = -EINVAL;
139 }
140
141 ACPI_FREE(obj);
142
143 return err;
144}
145
146static int intel_dsm(struct intel_host *intel_host, struct device *dev,
147 unsigned int fn, u32 *result)
148{
149 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
150 return -EOPNOTSUPP;
151
152 return __intel_dsm(intel_host, dev, fn, result);
153}
154
155static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
156 struct mmc_host *mmc)
157{
158 int err;
159
160 intel_host->hs_caps = ~0;
161
162 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
163 if (err) {
164 pr_debug("%s: DSM not supported, error %d\n",
165 mmc_hostname(mmc), err);
166 return;
167 }
168
169 pr_debug("%s: DSM function mask %#x\n",
170 mmc_hostname(mmc), intel_host->dsm_fns);
171
172 intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
173}
174
175static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
176 struct mmc_ios *ios)
177{
178 struct device *dev = mmc_dev(mmc);
179 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
180 struct intel_host *intel_host = sdhci_acpi_priv(c);
181 unsigned int fn;
182 u32 result = 0;
183 int err;
184
185 err = sdhci_start_signal_voltage_switch(mmc, ios);
186 if (err)
187 return err;
188
189 switch (ios->signal_voltage) {
190 case MMC_SIGNAL_VOLTAGE_330:
191 fn = INTEL_DSM_V33_SWITCH;
192 break;
193 case MMC_SIGNAL_VOLTAGE_180:
194 fn = INTEL_DSM_V18_SWITCH;
195 break;
196 default:
197 return 0;
198 }
199
200 err = intel_dsm(intel_host, dev, fn, &result);
201 pr_debug("%s: %s DSM fn %u error %d result %u\n",
202 mmc_hostname(mmc), __func__, fn, err, result);
203
204 return 0;
205}
206
207static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
208{
209 u8 reg;
210
211 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
212 reg |= 0x10;
213 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
214
215 udelay(9);
216 reg &= ~0x10;
217 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
218
219 usleep_range(300, 1000);
220}
221
222static const struct sdhci_ops sdhci_acpi_ops_dflt = {
223 .set_clock = sdhci_set_clock,
224 .set_bus_width = sdhci_set_bus_width,
225 .reset = sdhci_reset,
226 .set_uhs_signaling = sdhci_set_uhs_signaling,
227};
228
229static const struct sdhci_ops sdhci_acpi_ops_int = {
230 .set_clock = sdhci_set_clock,
231 .set_bus_width = sdhci_set_bus_width,
232 .reset = sdhci_reset,
233 .set_uhs_signaling = sdhci_set_uhs_signaling,
234 .hw_reset = sdhci_acpi_int_hw_reset,
235};
236
237static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
238 .ops = &sdhci_acpi_ops_int,
239};
240
241#ifdef CONFIG_X86
242
243static bool sdhci_acpi_byt(void)
244{
245 static const struct x86_cpu_id byt[] = {
246 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, NULL),
247 {}
248 };
249
250 return x86_match_cpu(byt);
251}
252
253static bool sdhci_acpi_cht(void)
254{
255 static const struct x86_cpu_id cht[] = {
256 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, NULL),
257 {}
258 };
259
260 return x86_match_cpu(cht);
261}
262
263#define BYT_IOSF_SCCEP 0x63
264#define BYT_IOSF_OCP_NETCTRL0 0x1078
265#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
266
267static void sdhci_acpi_byt_setting(struct device *dev)
268{
269 u32 val = 0;
270
271 if (!sdhci_acpi_byt())
272 return;
273
274 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
275 &val)) {
276 dev_err(dev, "%s read error\n", __func__);
277 return;
278 }
279
280 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
281 return;
282
283 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
284
285 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
286 val)) {
287 dev_err(dev, "%s write error\n", __func__);
288 return;
289 }
290
291 dev_dbg(dev, "%s completed\n", __func__);
292}
293
294static bool sdhci_acpi_byt_defer(struct device *dev)
295{
296 if (!sdhci_acpi_byt())
297 return false;
298
299 if (!iosf_mbi_available())
300 return true;
301
302 sdhci_acpi_byt_setting(dev);
303
304 return false;
305}
306
307static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
308 unsigned int slot, unsigned int parent_slot)
309{
310 struct pci_dev *dev, *parent, *from = NULL;
311
312 while (1) {
313 dev = pci_get_device(vendor, device, from);
314 pci_dev_put(from);
315 if (!dev)
316 break;
317 parent = pci_upstream_bridge(dev);
318 if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
319 parent && PCI_SLOT(parent->devfn) == parent_slot &&
320 !pci_upstream_bridge(parent)) {
321 pci_dev_put(dev);
322 return true;
323 }
324 from = dev;
325 }
326
327 return false;
328}
329
330
331
332
333
334
335
336
337static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
338{
339 return sdhci_acpi_cht() &&
340 acpi_dev_hid_uid_match(adev, "80860F14", "2") &&
341 sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
342}
343
344#else
345
346static inline void sdhci_acpi_byt_setting(struct device *dev)
347{
348}
349
350static inline bool sdhci_acpi_byt_defer(struct device *dev)
351{
352 return false;
353}
354
355static inline bool sdhci_acpi_no_fixup_child_power(struct acpi_device *adev)
356{
357 return false;
358}
359
360#endif
361
362static int bxt_get_cd(struct mmc_host *mmc)
363{
364 int gpio_cd = mmc_gpio_get_cd(mmc);
365 struct sdhci_host *host = mmc_priv(mmc);
366 unsigned long flags;
367 int ret = 0;
368
369 if (!gpio_cd)
370 return 0;
371
372 spin_lock_irqsave(&host->lock, flags);
373
374 if (host->flags & SDHCI_DEVICE_DEAD)
375 goto out;
376
377 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
378out:
379 spin_unlock_irqrestore(&host->lock, flags);
380
381 return ret;
382}
383
384static int intel_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
385{
386 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
387 struct intel_host *intel_host = sdhci_acpi_priv(c);
388 struct sdhci_host *host = c->host;
389
390 if (acpi_dev_hid_uid_match(adev, "80860F14", "1") &&
391 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
392 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
393 host->timeout_clk = 1000;
394
395 if (acpi_dev_hid_uid_match(adev, "80865ACA", NULL))
396 host->mmc_host_ops.get_cd = bxt_get_cd;
397
398 intel_dsm_init(intel_host, &pdev->dev, host->mmc);
399
400 host->mmc_host_ops.start_signal_voltage_switch =
401 intel_start_signal_voltage_switch;
402
403 c->is_intel = true;
404
405 return 0;
406}
407
408static int intel_setup_host(struct platform_device *pdev)
409{
410 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
411 struct intel_host *intel_host = sdhci_acpi_priv(c);
412
413 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
414 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
415
416 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
417 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
418
419 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
420 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
421
422 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
423 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
424
425 return 0;
426}
427
428static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
429 .chip = &sdhci_acpi_chip_int,
430 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
431 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
432 MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
433 .flags = SDHCI_ACPI_RUNTIME_PM,
434 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
435 SDHCI_QUIRK_NO_LED,
436 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
437 SDHCI_QUIRK2_STOP_WITH_TC |
438 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
439 .probe_slot = intel_probe_slot,
440 .setup_host = intel_setup_host,
441 .priv_size = sizeof(struct intel_host),
442};
443
444static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
445 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
446 SDHCI_QUIRK_NO_LED |
447 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
448 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
449 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
450 MMC_CAP_WAIT_WHILE_BUSY,
451 .flags = SDHCI_ACPI_RUNTIME_PM,
452 .pm_caps = MMC_PM_KEEP_POWER,
453 .probe_slot = intel_probe_slot,
454 .setup_host = intel_setup_host,
455 .priv_size = sizeof(struct intel_host),
456};
457
458static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
459 .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
460 SDHCI_ACPI_RUNTIME_PM,
461 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
462 SDHCI_QUIRK_NO_LED,
463 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
464 SDHCI_QUIRK2_STOP_WITH_TC,
465 .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
466 .probe_slot = intel_probe_slot,
467 .setup_host = intel_setup_host,
468 .priv_size = sizeof(struct intel_host),
469};
470
471#define VENDOR_SPECIFIC_PWRCTL_CLEAR_REG 0x1a8
472#define VENDOR_SPECIFIC_PWRCTL_CTL_REG 0x1ac
473static irqreturn_t sdhci_acpi_qcom_handler(int irq, void *ptr)
474{
475 struct sdhci_host *host = ptr;
476
477 sdhci_writel(host, 0x3, VENDOR_SPECIFIC_PWRCTL_CLEAR_REG);
478 sdhci_writel(host, 0x1, VENDOR_SPECIFIC_PWRCTL_CTL_REG);
479
480 return IRQ_HANDLED;
481}
482
483static int qcom_probe_slot(struct platform_device *pdev, struct acpi_device *adev)
484{
485 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
486 struct sdhci_host *host = c->host;
487 int *irq = sdhci_acpi_priv(c);
488
489 *irq = -EINVAL;
490
491 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
492 return 0;
493
494 *irq = platform_get_irq(pdev, 1);
495 if (*irq < 0)
496 return 0;
497
498 return request_threaded_irq(*irq, NULL, sdhci_acpi_qcom_handler,
499 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
500 "sdhci_qcom", host);
501}
502
503static int qcom_free_slot(struct platform_device *pdev)
504{
505 struct device *dev = &pdev->dev;
506 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
507 struct sdhci_host *host = c->host;
508 struct acpi_device *adev;
509 int *irq = sdhci_acpi_priv(c);
510
511 adev = ACPI_COMPANION(dev);
512 if (!adev)
513 return -ENODEV;
514
515 if (!acpi_dev_hid_uid_match(adev, "QCOM8051", NULL))
516 return 0;
517
518 if (*irq < 0)
519 return 0;
520
521 free_irq(*irq, host);
522 return 0;
523}
524
525static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
526 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
527 .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
528 .caps = MMC_CAP_NONREMOVABLE,
529 .priv_size = sizeof(int),
530 .probe_slot = qcom_probe_slot,
531 .free_slot = qcom_free_slot,
532};
533
534static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
535 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
536 .caps = MMC_CAP_NONREMOVABLE,
537};
538
539struct amd_sdhci_host {
540 bool tuned_clock;
541 bool dll_enabled;
542};
543
544
545#define SDHCI_AMD_RESET_DLL_REGISTER 0x908
546
547static int amd_select_drive_strength(struct mmc_card *card,
548 unsigned int max_dtr, int host_drv,
549 int card_drv, int *host_driver_strength)
550{
551 struct sdhci_host *host = mmc_priv(card->host);
552 u16 preset, preset_driver_strength;
553
554
555
556
557
558
559
560
561 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
562 preset_driver_strength = FIELD_GET(SDHCI_PRESET_DRV_MASK, preset);
563
564
565
566
567
568
569
570
571
572
573
574
575
576 *host_driver_strength = preset_driver_strength;
577
578
579
580
581
582
583 return preset_driver_strength;
584}
585
586static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host, bool enable)
587{
588 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
589 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
590
591
592 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
593 usleep_range(10, 20);
594 if (enable)
595 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
596
597 amd_host->dll_enabled = enable;
598}
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
614{
615 struct sdhci_host *host = mmc_priv(mmc);
616 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
617 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
618 unsigned int old_timing = host->timing;
619 u16 val;
620
621 sdhci_set_ios(mmc, ios);
622
623 if (old_timing != host->timing && amd_host->tuned_clock) {
624 if (host->timing == MMC_TIMING_MMC_HS400 ||
625 host->timing == MMC_TIMING_MMC_HS200) {
626 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
627 val |= SDHCI_CTRL_TUNED_CLK;
628 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
629 } else {
630 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
631 val &= ~SDHCI_CTRL_TUNED_CLK;
632 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
633 }
634
635
636 if (host->timing == MMC_TIMING_MMC_HS400 &&
637 !amd_host->dll_enabled)
638 sdhci_acpi_amd_hs400_dll(host, true);
639 }
640}
641
642static int amd_sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
643{
644 int err;
645 struct sdhci_host *host = mmc_priv(mmc);
646 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
647 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
648
649 amd_host->tuned_clock = false;
650
651 err = sdhci_execute_tuning(mmc, opcode);
652
653 if (!err && !host->tuning_err)
654 amd_host->tuned_clock = true;
655
656 return err;
657}
658
659static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
660{
661 struct sdhci_acpi_host *acpi_host = sdhci_priv(host);
662 struct amd_sdhci_host *amd_host = sdhci_acpi_priv(acpi_host);
663
664 if (mask & SDHCI_RESET_ALL) {
665 amd_host->tuned_clock = false;
666 sdhci_acpi_amd_hs400_dll(host, false);
667 }
668
669 sdhci_reset(host, mask);
670}
671
672static const struct sdhci_ops sdhci_acpi_ops_amd = {
673 .set_clock = sdhci_set_clock,
674 .set_bus_width = sdhci_set_bus_width,
675 .reset = amd_sdhci_reset,
676 .set_uhs_signaling = sdhci_set_uhs_signaling,
677};
678
679static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
680 .ops = &sdhci_acpi_ops_amd,
681};
682
683static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
684 struct acpi_device *adev)
685{
686 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
687 struct sdhci_host *host = c->host;
688
689 sdhci_read_caps(host);
690 if (host->caps1 & SDHCI_SUPPORT_DDR50)
691 host->mmc->caps = MMC_CAP_1_8V_DDR;
692
693 if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
694 (host->mmc->caps & MMC_CAP_1_8V_DDR))
695 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
733
734 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
735 host->mmc_host_ops.set_ios = amd_set_ios;
736 host->mmc_host_ops.execute_tuning = amd_sdhci_execute_tuning;
737 return 0;
738}
739
740static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
741 .chip = &sdhci_acpi_chip_amd,
742 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
743 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
744 SDHCI_QUIRK_32BIT_DMA_SIZE |
745 SDHCI_QUIRK_32BIT_ADMA_SIZE,
746 .quirks2 = SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
747 .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
748 .priv_size = sizeof(struct amd_sdhci_host),
749};
750
751struct sdhci_acpi_uid_slot {
752 const char *hid;
753 const char *uid;
754 const struct sdhci_acpi_slot *slot;
755};
756
757static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
758 { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
759 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
760 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
761 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
762 { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
763 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
764 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
765 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
766 { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
767 { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
768 { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
769 { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
770 { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
771 { "PNP0D40" },
772 { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
773 { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
774 { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
775 { "AMDI0041", NULL, &sdhci_acpi_slot_amd_emmc },
776 { },
777};
778
779static const struct acpi_device_id sdhci_acpi_ids[] = {
780 { "80865ACA" },
781 { "80865ACC" },
782 { "80865AD0" },
783 { "80860F14" },
784 { "80860F16" },
785 { "INT33BB" },
786 { "INT33C6" },
787 { "INT3436" },
788 { "INT344D" },
789 { "PNP0D40" },
790 { "QCOM8051" },
791 { "QCOM8052" },
792 { "AMDI0040" },
793 { "AMDI0041" },
794 { },
795};
796MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
797
798static const struct dmi_system_id sdhci_acpi_quirks[] = {
799 {
800
801
802
803
804
805
806
807 .matches = {
808 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
809 DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
810 },
811 .driver_data = (void *)DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP,
812 },
813 {
814
815
816
817
818
819 .matches = {
820 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
821 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire SW5-012"),
822 },
823 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
824 },
825 {
826
827
828
829
830 .matches = {
831 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
832 DMI_MATCH(DMI_PRODUCT_NAME, "TOSHIBA ENCORE 2 WT8-B"),
833 },
834 .driver_data = (void *)DMI_QUIRK_SD_NO_WRITE_PROTECT,
835 },
836 {}
837};
838
839static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(struct acpi_device *adev)
840{
841 const struct sdhci_acpi_uid_slot *u;
842
843 for (u = sdhci_acpi_uids; u->hid; u++) {
844 if (acpi_dev_hid_uid_match(adev, u->hid, u->uid))
845 return u->slot;
846 }
847 return NULL;
848}
849
850static int sdhci_acpi_probe(struct platform_device *pdev)
851{
852 struct device *dev = &pdev->dev;
853 const struct sdhci_acpi_slot *slot;
854 struct acpi_device *device, *child;
855 const struct dmi_system_id *id;
856 struct sdhci_acpi_host *c;
857 struct sdhci_host *host;
858 struct resource *iomem;
859 resource_size_t len;
860 size_t priv_size;
861 int quirks = 0;
862 int err;
863
864 device = ACPI_COMPANION(dev);
865 if (!device)
866 return -ENODEV;
867
868 id = dmi_first_match(sdhci_acpi_quirks);
869 if (id)
870 quirks = (long)id->driver_data;
871
872 slot = sdhci_acpi_get_slot(device);
873
874
875 acpi_device_fix_up_power(device);
876 if (!sdhci_acpi_no_fixup_child_power(device)) {
877 list_for_each_entry(child, &device->children, node)
878 if (child->status.present && child->status.enabled)
879 acpi_device_fix_up_power(child);
880 }
881
882 if (sdhci_acpi_byt_defer(dev))
883 return -EPROBE_DEFER;
884
885 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
886 if (!iomem)
887 return -ENOMEM;
888
889 len = resource_size(iomem);
890 if (len < 0x100)
891 dev_err(dev, "Invalid iomem size!\n");
892
893 if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
894 return -ENOMEM;
895
896 priv_size = slot ? slot->priv_size : 0;
897 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
898 if (IS_ERR(host))
899 return PTR_ERR(host);
900
901 c = sdhci_priv(host);
902 c->host = host;
903 c->slot = slot;
904 c->pdev = pdev;
905 c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
906
907 platform_set_drvdata(pdev, c);
908
909 host->hw_name = "ACPI";
910 host->ops = &sdhci_acpi_ops_dflt;
911 host->irq = platform_get_irq(pdev, 0);
912 if (host->irq < 0) {
913 err = -EINVAL;
914 goto err_free;
915 }
916
917 host->ioaddr = devm_ioremap(dev, iomem->start,
918 resource_size(iomem));
919 if (host->ioaddr == NULL) {
920 err = -ENOMEM;
921 goto err_free;
922 }
923
924 if (c->slot) {
925 if (c->slot->probe_slot) {
926 err = c->slot->probe_slot(pdev, device);
927 if (err)
928 goto err_free;
929 }
930 if (c->slot->chip) {
931 host->ops = c->slot->chip->ops;
932 host->quirks |= c->slot->chip->quirks;
933 host->quirks2 |= c->slot->chip->quirks2;
934 host->mmc->caps |= c->slot->chip->caps;
935 host->mmc->caps2 |= c->slot->chip->caps2;
936 host->mmc->pm_caps |= c->slot->chip->pm_caps;
937 }
938 host->quirks |= c->slot->quirks;
939 host->quirks2 |= c->slot->quirks2;
940 host->mmc->caps |= c->slot->caps;
941 host->mmc->caps2 |= c->slot->caps2;
942 host->mmc->pm_caps |= c->slot->pm_caps;
943 }
944
945 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
946
947 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
948 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
949
950 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0);
951 if (err) {
952 if (err == -EPROBE_DEFER)
953 goto err_free;
954 dev_warn(dev, "failed to setup card detect gpio\n");
955 c->use_runtime_pm = false;
956 }
957
958 if (quirks & DMI_QUIRK_RESET_SD_SIGNAL_VOLT_ON_SUSP)
959 c->reset_signal_volt_on_suspend = true;
960
961 if (quirks & DMI_QUIRK_SD_NO_WRITE_PROTECT)
962 host->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
963 }
964
965 err = sdhci_setup_host(host);
966 if (err)
967 goto err_free;
968
969 if (c->slot && c->slot->setup_host) {
970 err = c->slot->setup_host(pdev);
971 if (err)
972 goto err_cleanup;
973 }
974
975 err = __sdhci_add_host(host);
976 if (err)
977 goto err_cleanup;
978
979 if (c->use_runtime_pm) {
980 pm_runtime_set_active(dev);
981 pm_suspend_ignore_children(dev, 1);
982 pm_runtime_set_autosuspend_delay(dev, 50);
983 pm_runtime_use_autosuspend(dev);
984 pm_runtime_enable(dev);
985 }
986
987 device_enable_async_suspend(dev);
988
989 return 0;
990
991err_cleanup:
992 sdhci_cleanup_host(c->host);
993err_free:
994 if (c->slot && c->slot->free_slot)
995 c->slot->free_slot(pdev);
996
997 sdhci_free_host(c->host);
998 return err;
999}
1000
1001static int sdhci_acpi_remove(struct platform_device *pdev)
1002{
1003 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
1004 struct device *dev = &pdev->dev;
1005 int dead;
1006
1007 if (c->use_runtime_pm) {
1008 pm_runtime_get_sync(dev);
1009 pm_runtime_disable(dev);
1010 pm_runtime_put_noidle(dev);
1011 }
1012
1013 if (c->slot && c->slot->remove_slot)
1014 c->slot->remove_slot(pdev);
1015
1016 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
1017 sdhci_remove_host(c->host, dead);
1018
1019 if (c->slot && c->slot->free_slot)
1020 c->slot->free_slot(pdev);
1021
1022 sdhci_free_host(c->host);
1023
1024 return 0;
1025}
1026
1027static void __maybe_unused sdhci_acpi_reset_signal_voltage_if_needed(
1028 struct device *dev)
1029{
1030 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1031 struct sdhci_host *host = c->host;
1032
1033 if (c->is_intel && c->reset_signal_volt_on_suspend &&
1034 host->mmc->ios.signal_voltage != MMC_SIGNAL_VOLTAGE_330) {
1035 struct intel_host *intel_host = sdhci_acpi_priv(c);
1036 unsigned int fn = INTEL_DSM_V33_SWITCH;
1037 u32 result = 0;
1038
1039 intel_dsm(intel_host, dev, fn, &result);
1040 }
1041}
1042
1043#ifdef CONFIG_PM_SLEEP
1044
1045static int sdhci_acpi_suspend(struct device *dev)
1046{
1047 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1048 struct sdhci_host *host = c->host;
1049 int ret;
1050
1051 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1052 mmc_retune_needed(host->mmc);
1053
1054 ret = sdhci_suspend_host(host);
1055 if (ret)
1056 return ret;
1057
1058 sdhci_acpi_reset_signal_voltage_if_needed(dev);
1059 return 0;
1060}
1061
1062static int sdhci_acpi_resume(struct device *dev)
1063{
1064 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1065
1066 sdhci_acpi_byt_setting(&c->pdev->dev);
1067
1068 return sdhci_resume_host(c->host);
1069}
1070
1071#endif
1072
1073#ifdef CONFIG_PM
1074
1075static int sdhci_acpi_runtime_suspend(struct device *dev)
1076{
1077 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1078 struct sdhci_host *host = c->host;
1079 int ret;
1080
1081 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1082 mmc_retune_needed(host->mmc);
1083
1084 ret = sdhci_runtime_suspend_host(host);
1085 if (ret)
1086 return ret;
1087
1088 sdhci_acpi_reset_signal_voltage_if_needed(dev);
1089 return 0;
1090}
1091
1092static int sdhci_acpi_runtime_resume(struct device *dev)
1093{
1094 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
1095
1096 sdhci_acpi_byt_setting(&c->pdev->dev);
1097
1098 return sdhci_runtime_resume_host(c->host, 0);
1099}
1100
1101#endif
1102
1103static const struct dev_pm_ops sdhci_acpi_pm_ops = {
1104 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
1105 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
1106 sdhci_acpi_runtime_resume, NULL)
1107};
1108
1109static struct platform_driver sdhci_acpi_driver = {
1110 .driver = {
1111 .name = "sdhci-acpi",
1112 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1113 .acpi_match_table = sdhci_acpi_ids,
1114 .pm = &sdhci_acpi_pm_ops,
1115 },
1116 .probe = sdhci_acpi_probe,
1117 .remove = sdhci_acpi_remove,
1118};
1119
1120module_platform_driver(sdhci_acpi_driver);
1121
1122MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
1123MODULE_AUTHOR("Adrian Hunter");
1124MODULE_LICENSE("GPL v2");
1125