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11#include <linux/bitfield.h>
12#include <linux/io.h>
13#include <linux/iopoll.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/module.h>
18#include <linux/slab.h>
19#include <linux/pm_qos.h>
20#include <linux/mmc/host.h>
21#include <linux/mmc/mmc.h>
22#include <linux/mmc/sdio.h>
23#include <linux/mmc/slot-gpio.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/pinctrl/consumer.h>
27#include <linux/pm_runtime.h>
28#include "sdhci-pltfm.h"
29#include "sdhci-esdhc.h"
30#include "cqhci.h"
31
32#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
33#define ESDHC_CTRL_D3CD 0x08
34#define ESDHC_BURST_LEN_EN_INCR (1 << 27)
35
36#define ESDHC_VENDOR_SPEC 0xc0
37#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
38#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
39#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
40#define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2
41#define ESDHC_DEBUG_SEL_REG 0xc3
42#define ESDHC_DEBUG_SEL_MASK 0xf
43#define ESDHC_DEBUG_SEL_CMD_STATE 1
44#define ESDHC_DEBUG_SEL_DATA_STATE 2
45#define ESDHC_DEBUG_SEL_TRANS_STATE 3
46#define ESDHC_DEBUG_SEL_DMA_STATE 4
47#define ESDHC_DEBUG_SEL_ADMA_STATE 5
48#define ESDHC_DEBUG_SEL_FIFO_STATE 6
49#define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7
50#define ESDHC_WTMK_LVL 0x44
51#define ESDHC_WTMK_DEFAULT_VAL 0x10401040
52#define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF
53#define ESDHC_WTMK_LVL_RD_WML_SHIFT 0
54#define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000
55#define ESDHC_WTMK_LVL_WR_WML_SHIFT 16
56#define ESDHC_WTMK_LVL_WML_VAL_DEF 64
57#define ESDHC_WTMK_LVL_WML_VAL_MAX 128
58#define ESDHC_MIX_CTRL 0x48
59#define ESDHC_MIX_CTRL_DDREN (1 << 3)
60#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
61#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
62#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
63#define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
64#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
65#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
66#define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27)
67
68#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
69
70#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
71
72
73#define ESDHC_DLL_CTRL 0x60
74#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
75#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
76
77
78#define ESDHC_TUNE_CTRL_STATUS 0x68
79#define ESDHC_TUNE_CTRL_STEP 1
80#define ESDHC_TUNE_CTRL_MIN 0
81#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
82
83
84#define ESDHC_STROBE_DLL_CTRL 0x70
85#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
86#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
87#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
88#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
89#define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20)
90
91#define ESDHC_STROBE_DLL_STATUS 0x74
92#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
93#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
94
95#define ESDHC_VEND_SPEC2 0xc8
96#define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8)
97#define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4)
98#define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4)
99#define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4)
100#define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6)
101#define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4)
102
103#define ESDHC_TUNING_CTRL 0xcc
104#define ESDHC_STD_TUNING_EN (1 << 24)
105
106#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
107#define ESDHC_TUNING_START_TAP_MASK 0x7f
108#define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7)
109#define ESDHC_TUNING_STEP_MASK 0x00070000
110#define ESDHC_TUNING_STEP_SHIFT 16
111
112
113#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
114#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
115
116
117
118
119#define ESDHC_CTRL_4BITBUS (0x1 << 1)
120#define ESDHC_CTRL_8BITBUS (0x2 << 1)
121#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
122#define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK)
123
124
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126
127
128
129
130#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
131
132
133#define ESDHC_CQHCI_ADDR_OFFSET 0x100
134
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143
144
145
146#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
147
148
149
150
151#define ESDHC_FLAG_USDHC BIT(3)
152
153#define ESDHC_FLAG_MAN_TUNING BIT(4)
154
155#define ESDHC_FLAG_STD_TUNING BIT(5)
156
157#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
158
159
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163
164
165#define ESDHC_FLAG_ERR004536 BIT(7)
166
167#define ESDHC_FLAG_HS200 BIT(8)
168
169#define ESDHC_FLAG_HS400 BIT(9)
170
171
172
173
174
175#define ESDHC_FLAG_ERR010450 BIT(10)
176
177#define ESDHC_FLAG_HS400_ES BIT(11)
178
179#define ESDHC_FLAG_CQHCI BIT(12)
180
181#define ESDHC_FLAG_PMQOS BIT(13)
182
183#define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14)
184
185#define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15)
186
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195
196
197#define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
198
199enum wp_types {
200 ESDHC_WP_NONE,
201 ESDHC_WP_CONTROLLER,
202 ESDHC_WP_GPIO,
203};
204
205enum cd_types {
206 ESDHC_CD_NONE,
207 ESDHC_CD_CONTROLLER,
208 ESDHC_CD_GPIO,
209 ESDHC_CD_PERMANENT,
210};
211
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219
220
221struct esdhc_platform_data {
222 enum wp_types wp_type;
223 enum cd_types cd_type;
224 int max_bus_width;
225 unsigned int delay_line;
226 unsigned int tuning_step;
227 unsigned int tuning_start_tap;
228 unsigned int strobe_dll_delay_target;
229};
230
231struct esdhc_soc_data {
232 u32 flags;
233};
234
235static const struct esdhc_soc_data esdhc_imx25_data = {
236 .flags = ESDHC_FLAG_ERR004536,
237};
238
239static const struct esdhc_soc_data esdhc_imx35_data = {
240 .flags = ESDHC_FLAG_ERR004536,
241};
242
243static const struct esdhc_soc_data esdhc_imx51_data = {
244 .flags = 0,
245};
246
247static const struct esdhc_soc_data esdhc_imx53_data = {
248 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
249};
250
251static const struct esdhc_soc_data usdhc_imx6q_data = {
252 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING
253 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
254};
255
256static const struct esdhc_soc_data usdhc_imx6sl_data = {
257 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
258 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
259 | ESDHC_FLAG_HS200
260 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
261};
262
263static const struct esdhc_soc_data usdhc_imx6sll_data = {
264 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
265 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
266 | ESDHC_FLAG_HS400
267 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
268};
269
270static const struct esdhc_soc_data usdhc_imx6sx_data = {
271 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
272 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
273 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
274 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
275};
276
277static const struct esdhc_soc_data usdhc_imx6ull_data = {
278 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
279 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
280 | ESDHC_FLAG_ERR010450
281 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
282};
283
284static const struct esdhc_soc_data usdhc_imx7d_data = {
285 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
286 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
287 | ESDHC_FLAG_HS400
288 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
289 | ESDHC_FLAG_BROKEN_AUTO_CMD23,
290};
291
292static struct esdhc_soc_data usdhc_imx7ulp_data = {
293 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
294 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
295 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400
296 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
297};
298
299static struct esdhc_soc_data usdhc_imx8qxp_data = {
300 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
301 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
302 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
303 | ESDHC_FLAG_CQHCI
304 | ESDHC_FLAG_STATE_LOST_IN_LPMODE
305 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME,
306};
307
308static struct esdhc_soc_data usdhc_imx8mm_data = {
309 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
310 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
311 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES
312 | ESDHC_FLAG_CQHCI
313 | ESDHC_FLAG_STATE_LOST_IN_LPMODE,
314};
315
316struct pltfm_imx_data {
317 u32 scratchpad;
318 struct pinctrl *pinctrl;
319 struct pinctrl_state *pins_100mhz;
320 struct pinctrl_state *pins_200mhz;
321 const struct esdhc_soc_data *socdata;
322 struct esdhc_platform_data boarddata;
323 struct clk *clk_ipg;
324 struct clk *clk_ahb;
325 struct clk *clk_per;
326 unsigned int actual_clock;
327 enum {
328 NO_CMD_PENDING,
329 MULTIBLK_IN_PROCESS,
330 WAIT_FOR_INT,
331 } multiblock_status;
332 u32 is_ddr;
333 struct pm_qos_request pm_qos_req;
334};
335
336static const struct of_device_id imx_esdhc_dt_ids[] = {
337 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
338 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
339 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
340 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
341 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
342 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
343 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, },
344 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
345 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, },
346 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
347 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, },
348 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, },
349 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, },
350 { }
351};
352MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
353
354static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
355{
356 return data->socdata == &esdhc_imx25_data;
357}
358
359static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
360{
361 return data->socdata == &esdhc_imx53_data;
362}
363
364static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
365{
366 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
367}
368
369static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
370{
371 void __iomem *base = host->ioaddr + (reg & ~0x3);
372 u32 shift = (reg & 0x3) * 8;
373
374 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
375}
376
377#define DRIVER_NAME "sdhci-esdhc-imx"
378#define ESDHC_IMX_DUMP(f, x...) \
379 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
380static void esdhc_dump_debug_regs(struct sdhci_host *host)
381{
382 int i;
383 char *debug_status[7] = {
384 "cmd debug status",
385 "data debug status",
386 "trans debug status",
387 "dma debug status",
388 "adma debug status",
389 "fifo debug status",
390 "async fifo debug status"
391 };
392
393 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");
394 for (i = 0; i < 7; i++) {
395 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK,
396 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG);
397 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i],
398 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG));
399 }
400
401 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG);
402
403}
404
405static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
406{
407 u32 present_state;
408 int ret;
409
410 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
411 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100);
412 if (ret == -ETIMEDOUT)
413 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
414}
415
416
417static inline void usdhc_auto_tuning_mode_sel(struct sdhci_host *host)
418{
419 u32 buswidth, auto_tune_buswidth;
420
421 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL));
422
423 switch (buswidth) {
424 case ESDHC_CTRL_8BITBUS:
425 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN;
426 break;
427 case ESDHC_CTRL_4BITBUS:
428 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN;
429 break;
430 default:
431 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
432 break;
433 }
434
435 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
436 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
437 ESDHC_VEND_SPEC2);
438}
439
440static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
441{
442 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
443 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
444 u32 val = readl(host->ioaddr + reg);
445
446 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
447 u32 fsl_prss = val;
448
449 val = fsl_prss & 0x000FFFFF;
450
451 val |= (fsl_prss & 0x0F000000) >> 4;
452
453 val |= (fsl_prss & 0x00800000) << 1;
454 }
455
456 if (unlikely(reg == SDHCI_CAPABILITIES)) {
457
458 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
459 val &= 0xffff0000;
460
461
462
463
464
465
466
467
468 if (val & SDHCI_CAN_DO_ADMA1) {
469 val &= ~SDHCI_CAN_DO_ADMA1;
470 val |= SDHCI_CAN_DO_ADMA2;
471 }
472 }
473
474 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
475 if (esdhc_is_usdhc(imx_data)) {
476 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
477 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
478 else
479
480 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
481 | SDHCI_SUPPORT_SDR50
482 | SDHCI_USE_SDR50_TUNING
483 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
484 SDHCI_TUNING_MODE_3);
485
486
487
488
489
490 if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
491 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
492 if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
493 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
494 }
495 }
496
497 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
498 val = 0;
499 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
500 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
501 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
502 }
503
504 if (unlikely(reg == SDHCI_INT_STATUS)) {
505 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
506 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
507 val |= SDHCI_INT_ADMA_ERROR;
508 }
509
510
511
512
513
514 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
515 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
516 val &= ~SDHCI_INT_RESPONSE;
517 writel(SDHCI_INT_RESPONSE, host->ioaddr +
518 SDHCI_INT_STATUS);
519 imx_data->multiblock_status = NO_CMD_PENDING;
520 }
521 }
522
523 return val;
524}
525
526static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
527{
528 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
529 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
530 u32 data;
531
532 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
533 reg == SDHCI_INT_STATUS)) {
534 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
535
536
537
538
539
540
541
542
543 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
544 data &= ~ESDHC_CTRL_D3CD;
545 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
546 data |= ESDHC_CTRL_D3CD;
547 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
548 }
549
550 if (val & SDHCI_INT_ADMA_ERROR) {
551 val &= ~SDHCI_INT_ADMA_ERROR;
552 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
553 }
554 }
555
556 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
557 && (reg == SDHCI_INT_STATUS)
558 && (val & SDHCI_INT_DATA_END))) {
559 u32 v;
560 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
561 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
562 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
563
564 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
565 {
566
567 data = MMC_STOP_TRANSMISSION << 24 |
568 SDHCI_CMD_ABORTCMD << 16;
569 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
570 imx_data->multiblock_status = WAIT_FOR_INT;
571 }
572 }
573
574 writel(val, host->ioaddr + reg);
575}
576
577static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
578{
579 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
580 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
581 u16 ret = 0;
582 u32 val;
583
584 if (unlikely(reg == SDHCI_HOST_VERSION)) {
585 reg ^= 2;
586 if (esdhc_is_usdhc(imx_data)) {
587
588
589
590
591 return SDHCI_SPEC_300;
592 }
593 }
594
595 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
596 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
597 if (val & ESDHC_VENDOR_SPEC_VSELECT)
598 ret |= SDHCI_CTRL_VDD_180;
599
600 if (esdhc_is_usdhc(imx_data)) {
601 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
602 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
603 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
604
605 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
606 }
607
608 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
609 ret |= SDHCI_CTRL_EXEC_TUNING;
610 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
611 ret |= SDHCI_CTRL_TUNED_CLK;
612
613 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
614
615 return ret;
616 }
617
618 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
619 if (esdhc_is_usdhc(imx_data)) {
620 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
621 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
622
623 if (m & ESDHC_MIX_CTRL_AC23EN) {
624 ret &= ~ESDHC_MIX_CTRL_AC23EN;
625 ret |= SDHCI_TRNS_AUTO_CMD23;
626 }
627 } else {
628 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
629 }
630
631 return ret;
632 }
633
634 return readw(host->ioaddr + reg);
635}
636
637static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
638{
639 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
640 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
641 u32 new_val = 0;
642
643 switch (reg) {
644 case SDHCI_CLOCK_CONTROL:
645 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
646 if (val & SDHCI_CLOCK_CARD_EN)
647 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
648 else
649 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
650 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
651 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
652 esdhc_wait_for_card_clock_gate_off(host);
653 return;
654 case SDHCI_HOST_CONTROL2:
655 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
656 if (val & SDHCI_CTRL_VDD_180)
657 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
658 else
659 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
660 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
661 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
662 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
663 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
664 if (val & SDHCI_CTRL_TUNED_CLK) {
665 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
666 } else {
667 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
668 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
669 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
670 }
671
672 if (val & SDHCI_CTRL_EXEC_TUNING) {
673 v |= ESDHC_MIX_CTRL_EXE_TUNE;
674 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
675 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
676 usdhc_auto_tuning_mode_sel(host);
677 } else {
678 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
679 }
680
681 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
682 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
683 }
684 return;
685 case SDHCI_TRANSFER_MODE:
686 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
687 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
688 && (host->cmd->data->blocks > 1)
689 && (host->cmd->data->flags & MMC_DATA_READ)) {
690 u32 v;
691 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
692 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
693 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
694 }
695
696 if (esdhc_is_usdhc(imx_data)) {
697 u32 wml;
698 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
699
700 if (val & SDHCI_TRNS_AUTO_CMD23) {
701 val &= ~SDHCI_TRNS_AUTO_CMD23;
702 val |= ESDHC_MIX_CTRL_AC23EN;
703 }
704 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
705 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
706
707
708
709
710
711 m = readl(host->ioaddr + ESDHC_WTMK_LVL);
712 if (val & SDHCI_TRNS_DMA) {
713 wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
714 } else {
715 u8 ctrl;
716 wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
717
718
719
720
721
722
723
724
725
726 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
727 ctrl &= ~SDHCI_CTRL_DMA_MASK;
728 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
729 }
730 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
731 ESDHC_WTMK_LVL_WR_WML_MASK);
732 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
733 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
734 writel(m, host->ioaddr + ESDHC_WTMK_LVL);
735 } else {
736
737
738
739
740 imx_data->scratchpad = val;
741 }
742 return;
743 case SDHCI_COMMAND:
744 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
745 val |= SDHCI_CMD_ABORTCMD;
746
747 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
748 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
749 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
750
751 if (esdhc_is_usdhc(imx_data))
752 writel(val << 16,
753 host->ioaddr + SDHCI_TRANSFER_MODE);
754 else
755 writel(val << 16 | imx_data->scratchpad,
756 host->ioaddr + SDHCI_TRANSFER_MODE);
757 return;
758 case SDHCI_BLOCK_SIZE:
759 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
760 break;
761 }
762 esdhc_clrset_le(host, 0xffff, val, reg);
763}
764
765static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
766{
767 u8 ret;
768 u32 val;
769
770 switch (reg) {
771 case SDHCI_HOST_CONTROL:
772 val = readl(host->ioaddr + reg);
773
774 ret = val & SDHCI_CTRL_LED;
775 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
776 ret |= (val & ESDHC_CTRL_4BITBUS);
777 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
778 return ret;
779 }
780
781 return readb(host->ioaddr + reg);
782}
783
784static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
785{
786 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
787 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
788 u32 new_val = 0;
789 u32 mask;
790
791 switch (reg) {
792 case SDHCI_POWER_CONTROL:
793
794
795
796
797 return;
798 case SDHCI_HOST_CONTROL:
799
800 new_val = val & SDHCI_CTRL_LED;
801
802 new_val |= ESDHC_HOST_CONTROL_LE;
803
804 if (!is_imx25_esdhc(imx_data)) {
805
806 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
807 }
808
809
810
811
812
813
814
815 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
816
817 esdhc_clrset_le(host, mask, new_val, reg);
818 return;
819 case SDHCI_SOFTWARE_RESET:
820 if (val & SDHCI_RESET_DATA)
821 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL);
822 break;
823 }
824 esdhc_clrset_le(host, 0xff, val, reg);
825
826 if (reg == SDHCI_SOFTWARE_RESET) {
827 if (val & SDHCI_RESET_ALL) {
828
829
830
831
832
833
834
835
836
837 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
838
839
840
841
842 if (esdhc_is_usdhc(imx_data)) {
843
844
845
846 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
847 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
848 host->ioaddr + ESDHC_MIX_CTRL);
849 imx_data->is_ddr = 0;
850 }
851 } else if (val & SDHCI_RESET_DATA) {
852
853
854
855
856
857 esdhc_clrset_le(host, 0xff, new_val,
858 SDHCI_HOST_CONTROL);
859 }
860 }
861}
862
863static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
864{
865 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
866
867 return pltfm_host->clock;
868}
869
870static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
871{
872 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
873
874 return pltfm_host->clock / 256 / 16;
875}
876
877static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
878 unsigned int clock)
879{
880 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
881 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
882 unsigned int host_clock = pltfm_host->clock;
883 int ddr_pre_div = imx_data->is_ddr ? 2 : 1;
884 int pre_div = 1;
885 int div = 1;
886 int ret;
887 u32 temp, val;
888
889 if (esdhc_is_usdhc(imx_data)) {
890 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
891 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
892 host->ioaddr + ESDHC_VENDOR_SPEC);
893 esdhc_wait_for_card_clock_gate_off(host);
894 }
895
896 if (clock == 0) {
897 host->mmc->actual_clock = 0;
898 return;
899 }
900
901
902 if (is_imx53_esdhc(imx_data)) {
903
904
905
906
907 val = readl(host->ioaddr + ESDHC_DLL_CTRL);
908 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
909 temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
910 writel(val, host->ioaddr + ESDHC_DLL_CTRL);
911 if (temp & BIT(10))
912 pre_div = 2;
913 }
914
915 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
916 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
917 | ESDHC_CLOCK_MASK);
918 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
919
920 if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) {
921 unsigned int max_clock;
922
923 max_clock = imx_data->is_ddr ? 45000000 : 150000000;
924
925 clock = min(clock, max_clock);
926 }
927
928 while (host_clock / (16 * pre_div * ddr_pre_div) > clock &&
929 pre_div < 256)
930 pre_div *= 2;
931
932 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16)
933 div++;
934
935 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div);
936 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
937 clock, host->mmc->actual_clock);
938
939 pre_div >>= 1;
940 div--;
941
942 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
943 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
944 | (div << ESDHC_DIVIDER_SHIFT)
945 | (pre_div << ESDHC_PREDIV_SHIFT));
946 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
947
948
949 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
950 (temp & ESDHC_CLOCK_STABLE), 2, 100);
951 if (ret == -ETIMEDOUT)
952 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
953
954 if (esdhc_is_usdhc(imx_data)) {
955 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
956 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
957 host->ioaddr + ESDHC_VENDOR_SPEC);
958 }
959
960}
961
962static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
963{
964 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
965 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
966 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
967
968 switch (boarddata->wp_type) {
969 case ESDHC_WP_GPIO:
970 return mmc_gpio_get_ro(host->mmc);
971 case ESDHC_WP_CONTROLLER:
972 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
973 SDHCI_WRITE_PROTECT);
974 case ESDHC_WP_NONE:
975 break;
976 }
977
978 return -ENOSYS;
979}
980
981static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
982{
983 u32 ctrl;
984
985 switch (width) {
986 case MMC_BUS_WIDTH_8:
987 ctrl = ESDHC_CTRL_8BITBUS;
988 break;
989 case MMC_BUS_WIDTH_4:
990 ctrl = ESDHC_CTRL_4BITBUS;
991 break;
992 default:
993 ctrl = 0;
994 break;
995 }
996
997 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
998 SDHCI_HOST_CONTROL);
999}
1000
1001static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
1002{
1003 struct sdhci_host *host = mmc_priv(mmc);
1004
1005
1006
1007
1008
1009 if (host->timing == MMC_TIMING_UHS_DDR50)
1010 return 0;
1011
1012 return sdhci_execute_tuning(mmc, opcode);
1013}
1014
1015static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
1016{
1017 u32 reg;
1018 u8 sw_rst;
1019 int ret;
1020
1021
1022 mdelay(1);
1023
1024
1025 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
1026 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
1027 !(sw_rst & SDHCI_RESET_ALL), 10, 100);
1028 if (ret == -ETIMEDOUT)
1029 dev_warn(mmc_dev(host->mmc),
1030 "warning! RESET_ALL never complete before sending tuning command\n");
1031
1032 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1033 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
1034 ESDHC_MIX_CTRL_FBCLK_SEL;
1035 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1036 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1037 dev_dbg(mmc_dev(host->mmc),
1038 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
1039 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
1040}
1041
1042static void esdhc_post_tuning(struct sdhci_host *host)
1043{
1044 u32 reg;
1045
1046 usdhc_auto_tuning_mode_sel(host);
1047
1048 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
1049 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1050 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
1051 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
1052}
1053
1054static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
1055{
1056 int min, max, avg, ret;
1057
1058
1059 min = ESDHC_TUNE_CTRL_MIN;
1060 while (min < ESDHC_TUNE_CTRL_MAX) {
1061 esdhc_prepare_tuning(host, min);
1062 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1063 break;
1064 min += ESDHC_TUNE_CTRL_STEP;
1065 }
1066
1067
1068 max = min + ESDHC_TUNE_CTRL_STEP;
1069 while (max < ESDHC_TUNE_CTRL_MAX) {
1070 esdhc_prepare_tuning(host, max);
1071 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1072 max -= ESDHC_TUNE_CTRL_STEP;
1073 break;
1074 }
1075 max += ESDHC_TUNE_CTRL_STEP;
1076 }
1077
1078
1079 avg = (min + max) / 2;
1080 esdhc_prepare_tuning(host, avg);
1081 ret = mmc_send_tuning(host->mmc, opcode, NULL);
1082 esdhc_post_tuning(host);
1083
1084 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
1085 ret ? "failed" : "passed", avg, ret);
1086
1087 return ret;
1088}
1089
1090static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios)
1091{
1092 struct sdhci_host *host = mmc_priv(mmc);
1093 u32 m;
1094
1095 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1096 if (ios->enhanced_strobe)
1097 m |= ESDHC_MIX_CTRL_HS400_ES_EN;
1098 else
1099 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
1100 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1101}
1102
1103static int esdhc_change_pinstate(struct sdhci_host *host,
1104 unsigned int uhs)
1105{
1106 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1107 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1108 struct pinctrl_state *pinctrl;
1109
1110 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
1111
1112 if (IS_ERR(imx_data->pinctrl) ||
1113 IS_ERR(imx_data->pins_100mhz) ||
1114 IS_ERR(imx_data->pins_200mhz))
1115 return -EINVAL;
1116
1117 switch (uhs) {
1118 case MMC_TIMING_UHS_SDR50:
1119 case MMC_TIMING_UHS_DDR50:
1120 pinctrl = imx_data->pins_100mhz;
1121 break;
1122 case MMC_TIMING_UHS_SDR104:
1123 case MMC_TIMING_MMC_HS200:
1124 case MMC_TIMING_MMC_HS400:
1125 pinctrl = imx_data->pins_200mhz;
1126 break;
1127 default:
1128
1129 return pinctrl_select_default_state(mmc_dev(host->mmc));
1130 }
1131
1132 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
1133}
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144static void esdhc_set_strobe_dll(struct sdhci_host *host)
1145{
1146 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1147 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1148 u32 strobe_delay;
1149 u32 v;
1150 int ret;
1151
1152
1153 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
1154 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
1155 host->ioaddr + ESDHC_VENDOR_SPEC);
1156 esdhc_wait_for_card_clock_gate_off(host);
1157
1158
1159 writel(ESDHC_STROBE_DLL_CTRL_RESET,
1160 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1161
1162 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1163
1164
1165
1166
1167
1168 if (imx_data->boarddata.strobe_dll_delay_target)
1169 strobe_delay = imx_data->boarddata.strobe_dll_delay_target;
1170 else
1171 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
1172 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
1173 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
1174 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
1175 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
1176
1177
1178 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
1179 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50);
1180 if (ret == -ETIMEDOUT)
1181 dev_warn(mmc_dev(host->mmc),
1182 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
1183}
1184
1185static void esdhc_reset_tuning(struct sdhci_host *host)
1186{
1187 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1188 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1189 u32 ctrl;
1190 int ret;
1191
1192
1193 if (esdhc_is_usdhc(imx_data)) {
1194 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1195 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
1196 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1197 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
1198 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
1199 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1200 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1201 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1202 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
1203 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
1204 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1205
1206 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
1207 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50);
1208 if (ret == -ETIMEDOUT)
1209 dev_warn(mmc_dev(host->mmc),
1210 "Warning! clear execute tuning bit failed\n");
1211
1212
1213
1214
1215
1216 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
1217 ctrl |= SDHCI_INT_DATA_AVAIL;
1218 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
1219 }
1220 }
1221}
1222
1223static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1224{
1225 u32 m;
1226 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1227 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1228 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1229
1230
1231 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
1232 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
1233 imx_data->is_ddr = 0;
1234
1235 switch (timing) {
1236 case MMC_TIMING_UHS_SDR12:
1237 case MMC_TIMING_UHS_SDR25:
1238 case MMC_TIMING_UHS_SDR50:
1239 case MMC_TIMING_UHS_SDR104:
1240 case MMC_TIMING_MMC_HS:
1241 case MMC_TIMING_MMC_HS200:
1242 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1243 break;
1244 case MMC_TIMING_UHS_DDR50:
1245 case MMC_TIMING_MMC_DDR52:
1246 m |= ESDHC_MIX_CTRL_DDREN;
1247 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1248 imx_data->is_ddr = 1;
1249 if (boarddata->delay_line) {
1250 u32 v;
1251 v = boarddata->delay_line <<
1252 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
1253 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
1254 if (is_imx53_esdhc(imx_data))
1255 v <<= 1;
1256 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
1257 }
1258 break;
1259 case MMC_TIMING_MMC_HS400:
1260 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
1261 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
1262 imx_data->is_ddr = 1;
1263
1264 host->ops->set_clock(host, host->clock);
1265 esdhc_set_strobe_dll(host);
1266 break;
1267 case MMC_TIMING_LEGACY:
1268 default:
1269 esdhc_reset_tuning(host);
1270 break;
1271 }
1272
1273 esdhc_change_pinstate(host, timing);
1274}
1275
1276static void esdhc_reset(struct sdhci_host *host, u8 mask)
1277{
1278 sdhci_reset(host, mask);
1279
1280 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1281 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1282}
1283
1284static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
1285{
1286 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1287 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1288
1289
1290 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
1291}
1292
1293static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1294{
1295 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1296 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1297
1298
1299 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
1300 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
1301 SDHCI_TIMEOUT_CONTROL);
1302}
1303
1304static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask)
1305{
1306 int cmd_error = 0;
1307 int data_error = 0;
1308
1309 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1310 return intmask;
1311
1312 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1313
1314 return 0;
1315}
1316
1317static struct sdhci_ops sdhci_esdhc_ops = {
1318 .read_l = esdhc_readl_le,
1319 .read_w = esdhc_readw_le,
1320 .read_b = esdhc_readb_le,
1321 .write_l = esdhc_writel_le,
1322 .write_w = esdhc_writew_le,
1323 .write_b = esdhc_writeb_le,
1324 .set_clock = esdhc_pltfm_set_clock,
1325 .get_max_clock = esdhc_pltfm_get_max_clock,
1326 .get_min_clock = esdhc_pltfm_get_min_clock,
1327 .get_max_timeout_count = esdhc_get_max_timeout_count,
1328 .get_ro = esdhc_pltfm_get_ro,
1329 .set_timeout = esdhc_set_timeout,
1330 .set_bus_width = esdhc_pltfm_set_bus_width,
1331 .set_uhs_signaling = esdhc_set_uhs_signaling,
1332 .reset = esdhc_reset,
1333 .irq = esdhc_cqhci_irq,
1334 .dump_vendor_regs = esdhc_dump_debug_regs,
1335};
1336
1337static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
1338 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
1339 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
1340 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
1341 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
1342 .ops = &sdhci_esdhc_ops,
1343};
1344
1345static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
1346{
1347 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1348 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1349 struct cqhci_host *cq_host = host->mmc->cqe_private;
1350 int tmp;
1351
1352 if (esdhc_is_usdhc(imx_data)) {
1353
1354
1355
1356
1357 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1371 | ESDHC_BURST_LEN_EN_INCR,
1372 host->ioaddr + SDHCI_HOST_CONTROL);
1373
1374
1375
1376
1377
1378 writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
1379 host->ioaddr + 0x6c);
1380
1381
1382 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1394 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
1395 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
1396 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
1397
1398 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
1399 }
1400
1401 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1402 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1403 tmp |= ESDHC_STD_TUNING_EN |
1404 ESDHC_TUNING_START_TAP_DEFAULT;
1405 if (imx_data->boarddata.tuning_start_tap) {
1406 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1407 tmp |= imx_data->boarddata.tuning_start_tap;
1408 }
1409
1410 if (imx_data->boarddata.tuning_step) {
1411 tmp &= ~ESDHC_TUNING_STEP_MASK;
1412 tmp |= imx_data->boarddata.tuning_step
1413 << ESDHC_TUNING_STEP_SHIFT;
1414 }
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
1427 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1428 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
1429
1430
1431
1432
1433
1434 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1435 tmp &= ~ESDHC_STD_TUNING_EN;
1436 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1437 }
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448 if (cq_host) {
1449 tmp = cqhci_readl(cq_host, CQHCI_IS);
1450 cqhci_writel(cq_host, tmp, CQHCI_IS);
1451 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
1452 }
1453 }
1454}
1455
1456static void esdhc_cqe_enable(struct mmc_host *mmc)
1457{
1458 struct sdhci_host *host = mmc_priv(mmc);
1459 struct cqhci_host *cq_host = mmc->cqe_private;
1460 u32 reg;
1461 u16 mode;
1462 int count = 10;
1463
1464
1465
1466
1467
1468 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1469 while (reg & SDHCI_DATA_AVAILABLE) {
1470 sdhci_readl(host, SDHCI_BUFFER);
1471 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
1472 if (count-- == 0) {
1473 dev_warn(mmc_dev(host->mmc),
1474 "CQE may get stuck because the Buffer Read Enable bit is set\n");
1475 break;
1476 }
1477 mdelay(1);
1478 }
1479
1480
1481
1482
1483
1484
1485 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1486 if (host->flags & SDHCI_REQ_USE_DMA)
1487 mode |= SDHCI_TRNS_DMA;
1488 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1489 mode |= SDHCI_TRNS_BLK_CNT_EN;
1490 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1491
1492
1493
1494
1495
1496
1497
1498 cqhci_writel(cq_host, 0, CQHCI_CTL);
1499 if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT)
1500 dev_err(mmc_dev(host->mmc),
1501 "failed to exit halt state when enable CQE\n");
1502
1503
1504 sdhci_cqe_enable(mmc);
1505}
1506
1507static void esdhc_sdhci_dumpregs(struct mmc_host *mmc)
1508{
1509 sdhci_dumpregs(mmc_priv(mmc));
1510}
1511
1512static const struct cqhci_host_ops esdhc_cqhci_ops = {
1513 .enable = esdhc_cqe_enable,
1514 .disable = sdhci_cqe_disable,
1515 .dumpregs = esdhc_sdhci_dumpregs,
1516};
1517
1518static int
1519sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
1520 struct sdhci_host *host,
1521 struct pltfm_imx_data *imx_data)
1522{
1523 struct device_node *np = pdev->dev.of_node;
1524 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1525 int ret;
1526
1527 if (of_get_property(np, "fsl,wp-controller", NULL))
1528 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1529
1530
1531
1532
1533
1534
1535 if (of_property_read_bool(np, "wp-gpios"))
1536 boarddata->wp_type = ESDHC_WP_GPIO;
1537
1538 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
1539 of_property_read_u32(np, "fsl,tuning-start-tap",
1540 &boarddata->tuning_start_tap);
1541
1542 of_property_read_u32(np, "fsl,strobe-dll-delay-target",
1543 &boarddata->strobe_dll_delay_target);
1544 if (of_find_property(np, "no-1-8-v", NULL))
1545 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1546
1547 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1548 boarddata->delay_line = 0;
1549
1550 mmc_of_parse_voltage(host->mmc, &host->ocr_mask);
1551
1552 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) {
1553 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1554 ESDHC_PINCTRL_STATE_100MHZ);
1555 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1556 ESDHC_PINCTRL_STATE_200MHZ);
1557 }
1558
1559
1560 ret = mmc_of_parse(host->mmc);
1561 if (ret)
1562 return ret;
1563
1564 if (mmc_gpio_get_cd(host->mmc) >= 0)
1565 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1566
1567 return 0;
1568}
1569
1570static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
1571{
1572 struct sdhci_pltfm_host *pltfm_host;
1573 struct sdhci_host *host;
1574 struct cqhci_host *cq_host;
1575 int err;
1576 struct pltfm_imx_data *imx_data;
1577
1578 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1579 sizeof(*imx_data));
1580 if (IS_ERR(host))
1581 return PTR_ERR(host);
1582
1583 pltfm_host = sdhci_priv(host);
1584
1585 imx_data = sdhci_pltfm_priv(pltfm_host);
1586
1587 imx_data->socdata = device_get_match_data(&pdev->dev);
1588
1589 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1590 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1591
1592 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1593 if (IS_ERR(imx_data->clk_ipg)) {
1594 err = PTR_ERR(imx_data->clk_ipg);
1595 goto free_sdhci;
1596 }
1597
1598 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1599 if (IS_ERR(imx_data->clk_ahb)) {
1600 err = PTR_ERR(imx_data->clk_ahb);
1601 goto free_sdhci;
1602 }
1603
1604 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1605 if (IS_ERR(imx_data->clk_per)) {
1606 err = PTR_ERR(imx_data->clk_per);
1607 goto free_sdhci;
1608 }
1609
1610 pltfm_host->clk = imx_data->clk_per;
1611 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
1612 err = clk_prepare_enable(imx_data->clk_per);
1613 if (err)
1614 goto free_sdhci;
1615 err = clk_prepare_enable(imx_data->clk_ipg);
1616 if (err)
1617 goto disable_per_clk;
1618 err = clk_prepare_enable(imx_data->clk_ahb);
1619 if (err)
1620 goto disable_ipg_clk;
1621
1622 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1623 if (IS_ERR(imx_data->pinctrl))
1624 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n");
1625
1626 if (esdhc_is_usdhc(imx_data)) {
1627 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1628 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
1629
1630
1631 host->mmc->caps |= MMC_CAP_CD_WAKE;
1632
1633 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1634 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
1635
1636
1637 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1638 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
1639 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
1640
1641
1642
1643
1644
1645 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
1646 }
1647
1648 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1649 sdhci_esdhc_ops.platform_execute_tuning =
1650 esdhc_executing_tuning;
1651
1652 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1653 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1654
1655 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1656 host->mmc->caps2 |= MMC_CAP2_HS400;
1657
1658 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
1659 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
1660
1661 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) {
1662 host->mmc->caps2 |= MMC_CAP2_HS400_ES;
1663 host->mmc_host_ops.hs400_enhanced_strobe =
1664 esdhc_hs400_enhanced_strobe;
1665 }
1666
1667 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
1668 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1669 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL);
1670 if (!cq_host) {
1671 err = -ENOMEM;
1672 goto disable_ahb_clk;
1673 }
1674
1675 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET;
1676 cq_host->ops = &esdhc_cqhci_ops;
1677
1678 err = cqhci_init(cq_host, host->mmc, false);
1679 if (err)
1680 goto disable_ahb_clk;
1681 }
1682
1683 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1684 if (err)
1685 goto disable_ahb_clk;
1686
1687 sdhci_esdhc_imx_hwinit(host);
1688
1689 err = sdhci_add_host(host);
1690 if (err)
1691 goto disable_ahb_clk;
1692
1693
1694
1695
1696
1697 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
1698 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
1699 device_set_wakeup_capable(&pdev->dev, true);
1700
1701 pm_runtime_set_active(&pdev->dev);
1702 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1703 pm_runtime_use_autosuspend(&pdev->dev);
1704 pm_suspend_ignore_children(&pdev->dev, 1);
1705 pm_runtime_enable(&pdev->dev);
1706
1707 return 0;
1708
1709disable_ahb_clk:
1710 clk_disable_unprepare(imx_data->clk_ahb);
1711disable_ipg_clk:
1712 clk_disable_unprepare(imx_data->clk_ipg);
1713disable_per_clk:
1714 clk_disable_unprepare(imx_data->clk_per);
1715free_sdhci:
1716 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1717 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1718 sdhci_pltfm_free(pdev);
1719 return err;
1720}
1721
1722static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1723{
1724 struct sdhci_host *host = platform_get_drvdata(pdev);
1725 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1726 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1727 int dead;
1728
1729 pm_runtime_get_sync(&pdev->dev);
1730 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1731 pm_runtime_disable(&pdev->dev);
1732 pm_runtime_put_noidle(&pdev->dev);
1733
1734 sdhci_remove_host(host, dead);
1735
1736 clk_disable_unprepare(imx_data->clk_per);
1737 clk_disable_unprepare(imx_data->clk_ipg);
1738 clk_disable_unprepare(imx_data->clk_ahb);
1739
1740 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1741 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1742
1743 sdhci_pltfm_free(pdev);
1744
1745 return 0;
1746}
1747
1748#ifdef CONFIG_PM_SLEEP
1749static int sdhci_esdhc_suspend(struct device *dev)
1750{
1751 struct sdhci_host *host = dev_get_drvdata(dev);
1752 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1753 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1754 int ret;
1755
1756 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1757 ret = cqhci_suspend(host->mmc);
1758 if (ret)
1759 return ret;
1760 }
1761
1762 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) &&
1763 (host->tuning_mode != SDHCI_TUNING_MODE_1)) {
1764 mmc_retune_timer_stop(host->mmc);
1765 mmc_retune_needed(host->mmc);
1766 }
1767
1768 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1769 mmc_retune_needed(host->mmc);
1770
1771 ret = sdhci_suspend_host(host);
1772 if (ret)
1773 return ret;
1774
1775 ret = pinctrl_pm_select_sleep_state(dev);
1776 if (ret)
1777 return ret;
1778
1779 ret = mmc_gpio_set_cd_wake(host->mmc, true);
1780
1781 return ret;
1782}
1783
1784static int sdhci_esdhc_resume(struct device *dev)
1785{
1786 struct sdhci_host *host = dev_get_drvdata(dev);
1787 int ret;
1788
1789 ret = pinctrl_pm_select_default_state(dev);
1790 if (ret)
1791 return ret;
1792
1793
1794 sdhci_esdhc_imx_hwinit(host);
1795
1796 ret = sdhci_resume_host(host);
1797 if (ret)
1798 return ret;
1799
1800 if (host->mmc->caps2 & MMC_CAP2_CQE)
1801 ret = cqhci_resume(host->mmc);
1802
1803 if (!ret)
1804 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1805
1806 return ret;
1807}
1808#endif
1809
1810#ifdef CONFIG_PM
1811static int sdhci_esdhc_runtime_suspend(struct device *dev)
1812{
1813 struct sdhci_host *host = dev_get_drvdata(dev);
1814 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1815 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1816 int ret;
1817
1818 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1819 ret = cqhci_suspend(host->mmc);
1820 if (ret)
1821 return ret;
1822 }
1823
1824 ret = sdhci_runtime_suspend_host(host);
1825 if (ret)
1826 return ret;
1827
1828 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
1829 mmc_retune_needed(host->mmc);
1830
1831 imx_data->actual_clock = host->mmc->actual_clock;
1832 esdhc_pltfm_set_clock(host, 0);
1833 clk_disable_unprepare(imx_data->clk_per);
1834 clk_disable_unprepare(imx_data->clk_ipg);
1835 clk_disable_unprepare(imx_data->clk_ahb);
1836
1837 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1838 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1839
1840 return ret;
1841}
1842
1843static int sdhci_esdhc_runtime_resume(struct device *dev)
1844{
1845 struct sdhci_host *host = dev_get_drvdata(dev);
1846 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1847 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
1848 int err;
1849
1850 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1851 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0);
1852
1853 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME)
1854 clk_set_rate(imx_data->clk_per, pltfm_host->clock);
1855
1856 err = clk_prepare_enable(imx_data->clk_ahb);
1857 if (err)
1858 goto remove_pm_qos_request;
1859
1860 err = clk_prepare_enable(imx_data->clk_per);
1861 if (err)
1862 goto disable_ahb_clk;
1863
1864 err = clk_prepare_enable(imx_data->clk_ipg);
1865 if (err)
1866 goto disable_per_clk;
1867
1868 esdhc_pltfm_set_clock(host, imx_data->actual_clock);
1869
1870 err = sdhci_runtime_resume_host(host, 0);
1871 if (err)
1872 goto disable_ipg_clk;
1873
1874 if (host->mmc->caps2 & MMC_CAP2_CQE)
1875 err = cqhci_resume(host->mmc);
1876
1877 return err;
1878
1879disable_ipg_clk:
1880 clk_disable_unprepare(imx_data->clk_ipg);
1881disable_per_clk:
1882 clk_disable_unprepare(imx_data->clk_per);
1883disable_ahb_clk:
1884 clk_disable_unprepare(imx_data->clk_ahb);
1885remove_pm_qos_request:
1886 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS)
1887 cpu_latency_qos_remove_request(&imx_data->pm_qos_req);
1888 return err;
1889}
1890#endif
1891
1892static const struct dev_pm_ops sdhci_esdhc_pmops = {
1893 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
1894 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1895 sdhci_esdhc_runtime_resume, NULL)
1896};
1897
1898static struct platform_driver sdhci_esdhc_imx_driver = {
1899 .driver = {
1900 .name = "sdhci-esdhc-imx",
1901 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1902 .of_match_table = imx_esdhc_dt_ids,
1903 .pm = &sdhci_esdhc_pmops,
1904 },
1905 .probe = sdhci_esdhc_imx_probe,
1906 .remove = sdhci_esdhc_imx_remove,
1907};
1908
1909module_platform_driver(sdhci_esdhc_imx_driver);
1910
1911MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1912MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1913MODULE_LICENSE("GPL v2");
1914