1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#include <linux/clk-provider.h>
19#include <linux/mfd/syscon.h>
20#include <linux/module.h>
21#include <linux/of_device.h>
22#include <linux/phy/phy.h>
23#include <linux/regmap.h>
24#include <linux/of.h>
25#include <linux/firmware/xlnx-zynqmp.h>
26
27#include "cqhci.h"
28#include "sdhci-pltfm.h"
29
30#define SDHCI_ARASAN_VENDOR_REGISTER 0x78
31
32#define SDHCI_ARASAN_ITAPDLY_REGISTER 0xF0F8
33#define SDHCI_ARASAN_ITAPDLY_SEL_MASK 0xFF
34
35#define SDHCI_ARASAN_OTAPDLY_REGISTER 0xF0FC
36#define SDHCI_ARASAN_OTAPDLY_SEL_MASK 0x3F
37
38#define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
39#define VENDOR_ENHANCED_STROBE BIT(0)
40
41#define PHY_CLK_TOO_SLOW_HZ 400000
42
43#define SDHCI_ITAPDLY_CHGWIN 0x200
44#define SDHCI_ITAPDLY_ENABLE 0x100
45#define SDHCI_OTAPDLY_ENABLE 0x40
46
47
48#define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
49#define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
50
51#define VERSAL_ICLK_PHASE {0, 132, 132, 0, 132, 0, 0, 162, 90, 0, 0}
52#define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
53
54
55
56
57
58
59
60#define HIWORD_UPDATE(val, mask, shift) \
61 ((val) << (shift) | (mask) << ((shift) + 16))
62
63
64
65
66
67
68
69
70struct sdhci_arasan_soc_ctl_field {
71 u32 reg;
72 u16 width;
73 s16 shift;
74};
75
76
77
78
79
80
81
82
83
84
85
86
87
88struct sdhci_arasan_soc_ctl_map {
89 struct sdhci_arasan_soc_ctl_field baseclkfreq;
90 struct sdhci_arasan_soc_ctl_field clockmultiplier;
91 struct sdhci_arasan_soc_ctl_field support64b;
92 bool hiword_update;
93};
94
95
96
97
98
99
100
101struct sdhci_arasan_clk_ops {
102 const struct clk_ops *sdcardclk_ops;
103 const struct clk_ops *sampleclk_ops;
104};
105
106
107
108
109
110
111
112
113
114
115
116
117
118struct sdhci_arasan_clk_data {
119 struct clk_hw sdcardclk_hw;
120 struct clk *sdcardclk;
121 struct clk_hw sampleclk_hw;
122 struct clk *sampleclk;
123 int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
124 int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
125 void (*set_clk_delays)(struct sdhci_host *host);
126 void *clk_of_data;
127};
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143struct sdhci_arasan_data {
144 struct sdhci_host *host;
145 struct clk *clk_ahb;
146 struct phy *phy;
147 bool is_phy_on;
148
149 bool has_cqe;
150 struct sdhci_arasan_clk_data clk_data;
151 const struct sdhci_arasan_clk_ops *clk_ops;
152
153 struct regmap *soc_ctl_base;
154 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
155 unsigned int quirks;
156
157
158#define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0)
159
160
161#define SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE BIT(1)
162
163
164
165
166
167#define SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN BIT(2)
168};
169
170struct sdhci_arasan_of_data {
171 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
172 const struct sdhci_pltfm_data *pdata;
173 const struct sdhci_arasan_clk_ops *clk_ops;
174};
175
176static const struct sdhci_arasan_soc_ctl_map rk3399_soc_ctl_map = {
177 .baseclkfreq = { .reg = 0xf000, .width = 8, .shift = 8 },
178 .clockmultiplier = { .reg = 0xf02c, .width = 8, .shift = 0},
179 .hiword_update = true,
180};
181
182static const struct sdhci_arasan_soc_ctl_map intel_lgm_emmc_soc_ctl_map = {
183 .baseclkfreq = { .reg = 0xa0, .width = 8, .shift = 2 },
184 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
185 .hiword_update = false,
186};
187
188static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = {
189 .baseclkfreq = { .reg = 0x80, .width = 8, .shift = 2 },
190 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
191 .hiword_update = false,
192};
193
194static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = {
195 .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 },
196 .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 },
197 .support64b = { .reg = 0x4, .width = 1, .shift = 24 },
198 .hiword_update = false,
199};
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215static int sdhci_arasan_syscon_write(struct sdhci_host *host,
216 const struct sdhci_arasan_soc_ctl_field *fld,
217 u32 val)
218{
219 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
220 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
221 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base;
222 u32 reg = fld->reg;
223 u16 width = fld->width;
224 s16 shift = fld->shift;
225 int ret;
226
227
228
229
230
231
232
233 if (shift < 0)
234 return -EINVAL;
235
236 if (sdhci_arasan->soc_ctl_map->hiword_update)
237 ret = regmap_write(soc_ctl_base, reg,
238 HIWORD_UPDATE(val, GENMASK(width, 0),
239 shift));
240 else
241 ret = regmap_update_bits(soc_ctl_base, reg,
242 GENMASK(shift + width, shift),
243 val << shift);
244
245
246 if (ret)
247 pr_warn("%s: Regmap write fail: %d\n",
248 mmc_hostname(host->mmc), ret);
249
250 return ret;
251}
252
253static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
254{
255 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
256 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
257 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
258 bool ctrl_phy = false;
259
260 if (!IS_ERR(sdhci_arasan->phy)) {
261 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) {
262
263
264
265
266
267
268
269
270
271
272
273
274
275 sdhci_set_clock(host, host->max_clk);
276 if (phy_power_on(sdhci_arasan->phy)) {
277 pr_err("%s: Cannot power on phy.\n",
278 mmc_hostname(host->mmc));
279 return;
280 }
281
282 sdhci_arasan->is_phy_on = true;
283
284
285
286
287
288
289 } else if (clock > PHY_CLK_TOO_SLOW_HZ) {
290
291
292
293
294
295 ctrl_phy = true;
296 }
297 }
298
299 if (ctrl_phy && sdhci_arasan->is_phy_on) {
300 phy_power_off(sdhci_arasan->phy);
301 sdhci_arasan->is_phy_on = false;
302 }
303
304 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) {
305
306
307
308
309
310 if (clock == DEFAULT_SPEED_MAX_DTR)
311 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25;
312 }
313
314
315 if (clk_data->set_clk_delays)
316 clk_data->set_clk_delays(host);
317
318 sdhci_set_clock(host, clock);
319
320 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
321
322
323
324
325
326
327
328 msleep(20);
329
330 if (ctrl_phy) {
331 if (phy_power_on(sdhci_arasan->phy)) {
332 pr_err("%s: Cannot power on phy.\n",
333 mmc_hostname(host->mmc));
334 return;
335 }
336
337 sdhci_arasan->is_phy_on = true;
338 }
339}
340
341static void sdhci_arasan_hs400_enhanced_strobe(struct mmc_host *mmc,
342 struct mmc_ios *ios)
343{
344 u32 vendor;
345 struct sdhci_host *host = mmc_priv(mmc);
346
347 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER);
348 if (ios->enhanced_strobe)
349 vendor |= VENDOR_ENHANCED_STROBE;
350 else
351 vendor &= ~VENDOR_ENHANCED_STROBE;
352
353 sdhci_writel(host, vendor, SDHCI_ARASAN_VENDOR_REGISTER);
354}
355
356static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
357{
358 u8 ctrl;
359 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
360 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
361
362 sdhci_reset(host, mask);
363
364 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) {
365 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
366 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN;
367 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
368 }
369}
370
371static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
372 struct mmc_ios *ios)
373{
374 switch (ios->signal_voltage) {
375 case MMC_SIGNAL_VOLTAGE_180:
376
377
378
379
380
381
382
383 return 0;
384 case MMC_SIGNAL_VOLTAGE_330:
385 case MMC_SIGNAL_VOLTAGE_120:
386
387 break;
388 }
389
390 return -EINVAL;
391}
392
393static const struct sdhci_ops sdhci_arasan_ops = {
394 .set_clock = sdhci_arasan_set_clock,
395 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
396 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
397 .set_bus_width = sdhci_set_bus_width,
398 .reset = sdhci_arasan_reset,
399 .set_uhs_signaling = sdhci_set_uhs_signaling,
400 .set_power = sdhci_set_power_and_bus_voltage,
401};
402
403static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
404{
405 int cmd_error = 0;
406 int data_error = 0;
407
408 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
409 return intmask;
410
411 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
412
413 return 0;
414}
415
416static void sdhci_arasan_dumpregs(struct mmc_host *mmc)
417{
418 sdhci_dumpregs(mmc_priv(mmc));
419}
420
421static void sdhci_arasan_cqe_enable(struct mmc_host *mmc)
422{
423 struct sdhci_host *host = mmc_priv(mmc);
424 u32 reg;
425
426 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
427 while (reg & SDHCI_DATA_AVAILABLE) {
428 sdhci_readl(host, SDHCI_BUFFER);
429 reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
430 }
431
432 sdhci_cqe_enable(mmc);
433}
434
435static const struct cqhci_host_ops sdhci_arasan_cqhci_ops = {
436 .enable = sdhci_arasan_cqe_enable,
437 .disable = sdhci_cqe_disable,
438 .dumpregs = sdhci_arasan_dumpregs,
439};
440
441static const struct sdhci_ops sdhci_arasan_cqe_ops = {
442 .set_clock = sdhci_arasan_set_clock,
443 .get_max_clock = sdhci_pltfm_clk_get_max_clock,
444 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
445 .set_bus_width = sdhci_set_bus_width,
446 .reset = sdhci_arasan_reset,
447 .set_uhs_signaling = sdhci_set_uhs_signaling,
448 .set_power = sdhci_set_power_and_bus_voltage,
449 .irq = sdhci_arasan_cqhci_irq,
450};
451
452static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = {
453 .ops = &sdhci_arasan_cqe_ops,
454 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
455 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
456 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
457};
458
459#ifdef CONFIG_PM_SLEEP
460
461
462
463
464
465
466
467
468static int sdhci_arasan_suspend(struct device *dev)
469{
470 struct sdhci_host *host = dev_get_drvdata(dev);
471 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
472 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
473 int ret;
474
475 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
476 mmc_retune_needed(host->mmc);
477
478 if (sdhci_arasan->has_cqe) {
479 ret = cqhci_suspend(host->mmc);
480 if (ret)
481 return ret;
482 }
483
484 ret = sdhci_suspend_host(host);
485 if (ret)
486 return ret;
487
488 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) {
489 ret = phy_power_off(sdhci_arasan->phy);
490 if (ret) {
491 dev_err(dev, "Cannot power off phy.\n");
492 if (sdhci_resume_host(host))
493 dev_err(dev, "Cannot resume host.\n");
494
495 return ret;
496 }
497 sdhci_arasan->is_phy_on = false;
498 }
499
500 clk_disable(pltfm_host->clk);
501 clk_disable(sdhci_arasan->clk_ahb);
502
503 return 0;
504}
505
506
507
508
509
510
511
512
513
514static int sdhci_arasan_resume(struct device *dev)
515{
516 struct sdhci_host *host = dev_get_drvdata(dev);
517 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
518 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
519 int ret;
520
521 ret = clk_enable(sdhci_arasan->clk_ahb);
522 if (ret) {
523 dev_err(dev, "Cannot enable AHB clock.\n");
524 return ret;
525 }
526
527 ret = clk_enable(pltfm_host->clk);
528 if (ret) {
529 dev_err(dev, "Cannot enable SD clock.\n");
530 return ret;
531 }
532
533 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) {
534 ret = phy_power_on(sdhci_arasan->phy);
535 if (ret) {
536 dev_err(dev, "Cannot power on phy.\n");
537 return ret;
538 }
539 sdhci_arasan->is_phy_on = true;
540 }
541
542 ret = sdhci_resume_host(host);
543 if (ret) {
544 dev_err(dev, "Cannot resume host.\n");
545 return ret;
546 }
547
548 if (sdhci_arasan->has_cqe)
549 return cqhci_resume(host->mmc);
550
551 return 0;
552}
553#endif
554
555static SIMPLE_DEV_PM_OPS(sdhci_arasan_dev_pm_ops, sdhci_arasan_suspend,
556 sdhci_arasan_resume);
557
558
559
560
561
562
563
564
565
566
567
568
569static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
570 unsigned long parent_rate)
571{
572 struct sdhci_arasan_clk_data *clk_data =
573 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
574 struct sdhci_arasan_data *sdhci_arasan =
575 container_of(clk_data, struct sdhci_arasan_data, clk_data);
576 struct sdhci_host *host = sdhci_arasan->host;
577
578 return host->mmc->actual_clock;
579}
580
581static const struct clk_ops arasan_sdcardclk_ops = {
582 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
583};
584
585
586
587
588
589
590
591
592
593
594
595
596static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
597 unsigned long parent_rate)
598{
599 struct sdhci_arasan_clk_data *clk_data =
600 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
601 struct sdhci_arasan_data *sdhci_arasan =
602 container_of(clk_data, struct sdhci_arasan_data, clk_data);
603 struct sdhci_host *host = sdhci_arasan->host;
604
605 return host->mmc->actual_clock;
606}
607
608static const struct clk_ops arasan_sampleclk_ops = {
609 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
610};
611
612
613
614
615
616
617
618
619
620
621
622static int sdhci_zynqmp_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
623{
624 struct sdhci_arasan_clk_data *clk_data =
625 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
626 struct sdhci_arasan_data *sdhci_arasan =
627 container_of(clk_data, struct sdhci_arasan_data, clk_data);
628 struct sdhci_host *host = sdhci_arasan->host;
629 const char *clk_name = clk_hw_get_name(hw);
630 u32 node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1;
631 u8 tap_delay, tap_max = 0;
632 int ret;
633
634
635 if (host->version < SDHCI_SPEC_300)
636 return 0;
637
638 switch (host->timing) {
639 case MMC_TIMING_MMC_HS:
640 case MMC_TIMING_SD_HS:
641 case MMC_TIMING_UHS_SDR25:
642 case MMC_TIMING_UHS_DDR50:
643 case MMC_TIMING_MMC_DDR52:
644
645 tap_max = 30;
646 break;
647 case MMC_TIMING_UHS_SDR50:
648
649 tap_max = 15;
650 break;
651 case MMC_TIMING_UHS_SDR104:
652 case MMC_TIMING_MMC_HS200:
653
654 tap_max = 8;
655 break;
656 default:
657 break;
658 }
659
660 tap_delay = (degrees * tap_max) / 360;
661
662
663 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_OUTPUT, tap_delay);
664 if (ret)
665 pr_err("Error setting Output Tap Delay\n");
666
667
668 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_RELEASE);
669
670 return ret;
671}
672
673static const struct clk_ops zynqmp_sdcardclk_ops = {
674 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
675 .set_phase = sdhci_zynqmp_sdcardclk_set_phase,
676};
677
678
679
680
681
682
683
684
685
686
687
688static int sdhci_zynqmp_sampleclk_set_phase(struct clk_hw *hw, int degrees)
689{
690 struct sdhci_arasan_clk_data *clk_data =
691 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
692 struct sdhci_arasan_data *sdhci_arasan =
693 container_of(clk_data, struct sdhci_arasan_data, clk_data);
694 struct sdhci_host *host = sdhci_arasan->host;
695 const char *clk_name = clk_hw_get_name(hw);
696 u32 node_id = !strcmp(clk_name, "clk_in_sd0") ? NODE_SD_0 : NODE_SD_1;
697 u8 tap_delay, tap_max = 0;
698 int ret;
699
700
701 if (host->version < SDHCI_SPEC_300)
702 return 0;
703
704
705 zynqmp_pm_sd_dll_reset(node_id, PM_DLL_RESET_ASSERT);
706
707 switch (host->timing) {
708 case MMC_TIMING_MMC_HS:
709 case MMC_TIMING_SD_HS:
710 case MMC_TIMING_UHS_SDR25:
711 case MMC_TIMING_UHS_DDR50:
712 case MMC_TIMING_MMC_DDR52:
713
714 tap_max = 120;
715 break;
716 case MMC_TIMING_UHS_SDR50:
717
718 tap_max = 60;
719 break;
720 case MMC_TIMING_UHS_SDR104:
721 case MMC_TIMING_MMC_HS200:
722
723 tap_max = 30;
724 break;
725 default:
726 break;
727 }
728
729 tap_delay = (degrees * tap_max) / 360;
730
731
732 ret = zynqmp_pm_set_sd_tapdelay(node_id, PM_TAPDELAY_INPUT, tap_delay);
733 if (ret)
734 pr_err("Error setting Input Tap Delay\n");
735
736 return ret;
737}
738
739static const struct clk_ops zynqmp_sampleclk_ops = {
740 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
741 .set_phase = sdhci_zynqmp_sampleclk_set_phase,
742};
743
744
745
746
747
748
749
750
751
752
753
754static int sdhci_versal_sdcardclk_set_phase(struct clk_hw *hw, int degrees)
755{
756 struct sdhci_arasan_clk_data *clk_data =
757 container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
758 struct sdhci_arasan_data *sdhci_arasan =
759 container_of(clk_data, struct sdhci_arasan_data, clk_data);
760 struct sdhci_host *host = sdhci_arasan->host;
761 u8 tap_delay, tap_max = 0;
762
763
764 if (host->version < SDHCI_SPEC_300)
765 return 0;
766
767 switch (host->timing) {
768 case MMC_TIMING_MMC_HS:
769 case MMC_TIMING_SD_HS:
770 case MMC_TIMING_UHS_SDR25:
771 case MMC_TIMING_UHS_DDR50:
772 case MMC_TIMING_MMC_DDR52:
773
774 tap_max = 30;
775 break;
776 case MMC_TIMING_UHS_SDR50:
777
778 tap_max = 15;
779 break;
780 case MMC_TIMING_UHS_SDR104:
781 case MMC_TIMING_MMC_HS200:
782
783 tap_max = 8;
784 break;
785 default:
786 break;
787 }
788
789 tap_delay = (degrees * tap_max) / 360;
790
791
792 if (tap_delay) {
793 u32 regval;
794
795 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER);
796 regval |= SDHCI_OTAPDLY_ENABLE;
797 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
798 regval &= ~SDHCI_ARASAN_OTAPDLY_SEL_MASK;
799 regval |= tap_delay;
800 sdhci_writel(host, regval, SDHCI_ARASAN_OTAPDLY_REGISTER);
801 }
802
803 return 0;
804}
805
806static const struct clk_ops versal_sdcardclk_ops = {
807 .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
808 .set_phase = sdhci_versal_sdcardclk_set_phase,
809};
810
811
812
813
814
815
816
817
818
819
820
821static int sdhci_versal_sampleclk_set_phase(struct clk_hw *hw, int degrees)
822{
823 struct sdhci_arasan_clk_data *clk_data =
824 container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
825 struct sdhci_arasan_data *sdhci_arasan =
826 container_of(clk_data, struct sdhci_arasan_data, clk_data);
827 struct sdhci_host *host = sdhci_arasan->host;
828 u8 tap_delay, tap_max = 0;
829
830
831 if (host->version < SDHCI_SPEC_300)
832 return 0;
833
834 switch (host->timing) {
835 case MMC_TIMING_MMC_HS:
836 case MMC_TIMING_SD_HS:
837 case MMC_TIMING_UHS_SDR25:
838 case MMC_TIMING_UHS_DDR50:
839 case MMC_TIMING_MMC_DDR52:
840
841 tap_max = 120;
842 break;
843 case MMC_TIMING_UHS_SDR50:
844
845 tap_max = 60;
846 break;
847 case MMC_TIMING_UHS_SDR104:
848 case MMC_TIMING_MMC_HS200:
849
850 tap_max = 30;
851 break;
852 default:
853 break;
854 }
855
856 tap_delay = (degrees * tap_max) / 360;
857
858
859 if (tap_delay) {
860 u32 regval;
861
862 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER);
863 regval |= SDHCI_ITAPDLY_CHGWIN;
864 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
865 regval |= SDHCI_ITAPDLY_ENABLE;
866 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
867 regval &= ~SDHCI_ARASAN_ITAPDLY_SEL_MASK;
868 regval |= tap_delay;
869 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
870 regval &= ~SDHCI_ITAPDLY_CHGWIN;
871 sdhci_writel(host, regval, SDHCI_ARASAN_ITAPDLY_REGISTER);
872 }
873
874 return 0;
875}
876
877static const struct clk_ops versal_sampleclk_ops = {
878 .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
879 .set_phase = sdhci_versal_sampleclk_set_phase,
880};
881
882static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 deviceid)
883{
884 u16 clk;
885
886 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
887 clk &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
888 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
889
890
891 zynqmp_pm_sd_dll_reset(deviceid, PM_DLL_RESET_PULSE);
892
893 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
894
895 sdhci_enable_clk(host, clk);
896}
897
898static int arasan_zynqmp_execute_tuning(struct mmc_host *mmc, u32 opcode)
899{
900 struct sdhci_host *host = mmc_priv(mmc);
901 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
902 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
903 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw;
904 const char *clk_name = clk_hw_get_name(hw);
905 u32 device_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 :
906 NODE_SD_1;
907 int err;
908
909
910 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50)
911 return 0;
912
913 arasan_zynqmp_dll_reset(host, device_id);
914
915 err = sdhci_execute_tuning(mmc, opcode);
916 if (err)
917 return err;
918
919 arasan_zynqmp_dll_reset(host, device_id);
920
921 return 0;
922}
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942static void sdhci_arasan_update_clockmultiplier(struct sdhci_host *host,
943 u32 value)
944{
945 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
946 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
947 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
948 sdhci_arasan->soc_ctl_map;
949
950
951 if (!soc_ctl_map)
952 return;
953
954
955 if (!sdhci_arasan->soc_ctl_base) {
956 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
957 mmc_hostname(host->mmc));
958 return;
959 }
960
961 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value);
962}
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
982{
983 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
984 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
985 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map =
986 sdhci_arasan->soc_ctl_map;
987 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000);
988
989
990 if (!soc_ctl_map)
991 return;
992
993
994 if (!sdhci_arasan->soc_ctl_base) {
995 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
996 mmc_hostname(host->mmc));
997 return;
998 }
999
1000 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
1001}
1002
1003static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
1004{
1005 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1006 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1007 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1008
1009 clk_set_phase(clk_data->sampleclk,
1010 clk_data->clk_phase_in[host->timing]);
1011 clk_set_phase(clk_data->sdcardclk,
1012 clk_data->clk_phase_out[host->timing]);
1013}
1014
1015static void arasan_dt_read_clk_phase(struct device *dev,
1016 struct sdhci_arasan_clk_data *clk_data,
1017 unsigned int timing, const char *prop)
1018{
1019 struct device_node *np = dev->of_node;
1020
1021 u32 clk_phase[2] = {0};
1022 int ret;
1023
1024
1025
1026
1027
1028 ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0],
1029 2, 0);
1030 if (ret < 0) {
1031 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
1032 prop, clk_data->clk_phase_in[timing],
1033 clk_data->clk_phase_out[timing]);
1034 return;
1035 }
1036
1037
1038 clk_data->clk_phase_in[timing] = clk_phase[0];
1039 clk_data->clk_phase_out[timing] = clk_phase[1];
1040}
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050static void arasan_dt_parse_clk_phases(struct device *dev,
1051 struct sdhci_arasan_clk_data *clk_data)
1052{
1053 u32 mio_bank = 0;
1054 int i;
1055
1056
1057
1058
1059
1060
1061 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
1062
1063 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) {
1064 u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1065 ZYNQMP_ICLK_PHASE;
1066 u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1067 ZYNQMP_OCLK_PHASE;
1068
1069 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank);
1070 if (mio_bank == 2) {
1071 zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90;
1072 zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90;
1073 }
1074
1075 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1076 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i];
1077 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i];
1078 }
1079 }
1080
1081 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) {
1082 u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1083 VERSAL_ICLK_PHASE;
1084 u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] =
1085 VERSAL_OCLK_PHASE;
1086
1087 for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) {
1088 clk_data->clk_phase_in[i] = versal_iclk_phase[i];
1089 clk_data->clk_phase_out[i] = versal_oclk_phase[i];
1090 }
1091 }
1092
1093 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
1094 "clk-phase-legacy");
1095 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
1096 "clk-phase-mmc-hs");
1097 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
1098 "clk-phase-sd-hs");
1099 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
1100 "clk-phase-uhs-sdr12");
1101 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
1102 "clk-phase-uhs-sdr25");
1103 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
1104 "clk-phase-uhs-sdr50");
1105 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
1106 "clk-phase-uhs-sdr104");
1107 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
1108 "clk-phase-uhs-ddr50");
1109 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
1110 "clk-phase-mmc-ddr52");
1111 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
1112 "clk-phase-mmc-hs200");
1113 arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
1114 "clk-phase-mmc-hs400");
1115}
1116
1117static const struct sdhci_pltfm_data sdhci_arasan_pdata = {
1118 .ops = &sdhci_arasan_ops,
1119 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1120 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1121 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1122 SDHCI_QUIRK2_STOP_WITH_TC,
1123};
1124
1125static const struct sdhci_arasan_clk_ops arasan_clk_ops = {
1126 .sdcardclk_ops = &arasan_sdcardclk_ops,
1127 .sampleclk_ops = &arasan_sampleclk_ops,
1128};
1129
1130static struct sdhci_arasan_of_data sdhci_arasan_generic_data = {
1131 .pdata = &sdhci_arasan_pdata,
1132 .clk_ops = &arasan_clk_ops,
1133};
1134
1135static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = {
1136 .ops = &sdhci_arasan_cqe_ops,
1137 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1138 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1139 SDHCI_QUIRK_NO_LED |
1140 SDHCI_QUIRK_32BIT_DMA_ADDR |
1141 SDHCI_QUIRK_32BIT_DMA_SIZE |
1142 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1143 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1144 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1145 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1146 SDHCI_QUIRK2_STOP_WITH_TC |
1147 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1148};
1149
1150static const struct sdhci_pltfm_data sdhci_keembay_sd_pdata = {
1151 .ops = &sdhci_arasan_ops,
1152 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1153 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1154 SDHCI_QUIRK_NO_LED |
1155 SDHCI_QUIRK_32BIT_DMA_ADDR |
1156 SDHCI_QUIRK_32BIT_DMA_SIZE |
1157 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1158 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1159 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1160 SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1161 SDHCI_QUIRK2_STOP_WITH_TC |
1162 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1163};
1164
1165static const struct sdhci_pltfm_data sdhci_keembay_sdio_pdata = {
1166 .ops = &sdhci_arasan_ops,
1167 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
1168 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1169 SDHCI_QUIRK_NO_LED |
1170 SDHCI_QUIRK_32BIT_DMA_ADDR |
1171 SDHCI_QUIRK_32BIT_DMA_SIZE |
1172 SDHCI_QUIRK_32BIT_ADMA_SIZE,
1173 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1174 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1175 SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1176 SDHCI_QUIRK2_BROKEN_64_BIT_DMA,
1177};
1178
1179static struct sdhci_arasan_of_data sdhci_arasan_rk3399_data = {
1180 .soc_ctl_map = &rk3399_soc_ctl_map,
1181 .pdata = &sdhci_arasan_cqe_pdata,
1182 .clk_ops = &arasan_clk_ops,
1183};
1184
1185static struct sdhci_arasan_of_data intel_lgm_emmc_data = {
1186 .soc_ctl_map = &intel_lgm_emmc_soc_ctl_map,
1187 .pdata = &sdhci_arasan_cqe_pdata,
1188 .clk_ops = &arasan_clk_ops,
1189};
1190
1191static struct sdhci_arasan_of_data intel_lgm_sdxc_data = {
1192 .soc_ctl_map = &intel_lgm_sdxc_soc_ctl_map,
1193 .pdata = &sdhci_arasan_cqe_pdata,
1194 .clk_ops = &arasan_clk_ops,
1195};
1196
1197static const struct sdhci_pltfm_data sdhci_arasan_zynqmp_pdata = {
1198 .ops = &sdhci_arasan_ops,
1199 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1200 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN |
1201 SDHCI_QUIRK2_STOP_WITH_TC,
1202};
1203
1204static const struct sdhci_arasan_clk_ops zynqmp_clk_ops = {
1205 .sdcardclk_ops = &zynqmp_sdcardclk_ops,
1206 .sampleclk_ops = &zynqmp_sampleclk_ops,
1207};
1208
1209static struct sdhci_arasan_of_data sdhci_arasan_zynqmp_data = {
1210 .pdata = &sdhci_arasan_zynqmp_pdata,
1211 .clk_ops = &zynqmp_clk_ops,
1212};
1213
1214static const struct sdhci_arasan_clk_ops versal_clk_ops = {
1215 .sdcardclk_ops = &versal_sdcardclk_ops,
1216 .sampleclk_ops = &versal_sampleclk_ops,
1217};
1218
1219static struct sdhci_arasan_of_data sdhci_arasan_versal_data = {
1220 .pdata = &sdhci_arasan_zynqmp_pdata,
1221 .clk_ops = &versal_clk_ops,
1222};
1223
1224static struct sdhci_arasan_of_data intel_keembay_emmc_data = {
1225 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1226 .pdata = &sdhci_keembay_emmc_pdata,
1227 .clk_ops = &arasan_clk_ops,
1228};
1229
1230static struct sdhci_arasan_of_data intel_keembay_sd_data = {
1231 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1232 .pdata = &sdhci_keembay_sd_pdata,
1233 .clk_ops = &arasan_clk_ops,
1234};
1235
1236static struct sdhci_arasan_of_data intel_keembay_sdio_data = {
1237 .soc_ctl_map = &intel_keembay_soc_ctl_map,
1238 .pdata = &sdhci_keembay_sdio_pdata,
1239 .clk_ops = &arasan_clk_ops,
1240};
1241
1242static const struct of_device_id sdhci_arasan_of_match[] = {
1243
1244 {
1245 .compatible = "rockchip,rk3399-sdhci-5.1",
1246 .data = &sdhci_arasan_rk3399_data,
1247 },
1248 {
1249 .compatible = "intel,lgm-sdhci-5.1-emmc",
1250 .data = &intel_lgm_emmc_data,
1251 },
1252 {
1253 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1254 .data = &intel_lgm_sdxc_data,
1255 },
1256 {
1257 .compatible = "intel,keembay-sdhci-5.1-emmc",
1258 .data = &intel_keembay_emmc_data,
1259 },
1260 {
1261 .compatible = "intel,keembay-sdhci-5.1-sd",
1262 .data = &intel_keembay_sd_data,
1263 },
1264 {
1265 .compatible = "intel,keembay-sdhci-5.1-sdio",
1266 .data = &intel_keembay_sdio_data,
1267 },
1268
1269 {
1270 .compatible = "arasan,sdhci-8.9a",
1271 .data = &sdhci_arasan_generic_data,
1272 },
1273 {
1274 .compatible = "arasan,sdhci-5.1",
1275 .data = &sdhci_arasan_generic_data,
1276 },
1277 {
1278 .compatible = "arasan,sdhci-4.9a",
1279 .data = &sdhci_arasan_generic_data,
1280 },
1281 {
1282 .compatible = "xlnx,zynqmp-8.9a",
1283 .data = &sdhci_arasan_zynqmp_data,
1284 },
1285 {
1286 .compatible = "xlnx,versal-8.9a",
1287 .data = &sdhci_arasan_versal_data,
1288 },
1289 { }
1290};
1291MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match);
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306static int
1307sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
1308 struct clk *clk_xin,
1309 struct device *dev)
1310{
1311 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1312 struct device_node *np = dev->of_node;
1313 struct clk_init_data sdcardclk_init;
1314 const char *parent_clk_name;
1315 int ret;
1316
1317 ret = of_property_read_string_index(np, "clock-output-names", 0,
1318 &sdcardclk_init.name);
1319 if (ret) {
1320 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1321 return ret;
1322 }
1323
1324 parent_clk_name = __clk_get_name(clk_xin);
1325 sdcardclk_init.parent_names = &parent_clk_name;
1326 sdcardclk_init.num_parents = 1;
1327 sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
1328 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops;
1329
1330 clk_data->sdcardclk_hw.init = &sdcardclk_init;
1331 clk_data->sdcardclk =
1332 devm_clk_register(dev, &clk_data->sdcardclk_hw);
1333 if (IS_ERR(clk_data->sdcardclk))
1334 return PTR_ERR(clk_data->sdcardclk);
1335 clk_data->sdcardclk_hw.init = NULL;
1336
1337 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1338 clk_data->sdcardclk);
1339 if (ret)
1340 dev_err(dev, "Failed to add sdcard clock provider\n");
1341
1342 return ret;
1343}
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358static int
1359sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
1360 struct clk *clk_xin,
1361 struct device *dev)
1362{
1363 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
1364 struct device_node *np = dev->of_node;
1365 struct clk_init_data sampleclk_init;
1366 const char *parent_clk_name;
1367 int ret;
1368
1369 ret = of_property_read_string_index(np, "clock-output-names", 1,
1370 &sampleclk_init.name);
1371 if (ret) {
1372 dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
1373 return ret;
1374 }
1375
1376 parent_clk_name = __clk_get_name(clk_xin);
1377 sampleclk_init.parent_names = &parent_clk_name;
1378 sampleclk_init.num_parents = 1;
1379 sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
1380 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops;
1381
1382 clk_data->sampleclk_hw.init = &sampleclk_init;
1383 clk_data->sampleclk =
1384 devm_clk_register(dev, &clk_data->sampleclk_hw);
1385 if (IS_ERR(clk_data->sampleclk))
1386 return PTR_ERR(clk_data->sampleclk);
1387 clk_data->sampleclk_hw.init = NULL;
1388
1389 ret = of_clk_add_provider(np, of_clk_src_simple_get,
1390 clk_data->sampleclk);
1391 if (ret)
1392 dev_err(dev, "Failed to add sample clock provider\n");
1393
1394 return ret;
1395}
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405static void sdhci_arasan_unregister_sdclk(struct device *dev)
1406{
1407 struct device_node *np = dev->of_node;
1408
1409 if (!of_find_property(np, "#clock-cells", NULL))
1410 return;
1411
1412 of_clk_del_provider(dev->of_node);
1413}
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value)
1429{
1430 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1431 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1432 const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
1433
1434
1435 soc_ctl_map = sdhci_arasan->soc_ctl_map;
1436 if (!soc_ctl_map)
1437 return;
1438
1439
1440 if (!sdhci_arasan->soc_ctl_base) {
1441 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n",
1442 mmc_hostname(host->mmc));
1443 return;
1444 }
1445
1446 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value);
1447}
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
1471 struct clk *clk_xin,
1472 struct device *dev)
1473{
1474 struct device_node *np = dev->of_node;
1475 u32 num_clks = 0;
1476 int ret;
1477
1478
1479 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
1480 return 0;
1481
1482 ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
1483 if (ret)
1484 return ret;
1485
1486 if (num_clks) {
1487 ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
1488 dev);
1489 if (ret) {
1490 sdhci_arasan_unregister_sdclk(dev);
1491 return ret;
1492 }
1493 }
1494
1495 return 0;
1496}
1497
1498static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
1499{
1500 struct sdhci_host *host = sdhci_arasan->host;
1501 struct cqhci_host *cq_host;
1502 bool dma64;
1503 int ret;
1504
1505 if (!sdhci_arasan->has_cqe)
1506 return sdhci_add_host(host);
1507
1508 ret = sdhci_setup_host(host);
1509 if (ret)
1510 return ret;
1511
1512 cq_host = devm_kzalloc(host->mmc->parent,
1513 sizeof(*cq_host), GFP_KERNEL);
1514 if (!cq_host) {
1515 ret = -ENOMEM;
1516 goto cleanup;
1517 }
1518
1519 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
1520 cq_host->ops = &sdhci_arasan_cqhci_ops;
1521
1522 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1523 if (dma64)
1524 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1525
1526 ret = cqhci_init(cq_host, host->mmc, dma64);
1527 if (ret)
1528 goto cleanup;
1529
1530 ret = __sdhci_add_host(host);
1531 if (ret)
1532 goto cleanup;
1533
1534 return 0;
1535
1536cleanup:
1537 sdhci_cleanup_host(host);
1538 return ret;
1539}
1540
1541static int sdhci_arasan_probe(struct platform_device *pdev)
1542{
1543 int ret;
1544 struct device_node *node;
1545 struct clk *clk_xin;
1546 struct sdhci_host *host;
1547 struct sdhci_pltfm_host *pltfm_host;
1548 struct device *dev = &pdev->dev;
1549 struct device_node *np = dev->of_node;
1550 struct sdhci_arasan_data *sdhci_arasan;
1551 const struct sdhci_arasan_of_data *data;
1552
1553 data = of_device_get_match_data(dev);
1554 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan));
1555
1556 if (IS_ERR(host))
1557 return PTR_ERR(host);
1558
1559 pltfm_host = sdhci_priv(host);
1560 sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1561 sdhci_arasan->host = host;
1562
1563 sdhci_arasan->soc_ctl_map = data->soc_ctl_map;
1564 sdhci_arasan->clk_ops = data->clk_ops;
1565
1566 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0);
1567 if (node) {
1568 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node);
1569 of_node_put(node);
1570
1571 if (IS_ERR(sdhci_arasan->soc_ctl_base)) {
1572 ret = dev_err_probe(dev,
1573 PTR_ERR(sdhci_arasan->soc_ctl_base),
1574 "Can't get syscon\n");
1575 goto err_pltfm_free;
1576 }
1577 }
1578
1579 sdhci_get_of_property(pdev);
1580
1581 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb");
1582 if (IS_ERR(sdhci_arasan->clk_ahb)) {
1583 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb),
1584 "clk_ahb clock not found.\n");
1585 goto err_pltfm_free;
1586 }
1587
1588 clk_xin = devm_clk_get(dev, "clk_xin");
1589 if (IS_ERR(clk_xin)) {
1590 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n");
1591 goto err_pltfm_free;
1592 }
1593
1594 ret = clk_prepare_enable(sdhci_arasan->clk_ahb);
1595 if (ret) {
1596 dev_err(dev, "Unable to enable AHB clock.\n");
1597 goto err_pltfm_free;
1598 }
1599
1600
1601 if (pltfm_host->clock &&
1602 pltfm_host->clock != clk_get_rate(clk_xin)) {
1603 ret = clk_set_rate(clk_xin, pltfm_host->clock);
1604 if (ret) {
1605 dev_err(&pdev->dev, "Failed to set SD clock rate\n");
1606 goto clk_dis_ahb;
1607 }
1608 }
1609
1610 ret = clk_prepare_enable(clk_xin);
1611 if (ret) {
1612 dev_err(dev, "Unable to enable SD clock.\n");
1613 goto clk_dis_ahb;
1614 }
1615
1616 if (of_property_read_bool(np, "xlnx,fails-without-test-cd"))
1617 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST;
1618
1619 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken"))
1620 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE;
1621
1622 pltfm_host->clk = clk_xin;
1623
1624 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1"))
1625 sdhci_arasan_update_clockmultiplier(host, 0x0);
1626
1627 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") ||
1628 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") ||
1629 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) {
1630 sdhci_arasan_update_clockmultiplier(host, 0x0);
1631 sdhci_arasan_update_support64b(host, 0x0);
1632
1633 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1634 }
1635
1636 sdhci_arasan_update_baseclkfreq(host);
1637
1638 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, dev);
1639 if (ret)
1640 goto clk_disable_all;
1641
1642 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) {
1643 host->mmc_host_ops.execute_tuning =
1644 arasan_zynqmp_execute_tuning;
1645
1646 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN;
1647 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
1648 }
1649
1650 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data);
1651
1652 ret = mmc_of_parse(host->mmc);
1653 if (ret) {
1654 ret = dev_err_probe(dev, ret, "parsing dt failed.\n");
1655 goto unreg_clk;
1656 }
1657
1658 sdhci_arasan->phy = ERR_PTR(-ENODEV);
1659 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) {
1660 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan");
1661 if (IS_ERR(sdhci_arasan->phy)) {
1662 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy),
1663 "No phy for arasan,sdhci-5.1.\n");
1664 goto unreg_clk;
1665 }
1666
1667 ret = phy_init(sdhci_arasan->phy);
1668 if (ret < 0) {
1669 dev_err(dev, "phy_init err.\n");
1670 goto unreg_clk;
1671 }
1672
1673 host->mmc_host_ops.hs400_enhanced_strobe =
1674 sdhci_arasan_hs400_enhanced_strobe;
1675 host->mmc_host_ops.start_signal_voltage_switch =
1676 sdhci_arasan_voltage_switch;
1677 sdhci_arasan->has_cqe = true;
1678 host->mmc->caps2 |= MMC_CAP2_CQE;
1679
1680 if (!of_property_read_bool(np, "disable-cqe-dcmd"))
1681 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
1682 }
1683
1684 ret = sdhci_arasan_add_host(sdhci_arasan);
1685 if (ret)
1686 goto err_add_host;
1687
1688 return 0;
1689
1690err_add_host:
1691 if (!IS_ERR(sdhci_arasan->phy))
1692 phy_exit(sdhci_arasan->phy);
1693unreg_clk:
1694 sdhci_arasan_unregister_sdclk(dev);
1695clk_disable_all:
1696 clk_disable_unprepare(clk_xin);
1697clk_dis_ahb:
1698 clk_disable_unprepare(sdhci_arasan->clk_ahb);
1699err_pltfm_free:
1700 sdhci_pltfm_free(pdev);
1701 return ret;
1702}
1703
1704static int sdhci_arasan_remove(struct platform_device *pdev)
1705{
1706 int ret;
1707 struct sdhci_host *host = platform_get_drvdata(pdev);
1708 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1709 struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
1710 struct clk *clk_ahb = sdhci_arasan->clk_ahb;
1711
1712 if (!IS_ERR(sdhci_arasan->phy)) {
1713 if (sdhci_arasan->is_phy_on)
1714 phy_power_off(sdhci_arasan->phy);
1715 phy_exit(sdhci_arasan->phy);
1716 }
1717
1718 sdhci_arasan_unregister_sdclk(&pdev->dev);
1719
1720 ret = sdhci_pltfm_unregister(pdev);
1721
1722 clk_disable_unprepare(clk_ahb);
1723
1724 return ret;
1725}
1726
1727static struct platform_driver sdhci_arasan_driver = {
1728 .driver = {
1729 .name = "sdhci-arasan",
1730 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1731 .of_match_table = sdhci_arasan_of_match,
1732 .pm = &sdhci_arasan_dev_pm_ops,
1733 },
1734 .probe = sdhci_arasan_probe,
1735 .remove = sdhci_arasan_remove,
1736};
1737
1738module_platform_driver(sdhci_arasan_driver);
1739
1740MODULE_DESCRIPTION("Driver for the Arasan SDHCI Controller");
1741MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
1742MODULE_LICENSE("GPL");
1743