1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48#include <linux/clk.h>
49#include <linux/dma-mapping.h>
50#include <linux/dmaengine.h>
51#include <linux/genalloc.h>
52#include <linux/gpio/consumer.h>
53#include <linux/interrupt.h>
54#include <linux/mfd/syscon.h>
55#include <linux/mfd/syscon/atmel-matrix.h>
56#include <linux/mfd/syscon/atmel-smc.h>
57#include <linux/module.h>
58#include <linux/mtd/rawnand.h>
59#include <linux/of_address.h>
60#include <linux/of_irq.h>
61#include <linux/of_platform.h>
62#include <linux/iopoll.h>
63#include <linux/platform_device.h>
64#include <linux/regmap.h>
65#include <soc/at91/atmel-sfr.h>
66
67#include "pmecc.h"
68
69#define ATMEL_HSMC_NFC_CFG 0x0
70#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
71#define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
72#define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
73#define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
74#define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
75#define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
76#define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
77#define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
78#define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
79#define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
80
81#define ATMEL_HSMC_NFC_CTRL 0x4
82#define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
83#define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
84
85#define ATMEL_HSMC_NFC_SR 0x8
86#define ATMEL_HSMC_NFC_IER 0xc
87#define ATMEL_HSMC_NFC_IDR 0x10
88#define ATMEL_HSMC_NFC_IMR 0x14
89#define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
90#define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
91#define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
92#define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
93#define ATMEL_HSMC_NFC_SR_WR BIT(11)
94#define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
95#define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
96#define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
97#define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
98#define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
99#define ATMEL_HSMC_NFC_SR_AWB BIT(22)
100#define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
101#define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
102 ATMEL_HSMC_NFC_SR_UNDEF | \
103 ATMEL_HSMC_NFC_SR_AWB | \
104 ATMEL_HSMC_NFC_SR_NFCASE)
105#define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
106
107#define ATMEL_HSMC_NFC_ADDR 0x18
108#define ATMEL_HSMC_NFC_BANK 0x1c
109
110#define ATMEL_NFC_MAX_RB_ID 7
111
112#define ATMEL_NFC_SRAM_SIZE 0x2400
113
114#define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
115#define ATMEL_NFC_VCMD2 BIT(18)
116#define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
117#define ATMEL_NFC_CSID(cs) ((cs) << 22)
118#define ATMEL_NFC_DATAEN BIT(25)
119#define ATMEL_NFC_NFCWR BIT(26)
120
121#define ATMEL_NFC_MAX_ADDR_CYCLES 5
122
123#define ATMEL_NAND_ALE_OFFSET BIT(21)
124#define ATMEL_NAND_CLE_OFFSET BIT(22)
125
126#define DEFAULT_TIMEOUT_MS 1000
127#define MIN_DMA_LEN 128
128
129static bool atmel_nand_avoid_dma __read_mostly;
130
131MODULE_PARM_DESC(avoiddma, "Avoid using DMA");
132module_param_named(avoiddma, atmel_nand_avoid_dma, bool, 0400);
133
134enum atmel_nand_rb_type {
135 ATMEL_NAND_NO_RB,
136 ATMEL_NAND_NATIVE_RB,
137 ATMEL_NAND_GPIO_RB,
138};
139
140struct atmel_nand_rb {
141 enum atmel_nand_rb_type type;
142 union {
143 struct gpio_desc *gpio;
144 int id;
145 };
146};
147
148struct atmel_nand_cs {
149 int id;
150 struct atmel_nand_rb rb;
151 struct gpio_desc *csgpio;
152 struct {
153 void __iomem *virt;
154 dma_addr_t dma;
155 } io;
156
157 struct atmel_smc_cs_conf smcconf;
158};
159
160struct atmel_nand {
161 struct list_head node;
162 struct device *dev;
163 struct nand_chip base;
164 struct atmel_nand_cs *activecs;
165 struct atmel_pmecc_user *pmecc;
166 struct gpio_desc *cdgpio;
167 int numcs;
168 struct atmel_nand_cs cs[];
169};
170
171static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
172{
173 return container_of(chip, struct atmel_nand, base);
174}
175
176enum atmel_nfc_data_xfer {
177 ATMEL_NFC_NO_DATA,
178 ATMEL_NFC_READ_DATA,
179 ATMEL_NFC_WRITE_DATA,
180};
181
182struct atmel_nfc_op {
183 u8 cs;
184 u8 ncmds;
185 u8 cmds[2];
186 u8 naddrs;
187 u8 addrs[5];
188 enum atmel_nfc_data_xfer data;
189 u32 wait;
190 u32 errors;
191};
192
193struct atmel_nand_controller;
194struct atmel_nand_controller_caps;
195
196struct atmel_nand_controller_ops {
197 int (*probe)(struct platform_device *pdev,
198 const struct atmel_nand_controller_caps *caps);
199 int (*remove)(struct atmel_nand_controller *nc);
200 void (*nand_init)(struct atmel_nand_controller *nc,
201 struct atmel_nand *nand);
202 int (*ecc_init)(struct nand_chip *chip);
203 int (*setup_interface)(struct atmel_nand *nand, int csline,
204 const struct nand_interface_config *conf);
205 int (*exec_op)(struct atmel_nand *nand,
206 const struct nand_operation *op, bool check_only);
207};
208
209struct atmel_nand_controller_caps {
210 bool has_dma;
211 bool legacy_of_bindings;
212 u32 ale_offs;
213 u32 cle_offs;
214 const char *ebi_csa_regmap_name;
215 const struct atmel_nand_controller_ops *ops;
216};
217
218struct atmel_nand_controller {
219 struct nand_controller base;
220 const struct atmel_nand_controller_caps *caps;
221 struct device *dev;
222 struct regmap *smc;
223 struct dma_chan *dmac;
224 struct atmel_pmecc *pmecc;
225 struct list_head chips;
226 struct clk *mck;
227};
228
229static inline struct atmel_nand_controller *
230to_nand_controller(struct nand_controller *ctl)
231{
232 return container_of(ctl, struct atmel_nand_controller, base);
233}
234
235struct atmel_smc_nand_ebi_csa_cfg {
236 u32 offs;
237 u32 nfd0_on_d16;
238};
239
240struct atmel_smc_nand_controller {
241 struct atmel_nand_controller base;
242 struct regmap *ebi_csa_regmap;
243 struct atmel_smc_nand_ebi_csa_cfg *ebi_csa;
244};
245
246static inline struct atmel_smc_nand_controller *
247to_smc_nand_controller(struct nand_controller *ctl)
248{
249 return container_of(to_nand_controller(ctl),
250 struct atmel_smc_nand_controller, base);
251}
252
253struct atmel_hsmc_nand_controller {
254 struct atmel_nand_controller base;
255 struct {
256 struct gen_pool *pool;
257 void __iomem *virt;
258 dma_addr_t dma;
259 } sram;
260 const struct atmel_hsmc_reg_layout *hsmc_layout;
261 struct regmap *io;
262 struct atmel_nfc_op op;
263 struct completion complete;
264 u32 cfg;
265 int irq;
266
267
268 struct clk *clk;
269};
270
271static inline struct atmel_hsmc_nand_controller *
272to_hsmc_nand_controller(struct nand_controller *ctl)
273{
274 return container_of(to_nand_controller(ctl),
275 struct atmel_hsmc_nand_controller, base);
276}
277
278static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
279{
280 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
281 op->wait ^= status & op->wait;
282
283 return !op->wait || op->errors;
284}
285
286static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
287{
288 struct atmel_hsmc_nand_controller *nc = data;
289 u32 sr, rcvd;
290 bool done;
291
292 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
293
294 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
295 done = atmel_nfc_op_done(&nc->op, sr);
296
297 if (rcvd)
298 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
299
300 if (done)
301 complete(&nc->complete);
302
303 return rcvd ? IRQ_HANDLED : IRQ_NONE;
304}
305
306static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
307 unsigned int timeout_ms)
308{
309 int ret;
310
311 if (!timeout_ms)
312 timeout_ms = DEFAULT_TIMEOUT_MS;
313
314 if (poll) {
315 u32 status;
316
317 ret = regmap_read_poll_timeout(nc->base.smc,
318 ATMEL_HSMC_NFC_SR, status,
319 atmel_nfc_op_done(&nc->op,
320 status),
321 0, timeout_ms * 1000);
322 } else {
323 init_completion(&nc->complete);
324 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
325 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
326 ret = wait_for_completion_timeout(&nc->complete,
327 msecs_to_jiffies(timeout_ms));
328 if (!ret)
329 ret = -ETIMEDOUT;
330 else
331 ret = 0;
332
333 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
334 }
335
336 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
338 ret = -ETIMEDOUT;
339 }
340
341 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
342 dev_err(nc->base.dev, "Access to an undefined area\n");
343 ret = -EIO;
344 }
345
346 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
347 dev_err(nc->base.dev, "Access while busy\n");
348 ret = -EIO;
349 }
350
351 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
352 dev_err(nc->base.dev, "Wrong access size\n");
353 ret = -EIO;
354 }
355
356 return ret;
357}
358
359static void atmel_nand_dma_transfer_finished(void *data)
360{
361 struct completion *finished = data;
362
363 complete(finished);
364}
365
366static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
367 void *buf, dma_addr_t dev_dma, size_t len,
368 enum dma_data_direction dir)
369{
370 DECLARE_COMPLETION_ONSTACK(finished);
371 dma_addr_t src_dma, dst_dma, buf_dma;
372 struct dma_async_tx_descriptor *tx;
373 dma_cookie_t cookie;
374
375 buf_dma = dma_map_single(nc->dev, buf, len, dir);
376 if (dma_mapping_error(nc->dev, dev_dma)) {
377 dev_err(nc->dev,
378 "Failed to prepare a buffer for DMA access\n");
379 goto err;
380 }
381
382 if (dir == DMA_FROM_DEVICE) {
383 src_dma = dev_dma;
384 dst_dma = buf_dma;
385 } else {
386 src_dma = buf_dma;
387 dst_dma = dev_dma;
388 }
389
390 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
391 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
392 if (!tx) {
393 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
394 goto err_unmap;
395 }
396
397 tx->callback = atmel_nand_dma_transfer_finished;
398 tx->callback_param = &finished;
399
400 cookie = dmaengine_submit(tx);
401 if (dma_submit_error(cookie)) {
402 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
403 goto err_unmap;
404 }
405
406 dma_async_issue_pending(nc->dmac);
407 wait_for_completion(&finished);
408
409 return 0;
410
411err_unmap:
412 dma_unmap_single(nc->dev, buf_dma, len, dir);
413
414err:
415 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
416
417 return -EIO;
418}
419
420static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
421{
422 u8 *addrs = nc->op.addrs;
423 unsigned int op = 0;
424 u32 addr, val;
425 int i, ret;
426
427 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
428
429 for (i = 0; i < nc->op.ncmds; i++)
430 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
431
432 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
433 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
434
435 op |= ATMEL_NFC_CSID(nc->op.cs) |
436 ATMEL_NFC_ACYCLE(nc->op.naddrs);
437
438 if (nc->op.ncmds > 1)
439 op |= ATMEL_NFC_VCMD2;
440
441 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
442 (addrs[3] << 24);
443
444 if (nc->op.data != ATMEL_NFC_NO_DATA) {
445 op |= ATMEL_NFC_DATAEN;
446 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
447
448 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
449 op |= ATMEL_NFC_NFCWR;
450 }
451
452
453 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
454
455
456 regmap_write(nc->io, op, addr);
457
458 ret = atmel_nfc_wait(nc, poll, 0);
459 if (ret)
460 dev_err(nc->base.dev,
461 "Failed to send NAND command (err = %d)!",
462 ret);
463
464
465 memset(&nc->op, 0, sizeof(nc->op));
466
467 return ret;
468}
469
470static void atmel_nand_data_in(struct atmel_nand *nand, void *buf,
471 unsigned int len, bool force_8bit)
472{
473 struct atmel_nand_controller *nc;
474
475 nc = to_nand_controller(nand->base.controller);
476
477
478
479
480
481
482 if (nc->dmac && virt_addr_valid(buf) &&
483 len >= MIN_DMA_LEN && !force_8bit &&
484 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
485 DMA_FROM_DEVICE))
486 return;
487
488 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
489 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
490 else
491 ioread8_rep(nand->activecs->io.virt, buf, len);
492}
493
494static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf,
495 unsigned int len, bool force_8bit)
496{
497 struct atmel_nand_controller *nc;
498
499 nc = to_nand_controller(nand->base.controller);
500
501
502
503
504
505
506 if (nc->dmac && virt_addr_valid(buf) &&
507 len >= MIN_DMA_LEN && !force_8bit &&
508 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
509 len, DMA_TO_DEVICE))
510 return;
511
512 if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
513 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
514 else
515 iowrite8_rep(nand->activecs->io.virt, buf, len);
516}
517
518static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms)
519{
520 if (nand->activecs->rb.type == ATMEL_NAND_NO_RB)
521 return nand_soft_waitrdy(&nand->base, timeout_ms);
522
523 return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio,
524 timeout_ms);
525}
526
527static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand,
528 unsigned int timeout_ms)
529{
530 struct atmel_hsmc_nand_controller *nc;
531 u32 status, mask;
532
533 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
534 return atmel_nand_waitrdy(nand, timeout_ms);
535
536 nc = to_hsmc_nand_controller(nand->base.controller);
537 mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
538 return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,
539 status, status & mask,
540 10, timeout_ms * 1000);
541}
542
543static void atmel_nand_select_target(struct atmel_nand *nand,
544 unsigned int cs)
545{
546 nand->activecs = &nand->cs[cs];
547}
548
549static void atmel_hsmc_nand_select_target(struct atmel_nand *nand,
550 unsigned int cs)
551{
552 struct mtd_info *mtd = nand_to_mtd(&nand->base);
553 struct atmel_hsmc_nand_controller *nc;
554 u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
555 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
556 ATMEL_HSMC_NFC_CFG_RSPARE;
557
558 nand->activecs = &nand->cs[cs];
559 nc = to_hsmc_nand_controller(nand->base.controller);
560 if (nc->cfg == cfg)
561 return;
562
563 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
564 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
565 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
566 ATMEL_HSMC_NFC_CFG_RSPARE |
567 ATMEL_HSMC_NFC_CFG_WSPARE,
568 cfg);
569 nc->cfg = cfg;
570}
571
572static int atmel_smc_nand_exec_instr(struct atmel_nand *nand,
573 const struct nand_op_instr *instr)
574{
575 struct atmel_nand_controller *nc;
576 unsigned int i;
577
578 nc = to_nand_controller(nand->base.controller);
579 switch (instr->type) {
580 case NAND_OP_CMD_INSTR:
581 writeb(instr->ctx.cmd.opcode,
582 nand->activecs->io.virt + nc->caps->cle_offs);
583 return 0;
584 case NAND_OP_ADDR_INSTR:
585 for (i = 0; i < instr->ctx.addr.naddrs; i++)
586 writeb(instr->ctx.addr.addrs[i],
587 nand->activecs->io.virt + nc->caps->ale_offs);
588 return 0;
589 case NAND_OP_DATA_IN_INSTR:
590 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
591 instr->ctx.data.len,
592 instr->ctx.data.force_8bit);
593 return 0;
594 case NAND_OP_DATA_OUT_INSTR:
595 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
596 instr->ctx.data.len,
597 instr->ctx.data.force_8bit);
598 return 0;
599 case NAND_OP_WAITRDY_INSTR:
600 return atmel_nand_waitrdy(nand,
601 instr->ctx.waitrdy.timeout_ms);
602 default:
603 break;
604 }
605
606 return -EINVAL;
607}
608
609static int atmel_smc_nand_exec_op(struct atmel_nand *nand,
610 const struct nand_operation *op,
611 bool check_only)
612{
613 unsigned int i;
614 int ret = 0;
615
616 if (check_only)
617 return 0;
618
619 atmel_nand_select_target(nand, op->cs);
620 gpiod_set_value(nand->activecs->csgpio, 0);
621 for (i = 0; i < op->ninstrs; i++) {
622 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]);
623 if (ret)
624 break;
625 }
626 gpiod_set_value(nand->activecs->csgpio, 1);
627
628 return ret;
629}
630
631static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip,
632 const struct nand_subop *subop)
633{
634 struct atmel_nand *nand = to_atmel_nand(chip);
635 struct atmel_hsmc_nand_controller *nc;
636 unsigned int i, j;
637
638 nc = to_hsmc_nand_controller(chip->controller);
639
640 nc->op.cs = nand->activecs->id;
641 for (i = 0; i < subop->ninstrs; i++) {
642 const struct nand_op_instr *instr = &subop->instrs[i];
643
644 if (instr->type == NAND_OP_CMD_INSTR) {
645 nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;
646 continue;
647 }
648
649 for (j = nand_subop_get_addr_start_off(subop, i);
650 j < nand_subop_get_num_addr_cyc(subop, i); j++) {
651 nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];
652 nc->op.naddrs++;
653 }
654 }
655
656 return atmel_nfc_exec_op(nc, true);
657}
658
659static int atmel_hsmc_exec_rw(struct nand_chip *chip,
660 const struct nand_subop *subop)
661{
662 const struct nand_op_instr *instr = subop->instrs;
663 struct atmel_nand *nand = to_atmel_nand(chip);
664
665 if (instr->type == NAND_OP_DATA_IN_INSTR)
666 atmel_nand_data_in(nand, instr->ctx.data.buf.in,
667 instr->ctx.data.len,
668 instr->ctx.data.force_8bit);
669 else
670 atmel_nand_data_out(nand, instr->ctx.data.buf.out,
671 instr->ctx.data.len,
672 instr->ctx.data.force_8bit);
673
674 return 0;
675}
676
677static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip,
678 const struct nand_subop *subop)
679{
680 const struct nand_op_instr *instr = subop->instrs;
681 struct atmel_nand *nand = to_atmel_nand(chip);
682
683 return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms);
684}
685
686static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER(
687 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr,
688 NAND_OP_PARSER_PAT_CMD_ELEM(true),
689 NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
690 NAND_OP_PARSER_PAT_CMD_ELEM(true)),
691 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
692 NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)),
693 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
694 NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)),
695 NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy,
696 NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
697);
698
699static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand,
700 const struct nand_operation *op,
701 bool check_only)
702{
703 int ret;
704
705 if (check_only)
706 return nand_op_parser_exec_op(&nand->base,
707 &atmel_hsmc_op_parser, op, true);
708
709 atmel_hsmc_nand_select_target(nand, op->cs);
710 ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op,
711 false);
712
713 return ret;
714}
715
716static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
717 bool oob_required)
718{
719 struct mtd_info *mtd = nand_to_mtd(chip);
720 struct atmel_hsmc_nand_controller *nc;
721 int ret = -EIO;
722
723 nc = to_hsmc_nand_controller(chip->controller);
724
725 if (nc->base.dmac)
726 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
727 nc->sram.dma, mtd->writesize,
728 DMA_TO_DEVICE);
729
730
731 if (ret)
732 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
733
734 if (oob_required)
735 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
736 mtd->oobsize);
737}
738
739static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
740 bool oob_required)
741{
742 struct mtd_info *mtd = nand_to_mtd(chip);
743 struct atmel_hsmc_nand_controller *nc;
744 int ret = -EIO;
745
746 nc = to_hsmc_nand_controller(chip->controller);
747
748 if (nc->base.dmac)
749 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
750 mtd->writesize, DMA_FROM_DEVICE);
751
752
753 if (ret)
754 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
755
756 if (oob_required)
757 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
758 mtd->oobsize);
759}
760
761static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
762{
763 struct mtd_info *mtd = nand_to_mtd(chip);
764 struct atmel_hsmc_nand_controller *nc;
765
766 nc = to_hsmc_nand_controller(chip->controller);
767
768 if (column >= 0) {
769 nc->op.addrs[nc->op.naddrs++] = column;
770
771
772
773
774 if (mtd->writesize > 512)
775 nc->op.addrs[nc->op.naddrs++] = column >> 8;
776 }
777
778 if (page >= 0) {
779 nc->op.addrs[nc->op.naddrs++] = page;
780 nc->op.addrs[nc->op.naddrs++] = page >> 8;
781
782 if (chip->options & NAND_ROW_ADDR_3)
783 nc->op.addrs[nc->op.naddrs++] = page >> 16;
784 }
785}
786
787static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
788{
789 struct atmel_nand *nand = to_atmel_nand(chip);
790 struct atmel_nand_controller *nc;
791 int ret;
792
793 nc = to_nand_controller(chip->controller);
794
795 if (raw)
796 return 0;
797
798 ret = atmel_pmecc_enable(nand->pmecc, op);
799 if (ret)
800 dev_err(nc->dev,
801 "Failed to enable ECC engine (err = %d)\n", ret);
802
803 return ret;
804}
805
806static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
807{
808 struct atmel_nand *nand = to_atmel_nand(chip);
809
810 if (!raw)
811 atmel_pmecc_disable(nand->pmecc);
812}
813
814static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
815{
816 struct atmel_nand *nand = to_atmel_nand(chip);
817 struct mtd_info *mtd = nand_to_mtd(chip);
818 struct atmel_nand_controller *nc;
819 struct mtd_oob_region oobregion;
820 void *eccbuf;
821 int ret, i;
822
823 nc = to_nand_controller(chip->controller);
824
825 if (raw)
826 return 0;
827
828 ret = atmel_pmecc_wait_rdy(nand->pmecc);
829 if (ret) {
830 dev_err(nc->dev,
831 "Failed to transfer NAND page data (err = %d)\n",
832 ret);
833 return ret;
834 }
835
836 mtd_ooblayout_ecc(mtd, 0, &oobregion);
837 eccbuf = chip->oob_poi + oobregion.offset;
838
839 for (i = 0; i < chip->ecc.steps; i++) {
840 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
841 eccbuf);
842 eccbuf += chip->ecc.bytes;
843 }
844
845 return 0;
846}
847
848static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
849 bool raw)
850{
851 struct atmel_nand *nand = to_atmel_nand(chip);
852 struct mtd_info *mtd = nand_to_mtd(chip);
853 struct atmel_nand_controller *nc;
854 struct mtd_oob_region oobregion;
855 int ret, i, max_bitflips = 0;
856 void *databuf, *eccbuf;
857
858 nc = to_nand_controller(chip->controller);
859
860 if (raw)
861 return 0;
862
863 ret = atmel_pmecc_wait_rdy(nand->pmecc);
864 if (ret) {
865 dev_err(nc->dev,
866 "Failed to read NAND page data (err = %d)\n",
867 ret);
868 return ret;
869 }
870
871 mtd_ooblayout_ecc(mtd, 0, &oobregion);
872 eccbuf = chip->oob_poi + oobregion.offset;
873 databuf = buf;
874
875 for (i = 0; i < chip->ecc.steps; i++) {
876 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
877 eccbuf);
878 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
879 ret = nand_check_erased_ecc_chunk(databuf,
880 chip->ecc.size,
881 eccbuf,
882 chip->ecc.bytes,
883 NULL, 0,
884 chip->ecc.strength);
885
886 if (ret >= 0) {
887 mtd->ecc_stats.corrected += ret;
888 max_bitflips = max(ret, max_bitflips);
889 } else {
890 mtd->ecc_stats.failed++;
891 }
892
893 databuf += chip->ecc.size;
894 eccbuf += chip->ecc.bytes;
895 }
896
897 return max_bitflips;
898}
899
900static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
901 bool oob_required, int page, bool raw)
902{
903 struct mtd_info *mtd = nand_to_mtd(chip);
904 struct atmel_nand *nand = to_atmel_nand(chip);
905 int ret;
906
907 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
908
909 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
910 if (ret)
911 return ret;
912
913 nand_write_data_op(chip, buf, mtd->writesize, false);
914
915 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
916 if (ret) {
917 atmel_pmecc_disable(nand->pmecc);
918 return ret;
919 }
920
921 atmel_nand_pmecc_disable(chip, raw);
922
923 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
924
925 return nand_prog_page_end_op(chip);
926}
927
928static int atmel_nand_pmecc_write_page(struct nand_chip *chip, const u8 *buf,
929 int oob_required, int page)
930{
931 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
932}
933
934static int atmel_nand_pmecc_write_page_raw(struct nand_chip *chip,
935 const u8 *buf, int oob_required,
936 int page)
937{
938 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
939}
940
941static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
942 bool oob_required, int page, bool raw)
943{
944 struct mtd_info *mtd = nand_to_mtd(chip);
945 int ret;
946
947 nand_read_page_op(chip, page, 0, NULL, 0);
948
949 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
950 if (ret)
951 return ret;
952
953 ret = nand_read_data_op(chip, buf, mtd->writesize, false, false);
954 if (ret)
955 goto out_disable;
956
957 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false);
958 if (ret)
959 goto out_disable;
960
961 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
962
963out_disable:
964 atmel_nand_pmecc_disable(chip, raw);
965
966 return ret;
967}
968
969static int atmel_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
970 int oob_required, int page)
971{
972 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
973}
974
975static int atmel_nand_pmecc_read_page_raw(struct nand_chip *chip, u8 *buf,
976 int oob_required, int page)
977{
978 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
979}
980
981static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
982 const u8 *buf, bool oob_required,
983 int page, bool raw)
984{
985 struct mtd_info *mtd = nand_to_mtd(chip);
986 struct atmel_nand *nand = to_atmel_nand(chip);
987 struct atmel_hsmc_nand_controller *nc;
988 int ret;
989
990 atmel_hsmc_nand_select_target(nand, chip->cur_cs);
991 nc = to_hsmc_nand_controller(chip->controller);
992
993 atmel_nfc_copy_to_sram(chip, buf, false);
994
995 nc->op.cmds[0] = NAND_CMD_SEQIN;
996 nc->op.ncmds = 1;
997 atmel_nfc_set_op_addr(chip, page, 0x0);
998 nc->op.cs = nand->activecs->id;
999 nc->op.data = ATMEL_NFC_WRITE_DATA;
1000
1001 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
1002 if (ret)
1003 return ret;
1004
1005 ret = atmel_nfc_exec_op(nc, false);
1006 if (ret) {
1007 atmel_nand_pmecc_disable(chip, raw);
1008 dev_err(nc->base.dev,
1009 "Failed to transfer NAND page data (err = %d)\n",
1010 ret);
1011 return ret;
1012 }
1013
1014 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
1015
1016 atmel_nand_pmecc_disable(chip, raw);
1017
1018 if (ret)
1019 return ret;
1020
1021 nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false);
1022
1023 return nand_prog_page_end_op(chip);
1024}
1025
1026static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip,
1027 const u8 *buf, int oob_required,
1028 int page)
1029{
1030 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1031 false);
1032}
1033
1034static int atmel_hsmc_nand_pmecc_write_page_raw(struct nand_chip *chip,
1035 const u8 *buf,
1036 int oob_required, int page)
1037{
1038 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
1039 true);
1040}
1041
1042static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
1043 bool oob_required, int page,
1044 bool raw)
1045{
1046 struct mtd_info *mtd = nand_to_mtd(chip);
1047 struct atmel_nand *nand = to_atmel_nand(chip);
1048 struct atmel_hsmc_nand_controller *nc;
1049 int ret;
1050
1051 atmel_hsmc_nand_select_target(nand, chip->cur_cs);
1052 nc = to_hsmc_nand_controller(chip->controller);
1053
1054
1055
1056
1057
1058
1059 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
1060 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1061 raw);
1062
1063 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1064
1065 if (mtd->writesize > 512)
1066 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1067
1068 atmel_nfc_set_op_addr(chip, page, 0x0);
1069 nc->op.cs = nand->activecs->id;
1070 nc->op.data = ATMEL_NFC_READ_DATA;
1071
1072 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1073 if (ret)
1074 return ret;
1075
1076 ret = atmel_nfc_exec_op(nc, false);
1077 if (ret) {
1078 atmel_nand_pmecc_disable(chip, raw);
1079 dev_err(nc->base.dev,
1080 "Failed to load NAND page data (err = %d)\n",
1081 ret);
1082 return ret;
1083 }
1084
1085 atmel_nfc_copy_from_sram(chip, buf, true);
1086
1087 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1088
1089 atmel_nand_pmecc_disable(chip, raw);
1090
1091 return ret;
1092}
1093
1094static int atmel_hsmc_nand_pmecc_read_page(struct nand_chip *chip, u8 *buf,
1095 int oob_required, int page)
1096{
1097 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1098 false);
1099}
1100
1101static int atmel_hsmc_nand_pmecc_read_page_raw(struct nand_chip *chip,
1102 u8 *buf, int oob_required,
1103 int page)
1104{
1105 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1106 true);
1107}
1108
1109static int atmel_nand_pmecc_init(struct nand_chip *chip)
1110{
1111 const struct nand_ecc_props *requirements =
1112 nanddev_get_ecc_requirements(&chip->base);
1113 struct mtd_info *mtd = nand_to_mtd(chip);
1114 struct nand_device *nanddev = mtd_to_nanddev(mtd);
1115 struct atmel_nand *nand = to_atmel_nand(chip);
1116 struct atmel_nand_controller *nc;
1117 struct atmel_pmecc_user_req req;
1118
1119 nc = to_nand_controller(chip->controller);
1120
1121 if (!nc->pmecc) {
1122 dev_err(nc->dev, "HW ECC not supported\n");
1123 return -ENOTSUPP;
1124 }
1125
1126 if (nc->caps->legacy_of_bindings) {
1127 u32 val;
1128
1129 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1130 &val))
1131 chip->ecc.strength = val;
1132
1133 if (!of_property_read_u32(nc->dev->of_node,
1134 "atmel,pmecc-sector-size",
1135 &val))
1136 chip->ecc.size = val;
1137 }
1138
1139 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH)
1140 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1141 else if (chip->ecc.strength)
1142 req.ecc.strength = chip->ecc.strength;
1143 else if (requirements->strength)
1144 req.ecc.strength = requirements->strength;
1145 else
1146 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1147
1148 if (chip->ecc.size)
1149 req.ecc.sectorsize = chip->ecc.size;
1150 else if (requirements->step_size)
1151 req.ecc.sectorsize = requirements->step_size;
1152 else
1153 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1154
1155 req.pagesize = mtd->writesize;
1156 req.oobsize = mtd->oobsize;
1157
1158 if (mtd->writesize <= 512) {
1159 req.ecc.bytes = 4;
1160 req.ecc.ooboffset = 0;
1161 } else {
1162 req.ecc.bytes = mtd->oobsize - 2;
1163 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1164 }
1165
1166 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1167 if (IS_ERR(nand->pmecc))
1168 return PTR_ERR(nand->pmecc);
1169
1170 chip->ecc.algo = NAND_ECC_ALGO_BCH;
1171 chip->ecc.size = req.ecc.sectorsize;
1172 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1173 chip->ecc.strength = req.ecc.strength;
1174
1175 chip->options |= NAND_NO_SUBPAGE_WRITE;
1176
1177 mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout());
1178
1179 return 0;
1180}
1181
1182static int atmel_nand_ecc_init(struct nand_chip *chip)
1183{
1184 struct atmel_nand_controller *nc;
1185 int ret;
1186
1187 nc = to_nand_controller(chip->controller);
1188
1189 switch (chip->ecc.engine_type) {
1190 case NAND_ECC_ENGINE_TYPE_NONE:
1191 case NAND_ECC_ENGINE_TYPE_SOFT:
1192
1193
1194
1195 break;
1196
1197 case NAND_ECC_ENGINE_TYPE_ON_HOST:
1198 ret = atmel_nand_pmecc_init(chip);
1199 if (ret)
1200 return ret;
1201
1202 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1203 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1204 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1205 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1206 break;
1207
1208 default:
1209
1210 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1211 chip->ecc.engine_type);
1212 return -ENOTSUPP;
1213 }
1214
1215 return 0;
1216}
1217
1218static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
1219{
1220 int ret;
1221
1222 ret = atmel_nand_ecc_init(chip);
1223 if (ret)
1224 return ret;
1225
1226 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
1227 return 0;
1228
1229
1230 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1231 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1232 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1233 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1234
1235 return 0;
1236}
1237
1238static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1239 const struct nand_interface_config *conf,
1240 struct atmel_smc_cs_conf *smcconf)
1241{
1242 u32 ncycles, totalcycles, timeps, mckperiodps;
1243 struct atmel_nand_controller *nc;
1244 int ret;
1245
1246 nc = to_nand_controller(nand->base.controller);
1247
1248
1249 if (!nand_interface_is_sdr(conf))
1250 return -ENOTSUPP;
1251
1252
1253
1254
1255
1256 if (conf->timings.sdr.tRC_min < 30000)
1257 return -ENOTSUPP;
1258
1259 atmel_smc_cs_conf_init(smcconf);
1260
1261 mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1262 mckperiodps *= 1000;
1263
1264
1265
1266
1267
1268
1269 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1270 totalcycles = ncycles;
1271 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1272 ncycles);
1273 if (ret)
1274 return ret;
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1288 conf->timings.sdr.tALS_min);
1289 timeps = max(timeps, conf->timings.sdr.tDS_min);
1290 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1291 ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1292 totalcycles += ncycles;
1293 ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1294 ncycles);
1295 if (ret)
1296 return ret;
1297
1298
1299
1300
1301
1302
1303
1304 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1305 conf->timings.sdr.tALH_min);
1306 timeps = max3(timeps, conf->timings.sdr.tDH_min,
1307 conf->timings.sdr.tWH_min);
1308 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1309 totalcycles += ncycles;
1310
1311
1312
1313
1314
1315
1316
1317
1318 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1319 ncycles = max(totalcycles, ncycles);
1320 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1321 ncycles);
1322 if (ret)
1323 return ret;
1324
1325
1326
1327
1328
1329
1330
1331
1332 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1333 ncycles);
1334 if (ret)
1335 return ret;
1336
1337
1338
1339
1340
1341
1342
1343 timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1344 ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1345 totalcycles = ncycles;
1346
1347
1348
1349
1350 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1351 ncycles -= totalcycles;
1352
1353
1354
1355
1356
1357
1358
1359 if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1360 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1361 else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1362 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1363
1364 smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1365 ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1366
1367
1368
1369
1370
1371
1372 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1373 totalcycles += ncycles;
1374 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1375 ncycles);
1376 if (ret)
1377 return ret;
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1389 ncycles = max(totalcycles, ncycles);
1390 ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1391 ncycles);
1392 if (ret)
1393 return ret;
1394
1395
1396
1397
1398
1399
1400
1401
1402 ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1403 ncycles);
1404 if (ret)
1405 return ret;
1406
1407
1408 ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1409 ret = atmel_smc_cs_conf_set_timing(smcconf,
1410 ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1411 ncycles);
1412 if (ret)
1413 return ret;
1414
1415 ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1416 ret = atmel_smc_cs_conf_set_timing(smcconf,
1417 ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1418 ncycles);
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430 if (ret && ret != -ERANGE)
1431 return ret;
1432
1433 ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1434 ret = atmel_smc_cs_conf_set_timing(smcconf,
1435 ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1436 ncycles);
1437 if (ret)
1438 return ret;
1439
1440 ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1441 ret = atmel_smc_cs_conf_set_timing(smcconf,
1442 ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1443 ncycles);
1444 if (ret)
1445 return ret;
1446
1447 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1448 ret = atmel_smc_cs_conf_set_timing(smcconf,
1449 ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1450 ncycles);
1451 if (ret)
1452 return ret;
1453
1454
1455 smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1456
1457
1458 if (nand->base.options & NAND_BUSWIDTH_16)
1459 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1460
1461
1462 smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1463 ATMEL_SMC_MODE_WRITEMODE_NWE;
1464
1465 return 0;
1466}
1467
1468static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
1469 int csline,
1470 const struct nand_interface_config *conf)
1471{
1472 struct atmel_nand_controller *nc;
1473 struct atmel_smc_cs_conf smcconf;
1474 struct atmel_nand_cs *cs;
1475 int ret;
1476
1477 nc = to_nand_controller(nand->base.controller);
1478
1479 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1480 if (ret)
1481 return ret;
1482
1483 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1484 return 0;
1485
1486 cs = &nand->cs[csline];
1487 cs->smcconf = smcconf;
1488 atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1489
1490 return 0;
1491}
1492
1493static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
1494 int csline,
1495 const struct nand_interface_config *conf)
1496{
1497 struct atmel_hsmc_nand_controller *nc;
1498 struct atmel_smc_cs_conf smcconf;
1499 struct atmel_nand_cs *cs;
1500 int ret;
1501
1502 nc = to_hsmc_nand_controller(nand->base.controller);
1503
1504 ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1505 if (ret)
1506 return ret;
1507
1508 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1509 return 0;
1510
1511 cs = &nand->cs[csline];
1512 cs->smcconf = smcconf;
1513
1514 if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1515 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1516
1517 atmel_hsmc_cs_conf_apply(nc->base.smc, nc->hsmc_layout, cs->id,
1518 &cs->smcconf);
1519
1520 return 0;
1521}
1522
1523static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
1524 const struct nand_interface_config *conf)
1525{
1526 struct atmel_nand *nand = to_atmel_nand(chip);
1527 const struct nand_sdr_timings *sdr;
1528 struct atmel_nand_controller *nc;
1529
1530 sdr = nand_get_sdr_timings(conf);
1531 if (IS_ERR(sdr))
1532 return PTR_ERR(sdr);
1533
1534 nc = to_nand_controller(nand->base.controller);
1535
1536 if (csline >= nand->numcs ||
1537 (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1538 return -EINVAL;
1539
1540 return nc->caps->ops->setup_interface(nand, csline, conf);
1541}
1542
1543static int atmel_nand_exec_op(struct nand_chip *chip,
1544 const struct nand_operation *op,
1545 bool check_only)
1546{
1547 struct atmel_nand *nand = to_atmel_nand(chip);
1548 struct atmel_nand_controller *nc;
1549
1550 nc = to_nand_controller(nand->base.controller);
1551
1552 return nc->caps->ops->exec_op(nand, op, check_only);
1553}
1554
1555static void atmel_nand_init(struct atmel_nand_controller *nc,
1556 struct atmel_nand *nand)
1557{
1558 struct nand_chip *chip = &nand->base;
1559 struct mtd_info *mtd = nand_to_mtd(chip);
1560
1561 mtd->dev.parent = nc->dev;
1562 nand->base.controller = &nc->base;
1563
1564 if (!nc->mck || !nc->caps->ops->setup_interface)
1565 chip->options |= NAND_KEEP_TIMINGS;
1566
1567
1568
1569
1570
1571 if (nc->dmac)
1572 chip->options |= NAND_USES_DMA;
1573
1574
1575 if (nc->pmecc)
1576 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
1577}
1578
1579static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1580 struct atmel_nand *nand)
1581{
1582 struct nand_chip *chip = &nand->base;
1583 struct atmel_smc_nand_controller *smc_nc;
1584 int i;
1585
1586 atmel_nand_init(nc, nand);
1587
1588 smc_nc = to_smc_nand_controller(chip->controller);
1589 if (!smc_nc->ebi_csa_regmap)
1590 return;
1591
1592
1593 for (i = 0; i < nand->numcs; i++)
1594 regmap_update_bits(smc_nc->ebi_csa_regmap,
1595 smc_nc->ebi_csa->offs,
1596 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1597
1598 if (smc_nc->ebi_csa->nfd0_on_d16)
1599 regmap_update_bits(smc_nc->ebi_csa_regmap,
1600 smc_nc->ebi_csa->offs,
1601 smc_nc->ebi_csa->nfd0_on_d16,
1602 smc_nc->ebi_csa->nfd0_on_d16);
1603}
1604
1605static int atmel_nand_controller_remove_nand(struct atmel_nand *nand)
1606{
1607 struct nand_chip *chip = &nand->base;
1608 struct mtd_info *mtd = nand_to_mtd(chip);
1609 int ret;
1610
1611 ret = mtd_device_unregister(mtd);
1612 if (ret)
1613 return ret;
1614
1615 nand_cleanup(chip);
1616 list_del(&nand->node);
1617
1618 return 0;
1619}
1620
1621static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1622 struct device_node *np,
1623 int reg_cells)
1624{
1625 struct atmel_nand *nand;
1626 struct gpio_desc *gpio;
1627 int numcs, ret, i;
1628
1629 numcs = of_property_count_elems_of_size(np, "reg",
1630 reg_cells * sizeof(u32));
1631 if (numcs < 1) {
1632 dev_err(nc->dev, "Missing or invalid reg property\n");
1633 return ERR_PTR(-EINVAL);
1634 }
1635
1636 nand = devm_kzalloc(nc->dev, struct_size(nand, cs, numcs), GFP_KERNEL);
1637 if (!nand)
1638 return ERR_PTR(-ENOMEM);
1639
1640 nand->numcs = numcs;
1641
1642 gpio = devm_fwnode_gpiod_get(nc->dev, of_fwnode_handle(np),
1643 "det", GPIOD_IN, "nand-det");
1644 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1645 dev_err(nc->dev,
1646 "Failed to get detect gpio (err = %ld)\n",
1647 PTR_ERR(gpio));
1648 return ERR_CAST(gpio);
1649 }
1650
1651 if (!IS_ERR(gpio))
1652 nand->cdgpio = gpio;
1653
1654 for (i = 0; i < numcs; i++) {
1655 struct resource res;
1656 u32 val;
1657
1658 ret = of_address_to_resource(np, 0, &res);
1659 if (ret) {
1660 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1661 ret);
1662 return ERR_PTR(ret);
1663 }
1664
1665 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1666 &val);
1667 if (ret) {
1668 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1669 ret);
1670 return ERR_PTR(ret);
1671 }
1672
1673 nand->cs[i].id = val;
1674
1675 nand->cs[i].io.dma = res.start;
1676 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1677 if (IS_ERR(nand->cs[i].io.virt))
1678 return ERR_CAST(nand->cs[i].io.virt);
1679
1680 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1681 if (val > ATMEL_NFC_MAX_RB_ID)
1682 return ERR_PTR(-EINVAL);
1683
1684 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1685 nand->cs[i].rb.id = val;
1686 } else {
1687 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1688 of_fwnode_handle(np),
1689 "rb", i, GPIOD_IN,
1690 "nand-rb");
1691 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1692 dev_err(nc->dev,
1693 "Failed to get R/B gpio (err = %ld)\n",
1694 PTR_ERR(gpio));
1695 return ERR_CAST(gpio);
1696 }
1697
1698 if (!IS_ERR(gpio)) {
1699 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1700 nand->cs[i].rb.gpio = gpio;
1701 }
1702 }
1703
1704 gpio = devm_fwnode_gpiod_get_index(nc->dev,
1705 of_fwnode_handle(np),
1706 "cs", i, GPIOD_OUT_HIGH,
1707 "nand-cs");
1708 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1709 dev_err(nc->dev,
1710 "Failed to get CS gpio (err = %ld)\n",
1711 PTR_ERR(gpio));
1712 return ERR_CAST(gpio);
1713 }
1714
1715 if (!IS_ERR(gpio))
1716 nand->cs[i].csgpio = gpio;
1717 }
1718
1719 nand_set_flash_node(&nand->base, np);
1720
1721 return nand;
1722}
1723
1724static int
1725atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1726 struct atmel_nand *nand)
1727{
1728 struct nand_chip *chip = &nand->base;
1729 struct mtd_info *mtd = nand_to_mtd(chip);
1730 int ret;
1731
1732
1733 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1734 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1735 return 0;
1736 }
1737
1738 nc->caps->ops->nand_init(nc, nand);
1739
1740 ret = nand_scan(chip, nand->numcs);
1741 if (ret) {
1742 dev_err(nc->dev, "NAND scan failed: %d\n", ret);
1743 return ret;
1744 }
1745
1746 ret = mtd_device_register(mtd, NULL, 0);
1747 if (ret) {
1748 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1749 nand_cleanup(chip);
1750 return ret;
1751 }
1752
1753 list_add_tail(&nand->node, &nc->chips);
1754
1755 return 0;
1756}
1757
1758static int
1759atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1760{
1761 struct atmel_nand *nand, *tmp;
1762 int ret;
1763
1764 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1765 ret = atmel_nand_controller_remove_nand(nand);
1766 if (ret)
1767 return ret;
1768 }
1769
1770 return 0;
1771}
1772
1773static int
1774atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1775{
1776 struct device *dev = nc->dev;
1777 struct platform_device *pdev = to_platform_device(dev);
1778 struct atmel_nand *nand;
1779 struct gpio_desc *gpio;
1780 struct resource *res;
1781
1782
1783
1784
1785
1786 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1787 GFP_KERNEL);
1788 if (!nand)
1789 return -ENOMEM;
1790
1791 nand->numcs = 1;
1792
1793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1794 nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1795 if (IS_ERR(nand->cs[0].io.virt))
1796 return PTR_ERR(nand->cs[0].io.virt);
1797
1798 nand->cs[0].io.dma = res->start;
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808 nand->cs[0].id = 3;
1809
1810
1811 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);
1812 if (IS_ERR(gpio)) {
1813 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1814 PTR_ERR(gpio));
1815 return PTR_ERR(gpio);
1816 }
1817
1818 if (gpio) {
1819 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1820 nand->cs[0].rb.gpio = gpio;
1821 }
1822
1823
1824 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1825 if (IS_ERR(gpio)) {
1826 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1827 PTR_ERR(gpio));
1828 return PTR_ERR(gpio);
1829 }
1830
1831 nand->cs[0].csgpio = gpio;
1832
1833
1834 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1835 if (IS_ERR(gpio)) {
1836 dev_err(dev,
1837 "Failed to get detect gpio (err = %ld)\n",
1838 PTR_ERR(gpio));
1839 return PTR_ERR(gpio);
1840 }
1841
1842 nand->cdgpio = gpio;
1843
1844 nand_set_flash_node(&nand->base, nc->dev->of_node);
1845
1846 return atmel_nand_controller_add_nand(nc, nand);
1847}
1848
1849static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1850{
1851 struct device_node *np, *nand_np;
1852 struct device *dev = nc->dev;
1853 int ret, reg_cells;
1854 u32 val;
1855
1856
1857 if (nc->caps->legacy_of_bindings)
1858 return atmel_nand_controller_legacy_add_nands(nc);
1859
1860 np = dev->of_node;
1861
1862 ret = of_property_read_u32(np, "#address-cells", &val);
1863 if (ret) {
1864 dev_err(dev, "missing #address-cells property\n");
1865 return ret;
1866 }
1867
1868 reg_cells = val;
1869
1870 ret = of_property_read_u32(np, "#size-cells", &val);
1871 if (ret) {
1872 dev_err(dev, "missing #size-cells property\n");
1873 return ret;
1874 }
1875
1876 reg_cells += val;
1877
1878 for_each_child_of_node(np, nand_np) {
1879 struct atmel_nand *nand;
1880
1881 nand = atmel_nand_create(nc, nand_np, reg_cells);
1882 if (IS_ERR(nand)) {
1883 ret = PTR_ERR(nand);
1884 goto err;
1885 }
1886
1887 ret = atmel_nand_controller_add_nand(nc, nand);
1888 if (ret)
1889 goto err;
1890 }
1891
1892 return 0;
1893
1894err:
1895 atmel_nand_controller_remove_nands(nc);
1896
1897 return ret;
1898}
1899
1900static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1901{
1902 if (nc->dmac)
1903 dma_release_channel(nc->dmac);
1904
1905 clk_put(nc->mck);
1906}
1907
1908static const struct atmel_smc_nand_ebi_csa_cfg at91sam9260_ebi_csa = {
1909 .offs = AT91SAM9260_MATRIX_EBICSA,
1910};
1911
1912static const struct atmel_smc_nand_ebi_csa_cfg at91sam9261_ebi_csa = {
1913 .offs = AT91SAM9261_MATRIX_EBICSA,
1914};
1915
1916static const struct atmel_smc_nand_ebi_csa_cfg at91sam9263_ebi_csa = {
1917 .offs = AT91SAM9263_MATRIX_EBI0CSA,
1918};
1919
1920static const struct atmel_smc_nand_ebi_csa_cfg at91sam9rl_ebi_csa = {
1921 .offs = AT91SAM9RL_MATRIX_EBICSA,
1922};
1923
1924static const struct atmel_smc_nand_ebi_csa_cfg at91sam9g45_ebi_csa = {
1925 .offs = AT91SAM9G45_MATRIX_EBICSA,
1926};
1927
1928static const struct atmel_smc_nand_ebi_csa_cfg at91sam9n12_ebi_csa = {
1929 .offs = AT91SAM9N12_MATRIX_EBICSA,
1930};
1931
1932static const struct atmel_smc_nand_ebi_csa_cfg at91sam9x5_ebi_csa = {
1933 .offs = AT91SAM9X5_MATRIX_EBICSA,
1934};
1935
1936static const struct atmel_smc_nand_ebi_csa_cfg sam9x60_ebi_csa = {
1937 .offs = AT91_SFR_CCFG_EBICSA,
1938 .nfd0_on_d16 = AT91_SFR_CCFG_NFD0_ON_D16,
1939};
1940
1941static const struct of_device_id atmel_ebi_csa_regmap_of_ids[] = {
1942 {
1943 .compatible = "atmel,at91sam9260-matrix",
1944 .data = &at91sam9260_ebi_csa,
1945 },
1946 {
1947 .compatible = "atmel,at91sam9261-matrix",
1948 .data = &at91sam9261_ebi_csa,
1949 },
1950 {
1951 .compatible = "atmel,at91sam9263-matrix",
1952 .data = &at91sam9263_ebi_csa,
1953 },
1954 {
1955 .compatible = "atmel,at91sam9rl-matrix",
1956 .data = &at91sam9rl_ebi_csa,
1957 },
1958 {
1959 .compatible = "atmel,at91sam9g45-matrix",
1960 .data = &at91sam9g45_ebi_csa,
1961 },
1962 {
1963 .compatible = "atmel,at91sam9n12-matrix",
1964 .data = &at91sam9n12_ebi_csa,
1965 },
1966 {
1967 .compatible = "atmel,at91sam9x5-matrix",
1968 .data = &at91sam9x5_ebi_csa,
1969 },
1970 {
1971 .compatible = "microchip,sam9x60-sfr",
1972 .data = &sam9x60_ebi_csa,
1973 },
1974 { },
1975};
1976
1977static int atmel_nand_attach_chip(struct nand_chip *chip)
1978{
1979 struct atmel_nand_controller *nc = to_nand_controller(chip->controller);
1980 struct atmel_nand *nand = to_atmel_nand(chip);
1981 struct mtd_info *mtd = nand_to_mtd(chip);
1982 int ret;
1983
1984 ret = nc->caps->ops->ecc_init(chip);
1985 if (ret)
1986 return ret;
1987
1988 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1989
1990
1991
1992
1993
1994 mtd->name = "atmel_nand";
1995 } else if (!mtd->name) {
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
2007 "%s:nand.%d", dev_name(nc->dev),
2008 nand->cs[0].id);
2009 if (!mtd->name) {
2010 dev_err(nc->dev, "Failed to allocate mtd->name\n");
2011 return -ENOMEM;
2012 }
2013 }
2014
2015 return 0;
2016}
2017
2018static const struct nand_controller_ops atmel_nand_controller_ops = {
2019 .attach_chip = atmel_nand_attach_chip,
2020 .setup_interface = atmel_nand_setup_interface,
2021 .exec_op = atmel_nand_exec_op,
2022};
2023
2024static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
2025 struct platform_device *pdev,
2026 const struct atmel_nand_controller_caps *caps)
2027{
2028 struct device *dev = &pdev->dev;
2029 struct device_node *np = dev->of_node;
2030 int ret;
2031
2032 nand_controller_init(&nc->base);
2033 nc->base.ops = &atmel_nand_controller_ops;
2034 INIT_LIST_HEAD(&nc->chips);
2035 nc->dev = dev;
2036 nc->caps = caps;
2037
2038 platform_set_drvdata(pdev, nc);
2039
2040 nc->pmecc = devm_atmel_pmecc_get(dev);
2041 if (IS_ERR(nc->pmecc))
2042 return dev_err_probe(dev, PTR_ERR(nc->pmecc),
2043 "Could not get PMECC object\n");
2044
2045 if (nc->caps->has_dma && !atmel_nand_avoid_dma) {
2046 dma_cap_mask_t mask;
2047
2048 dma_cap_zero(mask);
2049 dma_cap_set(DMA_MEMCPY, mask);
2050
2051 nc->dmac = dma_request_channel(mask, NULL, NULL);
2052 if (!nc->dmac)
2053 dev_err(nc->dev, "Failed to request DMA channel\n");
2054 }
2055
2056
2057 if (nc->caps->legacy_of_bindings)
2058 return 0;
2059
2060 nc->mck = of_clk_get(dev->parent->of_node, 0);
2061 if (IS_ERR(nc->mck)) {
2062 dev_err(dev, "Failed to retrieve MCK clk\n");
2063 return PTR_ERR(nc->mck);
2064 }
2065
2066 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2067 if (!np) {
2068 dev_err(dev, "Missing or invalid atmel,smc property\n");
2069 return -EINVAL;
2070 }
2071
2072 nc->smc = syscon_node_to_regmap(np);
2073 of_node_put(np);
2074 if (IS_ERR(nc->smc)) {
2075 ret = PTR_ERR(nc->smc);
2076 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
2077 return ret;
2078 }
2079
2080 return 0;
2081}
2082
2083static int
2084atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2085{
2086 struct device *dev = nc->base.dev;
2087 const struct of_device_id *match;
2088 struct device_node *np;
2089 int ret;
2090
2091
2092 if (nc->base.caps->legacy_of_bindings)
2093 return 0;
2094
2095 np = of_parse_phandle(dev->parent->of_node,
2096 nc->base.caps->ebi_csa_regmap_name, 0);
2097 if (!np)
2098 return 0;
2099
2100 match = of_match_node(atmel_ebi_csa_regmap_of_ids, np);
2101 if (!match) {
2102 of_node_put(np);
2103 return 0;
2104 }
2105
2106 nc->ebi_csa_regmap = syscon_node_to_regmap(np);
2107 of_node_put(np);
2108 if (IS_ERR(nc->ebi_csa_regmap)) {
2109 ret = PTR_ERR(nc->ebi_csa_regmap);
2110 dev_err(dev, "Could not get EBICSA regmap (err = %d)\n", ret);
2111 return ret;
2112 }
2113
2114 nc->ebi_csa = (struct atmel_smc_nand_ebi_csa_cfg *)match->data;
2115
2116
2117
2118
2119
2120 if (of_device_is_compatible(dev->parent->of_node,
2121 "atmel,at91sam9263-ebi1"))
2122 nc->ebi_csa->offs += 4;
2123
2124 return 0;
2125}
2126
2127static int
2128atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2129{
2130 struct regmap_config regmap_conf = {
2131 .reg_bits = 32,
2132 .val_bits = 32,
2133 .reg_stride = 4,
2134 };
2135
2136 struct device *dev = nc->base.dev;
2137 struct device_node *nand_np, *nfc_np;
2138 void __iomem *iomem;
2139 struct resource res;
2140 int ret;
2141
2142 nand_np = dev->of_node;
2143 nfc_np = of_get_compatible_child(dev->of_node, "atmel,sama5d3-nfc");
2144 if (!nfc_np) {
2145 dev_err(dev, "Could not find device node for sama5d3-nfc\n");
2146 return -ENODEV;
2147 }
2148
2149 nc->clk = of_clk_get(nfc_np, 0);
2150 if (IS_ERR(nc->clk)) {
2151 ret = PTR_ERR(nc->clk);
2152 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2153 ret);
2154 goto out;
2155 }
2156
2157 ret = clk_prepare_enable(nc->clk);
2158 if (ret) {
2159 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2160 ret);
2161 goto out;
2162 }
2163
2164 nc->irq = of_irq_get(nand_np, 0);
2165 if (nc->irq <= 0) {
2166 ret = nc->irq ?: -ENXIO;
2167 if (ret != -EPROBE_DEFER)
2168 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2169 ret);
2170 goto out;
2171 }
2172
2173 ret = of_address_to_resource(nfc_np, 0, &res);
2174 if (ret) {
2175 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2176 ret);
2177 goto out;
2178 }
2179
2180 iomem = devm_ioremap_resource(dev, &res);
2181 if (IS_ERR(iomem)) {
2182 ret = PTR_ERR(iomem);
2183 goto out;
2184 }
2185
2186 regmap_conf.name = "nfc-io";
2187 regmap_conf.max_register = resource_size(&res) - 4;
2188 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf);
2189 if (IS_ERR(nc->io)) {
2190 ret = PTR_ERR(nc->io);
2191 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2192 ret);
2193 goto out;
2194 }
2195
2196 ret = of_address_to_resource(nfc_np, 1, &res);
2197 if (ret) {
2198 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2199 ret);
2200 goto out;
2201 }
2202
2203 iomem = devm_ioremap_resource(dev, &res);
2204 if (IS_ERR(iomem)) {
2205 ret = PTR_ERR(iomem);
2206 goto out;
2207 }
2208
2209 regmap_conf.name = "smc";
2210 regmap_conf.max_register = resource_size(&res) - 4;
2211 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf);
2212 if (IS_ERR(nc->base.smc)) {
2213 ret = PTR_ERR(nc->base.smc);
2214 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2215 ret);
2216 goto out;
2217 }
2218
2219 ret = of_address_to_resource(nfc_np, 2, &res);
2220 if (ret) {
2221 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2222 ret);
2223 goto out;
2224 }
2225
2226 nc->sram.virt = devm_ioremap_resource(dev, &res);
2227 if (IS_ERR(nc->sram.virt)) {
2228 ret = PTR_ERR(nc->sram.virt);
2229 goto out;
2230 }
2231
2232 nc->sram.dma = res.start;
2233
2234out:
2235 of_node_put(nfc_np);
2236
2237 return ret;
2238}
2239
2240static int
2241atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2242{
2243 struct device *dev = nc->base.dev;
2244 struct device_node *np;
2245 int ret;
2246
2247 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2248 if (!np) {
2249 dev_err(dev, "Missing or invalid atmel,smc property\n");
2250 return -EINVAL;
2251 }
2252
2253 nc->hsmc_layout = atmel_hsmc_get_reg_layout(np);
2254
2255 nc->irq = of_irq_get(np, 0);
2256 of_node_put(np);
2257 if (nc->irq <= 0) {
2258 ret = nc->irq ?: -ENXIO;
2259 if (ret != -EPROBE_DEFER)
2260 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2261 ret);
2262 return ret;
2263 }
2264
2265 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2266 if (!np) {
2267 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2268 return -EINVAL;
2269 }
2270
2271 nc->io = syscon_node_to_regmap(np);
2272 of_node_put(np);
2273 if (IS_ERR(nc->io)) {
2274 ret = PTR_ERR(nc->io);
2275 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2276 return ret;
2277 }
2278
2279 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2280 "atmel,nfc-sram", 0);
2281 if (!nc->sram.pool) {
2282 dev_err(nc->base.dev, "Missing SRAM\n");
2283 return -ENOMEM;
2284 }
2285
2286 nc->sram.virt = (void __iomem *)gen_pool_dma_alloc(nc->sram.pool,
2287 ATMEL_NFC_SRAM_SIZE,
2288 &nc->sram.dma);
2289 if (!nc->sram.virt) {
2290 dev_err(nc->base.dev,
2291 "Could not allocate memory from the NFC SRAM pool\n");
2292 return -ENOMEM;
2293 }
2294
2295 return 0;
2296}
2297
2298static int
2299atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2300{
2301 struct atmel_hsmc_nand_controller *hsmc_nc;
2302 int ret;
2303
2304 ret = atmel_nand_controller_remove_nands(nc);
2305 if (ret)
2306 return ret;
2307
2308 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2309 regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2310 ATMEL_HSMC_NFC_CTRL_DIS);
2311
2312 if (hsmc_nc->sram.pool)
2313 gen_pool_free(hsmc_nc->sram.pool,
2314 (unsigned long)hsmc_nc->sram.virt,
2315 ATMEL_NFC_SRAM_SIZE);
2316
2317 if (hsmc_nc->clk) {
2318 clk_disable_unprepare(hsmc_nc->clk);
2319 clk_put(hsmc_nc->clk);
2320 }
2321
2322 atmel_nand_controller_cleanup(nc);
2323
2324 return 0;
2325}
2326
2327static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2328 const struct atmel_nand_controller_caps *caps)
2329{
2330 struct device *dev = &pdev->dev;
2331 struct atmel_hsmc_nand_controller *nc;
2332 int ret;
2333
2334 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2335 if (!nc)
2336 return -ENOMEM;
2337
2338 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2339 if (ret)
2340 return ret;
2341
2342 if (caps->legacy_of_bindings)
2343 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2344 else
2345 ret = atmel_hsmc_nand_controller_init(nc);
2346
2347 if (ret)
2348 return ret;
2349
2350
2351 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2352 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2353 IRQF_SHARED, "nfc", nc);
2354 if (ret) {
2355 dev_err(dev,
2356 "Could not get register NFC interrupt handler (err = %d)\n",
2357 ret);
2358 goto err;
2359 }
2360
2361
2362 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2363 ATMEL_HSMC_NFC_CFG_DTO_MAX);
2364 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
2365 ATMEL_HSMC_NFC_CTRL_EN);
2366
2367 ret = atmel_nand_controller_add_nands(&nc->base);
2368 if (ret)
2369 goto err;
2370
2371 return 0;
2372
2373err:
2374 atmel_hsmc_nand_controller_remove(&nc->base);
2375
2376 return ret;
2377}
2378
2379static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2380 .probe = atmel_hsmc_nand_controller_probe,
2381 .remove = atmel_hsmc_nand_controller_remove,
2382 .ecc_init = atmel_hsmc_nand_ecc_init,
2383 .nand_init = atmel_nand_init,
2384 .setup_interface = atmel_hsmc_nand_setup_interface,
2385 .exec_op = atmel_hsmc_nand_exec_op,
2386};
2387
2388static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2389 .has_dma = true,
2390 .ale_offs = BIT(21),
2391 .cle_offs = BIT(22),
2392 .ops = &atmel_hsmc_nc_ops,
2393};
2394
2395
2396static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2397 .has_dma = true,
2398 .ale_offs = BIT(21),
2399 .cle_offs = BIT(22),
2400 .ops = &atmel_hsmc_nc_ops,
2401 .legacy_of_bindings = true,
2402};
2403
2404static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2405 const struct atmel_nand_controller_caps *caps)
2406{
2407 struct device *dev = &pdev->dev;
2408 struct atmel_smc_nand_controller *nc;
2409 int ret;
2410
2411 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2412 if (!nc)
2413 return -ENOMEM;
2414
2415 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2416 if (ret)
2417 return ret;
2418
2419 ret = atmel_smc_nand_controller_init(nc);
2420 if (ret)
2421 return ret;
2422
2423 return atmel_nand_controller_add_nands(&nc->base);
2424}
2425
2426static int
2427atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2428{
2429 int ret;
2430
2431 ret = atmel_nand_controller_remove_nands(nc);
2432 if (ret)
2433 return ret;
2434
2435 atmel_nand_controller_cleanup(nc);
2436
2437 return 0;
2438}
2439
2440
2441
2442
2443
2444
2445
2446
2447static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2448 .probe = atmel_smc_nand_controller_probe,
2449 .remove = atmel_smc_nand_controller_remove,
2450 .ecc_init = atmel_nand_ecc_init,
2451 .nand_init = atmel_smc_nand_init,
2452 .exec_op = atmel_smc_nand_exec_op,
2453};
2454
2455static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2456 .ale_offs = BIT(21),
2457 .cle_offs = BIT(22),
2458 .ebi_csa_regmap_name = "atmel,matrix",
2459 .ops = &at91rm9200_nc_ops,
2460};
2461
2462static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2463 .probe = atmel_smc_nand_controller_probe,
2464 .remove = atmel_smc_nand_controller_remove,
2465 .ecc_init = atmel_nand_ecc_init,
2466 .nand_init = atmel_smc_nand_init,
2467 .setup_interface = atmel_smc_nand_setup_interface,
2468 .exec_op = atmel_smc_nand_exec_op,
2469};
2470
2471static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2472 .ale_offs = BIT(21),
2473 .cle_offs = BIT(22),
2474 .ebi_csa_regmap_name = "atmel,matrix",
2475 .ops = &atmel_smc_nc_ops,
2476};
2477
2478static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2479 .ale_offs = BIT(22),
2480 .cle_offs = BIT(21),
2481 .ebi_csa_regmap_name = "atmel,matrix",
2482 .ops = &atmel_smc_nc_ops,
2483};
2484
2485static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2486 .has_dma = true,
2487 .ale_offs = BIT(21),
2488 .cle_offs = BIT(22),
2489 .ebi_csa_regmap_name = "atmel,matrix",
2490 .ops = &atmel_smc_nc_ops,
2491};
2492
2493static const struct atmel_nand_controller_caps microchip_sam9x60_nc_caps = {
2494 .has_dma = true,
2495 .ale_offs = BIT(21),
2496 .cle_offs = BIT(22),
2497 .ebi_csa_regmap_name = "microchip,sfr",
2498 .ops = &atmel_smc_nc_ops,
2499};
2500
2501
2502static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2503 .ale_offs = BIT(21),
2504 .cle_offs = BIT(22),
2505 .ops = &atmel_smc_nc_ops,
2506 .legacy_of_bindings = true,
2507};
2508
2509static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2510 .ale_offs = BIT(22),
2511 .cle_offs = BIT(21),
2512 .ops = &atmel_smc_nc_ops,
2513 .legacy_of_bindings = true,
2514};
2515
2516static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2517 .has_dma = true,
2518 .ale_offs = BIT(21),
2519 .cle_offs = BIT(22),
2520 .ops = &atmel_smc_nc_ops,
2521 .legacy_of_bindings = true,
2522};
2523
2524static const struct of_device_id atmel_nand_controller_of_ids[] = {
2525 {
2526 .compatible = "atmel,at91rm9200-nand-controller",
2527 .data = &atmel_rm9200_nc_caps,
2528 },
2529 {
2530 .compatible = "atmel,at91sam9260-nand-controller",
2531 .data = &atmel_sam9260_nc_caps,
2532 },
2533 {
2534 .compatible = "atmel,at91sam9261-nand-controller",
2535 .data = &atmel_sam9261_nc_caps,
2536 },
2537 {
2538 .compatible = "atmel,at91sam9g45-nand-controller",
2539 .data = &atmel_sam9g45_nc_caps,
2540 },
2541 {
2542 .compatible = "atmel,sama5d3-nand-controller",
2543 .data = &atmel_sama5_nc_caps,
2544 },
2545 {
2546 .compatible = "microchip,sam9x60-nand-controller",
2547 .data = µchip_sam9x60_nc_caps,
2548 },
2549
2550 {
2551 .compatible = "atmel,at91rm9200-nand",
2552 .data = &atmel_rm9200_nand_caps,
2553 },
2554 {
2555 .compatible = "atmel,sama5d4-nand",
2556 .data = &atmel_rm9200_nand_caps,
2557 },
2558 {
2559 .compatible = "atmel,sama5d2-nand",
2560 .data = &atmel_rm9200_nand_caps,
2561 },
2562 { },
2563};
2564MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2565
2566static int atmel_nand_controller_probe(struct platform_device *pdev)
2567{
2568 const struct atmel_nand_controller_caps *caps;
2569
2570 if (pdev->id_entry)
2571 caps = (void *)pdev->id_entry->driver_data;
2572 else
2573 caps = of_device_get_match_data(&pdev->dev);
2574
2575 if (!caps) {
2576 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2577 return -EINVAL;
2578 }
2579
2580 if (caps->legacy_of_bindings) {
2581 struct device_node *nfc_node;
2582 u32 ale_offs = 21;
2583
2584
2585
2586
2587
2588 nfc_node = of_get_compatible_child(pdev->dev.of_node,
2589 "atmel,sama5d3-nfc");
2590 if (nfc_node) {
2591 caps = &atmel_sama5_nand_caps;
2592 of_node_put(nfc_node);
2593 }
2594
2595
2596
2597
2598
2599
2600
2601 if (!caps->has_dma &&
2602 of_property_read_bool(pdev->dev.of_node,
2603 "atmel,nand-has-dma"))
2604 caps = &atmel_sam9g45_nand_caps;
2605
2606
2607
2608
2609
2610
2611 of_property_read_u32(pdev->dev.of_node,
2612 "atmel,nand-addr-offset", &ale_offs);
2613 if (ale_offs != 21)
2614 caps = &atmel_sam9261_nand_caps;
2615 }
2616
2617 return caps->ops->probe(pdev, caps);
2618}
2619
2620static int atmel_nand_controller_remove(struct platform_device *pdev)
2621{
2622 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2623
2624 return nc->caps->ops->remove(nc);
2625}
2626
2627static __maybe_unused int atmel_nand_controller_resume(struct device *dev)
2628{
2629 struct atmel_nand_controller *nc = dev_get_drvdata(dev);
2630 struct atmel_nand *nand;
2631
2632 if (nc->pmecc)
2633 atmel_pmecc_reset(nc->pmecc);
2634
2635 list_for_each_entry(nand, &nc->chips, node) {
2636 int i;
2637
2638 for (i = 0; i < nand->numcs; i++)
2639 nand_reset(&nand->base, i);
2640 }
2641
2642 return 0;
2643}
2644
2645static SIMPLE_DEV_PM_OPS(atmel_nand_controller_pm_ops, NULL,
2646 atmel_nand_controller_resume);
2647
2648static struct platform_driver atmel_nand_controller_driver = {
2649 .driver = {
2650 .name = "atmel-nand-controller",
2651 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2652 .pm = &atmel_nand_controller_pm_ops,
2653 },
2654 .probe = atmel_nand_controller_probe,
2655 .remove = atmel_nand_controller_remove,
2656};
2657module_platform_driver(atmel_nand_controller_driver);
2658
2659MODULE_LICENSE("GPL");
2660MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2661MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2662MODULE_ALIAS("platform:atmel-nand-controller");
2663