linux/drivers/net/can/flexcan.c
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   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// flexcan.c - FLEXCAN CAN controller driver
   4//
   5// Copyright (c) 2005-2006 Varma Electronics Oy
   6// Copyright (c) 2009 Sascha Hauer, Pengutronix
   7// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
   8// Copyright (c) 2014 David Jander, Protonic Holland
   9//
  10// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
  11
  12#include <linux/netdevice.h>
  13#include <linux/can.h>
  14#include <linux/can/dev.h>
  15#include <linux/can/error.h>
  16#include <linux/can/led.h>
  17#include <linux/can/rx-offload.h>
  18#include <linux/clk.h>
  19#include <linux/delay.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/mfd/syscon.h>
  23#include <linux/module.h>
  24#include <linux/of.h>
  25#include <linux/of_device.h>
  26#include <linux/platform_device.h>
  27#include <linux/pm_runtime.h>
  28#include <linux/regulator/consumer.h>
  29#include <linux/regmap.h>
  30
  31#define DRV_NAME                        "flexcan"
  32
  33/* 8 for RX fifo and 2 error handling */
  34#define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  35
  36/* FLEXCAN module configuration register (CANMCR) bits */
  37#define FLEXCAN_MCR_MDIS                BIT(31)
  38#define FLEXCAN_MCR_FRZ                 BIT(30)
  39#define FLEXCAN_MCR_FEN                 BIT(29)
  40#define FLEXCAN_MCR_HALT                BIT(28)
  41#define FLEXCAN_MCR_NOT_RDY             BIT(27)
  42#define FLEXCAN_MCR_WAK_MSK             BIT(26)
  43#define FLEXCAN_MCR_SOFTRST             BIT(25)
  44#define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  45#define FLEXCAN_MCR_SUPV                BIT(23)
  46#define FLEXCAN_MCR_SLF_WAK             BIT(22)
  47#define FLEXCAN_MCR_WRN_EN              BIT(21)
  48#define FLEXCAN_MCR_LPM_ACK             BIT(20)
  49#define FLEXCAN_MCR_WAK_SRC             BIT(19)
  50#define FLEXCAN_MCR_DOZE                BIT(18)
  51#define FLEXCAN_MCR_SRX_DIS             BIT(17)
  52#define FLEXCAN_MCR_IRMQ                BIT(16)
  53#define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  54#define FLEXCAN_MCR_AEN                 BIT(12)
  55/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
  56#define FLEXCAN_MCR_MAXMB(x)            ((x) & 0x7f)
  57#define FLEXCAN_MCR_IDAM_A              (0x0 << 8)
  58#define FLEXCAN_MCR_IDAM_B              (0x1 << 8)
  59#define FLEXCAN_MCR_IDAM_C              (0x2 << 8)
  60#define FLEXCAN_MCR_IDAM_D              (0x3 << 8)
  61
  62/* FLEXCAN control register (CANCTRL) bits */
  63#define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  64#define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  65#define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  66#define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  67#define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  68#define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  69#define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  70#define FLEXCAN_CTRL_LPB                BIT(12)
  71#define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  72#define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  73#define FLEXCAN_CTRL_SMP                BIT(7)
  74#define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  75#define FLEXCAN_CTRL_TSYN               BIT(5)
  76#define FLEXCAN_CTRL_LBUF               BIT(4)
  77#define FLEXCAN_CTRL_LOM                BIT(3)
  78#define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  79#define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  80#define FLEXCAN_CTRL_ERR_STATE \
  81        (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  82         FLEXCAN_CTRL_BOFF_MSK)
  83#define FLEXCAN_CTRL_ERR_ALL \
  84        (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  85
  86/* FLEXCAN control register 2 (CTRL2) bits */
  87#define FLEXCAN_CTRL2_ECRWRE            BIT(29)
  88#define FLEXCAN_CTRL2_WRMFRZ            BIT(28)
  89#define FLEXCAN_CTRL2_RFFN(x)           (((x) & 0x0f) << 24)
  90#define FLEXCAN_CTRL2_TASD(x)           (((x) & 0x1f) << 19)
  91#define FLEXCAN_CTRL2_MRP               BIT(18)
  92#define FLEXCAN_CTRL2_RRS               BIT(17)
  93#define FLEXCAN_CTRL2_EACEN             BIT(16)
  94
  95/* FLEXCAN memory error control register (MECR) bits */
  96#define FLEXCAN_MECR_ECRWRDIS           BIT(31)
  97#define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
  98#define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
  99#define FLEXCAN_MECR_CEI_MSK            BIT(16)
 100#define FLEXCAN_MECR_HAERRIE            BIT(15)
 101#define FLEXCAN_MECR_FAERRIE            BIT(14)
 102#define FLEXCAN_MECR_EXTERRIE           BIT(13)
 103#define FLEXCAN_MECR_RERRDIS            BIT(9)
 104#define FLEXCAN_MECR_ECCDIS             BIT(8)
 105#define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
 106
 107/* FLEXCAN error and status register (ESR) bits */
 108#define FLEXCAN_ESR_TWRN_INT            BIT(17)
 109#define FLEXCAN_ESR_RWRN_INT            BIT(16)
 110#define FLEXCAN_ESR_BIT1_ERR            BIT(15)
 111#define FLEXCAN_ESR_BIT0_ERR            BIT(14)
 112#define FLEXCAN_ESR_ACK_ERR             BIT(13)
 113#define FLEXCAN_ESR_CRC_ERR             BIT(12)
 114#define FLEXCAN_ESR_FRM_ERR             BIT(11)
 115#define FLEXCAN_ESR_STF_ERR             BIT(10)
 116#define FLEXCAN_ESR_TX_WRN              BIT(9)
 117#define FLEXCAN_ESR_RX_WRN              BIT(8)
 118#define FLEXCAN_ESR_IDLE                BIT(7)
 119#define FLEXCAN_ESR_TXRX                BIT(6)
 120#define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 121#define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 122#define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 123#define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 124#define FLEXCAN_ESR_BOFF_INT            BIT(2)
 125#define FLEXCAN_ESR_ERR_INT             BIT(1)
 126#define FLEXCAN_ESR_WAK_INT             BIT(0)
 127#define FLEXCAN_ESR_ERR_BUS \
 128        (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 129         FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 130         FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 131#define FLEXCAN_ESR_ERR_STATE \
 132        (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 133#define FLEXCAN_ESR_ERR_ALL \
 134        (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 135#define FLEXCAN_ESR_ALL_INT \
 136        (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 137         FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
 138         FLEXCAN_ESR_WAK_INT)
 139
 140/* FLEXCAN interrupt flag register (IFLAG) bits */
 141/* Errata ERR005829 step7: Reserve first valid MB */
 142#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO         8
 143#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP    0
 144#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST       (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
 145#define FLEXCAN_IFLAG_MB(x)             BIT((x) & 0x1f)
 146#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 147#define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 148#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 149
 150/* FLEXCAN message buffers */
 151#define FLEXCAN_MB_CODE_MASK            (0xf << 24)
 152#define FLEXCAN_MB_CODE_RX_BUSY_BIT     (0x1 << 24)
 153#define FLEXCAN_MB_CODE_RX_INACTIVE     (0x0 << 24)
 154#define FLEXCAN_MB_CODE_RX_EMPTY        (0x4 << 24)
 155#define FLEXCAN_MB_CODE_RX_FULL         (0x2 << 24)
 156#define FLEXCAN_MB_CODE_RX_OVERRUN      (0x6 << 24)
 157#define FLEXCAN_MB_CODE_RX_RANSWER      (0xa << 24)
 158
 159#define FLEXCAN_MB_CODE_TX_INACTIVE     (0x8 << 24)
 160#define FLEXCAN_MB_CODE_TX_ABORT        (0x9 << 24)
 161#define FLEXCAN_MB_CODE_TX_DATA         (0xc << 24)
 162#define FLEXCAN_MB_CODE_TX_TANSWER      (0xe << 24)
 163
 164#define FLEXCAN_MB_CNT_SRR              BIT(22)
 165#define FLEXCAN_MB_CNT_IDE              BIT(21)
 166#define FLEXCAN_MB_CNT_RTR              BIT(20)
 167#define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 168#define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 169
 170#define FLEXCAN_TIMEOUT_US              (250)
 171
 172/* FLEXCAN hardware feature flags
 173 *
 174 * Below is some version info we got:
 175 *    SOC   Version   IP-Version  Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
 176 *                                Filter? connected?  Passive detection  ception in MB
 177 *   MX25  FlexCAN2  03.00.00.00     no        no        no       no        no
 178 *   MX28  FlexCAN2  03.00.04.00    yes       yes        no       no        no
 179 *   MX35  FlexCAN2  03.00.00.00     no        no        no       no        no
 180 *   MX53  FlexCAN2  03.00.00.00    yes        no        no       no        no
 181 *   MX6s  FlexCAN3  10.00.12.00    yes       yes        no       no       yes
 182 *   VF610 FlexCAN3  ?               no       yes        no      yes       yes?
 183 * LS1021A FlexCAN2  03.00.04.00     no       yes        no       no       yes
 184 *
 185 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
 186 */
 187#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
 188#define FLEXCAN_QUIRK_DISABLE_RXFG      BIT(2) /* Disable RX FIFO Global mask */
 189#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
 190#define FLEXCAN_QUIRK_DISABLE_MECR      BIT(4) /* Disable Memory error detection */
 191#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
 192#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
 193#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN        BIT(7) /* default to BE register access */
 194#define FLEXCAN_QUIRK_SETUP_STOP_MODE           BIT(8) /* Setup stop mode to support wakeup */
 195
 196/* Structure of the message buffer */
 197struct flexcan_mb {
 198        u32 can_ctrl;
 199        u32 can_id;
 200        u32 data[];
 201};
 202
 203/* Structure of the hardware registers */
 204struct flexcan_regs {
 205        u32 mcr;                /* 0x00 */
 206        u32 ctrl;               /* 0x04 */
 207        u32 timer;              /* 0x08 */
 208        u32 _reserved1;         /* 0x0c */
 209        u32 rxgmask;            /* 0x10 */
 210        u32 rx14mask;           /* 0x14 */
 211        u32 rx15mask;           /* 0x18 */
 212        u32 ecr;                /* 0x1c */
 213        u32 esr;                /* 0x20 */
 214        u32 imask2;             /* 0x24 */
 215        u32 imask1;             /* 0x28 */
 216        u32 iflag2;             /* 0x2c */
 217        u32 iflag1;             /* 0x30 */
 218        union {                 /* 0x34 */
 219                u32 gfwr_mx28;  /* MX28, MX53 */
 220                u32 ctrl2;      /* MX6, VF610 */
 221        };
 222        u32 esr2;               /* 0x38 */
 223        u32 imeur;              /* 0x3c */
 224        u32 lrfr;               /* 0x40 */
 225        u32 crcr;               /* 0x44 */
 226        u32 rxfgmask;           /* 0x48 */
 227        u32 rxfir;              /* 0x4c */
 228        u32 _reserved3[12];     /* 0x50 */
 229        u8 mb[2][512];          /* 0x80 */
 230        /* FIFO-mode:
 231         *                      MB
 232         * 0x080...0x08f        0       RX message buffer
 233         * 0x090...0x0df        1-5     reserverd
 234         * 0x0e0...0x0ff        6-7     8 entry ID table
 235         *                              (mx25, mx28, mx35, mx53)
 236         * 0x0e0...0x2df        6-7..37 8..128 entry ID table
 237         *                              size conf'ed via ctrl2::RFFN
 238         *                              (mx6, vf610)
 239         */
 240        u32 _reserved4[256];    /* 0x480 */
 241        u32 rximr[64];          /* 0x880 */
 242        u32 _reserved5[24];     /* 0x980 */
 243        u32 gfwr_mx6;           /* 0x9e0 - MX6 */
 244        u32 _reserved6[63];     /* 0x9e4 */
 245        u32 mecr;               /* 0xae0 */
 246        u32 erriar;             /* 0xae4 */
 247        u32 erridpr;            /* 0xae8 */
 248        u32 errippr;            /* 0xaec */
 249        u32 rerrar;             /* 0xaf0 */
 250        u32 rerrdr;             /* 0xaf4 */
 251        u32 rerrsynr;           /* 0xaf8 */
 252        u32 errsr;              /* 0xafc */
 253};
 254
 255struct flexcan_devtype_data {
 256        u32 quirks;             /* quirks needed for different IP cores */
 257};
 258
 259struct flexcan_stop_mode {
 260        struct regmap *gpr;
 261        u8 req_gpr;
 262        u8 req_bit;
 263        u8 ack_gpr;
 264        u8 ack_bit;
 265};
 266
 267struct flexcan_priv {
 268        struct can_priv can;
 269        struct can_rx_offload offload;
 270        struct device *dev;
 271
 272        struct flexcan_regs __iomem *regs;
 273        struct flexcan_mb __iomem *tx_mb;
 274        struct flexcan_mb __iomem *tx_mb_reserved;
 275        u8 tx_mb_idx;
 276        u8 mb_count;
 277        u8 mb_size;
 278        u8 clk_src;     /* clock source of CAN Protocol Engine */
 279
 280        u32 reg_ctrl_default;
 281        u32 reg_imask1_default;
 282        u32 reg_imask2_default;
 283
 284        struct clk *clk_ipg;
 285        struct clk *clk_per;
 286        const struct flexcan_devtype_data *devtype_data;
 287        struct regulator *reg_xceiver;
 288        struct flexcan_stop_mode stm;
 289
 290        /* Read and Write APIs */
 291        u32 (*read)(void __iomem *addr);
 292        void (*write)(u32 val, void __iomem *addr);
 293};
 294
 295static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
 296        .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 297                FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 298                FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
 299};
 300
 301static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
 302        .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 303                FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 304};
 305
 306static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
 307        .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 308};
 309
 310static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
 311        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 312                FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 313                FLEXCAN_QUIRK_SETUP_STOP_MODE,
 314};
 315
 316static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
 317        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 318                FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
 319                FLEXCAN_QUIRK_BROKEN_PERR_STATE,
 320};
 321
 322static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
 323        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
 324                FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
 325                FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
 326};
 327
 328static const struct can_bittiming_const flexcan_bittiming_const = {
 329        .name = DRV_NAME,
 330        .tseg1_min = 4,
 331        .tseg1_max = 16,
 332        .tseg2_min = 2,
 333        .tseg2_max = 8,
 334        .sjw_max = 4,
 335        .brp_min = 1,
 336        .brp_max = 256,
 337        .brp_inc = 1,
 338};
 339
 340/* FlexCAN module is essentially modelled as a little-endian IP in most
 341 * SoCs, i.e the registers as well as the message buffer areas are
 342 * implemented in a little-endian fashion.
 343 *
 344 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
 345 * module in a big-endian fashion (i.e the registers as well as the
 346 * message buffer areas are implemented in a big-endian way).
 347 *
 348 * In addition, the FlexCAN module can be found on SoCs having ARM or
 349 * PPC cores. So, we need to abstract off the register read/write
 350 * functions, ensuring that these cater to all the combinations of module
 351 * endianness and underlying CPU endianness.
 352 */
 353static inline u32 flexcan_read_be(void __iomem *addr)
 354{
 355        return ioread32be(addr);
 356}
 357
 358static inline void flexcan_write_be(u32 val, void __iomem *addr)
 359{
 360        iowrite32be(val, addr);
 361}
 362
 363static inline u32 flexcan_read_le(void __iomem *addr)
 364{
 365        return ioread32(addr);
 366}
 367
 368static inline void flexcan_write_le(u32 val, void __iomem *addr)
 369{
 370        iowrite32(val, addr);
 371}
 372
 373static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
 374                                                 u8 mb_index)
 375{
 376        u8 bank_size;
 377        bool bank;
 378
 379        if (WARN_ON(mb_index >= priv->mb_count))
 380                return NULL;
 381
 382        bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
 383
 384        bank = mb_index >= bank_size;
 385        if (bank)
 386                mb_index -= bank_size;
 387
 388        return (struct flexcan_mb __iomem *)
 389                (&priv->regs->mb[bank][priv->mb_size * mb_index]);
 390}
 391
 392static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
 393{
 394        struct flexcan_regs __iomem *regs = priv->regs;
 395        u32 reg_mcr;
 396
 397        reg_mcr = priv->read(&regs->mcr);
 398
 399        if (enable)
 400                reg_mcr |= FLEXCAN_MCR_WAK_MSK;
 401        else
 402                reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
 403
 404        priv->write(reg_mcr, &regs->mcr);
 405}
 406
 407static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
 408{
 409        struct flexcan_regs __iomem *regs = priv->regs;
 410        unsigned int ackval;
 411        u32 reg_mcr;
 412
 413        reg_mcr = priv->read(&regs->mcr);
 414        reg_mcr |= FLEXCAN_MCR_SLF_WAK;
 415        priv->write(reg_mcr, &regs->mcr);
 416
 417        /* enable stop request */
 418        regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 419                           1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
 420
 421        /* get stop acknowledgment */
 422        if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
 423                                     ackval, ackval & (1 << priv->stm.ack_bit),
 424                                     0, FLEXCAN_TIMEOUT_US))
 425                return -ETIMEDOUT;
 426
 427        return 0;
 428}
 429
 430static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
 431{
 432        struct flexcan_regs __iomem *regs = priv->regs;
 433        unsigned int ackval;
 434        u32 reg_mcr;
 435
 436        /* remove stop request */
 437        regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
 438                           1 << priv->stm.req_bit, 0);
 439
 440        /* get stop acknowledgment */
 441        if (regmap_read_poll_timeout(priv->stm.gpr, priv->stm.ack_gpr,
 442                                     ackval, !(ackval & (1 << priv->stm.ack_bit)),
 443                                     0, FLEXCAN_TIMEOUT_US))
 444                return -ETIMEDOUT;
 445
 446        reg_mcr = priv->read(&regs->mcr);
 447        reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
 448        priv->write(reg_mcr, &regs->mcr);
 449
 450        return 0;
 451}
 452
 453static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
 454{
 455        struct flexcan_regs __iomem *regs = priv->regs;
 456        u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
 457
 458        priv->write(reg_ctrl, &regs->ctrl);
 459}
 460
 461static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
 462{
 463        struct flexcan_regs __iomem *regs = priv->regs;
 464        u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
 465
 466        priv->write(reg_ctrl, &regs->ctrl);
 467}
 468
 469static int flexcan_clks_enable(const struct flexcan_priv *priv)
 470{
 471        int err;
 472
 473        err = clk_prepare_enable(priv->clk_ipg);
 474        if (err)
 475                return err;
 476
 477        err = clk_prepare_enable(priv->clk_per);
 478        if (err)
 479                clk_disable_unprepare(priv->clk_ipg);
 480
 481        return err;
 482}
 483
 484static void flexcan_clks_disable(const struct flexcan_priv *priv)
 485{
 486        clk_disable_unprepare(priv->clk_per);
 487        clk_disable_unprepare(priv->clk_ipg);
 488}
 489
 490static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
 491{
 492        if (!priv->reg_xceiver)
 493                return 0;
 494
 495        return regulator_enable(priv->reg_xceiver);
 496}
 497
 498static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
 499{
 500        if (!priv->reg_xceiver)
 501                return 0;
 502
 503        return regulator_disable(priv->reg_xceiver);
 504}
 505
 506static int flexcan_chip_enable(struct flexcan_priv *priv)
 507{
 508        struct flexcan_regs __iomem *regs = priv->regs;
 509        unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 510        u32 reg;
 511
 512        reg = priv->read(&regs->mcr);
 513        reg &= ~FLEXCAN_MCR_MDIS;
 514        priv->write(reg, &regs->mcr);
 515
 516        while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 517                udelay(10);
 518
 519        if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
 520                return -ETIMEDOUT;
 521
 522        return 0;
 523}
 524
 525static int flexcan_chip_disable(struct flexcan_priv *priv)
 526{
 527        struct flexcan_regs __iomem *regs = priv->regs;
 528        unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 529        u32 reg;
 530
 531        reg = priv->read(&regs->mcr);
 532        reg |= FLEXCAN_MCR_MDIS;
 533        priv->write(reg, &regs->mcr);
 534
 535        while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 536                udelay(10);
 537
 538        if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
 539                return -ETIMEDOUT;
 540
 541        return 0;
 542}
 543
 544static int flexcan_chip_freeze(struct flexcan_priv *priv)
 545{
 546        struct flexcan_regs __iomem *regs = priv->regs;
 547        unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
 548        u32 reg;
 549
 550        reg = priv->read(&regs->mcr);
 551        reg |= FLEXCAN_MCR_HALT;
 552        priv->write(reg, &regs->mcr);
 553
 554        while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 555                udelay(100);
 556
 557        if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 558                return -ETIMEDOUT;
 559
 560        return 0;
 561}
 562
 563static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
 564{
 565        struct flexcan_regs __iomem *regs = priv->regs;
 566        unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 567        u32 reg;
 568
 569        reg = priv->read(&regs->mcr);
 570        reg &= ~FLEXCAN_MCR_HALT;
 571        priv->write(reg, &regs->mcr);
 572
 573        while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
 574                udelay(10);
 575
 576        if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
 577                return -ETIMEDOUT;
 578
 579        return 0;
 580}
 581
 582static int flexcan_chip_softreset(struct flexcan_priv *priv)
 583{
 584        struct flexcan_regs __iomem *regs = priv->regs;
 585        unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
 586
 587        priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 588        while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
 589                udelay(10);
 590
 591        if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
 592                return -ETIMEDOUT;
 593
 594        return 0;
 595}
 596
 597static int __flexcan_get_berr_counter(const struct net_device *dev,
 598                                      struct can_berr_counter *bec)
 599{
 600        const struct flexcan_priv *priv = netdev_priv(dev);
 601        struct flexcan_regs __iomem *regs = priv->regs;
 602        u32 reg = priv->read(&regs->ecr);
 603
 604        bec->txerr = (reg >> 0) & 0xff;
 605        bec->rxerr = (reg >> 8) & 0xff;
 606
 607        return 0;
 608}
 609
 610static int flexcan_get_berr_counter(const struct net_device *dev,
 611                                    struct can_berr_counter *bec)
 612{
 613        const struct flexcan_priv *priv = netdev_priv(dev);
 614        int err;
 615
 616        err = pm_runtime_get_sync(priv->dev);
 617        if (err < 0)
 618                return err;
 619
 620        err = __flexcan_get_berr_counter(dev, bec);
 621
 622        pm_runtime_put(priv->dev);
 623
 624        return err;
 625}
 626
 627static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 628{
 629        const struct flexcan_priv *priv = netdev_priv(dev);
 630        struct can_frame *cf = (struct can_frame *)skb->data;
 631        u32 can_id;
 632        u32 data;
 633        u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
 634        int i;
 635
 636        if (can_dropped_invalid_skb(dev, skb))
 637                return NETDEV_TX_OK;
 638
 639        netif_stop_queue(dev);
 640
 641        if (cf->can_id & CAN_EFF_FLAG) {
 642                can_id = cf->can_id & CAN_EFF_MASK;
 643                ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 644        } else {
 645                can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 646        }
 647
 648        if (cf->can_id & CAN_RTR_FLAG)
 649                ctrl |= FLEXCAN_MB_CNT_RTR;
 650
 651        for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 652                data = be32_to_cpup((__be32 *)&cf->data[i]);
 653                priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
 654        }
 655
 656        can_put_echo_skb(skb, dev, 0);
 657
 658        priv->write(can_id, &priv->tx_mb->can_id);
 659        priv->write(ctrl, &priv->tx_mb->can_ctrl);
 660
 661        /* Errata ERR005829 step8:
 662         * Write twice INACTIVE(0x8) code to first MB.
 663         */
 664        priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 665                    &priv->tx_mb_reserved->can_ctrl);
 666        priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 667                    &priv->tx_mb_reserved->can_ctrl);
 668
 669        return NETDEV_TX_OK;
 670}
 671
 672static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
 673{
 674        struct flexcan_priv *priv = netdev_priv(dev);
 675        struct flexcan_regs __iomem *regs = priv->regs;
 676        struct sk_buff *skb;
 677        struct can_frame *cf;
 678        bool rx_errors = false, tx_errors = false;
 679        u32 timestamp;
 680        int err;
 681
 682        timestamp = priv->read(&regs->timer) << 16;
 683
 684        skb = alloc_can_err_skb(dev, &cf);
 685        if (unlikely(!skb))
 686                return;
 687
 688        cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 689
 690        if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 691                netdev_dbg(dev, "BIT1_ERR irq\n");
 692                cf->data[2] |= CAN_ERR_PROT_BIT1;
 693                tx_errors = true;
 694        }
 695        if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 696                netdev_dbg(dev, "BIT0_ERR irq\n");
 697                cf->data[2] |= CAN_ERR_PROT_BIT0;
 698                tx_errors = true;
 699        }
 700        if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 701                netdev_dbg(dev, "ACK_ERR irq\n");
 702                cf->can_id |= CAN_ERR_ACK;
 703                cf->data[3] = CAN_ERR_PROT_LOC_ACK;
 704                tx_errors = true;
 705        }
 706        if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 707                netdev_dbg(dev, "CRC_ERR irq\n");
 708                cf->data[2] |= CAN_ERR_PROT_BIT;
 709                cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
 710                rx_errors = true;
 711        }
 712        if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 713                netdev_dbg(dev, "FRM_ERR irq\n");
 714                cf->data[2] |= CAN_ERR_PROT_FORM;
 715                rx_errors = true;
 716        }
 717        if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 718                netdev_dbg(dev, "STF_ERR irq\n");
 719                cf->data[2] |= CAN_ERR_PROT_STUFF;
 720                rx_errors = true;
 721        }
 722
 723        priv->can.can_stats.bus_error++;
 724        if (rx_errors)
 725                dev->stats.rx_errors++;
 726        if (tx_errors)
 727                dev->stats.tx_errors++;
 728
 729        err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 730        if (err)
 731                dev->stats.rx_fifo_errors++;
 732}
 733
 734static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
 735{
 736        struct flexcan_priv *priv = netdev_priv(dev);
 737        struct flexcan_regs __iomem *regs = priv->regs;
 738        struct sk_buff *skb;
 739        struct can_frame *cf;
 740        enum can_state new_state, rx_state, tx_state;
 741        int flt;
 742        struct can_berr_counter bec;
 743        u32 timestamp;
 744        int err;
 745
 746        timestamp = priv->read(&regs->timer) << 16;
 747
 748        flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 749        if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 750                tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
 751                        CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 752                rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
 753                        CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
 754                new_state = max(tx_state, rx_state);
 755        } else {
 756                __flexcan_get_berr_counter(dev, &bec);
 757                new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
 758                        CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
 759                rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
 760                tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
 761        }
 762
 763        /* state hasn't changed */
 764        if (likely(new_state == priv->can.state))
 765                return;
 766
 767        skb = alloc_can_err_skb(dev, &cf);
 768        if (unlikely(!skb))
 769                return;
 770
 771        can_change_state(dev, cf, tx_state, rx_state);
 772
 773        if (unlikely(new_state == CAN_STATE_BUS_OFF))
 774                can_bus_off(dev);
 775
 776        err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
 777        if (err)
 778                dev->stats.rx_fifo_errors++;
 779}
 780
 781static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
 782{
 783        return container_of(offload, struct flexcan_priv, offload);
 784}
 785
 786static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
 787                                         struct can_frame *cf,
 788                                         u32 *timestamp, unsigned int n)
 789{
 790        struct flexcan_priv *priv = rx_offload_to_priv(offload);
 791        struct flexcan_regs __iomem *regs = priv->regs;
 792        struct flexcan_mb __iomem *mb;
 793        u32 reg_ctrl, reg_id, reg_iflag1;
 794        int i;
 795
 796        mb = flexcan_get_mb(priv, n);
 797
 798        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 799                u32 code;
 800
 801                do {
 802                        reg_ctrl = priv->read(&mb->can_ctrl);
 803                } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
 804
 805                /* is this MB empty? */
 806                code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
 807                if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
 808                    (code != FLEXCAN_MB_CODE_RX_OVERRUN))
 809                        return 0;
 810
 811                if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
 812                        /* This MB was overrun, we lost data */
 813                        offload->dev->stats.rx_over_errors++;
 814                        offload->dev->stats.rx_errors++;
 815                }
 816        } else {
 817                reg_iflag1 = priv->read(&regs->iflag1);
 818                if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
 819                        return 0;
 820
 821                reg_ctrl = priv->read(&mb->can_ctrl);
 822        }
 823
 824        /* increase timstamp to full 32 bit */
 825        *timestamp = reg_ctrl << 16;
 826
 827        reg_id = priv->read(&mb->can_id);
 828        if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 829                cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 830        else
 831                cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 832
 833        if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 834                cf->can_id |= CAN_RTR_FLAG;
 835        cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 836
 837        for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
 838                __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
 839                *(__be32 *)(cf->data + i) = data;
 840        }
 841
 842        /* mark as read */
 843        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 844                /* Clear IRQ */
 845                if (n < 32)
 846                        priv->write(BIT(n), &regs->iflag1);
 847                else
 848                        priv->write(BIT(n - 32), &regs->iflag2);
 849        } else {
 850                priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 851        }
 852
 853        /* Read the Free Running Timer. It is optional but recommended
 854         * to unlock Mailbox as soon as possible and make it available
 855         * for reception.
 856         */
 857        priv->read(&regs->timer);
 858
 859        return 1;
 860}
 861
 862
 863static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
 864{
 865        struct flexcan_regs __iomem *regs = priv->regs;
 866        u32 iflag1, iflag2;
 867
 868        iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
 869                ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
 870        iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
 871
 872        return (u64)iflag2 << 32 | iflag1;
 873}
 874
 875static irqreturn_t flexcan_irq(int irq, void *dev_id)
 876{
 877        struct net_device *dev = dev_id;
 878        struct net_device_stats *stats = &dev->stats;
 879        struct flexcan_priv *priv = netdev_priv(dev);
 880        struct flexcan_regs __iomem *regs = priv->regs;
 881        irqreturn_t handled = IRQ_NONE;
 882        u32 reg_iflag2, reg_esr;
 883        enum can_state last_state = priv->can.state;
 884
 885        /* reception interrupt */
 886        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
 887                u64 reg_iflag;
 888                int ret;
 889
 890                while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
 891                        handled = IRQ_HANDLED;
 892                        ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
 893                                                                   reg_iflag);
 894                        if (!ret)
 895                                break;
 896                }
 897        } else {
 898                u32 reg_iflag1;
 899
 900                reg_iflag1 = priv->read(&regs->iflag1);
 901                if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
 902                        handled = IRQ_HANDLED;
 903                        can_rx_offload_irq_offload_fifo(&priv->offload);
 904                }
 905
 906                /* FIFO overflow interrupt */
 907                if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 908                        handled = IRQ_HANDLED;
 909                        priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
 910                                    &regs->iflag1);
 911                        dev->stats.rx_over_errors++;
 912                        dev->stats.rx_errors++;
 913                }
 914        }
 915
 916        reg_iflag2 = priv->read(&regs->iflag2);
 917
 918        /* transmission complete interrupt */
 919        if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
 920                u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
 921
 922                handled = IRQ_HANDLED;
 923                stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
 924                                                               0, reg_ctrl << 16);
 925                stats->tx_packets++;
 926                can_led_event(dev, CAN_LED_EVENT_TX);
 927
 928                /* after sending a RTR frame MB is in RX mode */
 929                priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
 930                            &priv->tx_mb->can_ctrl);
 931                priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
 932                netif_wake_queue(dev);
 933        }
 934
 935        reg_esr = priv->read(&regs->esr);
 936
 937        /* ACK all bus error and state change IRQ sources */
 938        if (reg_esr & FLEXCAN_ESR_ALL_INT) {
 939                handled = IRQ_HANDLED;
 940                priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 941        }
 942
 943        /* state change interrupt or broken error state quirk fix is enabled */
 944        if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 945            (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
 946                                           FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
 947                flexcan_irq_state(dev, reg_esr);
 948
 949        /* bus error IRQ - handle if bus error reporting is activated */
 950        if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
 951            (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
 952                flexcan_irq_bus_err(dev, reg_esr);
 953
 954        /* availability of error interrupt among state transitions in case
 955         * bus error reporting is de-activated and
 956         * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
 957         *  +--------------------------------------------------------------+
 958         *  | +----------------------------------------------+ [stopped /  |
 959         *  | |                                              |  sleeping] -+
 960         *  +-+-> active <-> warning <-> passive -> bus off -+
 961         *        ___________^^^^^^^^^^^^_______________________________
 962         *        disabled(1)  enabled             disabled
 963         *
 964         * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
 965         */
 966        if ((last_state != priv->can.state) &&
 967            (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
 968            !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
 969                switch (priv->can.state) {
 970                case CAN_STATE_ERROR_ACTIVE:
 971                        if (priv->devtype_data->quirks &
 972                            FLEXCAN_QUIRK_BROKEN_WERR_STATE)
 973                                flexcan_error_irq_enable(priv);
 974                        else
 975                                flexcan_error_irq_disable(priv);
 976                        break;
 977
 978                case CAN_STATE_ERROR_WARNING:
 979                        flexcan_error_irq_enable(priv);
 980                        break;
 981
 982                case CAN_STATE_ERROR_PASSIVE:
 983                case CAN_STATE_BUS_OFF:
 984                        flexcan_error_irq_disable(priv);
 985                        break;
 986
 987                default:
 988                        break;
 989                }
 990        }
 991
 992        return handled;
 993}
 994
 995static void flexcan_set_bittiming(struct net_device *dev)
 996{
 997        const struct flexcan_priv *priv = netdev_priv(dev);
 998        const struct can_bittiming *bt = &priv->can.bittiming;
 999        struct flexcan_regs __iomem *regs = priv->regs;
1000        u32 reg;
1001
1002        reg = priv->read(&regs->ctrl);
1003        reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1004                 FLEXCAN_CTRL_RJW(0x3) |
1005                 FLEXCAN_CTRL_PSEG1(0x7) |
1006                 FLEXCAN_CTRL_PSEG2(0x7) |
1007                 FLEXCAN_CTRL_PROPSEG(0x7) |
1008                 FLEXCAN_CTRL_LPB |
1009                 FLEXCAN_CTRL_SMP |
1010                 FLEXCAN_CTRL_LOM);
1011
1012        reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1013                FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1014                FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1015                FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1016                FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1017
1018        if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1019                reg |= FLEXCAN_CTRL_LPB;
1020        if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1021                reg |= FLEXCAN_CTRL_LOM;
1022        if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1023                reg |= FLEXCAN_CTRL_SMP;
1024
1025        netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
1026        priv->write(reg, &regs->ctrl);
1027
1028        /* print chip status */
1029        netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
1030                   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1031}
1032
1033/* flexcan_chip_start
1034 *
1035 * this functions is entered with clocks enabled
1036 *
1037 */
1038static int flexcan_chip_start(struct net_device *dev)
1039{
1040        struct flexcan_priv *priv = netdev_priv(dev);
1041        struct flexcan_regs __iomem *regs = priv->regs;
1042        u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1043        int err, i;
1044        struct flexcan_mb __iomem *mb;
1045
1046        /* enable module */
1047        err = flexcan_chip_enable(priv);
1048        if (err)
1049                return err;
1050
1051        /* soft reset */
1052        err = flexcan_chip_softreset(priv);
1053        if (err)
1054                goto out_chip_disable;
1055
1056        flexcan_set_bittiming(dev);
1057
1058        /* MCR
1059         *
1060         * enable freeze
1061         * halt now
1062         * only supervisor access
1063         * enable warning int
1064         * enable individual RX masking
1065         * choose format C
1066         * set max mailbox number
1067         */
1068        reg_mcr = priv->read(&regs->mcr);
1069        reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
1070        reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1071                FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1072                FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
1073
1074        /* MCR
1075         *
1076         * FIFO:
1077         * - disable for timestamp mode
1078         * - enable for FIFO mode
1079         */
1080        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1081                reg_mcr &= ~FLEXCAN_MCR_FEN;
1082        else
1083                reg_mcr |= FLEXCAN_MCR_FEN;
1084
1085        /* MCR
1086         *
1087         * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1088         *       asserted because this will impede the self reception
1089         *       of a transmitted message. This is not documented in
1090         *       earlier versions of flexcan block guide.
1091         *
1092         * Self Reception:
1093         * - enable Self Reception for loopback mode
1094         *   (by clearing "Self Reception Disable" bit)
1095         * - disable for normal operation
1096         */
1097        if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1098                reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1099        else
1100                reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1101
1102        netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
1103        priv->write(reg_mcr, &regs->mcr);
1104
1105        /* CTRL
1106         *
1107         * disable timer sync feature
1108         *
1109         * disable auto busoff recovery
1110         * transmit lowest buffer first
1111         *
1112         * enable tx and rx warning interrupt
1113         * enable bus off interrupt
1114         * (== FLEXCAN_CTRL_ERR_STATE)
1115         */
1116        reg_ctrl = priv->read(&regs->ctrl);
1117        reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1118        reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1119                FLEXCAN_CTRL_ERR_STATE;
1120
1121        /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1122         * on most Flexcan cores, too. Otherwise we don't get
1123         * any error warning or passive interrupts.
1124         */
1125        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
1126            priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1127                reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1128        else
1129                reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1130
1131        /* save for later use */
1132        priv->reg_ctrl_default = reg_ctrl;
1133        /* leave interrupts disabled for now */
1134        reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1135        netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
1136        priv->write(reg_ctrl, &regs->ctrl);
1137
1138        if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1139                reg_ctrl2 = priv->read(&regs->ctrl2);
1140                reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1141                priv->write(reg_ctrl2, &regs->ctrl2);
1142        }
1143
1144        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1145                for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1146                        mb = flexcan_get_mb(priv, i);
1147                        priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1148                                    &mb->can_ctrl);
1149                }
1150        } else {
1151                /* clear and invalidate unused mailboxes first */
1152                for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1153                        mb = flexcan_get_mb(priv, i);
1154                        priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1155                                    &mb->can_ctrl);
1156                }
1157        }
1158
1159        /* Errata ERR005829: mark first TX mailbox as INACTIVE */
1160        priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1161                    &priv->tx_mb_reserved->can_ctrl);
1162
1163        /* mark TX mailbox as INACTIVE */
1164        priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1165                    &priv->tx_mb->can_ctrl);
1166
1167        /* acceptance mask/acceptance code (accept everything) */
1168        priv->write(0x0, &regs->rxgmask);
1169        priv->write(0x0, &regs->rx14mask);
1170        priv->write(0x0, &regs->rx15mask);
1171
1172        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
1173                priv->write(0x0, &regs->rxfgmask);
1174
1175        /* clear acceptance filters */
1176        for (i = 0; i < priv->mb_count; i++)
1177                priv->write(0, &regs->rximr[i]);
1178
1179        /* On Vybrid, disable memory error detection interrupts
1180         * and freeze mode.
1181         * This also works around errata e5295 which generates
1182         * false positive memory errors and put the device in
1183         * freeze mode.
1184         */
1185        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1186                /* Follow the protocol as described in "Detection
1187                 * and Correction of Memory Errors" to write to
1188                 * MECR register
1189                 */
1190                reg_ctrl2 = priv->read(&regs->ctrl2);
1191                reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
1192                priv->write(reg_ctrl2, &regs->ctrl2);
1193
1194                reg_mecr = priv->read(&regs->mecr);
1195                reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
1196                priv->write(reg_mecr, &regs->mecr);
1197                reg_mecr |= FLEXCAN_MECR_ECCDIS;
1198                reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1199                              FLEXCAN_MECR_FANCEI_MSK);
1200                priv->write(reg_mecr, &regs->mecr);
1201        }
1202
1203        err = flexcan_transceiver_enable(priv);
1204        if (err)
1205                goto out_chip_disable;
1206
1207        /* synchronize with the can bus */
1208        err = flexcan_chip_unfreeze(priv);
1209        if (err)
1210                goto out_transceiver_disable;
1211
1212        priv->can.state = CAN_STATE_ERROR_ACTIVE;
1213
1214        /* enable interrupts atomically */
1215        disable_irq(dev->irq);
1216        priv->write(priv->reg_ctrl_default, &regs->ctrl);
1217        priv->write(priv->reg_imask1_default, &regs->imask1);
1218        priv->write(priv->reg_imask2_default, &regs->imask2);
1219        enable_irq(dev->irq);
1220
1221        /* print chip status */
1222        netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
1223                   priv->read(&regs->mcr), priv->read(&regs->ctrl));
1224
1225        return 0;
1226
1227 out_transceiver_disable:
1228        flexcan_transceiver_disable(priv);
1229 out_chip_disable:
1230        flexcan_chip_disable(priv);
1231        return err;
1232}
1233
1234/* flexcan_chip_stop
1235 *
1236 * this functions is entered with clocks enabled
1237 */
1238static void flexcan_chip_stop(struct net_device *dev)
1239{
1240        struct flexcan_priv *priv = netdev_priv(dev);
1241        struct flexcan_regs __iomem *regs = priv->regs;
1242
1243        /* freeze + disable module */
1244        flexcan_chip_freeze(priv);
1245        flexcan_chip_disable(priv);
1246
1247        /* Disable all interrupts */
1248        priv->write(0, &regs->imask2);
1249        priv->write(0, &regs->imask1);
1250        priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1251                    &regs->ctrl);
1252
1253        flexcan_transceiver_disable(priv);
1254        priv->can.state = CAN_STATE_STOPPED;
1255}
1256
1257static int flexcan_open(struct net_device *dev)
1258{
1259        struct flexcan_priv *priv = netdev_priv(dev);
1260        int err;
1261
1262        err = pm_runtime_get_sync(priv->dev);
1263        if (err < 0)
1264                return err;
1265
1266        err = open_candev(dev);
1267        if (err)
1268                goto out_runtime_put;
1269
1270        err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1271        if (err)
1272                goto out_close;
1273
1274        priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1275        priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1276                         (sizeof(priv->regs->mb[1]) / priv->mb_size);
1277
1278        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1279                priv->tx_mb_reserved =
1280                        flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1281        else
1282                priv->tx_mb_reserved =
1283                        flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1284        priv->tx_mb_idx = priv->mb_count - 1;
1285        priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1286
1287        priv->reg_imask1_default = 0;
1288        priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1289
1290        priv->offload.mailbox_read = flexcan_mailbox_read;
1291
1292        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1293                u64 imask;
1294
1295                priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1296                priv->offload.mb_last = priv->mb_count - 2;
1297
1298                imask = GENMASK_ULL(priv->offload.mb_last,
1299                                    priv->offload.mb_first);
1300                priv->reg_imask1_default |= imask;
1301                priv->reg_imask2_default |= imask >> 32;
1302
1303                err = can_rx_offload_add_timestamp(dev, &priv->offload);
1304        } else {
1305                priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1306                        FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1307                err = can_rx_offload_add_fifo(dev, &priv->offload,
1308                                              FLEXCAN_NAPI_WEIGHT);
1309        }
1310        if (err)
1311                goto out_free_irq;
1312
1313        /* start chip and queuing */
1314        err = flexcan_chip_start(dev);
1315        if (err)
1316                goto out_offload_del;
1317
1318        can_led_event(dev, CAN_LED_EVENT_OPEN);
1319
1320        can_rx_offload_enable(&priv->offload);
1321        netif_start_queue(dev);
1322
1323        return 0;
1324
1325 out_offload_del:
1326        can_rx_offload_del(&priv->offload);
1327 out_free_irq:
1328        free_irq(dev->irq, dev);
1329 out_close:
1330        close_candev(dev);
1331 out_runtime_put:
1332        pm_runtime_put(priv->dev);
1333
1334        return err;
1335}
1336
1337static int flexcan_close(struct net_device *dev)
1338{
1339        struct flexcan_priv *priv = netdev_priv(dev);
1340
1341        netif_stop_queue(dev);
1342        can_rx_offload_disable(&priv->offload);
1343        flexcan_chip_stop(dev);
1344
1345        can_rx_offload_del(&priv->offload);
1346        free_irq(dev->irq, dev);
1347
1348        close_candev(dev);
1349        pm_runtime_put(priv->dev);
1350
1351        can_led_event(dev, CAN_LED_EVENT_STOP);
1352
1353        return 0;
1354}
1355
1356static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1357{
1358        int err;
1359
1360        switch (mode) {
1361        case CAN_MODE_START:
1362                err = flexcan_chip_start(dev);
1363                if (err)
1364                        return err;
1365
1366                netif_wake_queue(dev);
1367                break;
1368
1369        default:
1370                return -EOPNOTSUPP;
1371        }
1372
1373        return 0;
1374}
1375
1376static const struct net_device_ops flexcan_netdev_ops = {
1377        .ndo_open       = flexcan_open,
1378        .ndo_stop       = flexcan_close,
1379        .ndo_start_xmit = flexcan_start_xmit,
1380        .ndo_change_mtu = can_change_mtu,
1381};
1382
1383static int register_flexcandev(struct net_device *dev)
1384{
1385        struct flexcan_priv *priv = netdev_priv(dev);
1386        struct flexcan_regs __iomem *regs = priv->regs;
1387        u32 reg, err;
1388
1389        err = flexcan_clks_enable(priv);
1390        if (err)
1391                return err;
1392
1393        /* select "bus clock", chip must be disabled */
1394        err = flexcan_chip_disable(priv);
1395        if (err)
1396                goto out_clks_disable;
1397
1398        reg = priv->read(&regs->ctrl);
1399        if (priv->clk_src)
1400                reg |= FLEXCAN_CTRL_CLK_SRC;
1401        else
1402                reg &= ~FLEXCAN_CTRL_CLK_SRC;
1403        priv->write(reg, &regs->ctrl);
1404
1405        err = flexcan_chip_enable(priv);
1406        if (err)
1407                goto out_chip_disable;
1408
1409        /* set freeze, halt and activate FIFO, restrict register access */
1410        reg = priv->read(&regs->mcr);
1411        reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1412                FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
1413        priv->write(reg, &regs->mcr);
1414
1415        /* Currently we only support newer versions of this core
1416         * featuring a RX hardware FIFO (although this driver doesn't
1417         * make use of it on some cores). Older cores, found on some
1418         * Coldfire derivates are not tested.
1419         */
1420        reg = priv->read(&regs->mcr);
1421        if (!(reg & FLEXCAN_MCR_FEN)) {
1422                netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1423                err = -ENODEV;
1424                goto out_chip_disable;
1425        }
1426
1427        err = register_candev(dev);
1428        if (err)
1429                goto out_chip_disable;
1430
1431        /* Disable core and let pm_runtime_put() disable the clocks.
1432         * If CONFIG_PM is not enabled, the clocks will stay powered.
1433         */
1434        flexcan_chip_disable(priv);
1435        pm_runtime_put(priv->dev);
1436
1437        return 0;
1438
1439 out_chip_disable:
1440        flexcan_chip_disable(priv);
1441 out_clks_disable:
1442        flexcan_clks_disable(priv);
1443        return err;
1444}
1445
1446static void unregister_flexcandev(struct net_device *dev)
1447{
1448        unregister_candev(dev);
1449}
1450
1451static int flexcan_setup_stop_mode(struct platform_device *pdev)
1452{
1453        struct net_device *dev = platform_get_drvdata(pdev);
1454        struct device_node *np = pdev->dev.of_node;
1455        struct device_node *gpr_np;
1456        struct flexcan_priv *priv;
1457        phandle phandle;
1458        u32 out_val[5];
1459        int ret;
1460
1461        if (!np)
1462                return -EINVAL;
1463
1464        /* stop mode property format is:
1465         * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1466         */
1467        ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1468                                         ARRAY_SIZE(out_val));
1469        if (ret) {
1470                dev_dbg(&pdev->dev, "no stop-mode property\n");
1471                return ret;
1472        }
1473        phandle = *out_val;
1474
1475        gpr_np = of_find_node_by_phandle(phandle);
1476        if (!gpr_np) {
1477                dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1478                return -ENODEV;
1479        }
1480
1481        priv = netdev_priv(dev);
1482        priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1483        if (IS_ERR(priv->stm.gpr)) {
1484                dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1485                ret = PTR_ERR(priv->stm.gpr);
1486                goto out_put_node;
1487        }
1488
1489        priv->stm.req_gpr = out_val[1];
1490        priv->stm.req_bit = out_val[2];
1491        priv->stm.ack_gpr = out_val[3];
1492        priv->stm.ack_bit = out_val[4];
1493
1494        dev_dbg(&pdev->dev,
1495                "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1496                gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1497                priv->stm.ack_gpr, priv->stm.ack_bit);
1498
1499        device_set_wakeup_capable(&pdev->dev, true);
1500
1501        if (of_property_read_bool(np, "wakeup-source"))
1502                device_set_wakeup_enable(&pdev->dev, true);
1503
1504        return 0;
1505
1506out_put_node:
1507        of_node_put(gpr_np);
1508        return ret;
1509}
1510
1511static const struct of_device_id flexcan_of_match[] = {
1512        { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1513        { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1514        { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1515        { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1516        { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1517        { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1518        { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1519        { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1520        { /* sentinel */ },
1521};
1522MODULE_DEVICE_TABLE(of, flexcan_of_match);
1523
1524static const struct platform_device_id flexcan_id_table[] = {
1525        { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1526        { /* sentinel */ },
1527};
1528MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1529
1530static int flexcan_probe(struct platform_device *pdev)
1531{
1532        const struct of_device_id *of_id;
1533        const struct flexcan_devtype_data *devtype_data;
1534        struct net_device *dev;
1535        struct flexcan_priv *priv;
1536        struct regulator *reg_xceiver;
1537        struct resource *mem;
1538        struct clk *clk_ipg = NULL, *clk_per = NULL;
1539        struct flexcan_regs __iomem *regs;
1540        int err, irq;
1541        u8 clk_src = 1;
1542        u32 clock_freq = 0;
1543
1544        reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1545        if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1546                return -EPROBE_DEFER;
1547        else if (IS_ERR(reg_xceiver))
1548                reg_xceiver = NULL;
1549
1550        if (pdev->dev.of_node) {
1551                of_property_read_u32(pdev->dev.of_node,
1552                                     "clock-frequency", &clock_freq);
1553                of_property_read_u8(pdev->dev.of_node,
1554                                    "fsl,clk-source", &clk_src);
1555        }
1556
1557        if (!clock_freq) {
1558                clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1559                if (IS_ERR(clk_ipg)) {
1560                        dev_err(&pdev->dev, "no ipg clock defined\n");
1561                        return PTR_ERR(clk_ipg);
1562                }
1563
1564                clk_per = devm_clk_get(&pdev->dev, "per");
1565                if (IS_ERR(clk_per)) {
1566                        dev_err(&pdev->dev, "no per clock defined\n");
1567                        return PTR_ERR(clk_per);
1568                }
1569                clock_freq = clk_get_rate(clk_per);
1570        }
1571
1572        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1573        irq = platform_get_irq(pdev, 0);
1574        if (irq <= 0)
1575                return -ENODEV;
1576
1577        regs = devm_ioremap_resource(&pdev->dev, mem);
1578        if (IS_ERR(regs))
1579                return PTR_ERR(regs);
1580
1581        of_id = of_match_device(flexcan_of_match, &pdev->dev);
1582        if (of_id) {
1583                devtype_data = of_id->data;
1584        } else if (platform_get_device_id(pdev)->driver_data) {
1585                devtype_data = (struct flexcan_devtype_data *)
1586                        platform_get_device_id(pdev)->driver_data;
1587        } else {
1588                return -ENODEV;
1589        }
1590
1591        dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1592        if (!dev)
1593                return -ENOMEM;
1594
1595        platform_set_drvdata(pdev, dev);
1596        SET_NETDEV_DEV(dev, &pdev->dev);
1597
1598        dev->netdev_ops = &flexcan_netdev_ops;
1599        dev->irq = irq;
1600        dev->flags |= IFF_ECHO;
1601
1602        priv = netdev_priv(dev);
1603
1604        if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1605            devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1606                priv->read = flexcan_read_be;
1607                priv->write = flexcan_write_be;
1608        } else {
1609                priv->read = flexcan_read_le;
1610                priv->write = flexcan_write_le;
1611        }
1612
1613        priv->dev = &pdev->dev;
1614        priv->can.clock.freq = clock_freq;
1615        priv->can.bittiming_const = &flexcan_bittiming_const;
1616        priv->can.do_set_mode = flexcan_set_mode;
1617        priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1618        priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1619                CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1620                CAN_CTRLMODE_BERR_REPORTING;
1621        priv->regs = regs;
1622        priv->clk_ipg = clk_ipg;
1623        priv->clk_per = clk_per;
1624        priv->clk_src = clk_src;
1625        priv->devtype_data = devtype_data;
1626        priv->reg_xceiver = reg_xceiver;
1627
1628        pm_runtime_get_noresume(&pdev->dev);
1629        pm_runtime_set_active(&pdev->dev);
1630        pm_runtime_enable(&pdev->dev);
1631
1632        err = register_flexcandev(dev);
1633        if (err) {
1634                dev_err(&pdev->dev, "registering netdev failed\n");
1635                goto failed_register;
1636        }
1637
1638        devm_can_led_init(dev);
1639
1640        if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1641                err = flexcan_setup_stop_mode(pdev);
1642                if (err)
1643                        dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1644        }
1645
1646        return 0;
1647
1648 failed_register:
1649        free_candev(dev);
1650        return err;
1651}
1652
1653static int flexcan_remove(struct platform_device *pdev)
1654{
1655        struct net_device *dev = platform_get_drvdata(pdev);
1656
1657        unregister_flexcandev(dev);
1658        pm_runtime_disable(&pdev->dev);
1659        free_candev(dev);
1660
1661        return 0;
1662}
1663
1664static int __maybe_unused flexcan_suspend(struct device *device)
1665{
1666        struct net_device *dev = dev_get_drvdata(device);
1667        struct flexcan_priv *priv = netdev_priv(dev);
1668        int err = 0;
1669
1670        if (netif_running(dev)) {
1671                /* if wakeup is enabled, enter stop mode
1672                 * else enter disabled mode.
1673                 */
1674                if (device_may_wakeup(device)) {
1675                        enable_irq_wake(dev->irq);
1676                        err = flexcan_enter_stop_mode(priv);
1677                        if (err)
1678                                return err;
1679                } else {
1680                        err = flexcan_chip_disable(priv);
1681                        if (err)
1682                                return err;
1683
1684                        err = pm_runtime_force_suspend(device);
1685                }
1686                netif_stop_queue(dev);
1687                netif_device_detach(dev);
1688        }
1689        priv->can.state = CAN_STATE_SLEEPING;
1690
1691        return err;
1692}
1693
1694static int __maybe_unused flexcan_resume(struct device *device)
1695{
1696        struct net_device *dev = dev_get_drvdata(device);
1697        struct flexcan_priv *priv = netdev_priv(dev);
1698        int err = 0;
1699
1700        priv->can.state = CAN_STATE_ERROR_ACTIVE;
1701        if (netif_running(dev)) {
1702                netif_device_attach(dev);
1703                netif_start_queue(dev);
1704                if (device_may_wakeup(device)) {
1705                        disable_irq_wake(dev->irq);
1706                } else {
1707                        err = pm_runtime_force_resume(device);
1708                        if (err)
1709                                return err;
1710
1711                        err = flexcan_chip_enable(priv);
1712                }
1713        }
1714
1715        return err;
1716}
1717
1718static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1719{
1720        struct net_device *dev = dev_get_drvdata(device);
1721        struct flexcan_priv *priv = netdev_priv(dev);
1722
1723        flexcan_clks_disable(priv);
1724
1725        return 0;
1726}
1727
1728static int __maybe_unused flexcan_runtime_resume(struct device *device)
1729{
1730        struct net_device *dev = dev_get_drvdata(device);
1731        struct flexcan_priv *priv = netdev_priv(dev);
1732
1733        return flexcan_clks_enable(priv);
1734}
1735
1736static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1737{
1738        struct net_device *dev = dev_get_drvdata(device);
1739        struct flexcan_priv *priv = netdev_priv(dev);
1740
1741        if (netif_running(dev) && device_may_wakeup(device))
1742                flexcan_enable_wakeup_irq(priv, true);
1743
1744        return 0;
1745}
1746
1747static int __maybe_unused flexcan_noirq_resume(struct device *device)
1748{
1749        struct net_device *dev = dev_get_drvdata(device);
1750        struct flexcan_priv *priv = netdev_priv(dev);
1751        int err;
1752
1753        if (netif_running(dev) && device_may_wakeup(device)) {
1754                flexcan_enable_wakeup_irq(priv, false);
1755                err = flexcan_exit_stop_mode(priv);
1756                if (err)
1757                        return err;
1758        }
1759
1760        return 0;
1761}
1762
1763static const struct dev_pm_ops flexcan_pm_ops = {
1764        SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1765        SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1766        SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1767};
1768
1769static struct platform_driver flexcan_driver = {
1770        .driver = {
1771                .name = DRV_NAME,
1772                .pm = &flexcan_pm_ops,
1773                .of_match_table = flexcan_of_match,
1774        },
1775        .probe = flexcan_probe,
1776        .remove = flexcan_remove,
1777        .id_table = flexcan_id_table,
1778};
1779
1780module_platform_driver(flexcan_driver);
1781
1782MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1783              "Marc Kleine-Budde <kernel@pengutronix.de>");
1784MODULE_LICENSE("GPL v2");
1785MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
1786