LXR linux/drivers/net/can/m_can/m

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* CAN bus driver for Bosch M_CAN controller
   3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   4 */
   5
   6#ifndef _CAN_M_CAN_H_
   7#define _CAN_M_CAN_H_
   8
   9#include <linux/can/core.h>
  10#include <linux/can/led.h>
  11#include <linux/can/rx-offload.h>
  12#include <linux/completion.h>
  13#include <linux/device.h>
  14#include <linux/dma-mapping.h>
  15#include <linux/freezer.h>
  16#include <linux/slab.h>
  17#include <linux/uaccess.h>
  18#include <linux/clk.h>
  19#include <linux/delay.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/kernel.h>
  23#include <linux/module.h>
  24#include <linux/netdevice.h>
  25#include <linux/of.h>
  26#include <linux/of_device.h>
  27#include <linux/pm_runtime.h>
  28#include <linux/iopoll.h>
  29#include <linux/can/dev.h>
  30#include <linux/pinctrl/consumer.h>
  31#include <linux/phy/phy.h>
  32
  33/* m_can lec values */
  34enum m_can_lec_type {
  35        LEC_NO_ERROR = 0,
  36        LEC_STUFF_ERROR,
  37        LEC_FORM_ERROR,
  38        LEC_ACK_ERROR,
  39        LEC_BIT1_ERROR,
  40        LEC_BIT0_ERROR,
  41        LEC_CRC_ERROR,
  42        LEC_UNUSED,
  43};
  44
  45enum m_can_mram_cfg {
  46        MRAM_SIDF = 0,
  47        MRAM_XIDF,
  48        MRAM_RXF0,
  49        MRAM_RXF1,
  50        MRAM_RXB,
  51        MRAM_TXE,
  52        MRAM_TXB,
  53        MRAM_CFG_NUM,
  54};
  55
  56/* address offset and element number for each FIFO/Buffer in the Message RAM */
  57struct mram_cfg {
  58        u16 off;
  59        u8  num;
  60};
  61
  62struct m_can_classdev;
  63struct m_can_ops {
  64        /* Device specific call backs */
  65        int (*clear_interrupts)(struct m_can_classdev *cdev);
  66        u32 (*read_reg)(struct m_can_classdev *cdev, int reg);
  67        int (*write_reg)(struct m_can_classdev *cdev, int reg, int val);
  68        int (*read_fifo)(struct m_can_classdev *cdev, int addr_offset, void *val, size_t val_count);
  69        int (*write_fifo)(struct m_can_classdev *cdev, int addr_offset,
  70                          const void *val, size_t val_count);
  71        int (*init)(struct m_can_classdev *cdev);
  72};
  73
  74struct m_can_classdev {
  75        struct can_priv can;
  76        struct can_rx_offload offload;
  77        struct napi_struct napi;
  78        struct net_device *net;
  79        struct device *dev;
  80        struct clk *hclk;
  81        struct clk *cclk;
  82
  83        struct workqueue_struct *tx_wq;
  84        struct work_struct tx_work;
  85        struct sk_buff *tx_skb;
  86        struct phy *transceiver;
  87
  88        struct m_can_ops *ops;
  89
  90        int version;
  91        u32 irqstatus;
  92
  93        int pm_clock_support;
  94        int is_peripheral;
  95
  96        struct mram_cfg mcfg[MRAM_CFG_NUM];
  97};
  98
  99struct m_can_classdev *m_can_class_allocate_dev(struct device *dev, int sizeof_priv);
 100void m_can_class_free_dev(struct net_device *net);
 101int m_can_class_register(struct m_can_classdev *cdev);
 102void m_can_class_unregister(struct m_can_classdev *cdev);
 103int m_can_class_get_clocks(struct m_can_classdev *cdev);
 104int m_can_init_ram(struct m_can_classdev *priv);
 105
 106int m_can_class_suspend(struct device *dev);
 107int m_can_class_resume(struct device *dev);
 108#endif  /* _CAN_M_H_ */
 109