1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#include <linux/can/core.h>
18#include <linux/can/dev.h>
19#include <linux/can/led.h>
20#include <linux/clk.h>
21#include <linux/completion.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/freezer.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
34#include <linux/slab.h>
35#include <linux/spi/spi.h>
36#include <linux/uaccess.h>
37
38#define HI3110_MASTER_RESET 0x56
39#define HI3110_READ_CTRL0 0xD2
40#define HI3110_READ_CTRL1 0xD4
41#define HI3110_READ_STATF 0xE2
42#define HI3110_WRITE_CTRL0 0x14
43#define HI3110_WRITE_CTRL1 0x16
44#define HI3110_WRITE_INTE 0x1C
45#define HI3110_WRITE_BTR0 0x18
46#define HI3110_WRITE_BTR1 0x1A
47#define HI3110_READ_BTR0 0xD6
48#define HI3110_READ_BTR1 0xD8
49#define HI3110_READ_INTF 0xDE
50#define HI3110_READ_ERR 0xDC
51#define HI3110_READ_FIFO_WOTIME 0x48
52#define HI3110_WRITE_FIFO 0x12
53#define HI3110_READ_MESSTAT 0xDA
54#define HI3110_READ_REC 0xEA
55#define HI3110_READ_TEC 0xEC
56
57#define HI3110_CTRL0_MODE_MASK (7 << 5)
58#define HI3110_CTRL0_NORMAL_MODE (0 << 5)
59#define HI3110_CTRL0_LOOPBACK_MODE (1 << 5)
60#define HI3110_CTRL0_MONITOR_MODE (2 << 5)
61#define HI3110_CTRL0_SLEEP_MODE (3 << 5)
62#define HI3110_CTRL0_INIT_MODE (4 << 5)
63
64#define HI3110_CTRL1_TXEN BIT(7)
65
66#define HI3110_INT_RXTMP BIT(7)
67#define HI3110_INT_RXFIFO BIT(6)
68#define HI3110_INT_TXCPLT BIT(5)
69#define HI3110_INT_BUSERR BIT(4)
70#define HI3110_INT_MCHG BIT(3)
71#define HI3110_INT_WAKEUP BIT(2)
72#define HI3110_INT_F1MESS BIT(1)
73#define HI3110_INT_F0MESS BIT(0)
74
75#define HI3110_ERR_BUSOFF BIT(7)
76#define HI3110_ERR_TXERRP BIT(6)
77#define HI3110_ERR_RXERRP BIT(5)
78#define HI3110_ERR_BITERR BIT(4)
79#define HI3110_ERR_FRMERR BIT(3)
80#define HI3110_ERR_CRCERR BIT(2)
81#define HI3110_ERR_ACKERR BIT(1)
82#define HI3110_ERR_STUFERR BIT(0)
83#define HI3110_ERR_PROTOCOL_MASK (0x1F)
84#define HI3110_ERR_PASSIVE_MASK (0x60)
85
86#define HI3110_STAT_RXFMTY BIT(1)
87#define HI3110_STAT_BUSOFF BIT(2)
88#define HI3110_STAT_ERRP BIT(3)
89#define HI3110_STAT_ERRW BIT(4)
90#define HI3110_STAT_TXMTY BIT(7)
91
92#define HI3110_BTR0_SJW_SHIFT 6
93#define HI3110_BTR0_BRP_SHIFT 0
94
95#define HI3110_BTR1_SAMP_3PERBIT (1 << 7)
96#define HI3110_BTR1_SAMP_1PERBIT (0 << 7)
97#define HI3110_BTR1_TSEG2_SHIFT 4
98#define HI3110_BTR1_TSEG1_SHIFT 0
99
100#define HI3110_FIFO_WOTIME_TAG_OFF 0
101#define HI3110_FIFO_WOTIME_ID_OFF 1
102#define HI3110_FIFO_WOTIME_DLC_OFF 5
103#define HI3110_FIFO_WOTIME_DAT_OFF 6
104
105#define HI3110_FIFO_WOTIME_TAG_IDE BIT(7)
106#define HI3110_FIFO_WOTIME_ID_RTR BIT(0)
107
108#define HI3110_FIFO_TAG_OFF 0
109#define HI3110_FIFO_ID_OFF 1
110#define HI3110_FIFO_STD_DLC_OFF 3
111#define HI3110_FIFO_STD_DATA_OFF 4
112#define HI3110_FIFO_EXT_DLC_OFF 5
113#define HI3110_FIFO_EXT_DATA_OFF 6
114
115#define HI3110_CAN_MAX_DATA_LEN 8
116#define HI3110_RX_BUF_LEN 15
117#define HI3110_TX_STD_BUF_LEN 12
118#define HI3110_TX_EXT_BUF_LEN 14
119#define HI3110_CAN_FRAME_MAX_BITS 128
120#define HI3110_EFF_FLAGS 0x18
121
122#define HI3110_TX_ECHO_SKB_MAX 1
123
124#define HI3110_OST_DELAY_MS (10)
125
126#define DEVICE_NAME "hi3110"
127
128static const struct can_bittiming_const hi3110_bittiming_const = {
129 .name = DEVICE_NAME,
130 .tseg1_min = 2,
131 .tseg1_max = 16,
132 .tseg2_min = 2,
133 .tseg2_max = 8,
134 .sjw_max = 4,
135 .brp_min = 1,
136 .brp_max = 64,
137 .brp_inc = 1,
138};
139
140enum hi3110_model {
141 CAN_HI3110_HI3110 = 0x3110,
142};
143
144struct hi3110_priv {
145 struct can_priv can;
146 struct net_device *net;
147 struct spi_device *spi;
148 enum hi3110_model model;
149
150 struct mutex hi3110_lock;
151
152 u8 *spi_tx_buf;
153 u8 *spi_rx_buf;
154
155 struct sk_buff *tx_skb;
156 int tx_len;
157
158 struct workqueue_struct *wq;
159 struct work_struct tx_work;
160 struct work_struct restart_work;
161
162 int force_quit;
163 int after_suspend;
164#define HI3110_AFTER_SUSPEND_UP 1
165#define HI3110_AFTER_SUSPEND_DOWN 2
166#define HI3110_AFTER_SUSPEND_POWER 4
167#define HI3110_AFTER_SUSPEND_RESTART 8
168 int restart_tx;
169 struct regulator *power;
170 struct regulator *transceiver;
171 struct clk *clk;
172};
173
174static void hi3110_clean(struct net_device *net)
175{
176 struct hi3110_priv *priv = netdev_priv(net);
177
178 if (priv->tx_skb || priv->tx_len)
179 net->stats.tx_errors++;
180 dev_kfree_skb(priv->tx_skb);
181 if (priv->tx_len)
182 can_free_echo_skb(priv->net, 0, NULL);
183 priv->tx_skb = NULL;
184 priv->tx_len = 0;
185}
186
187
188
189
190
191
192
193
194
195
196
197
198
199static int hi3110_spi_trans(struct spi_device *spi, int len)
200{
201 struct hi3110_priv *priv = spi_get_drvdata(spi);
202 struct spi_transfer t = {
203 .tx_buf = priv->spi_tx_buf,
204 .rx_buf = priv->spi_rx_buf,
205 .len = len,
206 .cs_change = 0,
207 };
208 struct spi_message m;
209 int ret;
210
211 spi_message_init(&m);
212 spi_message_add_tail(&t, &m);
213
214 ret = spi_sync(spi, &m);
215
216 if (ret)
217 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
218 return ret;
219}
220
221static int hi3110_cmd(struct spi_device *spi, u8 command)
222{
223 struct hi3110_priv *priv = spi_get_drvdata(spi);
224
225 priv->spi_tx_buf[0] = command;
226 dev_dbg(&spi->dev, "hi3110_cmd: %02X\n", command);
227
228 return hi3110_spi_trans(spi, 1);
229}
230
231static u8 hi3110_read(struct spi_device *spi, u8 command)
232{
233 struct hi3110_priv *priv = spi_get_drvdata(spi);
234 u8 val = 0;
235
236 priv->spi_tx_buf[0] = command;
237 hi3110_spi_trans(spi, 2);
238 val = priv->spi_rx_buf[1];
239
240 return val;
241}
242
243static void hi3110_write(struct spi_device *spi, u8 reg, u8 val)
244{
245 struct hi3110_priv *priv = spi_get_drvdata(spi);
246
247 priv->spi_tx_buf[0] = reg;
248 priv->spi_tx_buf[1] = val;
249 hi3110_spi_trans(spi, 2);
250}
251
252static void hi3110_hw_tx_frame(struct spi_device *spi, u8 *buf, int len)
253{
254 struct hi3110_priv *priv = spi_get_drvdata(spi);
255
256 priv->spi_tx_buf[0] = HI3110_WRITE_FIFO;
257 memcpy(priv->spi_tx_buf + 1, buf, len);
258 hi3110_spi_trans(spi, len + 1);
259}
260
261static void hi3110_hw_tx(struct spi_device *spi, struct can_frame *frame)
262{
263 u8 buf[HI3110_TX_EXT_BUF_LEN];
264
265 buf[HI3110_FIFO_TAG_OFF] = 0;
266
267 if (frame->can_id & CAN_EFF_FLAG) {
268
269 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_EFF_MASK) >> 21;
270 buf[HI3110_FIFO_ID_OFF + 1] =
271 (((frame->can_id & CAN_EFF_MASK) >> 13) & 0xe0) |
272 HI3110_EFF_FLAGS |
273 (((frame->can_id & CAN_EFF_MASK) >> 15) & 0x07);
274 buf[HI3110_FIFO_ID_OFF + 2] =
275 (frame->can_id & CAN_EFF_MASK) >> 7;
276 buf[HI3110_FIFO_ID_OFF + 3] =
277 ((frame->can_id & CAN_EFF_MASK) << 1) |
278 ((frame->can_id & CAN_RTR_FLAG) ? 1 : 0);
279
280 buf[HI3110_FIFO_EXT_DLC_OFF] = frame->len;
281
282 memcpy(buf + HI3110_FIFO_EXT_DATA_OFF,
283 frame->data, frame->len);
284
285 hi3110_hw_tx_frame(spi, buf, HI3110_TX_EXT_BUF_LEN -
286 (HI3110_CAN_MAX_DATA_LEN - frame->len));
287 } else {
288
289 buf[HI3110_FIFO_ID_OFF] = (frame->can_id & CAN_SFF_MASK) >> 3;
290 buf[HI3110_FIFO_ID_OFF + 1] =
291 ((frame->can_id & CAN_SFF_MASK) << 5) |
292 ((frame->can_id & CAN_RTR_FLAG) ? (1 << 4) : 0);
293
294 buf[HI3110_FIFO_STD_DLC_OFF] = frame->len;
295
296 memcpy(buf + HI3110_FIFO_STD_DATA_OFF,
297 frame->data, frame->len);
298
299 hi3110_hw_tx_frame(spi, buf, HI3110_TX_STD_BUF_LEN -
300 (HI3110_CAN_MAX_DATA_LEN - frame->len));
301 }
302}
303
304static void hi3110_hw_rx_frame(struct spi_device *spi, u8 *buf)
305{
306 struct hi3110_priv *priv = spi_get_drvdata(spi);
307
308 priv->spi_tx_buf[0] = HI3110_READ_FIFO_WOTIME;
309 hi3110_spi_trans(spi, HI3110_RX_BUF_LEN);
310 memcpy(buf, priv->spi_rx_buf + 1, HI3110_RX_BUF_LEN - 1);
311}
312
313static void hi3110_hw_rx(struct spi_device *spi)
314{
315 struct hi3110_priv *priv = spi_get_drvdata(spi);
316 struct sk_buff *skb;
317 struct can_frame *frame;
318 u8 buf[HI3110_RX_BUF_LEN - 1];
319
320 skb = alloc_can_skb(priv->net, &frame);
321 if (!skb) {
322 priv->net->stats.rx_dropped++;
323 return;
324 }
325
326 hi3110_hw_rx_frame(spi, buf);
327 if (buf[HI3110_FIFO_WOTIME_TAG_OFF] & HI3110_FIFO_WOTIME_TAG_IDE) {
328
329 frame->can_id = CAN_EFF_FLAG;
330 frame->can_id |=
331 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 21) |
332 (((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5) << 18) |
333 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0x07) << 15) |
334 (buf[HI3110_FIFO_WOTIME_ID_OFF + 2] << 7) |
335 (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] >> 1);
336 } else {
337
338 frame->can_id =
339 (buf[HI3110_FIFO_WOTIME_ID_OFF] << 3) |
340 ((buf[HI3110_FIFO_WOTIME_ID_OFF + 1] & 0xE0) >> 5);
341 }
342
343
344 frame->len = can_cc_dlc2len(buf[HI3110_FIFO_WOTIME_DLC_OFF] & 0x0F);
345
346 if (buf[HI3110_FIFO_WOTIME_ID_OFF + 3] & HI3110_FIFO_WOTIME_ID_RTR)
347 frame->can_id |= CAN_RTR_FLAG;
348 else
349 memcpy(frame->data, buf + HI3110_FIFO_WOTIME_DAT_OFF,
350 frame->len);
351
352 priv->net->stats.rx_packets++;
353 priv->net->stats.rx_bytes += frame->len;
354
355 can_led_event(priv->net, CAN_LED_EVENT_RX);
356
357 netif_rx_ni(skb);
358}
359
360static void hi3110_hw_sleep(struct spi_device *spi)
361{
362 hi3110_write(spi, HI3110_WRITE_CTRL0, HI3110_CTRL0_SLEEP_MODE);
363}
364
365static netdev_tx_t hi3110_hard_start_xmit(struct sk_buff *skb,
366 struct net_device *net)
367{
368 struct hi3110_priv *priv = netdev_priv(net);
369 struct spi_device *spi = priv->spi;
370
371 if (priv->tx_skb || priv->tx_len) {
372 dev_err(&spi->dev, "hard_xmit called while tx busy\n");
373 return NETDEV_TX_BUSY;
374 }
375
376 if (can_dropped_invalid_skb(net, skb))
377 return NETDEV_TX_OK;
378
379 netif_stop_queue(net);
380 priv->tx_skb = skb;
381 queue_work(priv->wq, &priv->tx_work);
382
383 return NETDEV_TX_OK;
384}
385
386static int hi3110_do_set_mode(struct net_device *net, enum can_mode mode)
387{
388 struct hi3110_priv *priv = netdev_priv(net);
389
390 switch (mode) {
391 case CAN_MODE_START:
392 hi3110_clean(net);
393
394 priv->can.state = CAN_STATE_ERROR_ACTIVE;
395 priv->restart_tx = 1;
396 if (priv->can.restart_ms == 0)
397 priv->after_suspend = HI3110_AFTER_SUSPEND_RESTART;
398 queue_work(priv->wq, &priv->restart_work);
399 break;
400 default:
401 return -EOPNOTSUPP;
402 }
403
404 return 0;
405}
406
407static int hi3110_get_berr_counter(const struct net_device *net,
408 struct can_berr_counter *bec)
409{
410 struct hi3110_priv *priv = netdev_priv(net);
411 struct spi_device *spi = priv->spi;
412
413 mutex_lock(&priv->hi3110_lock);
414 bec->txerr = hi3110_read(spi, HI3110_READ_TEC);
415 bec->rxerr = hi3110_read(spi, HI3110_READ_REC);
416 mutex_unlock(&priv->hi3110_lock);
417
418 return 0;
419}
420
421static int hi3110_set_normal_mode(struct spi_device *spi)
422{
423 struct hi3110_priv *priv = spi_get_drvdata(spi);
424 u8 reg = 0;
425
426 hi3110_write(spi, HI3110_WRITE_INTE, HI3110_INT_BUSERR |
427 HI3110_INT_RXFIFO | HI3110_INT_TXCPLT);
428
429
430 hi3110_write(spi, HI3110_WRITE_CTRL1, HI3110_CTRL1_TXEN);
431
432 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
433 reg = HI3110_CTRL0_LOOPBACK_MODE;
434 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
435 reg = HI3110_CTRL0_MONITOR_MODE;
436 else
437 reg = HI3110_CTRL0_NORMAL_MODE;
438
439 hi3110_write(spi, HI3110_WRITE_CTRL0, reg);
440
441
442 mdelay(HI3110_OST_DELAY_MS);
443 reg = hi3110_read(spi, HI3110_READ_CTRL0);
444 if ((reg & HI3110_CTRL0_MODE_MASK) != reg)
445 return -EBUSY;
446
447 priv->can.state = CAN_STATE_ERROR_ACTIVE;
448 return 0;
449}
450
451static int hi3110_do_set_bittiming(struct net_device *net)
452{
453 struct hi3110_priv *priv = netdev_priv(net);
454 struct can_bittiming *bt = &priv->can.bittiming;
455 struct spi_device *spi = priv->spi;
456
457 hi3110_write(spi, HI3110_WRITE_BTR0,
458 ((bt->sjw - 1) << HI3110_BTR0_SJW_SHIFT) |
459 ((bt->brp - 1) << HI3110_BTR0_BRP_SHIFT));
460
461 hi3110_write(spi, HI3110_WRITE_BTR1,
462 (priv->can.ctrlmode &
463 CAN_CTRLMODE_3_SAMPLES ?
464 HI3110_BTR1_SAMP_3PERBIT : HI3110_BTR1_SAMP_1PERBIT) |
465 ((bt->phase_seg1 + bt->prop_seg - 1)
466 << HI3110_BTR1_TSEG1_SHIFT) |
467 ((bt->phase_seg2 - 1) << HI3110_BTR1_TSEG2_SHIFT));
468
469 dev_dbg(&spi->dev, "BT: 0x%02x 0x%02x\n",
470 hi3110_read(spi, HI3110_READ_BTR0),
471 hi3110_read(spi, HI3110_READ_BTR1));
472
473 return 0;
474}
475
476static int hi3110_setup(struct net_device *net)
477{
478 hi3110_do_set_bittiming(net);
479 return 0;
480}
481
482static int hi3110_hw_reset(struct spi_device *spi)
483{
484 u8 reg;
485 int ret;
486
487
488 mdelay(HI3110_OST_DELAY_MS);
489
490 ret = hi3110_cmd(spi, HI3110_MASTER_RESET);
491 if (ret)
492 return ret;
493
494
495 mdelay(HI3110_OST_DELAY_MS);
496
497 reg = hi3110_read(spi, HI3110_READ_CTRL0);
498 if ((reg & HI3110_CTRL0_MODE_MASK) != HI3110_CTRL0_INIT_MODE)
499 return -ENODEV;
500
501
502
503
504 hi3110_read(spi, HI3110_READ_ERR);
505
506 return 0;
507}
508
509static int hi3110_hw_probe(struct spi_device *spi)
510{
511 u8 statf;
512
513 hi3110_hw_reset(spi);
514
515
516
517
518 statf = hi3110_read(spi, HI3110_READ_STATF);
519
520 dev_dbg(&spi->dev, "statf: %02X\n", statf);
521
522 if (statf != 0x82)
523 return -ENODEV;
524
525 return 0;
526}
527
528static int hi3110_power_enable(struct regulator *reg, int enable)
529{
530 if (IS_ERR_OR_NULL(reg))
531 return 0;
532
533 if (enable)
534 return regulator_enable(reg);
535 else
536 return regulator_disable(reg);
537}
538
539static int hi3110_stop(struct net_device *net)
540{
541 struct hi3110_priv *priv = netdev_priv(net);
542 struct spi_device *spi = priv->spi;
543
544 close_candev(net);
545
546 priv->force_quit = 1;
547 free_irq(spi->irq, priv);
548 destroy_workqueue(priv->wq);
549 priv->wq = NULL;
550
551 mutex_lock(&priv->hi3110_lock);
552
553
554 hi3110_write(spi, HI3110_WRITE_CTRL1, 0x0);
555 hi3110_write(spi, HI3110_WRITE_INTE, 0x0);
556 hi3110_read(spi, HI3110_READ_INTF);
557
558 hi3110_clean(net);
559
560 hi3110_hw_sleep(spi);
561
562 hi3110_power_enable(priv->transceiver, 0);
563
564 priv->can.state = CAN_STATE_STOPPED;
565
566 mutex_unlock(&priv->hi3110_lock);
567
568 can_led_event(net, CAN_LED_EVENT_STOP);
569
570 return 0;
571}
572
573static void hi3110_tx_work_handler(struct work_struct *ws)
574{
575 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
576 tx_work);
577 struct spi_device *spi = priv->spi;
578 struct net_device *net = priv->net;
579 struct can_frame *frame;
580
581 mutex_lock(&priv->hi3110_lock);
582 if (priv->tx_skb) {
583 if (priv->can.state == CAN_STATE_BUS_OFF) {
584 hi3110_clean(net);
585 } else {
586 frame = (struct can_frame *)priv->tx_skb->data;
587 hi3110_hw_tx(spi, frame);
588 priv->tx_len = 1 + frame->len;
589 can_put_echo_skb(priv->tx_skb, net, 0, 0);
590 priv->tx_skb = NULL;
591 }
592 }
593 mutex_unlock(&priv->hi3110_lock);
594}
595
596static void hi3110_restart_work_handler(struct work_struct *ws)
597{
598 struct hi3110_priv *priv = container_of(ws, struct hi3110_priv,
599 restart_work);
600 struct spi_device *spi = priv->spi;
601 struct net_device *net = priv->net;
602
603 mutex_lock(&priv->hi3110_lock);
604 if (priv->after_suspend) {
605 hi3110_hw_reset(spi);
606 hi3110_setup(net);
607 if (priv->after_suspend & HI3110_AFTER_SUSPEND_RESTART) {
608 hi3110_set_normal_mode(spi);
609 } else if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
610 netif_device_attach(net);
611 hi3110_clean(net);
612 hi3110_set_normal_mode(spi);
613 netif_wake_queue(net);
614 } else {
615 hi3110_hw_sleep(spi);
616 }
617 priv->after_suspend = 0;
618 priv->force_quit = 0;
619 }
620
621 if (priv->restart_tx) {
622 priv->restart_tx = 0;
623 hi3110_hw_reset(spi);
624 hi3110_setup(net);
625 hi3110_clean(net);
626 hi3110_set_normal_mode(spi);
627 netif_wake_queue(net);
628 }
629 mutex_unlock(&priv->hi3110_lock);
630}
631
632static irqreturn_t hi3110_can_ist(int irq, void *dev_id)
633{
634 struct hi3110_priv *priv = dev_id;
635 struct spi_device *spi = priv->spi;
636 struct net_device *net = priv->net;
637
638 mutex_lock(&priv->hi3110_lock);
639
640 while (!priv->force_quit) {
641 enum can_state new_state;
642 u8 intf, eflag, statf;
643
644 while (!(HI3110_STAT_RXFMTY &
645 (statf = hi3110_read(spi, HI3110_READ_STATF)))) {
646 hi3110_hw_rx(spi);
647 }
648
649 intf = hi3110_read(spi, HI3110_READ_INTF);
650 eflag = hi3110_read(spi, HI3110_READ_ERR);
651
652 if (eflag & HI3110_ERR_BUSOFF)
653 new_state = CAN_STATE_BUS_OFF;
654 else if (eflag & HI3110_ERR_PASSIVE_MASK)
655 new_state = CAN_STATE_ERROR_PASSIVE;
656 else if (statf & HI3110_STAT_ERRW)
657 new_state = CAN_STATE_ERROR_WARNING;
658 else
659 new_state = CAN_STATE_ERROR_ACTIVE;
660
661 if (new_state != priv->can.state) {
662 struct can_frame *cf;
663 struct sk_buff *skb;
664 enum can_state rx_state, tx_state;
665 u8 rxerr, txerr;
666
667 skb = alloc_can_err_skb(net, &cf);
668 if (!skb)
669 break;
670
671 txerr = hi3110_read(spi, HI3110_READ_TEC);
672 rxerr = hi3110_read(spi, HI3110_READ_REC);
673 cf->data[6] = txerr;
674 cf->data[7] = rxerr;
675 tx_state = txerr >= rxerr ? new_state : 0;
676 rx_state = txerr <= rxerr ? new_state : 0;
677 can_change_state(net, cf, tx_state, rx_state);
678 netif_rx_ni(skb);
679
680 if (new_state == CAN_STATE_BUS_OFF) {
681 can_bus_off(net);
682 if (priv->can.restart_ms == 0) {
683 priv->force_quit = 1;
684 hi3110_hw_sleep(spi);
685 break;
686 }
687 }
688 }
689
690
691 if ((intf & HI3110_INT_BUSERR) &&
692 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
693 struct can_frame *cf;
694 struct sk_buff *skb;
695
696
697 if (eflag & HI3110_ERR_PROTOCOL_MASK) {
698 skb = alloc_can_err_skb(net, &cf);
699 if (!skb)
700 break;
701
702 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
703 priv->can.can_stats.bus_error++;
704 priv->net->stats.rx_errors++;
705 if (eflag & HI3110_ERR_BITERR)
706 cf->data[2] |= CAN_ERR_PROT_BIT;
707 else if (eflag & HI3110_ERR_FRMERR)
708 cf->data[2] |= CAN_ERR_PROT_FORM;
709 else if (eflag & HI3110_ERR_STUFERR)
710 cf->data[2] |= CAN_ERR_PROT_STUFF;
711 else if (eflag & HI3110_ERR_CRCERR)
712 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
713 else if (eflag & HI3110_ERR_ACKERR)
714 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
715
716 cf->data[6] = hi3110_read(spi, HI3110_READ_TEC);
717 cf->data[7] = hi3110_read(spi, HI3110_READ_REC);
718 netdev_dbg(priv->net, "Bus Error\n");
719 netif_rx_ni(skb);
720 }
721 }
722
723 if (priv->tx_len && statf & HI3110_STAT_TXMTY) {
724 net->stats.tx_packets++;
725 net->stats.tx_bytes += priv->tx_len - 1;
726 can_led_event(net, CAN_LED_EVENT_TX);
727 if (priv->tx_len) {
728 can_get_echo_skb(net, 0, NULL);
729 priv->tx_len = 0;
730 }
731 netif_wake_queue(net);
732 }
733
734 if (intf == 0)
735 break;
736 }
737 mutex_unlock(&priv->hi3110_lock);
738 return IRQ_HANDLED;
739}
740
741static int hi3110_open(struct net_device *net)
742{
743 struct hi3110_priv *priv = netdev_priv(net);
744 struct spi_device *spi = priv->spi;
745 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_HIGH;
746 int ret;
747
748 ret = open_candev(net);
749 if (ret)
750 return ret;
751
752 mutex_lock(&priv->hi3110_lock);
753 hi3110_power_enable(priv->transceiver, 1);
754
755 priv->force_quit = 0;
756 priv->tx_skb = NULL;
757 priv->tx_len = 0;
758
759 ret = request_threaded_irq(spi->irq, NULL, hi3110_can_ist,
760 flags, DEVICE_NAME, priv);
761 if (ret) {
762 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
763 goto out_close;
764 }
765
766 priv->wq = alloc_workqueue("hi3110_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
767 0);
768 if (!priv->wq) {
769 ret = -ENOMEM;
770 goto out_free_irq;
771 }
772 INIT_WORK(&priv->tx_work, hi3110_tx_work_handler);
773 INIT_WORK(&priv->restart_work, hi3110_restart_work_handler);
774
775 ret = hi3110_hw_reset(spi);
776 if (ret)
777 goto out_free_wq;
778
779 ret = hi3110_setup(net);
780 if (ret)
781 goto out_free_wq;
782
783 ret = hi3110_set_normal_mode(spi);
784 if (ret)
785 goto out_free_wq;
786
787 can_led_event(net, CAN_LED_EVENT_OPEN);
788 netif_wake_queue(net);
789 mutex_unlock(&priv->hi3110_lock);
790
791 return 0;
792
793 out_free_wq:
794 destroy_workqueue(priv->wq);
795 out_free_irq:
796 free_irq(spi->irq, priv);
797 hi3110_hw_sleep(spi);
798 out_close:
799 hi3110_power_enable(priv->transceiver, 0);
800 close_candev(net);
801 mutex_unlock(&priv->hi3110_lock);
802 return ret;
803}
804
805static const struct net_device_ops hi3110_netdev_ops = {
806 .ndo_open = hi3110_open,
807 .ndo_stop = hi3110_stop,
808 .ndo_start_xmit = hi3110_hard_start_xmit,
809};
810
811static const struct of_device_id hi3110_of_match[] = {
812 {
813 .compatible = "holt,hi3110",
814 .data = (void *)CAN_HI3110_HI3110,
815 },
816 { }
817};
818MODULE_DEVICE_TABLE(of, hi3110_of_match);
819
820static const struct spi_device_id hi3110_id_table[] = {
821 {
822 .name = "hi3110",
823 .driver_data = (kernel_ulong_t)CAN_HI3110_HI3110,
824 },
825 { }
826};
827MODULE_DEVICE_TABLE(spi, hi3110_id_table);
828
829static int hi3110_can_probe(struct spi_device *spi)
830{
831 const struct of_device_id *of_id = of_match_device(hi3110_of_match,
832 &spi->dev);
833 struct net_device *net;
834 struct hi3110_priv *priv;
835 struct clk *clk;
836 int freq, ret;
837
838 clk = devm_clk_get(&spi->dev, NULL);
839 if (IS_ERR(clk)) {
840 dev_err(&spi->dev, "no CAN clock source defined\n");
841 return PTR_ERR(clk);
842 }
843 freq = clk_get_rate(clk);
844
845
846 if (freq > 40000000)
847 return -ERANGE;
848
849
850 net = alloc_candev(sizeof(struct hi3110_priv), HI3110_TX_ECHO_SKB_MAX);
851 if (!net)
852 return -ENOMEM;
853
854 if (!IS_ERR(clk)) {
855 ret = clk_prepare_enable(clk);
856 if (ret)
857 goto out_free;
858 }
859
860 net->netdev_ops = &hi3110_netdev_ops;
861 net->flags |= IFF_ECHO;
862
863 priv = netdev_priv(net);
864 priv->can.bittiming_const = &hi3110_bittiming_const;
865 priv->can.do_set_mode = hi3110_do_set_mode;
866 priv->can.do_get_berr_counter = hi3110_get_berr_counter;
867 priv->can.clock.freq = freq / 2;
868 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
869 CAN_CTRLMODE_LOOPBACK |
870 CAN_CTRLMODE_LISTENONLY |
871 CAN_CTRLMODE_BERR_REPORTING;
872
873 if (of_id)
874 priv->model = (enum hi3110_model)(uintptr_t)of_id->data;
875 else
876 priv->model = spi_get_device_id(spi)->driver_data;
877 priv->net = net;
878 priv->clk = clk;
879
880 spi_set_drvdata(spi, priv);
881
882
883 spi->bits_per_word = 8;
884 ret = spi_setup(spi);
885 if (ret)
886 goto out_clk;
887
888 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
889 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
890 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
891 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
892 ret = -EPROBE_DEFER;
893 goto out_clk;
894 }
895
896 ret = hi3110_power_enable(priv->power, 1);
897 if (ret)
898 goto out_clk;
899
900 priv->spi = spi;
901 mutex_init(&priv->hi3110_lock);
902
903 priv->spi_tx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
904 GFP_KERNEL);
905 if (!priv->spi_tx_buf) {
906 ret = -ENOMEM;
907 goto error_probe;
908 }
909 priv->spi_rx_buf = devm_kzalloc(&spi->dev, HI3110_RX_BUF_LEN,
910 GFP_KERNEL);
911
912 if (!priv->spi_rx_buf) {
913 ret = -ENOMEM;
914 goto error_probe;
915 }
916
917 SET_NETDEV_DEV(net, &spi->dev);
918
919 ret = hi3110_hw_probe(spi);
920 if (ret) {
921 if (ret == -ENODEV)
922 dev_err(&spi->dev, "Cannot initialize %x. Wrong wiring?\n",
923 priv->model);
924 goto error_probe;
925 }
926 hi3110_hw_sleep(spi);
927
928 ret = register_candev(net);
929 if (ret)
930 goto error_probe;
931
932 devm_can_led_init(net);
933 netdev_info(net, "%x successfully initialized.\n", priv->model);
934
935 return 0;
936
937 error_probe:
938 hi3110_power_enable(priv->power, 0);
939
940 out_clk:
941 if (!IS_ERR(clk))
942 clk_disable_unprepare(clk);
943
944 out_free:
945 free_candev(net);
946
947 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
948 return ret;
949}
950
951static int hi3110_can_remove(struct spi_device *spi)
952{
953 struct hi3110_priv *priv = spi_get_drvdata(spi);
954 struct net_device *net = priv->net;
955
956 unregister_candev(net);
957
958 hi3110_power_enable(priv->power, 0);
959
960 if (!IS_ERR(priv->clk))
961 clk_disable_unprepare(priv->clk);
962
963 free_candev(net);
964
965 return 0;
966}
967
968static int __maybe_unused hi3110_can_suspend(struct device *dev)
969{
970 struct spi_device *spi = to_spi_device(dev);
971 struct hi3110_priv *priv = spi_get_drvdata(spi);
972 struct net_device *net = priv->net;
973
974 priv->force_quit = 1;
975 disable_irq(spi->irq);
976
977
978
979
980 if (netif_running(net)) {
981 netif_device_detach(net);
982
983 hi3110_hw_sleep(spi);
984 hi3110_power_enable(priv->transceiver, 0);
985 priv->after_suspend = HI3110_AFTER_SUSPEND_UP;
986 } else {
987 priv->after_suspend = HI3110_AFTER_SUSPEND_DOWN;
988 }
989
990 if (!IS_ERR_OR_NULL(priv->power)) {
991 regulator_disable(priv->power);
992 priv->after_suspend |= HI3110_AFTER_SUSPEND_POWER;
993 }
994
995 return 0;
996}
997
998static int __maybe_unused hi3110_can_resume(struct device *dev)
999{
1000 struct spi_device *spi = to_spi_device(dev);
1001 struct hi3110_priv *priv = spi_get_drvdata(spi);
1002
1003 if (priv->after_suspend & HI3110_AFTER_SUSPEND_POWER)
1004 hi3110_power_enable(priv->power, 1);
1005
1006 if (priv->after_suspend & HI3110_AFTER_SUSPEND_UP) {
1007 hi3110_power_enable(priv->transceiver, 1);
1008 queue_work(priv->wq, &priv->restart_work);
1009 } else {
1010 priv->after_suspend = 0;
1011 }
1012
1013 priv->force_quit = 0;
1014 enable_irq(spi->irq);
1015 return 0;
1016}
1017
1018static SIMPLE_DEV_PM_OPS(hi3110_can_pm_ops, hi3110_can_suspend, hi3110_can_resume);
1019
1020static struct spi_driver hi3110_can_driver = {
1021 .driver = {
1022 .name = DEVICE_NAME,
1023 .of_match_table = hi3110_of_match,
1024 .pm = &hi3110_can_pm_ops,
1025 },
1026 .id_table = hi3110_id_table,
1027 .probe = hi3110_can_probe,
1028 .remove = hi3110_can_remove,
1029};
1030
1031module_spi_driver(hi3110_can_driver);
1032
1033MODULE_AUTHOR("Akshay Bhat <akshay.bhat@timesys.com>");
1034MODULE_AUTHOR("Casey Fitzpatrick <casey.fitzpatrick@timesys.com>");
1035MODULE_DESCRIPTION("Holt HI-3110 CAN driver");
1036MODULE_LICENSE("GPL v2");
1037
