LXR linux/drivers/net/dsa/mv88e6xxx/chip.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Marvell 88E6xxx Ethernet switch single-chip definition
   4 *
   5 * Copyright (c) 2008 Marvell Semiconductor
   6 */
   7
   8#ifndef _MV88E6XXX_CHIP_H
   9#define _MV88E6XXX_CHIP_H
  10
  11#include <linux/idr.h>
  12#include <linux/if_vlan.h>
  13#include <linux/irq.h>
  14#include <linux/gpio/consumer.h>
  15#include <linux/kthread.h>
  16#include <linux/phy.h>
  17#include <linux/ptp_clock_kernel.h>
  18#include <linux/timecounter.h>
  19#include <net/dsa.h>
  20
  21#define EDSA_HLEN               8
  22#define MV88E6XXX_N_FID         4096
  23
  24#define MV88E6XXX_FID_STANDALONE        0
  25#define MV88E6XXX_FID_BRIDGED           1
  26
  27/* PVT limits for 4-bit port and 5-bit switch */
  28#define MV88E6XXX_MAX_PVT_SWITCHES      32
  29#define MV88E6XXX_MAX_PVT_PORTS         16
  30#define MV88E6XXX_MAX_PVT_ENTRIES       \
  31        (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS)
  32
  33#define MV88E6XXX_MAX_GPIO      16
  34
  35enum mv88e6xxx_egress_mode {
  36        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
  37        MV88E6XXX_EGRESS_MODE_UNTAGGED,
  38        MV88E6XXX_EGRESS_MODE_TAGGED,
  39        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
  40};
  41
  42enum mv88e6xxx_egress_direction {
  43        MV88E6XXX_EGRESS_DIR_INGRESS,
  44        MV88E6XXX_EGRESS_DIR_EGRESS,
  45};
  46
  47enum mv88e6xxx_frame_mode {
  48        MV88E6XXX_FRAME_MODE_NORMAL,
  49        MV88E6XXX_FRAME_MODE_DSA,
  50        MV88E6XXX_FRAME_MODE_PROVIDER,
  51        MV88E6XXX_FRAME_MODE_ETHERTYPE,
  52};
  53
  54/* List of supported models */
  55enum mv88e6xxx_model {
  56        MV88E6085,
  57        MV88E6095,
  58        MV88E6097,
  59        MV88E6123,
  60        MV88E6131,
  61        MV88E6141,
  62        MV88E6161,
  63        MV88E6165,
  64        MV88E6171,
  65        MV88E6172,
  66        MV88E6175,
  67        MV88E6176,
  68        MV88E6185,
  69        MV88E6190,
  70        MV88E6190X,
  71        MV88E6191,
  72        MV88E6191X,
  73        MV88E6193X,
  74        MV88E6220,
  75        MV88E6240,
  76        MV88E6250,
  77        MV88E6290,
  78        MV88E6320,
  79        MV88E6321,
  80        MV88E6341,
  81        MV88E6350,
  82        MV88E6351,
  83        MV88E6352,
  84        MV88E6390,
  85        MV88E6390X,
  86        MV88E6393X,
  87};
  88
  89enum mv88e6xxx_family {
  90        MV88E6XXX_FAMILY_NONE,
  91        MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
  92        MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
  93        MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
  94        MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
  95        MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
  96        MV88E6XXX_FAMILY_6250,  /* 6220 6250 */
  97        MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
  98        MV88E6XXX_FAMILY_6341,  /* 6141 6341 */
  99        MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
 100        MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
 101        MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
 102        MV88E6XXX_FAMILY_6393,  /* 6191X 6193X 6393X */
 103};
 104
 105/**
 106 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
 107 * @MV88E6XXX_EDSA_UNSUPPORTED:  Device has no support for EDSA tags
 108 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that
 109 *                               egressing FORWARD frames with an EDSA
 110 *                               tag is reserved for future use, but
 111 *                               empirical data shows that this mode
 112 *                               is supported.
 113 * @MV88E6XXX_EDSA_SUPPORTED:    EDSA tags are fully supported.
 114 */
 115enum mv88e6xxx_edsa_support {
 116        MV88E6XXX_EDSA_UNSUPPORTED = 0,
 117        MV88E6XXX_EDSA_UNDOCUMENTED,
 118        MV88E6XXX_EDSA_SUPPORTED,
 119};
 120
 121struct mv88e6xxx_ops;
 122
 123struct mv88e6xxx_info {
 124        enum mv88e6xxx_family family;
 125        u16 prod_num;
 126        const char *name;
 127        unsigned int num_databases;
 128        unsigned int num_macs;
 129        unsigned int num_ports;
 130        unsigned int num_internal_phys;
 131        unsigned int num_gpio;
 132        unsigned int max_vid;
 133        unsigned int port_base_addr;
 134        unsigned int phy_base_addr;
 135        unsigned int global1_addr;
 136        unsigned int global2_addr;
 137        unsigned int age_time_coeff;
 138        unsigned int g1_irqs;
 139        unsigned int g2_irqs;
 140        bool pvt;
 141
 142        /* Mark certain ports as invalid. This is required for example for the
 143         * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
 144         * ports 2-4 are not routet to pins.
 145         */
 146        unsigned int invalid_port_mask;
 147        /* Multi-chip Addressing Mode.
 148         * Some chips respond to only 2 registers of its own SMI device address
 149         * when it is non-zero, and use indirect access to internal registers.
 150         */
 151        bool multi_chip;
 152        /* Dual-chip Addressing Mode
 153         * Some chips respond to only half of the 32 SMI addresses,
 154         * allowing two to coexist on the same SMI interface.
 155         */
 156        bool dual_chip;
 157
 158        enum mv88e6xxx_edsa_support edsa_support;
 159
 160        /* Mask for FromPort and ToPort value of PortVec used in ATU Move
 161         * operation. 0 means that the ATU Move operation is not supported.
 162         */
 163        u8 atu_move_port_mask;
 164        const struct mv88e6xxx_ops *ops;
 165
 166        /* Supports PTP */
 167        bool ptp_support;
 168};
 169
 170struct mv88e6xxx_atu_entry {
 171        u8      state;
 172        bool    trunk;
 173        u16     portvec;
 174        u8      mac[ETH_ALEN];
 175};
 176
 177struct mv88e6xxx_vtu_entry {
 178        u16     vid;
 179        u16     fid;
 180        u8      sid;
 181        bool    valid;
 182        u8      member[DSA_MAX_PORTS];
 183        u8      state[DSA_MAX_PORTS];
 184};
 185
 186struct mv88e6xxx_bus_ops;
 187struct mv88e6xxx_irq_ops;
 188struct mv88e6xxx_gpio_ops;
 189struct mv88e6xxx_avb_ops;
 190struct mv88e6xxx_ptp_ops;
 191
 192struct mv88e6xxx_irq {
 193        u16 masked;
 194        struct irq_chip chip;
 195        struct irq_domain *domain;
 196        int nirqs;
 197};
 198
 199/* state flags for mv88e6xxx_port_hwtstamp::state */
 200enum {
 201        MV88E6XXX_HWTSTAMP_ENABLED,
 202        MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
 203};
 204
 205struct mv88e6xxx_port_hwtstamp {
 206        /* Port index */
 207        int port_id;
 208
 209        /* Timestamping state */
 210        unsigned long state;
 211
 212        /* Resources for receive timestamping */
 213        struct sk_buff_head rx_queue;
 214        struct sk_buff_head rx_queue2;
 215
 216        /* Resources for transmit timestamping */
 217        unsigned long tx_tstamp_start;
 218        struct sk_buff *tx_skb;
 219        u16 tx_seq_id;
 220
 221        /* Current timestamp configuration */
 222        struct hwtstamp_config tstamp_config;
 223};
 224
 225enum mv88e6xxx_policy_mapping {
 226        MV88E6XXX_POLICY_MAPPING_DA,
 227        MV88E6XXX_POLICY_MAPPING_SA,
 228        MV88E6XXX_POLICY_MAPPING_VTU,
 229        MV88E6XXX_POLICY_MAPPING_ETYPE,
 230        MV88E6XXX_POLICY_MAPPING_PPPOE,
 231        MV88E6XXX_POLICY_MAPPING_VBAS,
 232        MV88E6XXX_POLICY_MAPPING_OPT82,
 233        MV88E6XXX_POLICY_MAPPING_UDP,
 234};
 235
 236enum mv88e6xxx_policy_action {
 237        MV88E6XXX_POLICY_ACTION_NORMAL,
 238        MV88E6XXX_POLICY_ACTION_MIRROR,
 239        MV88E6XXX_POLICY_ACTION_TRAP,
 240        MV88E6XXX_POLICY_ACTION_DISCARD,
 241};
 242
 243struct mv88e6xxx_policy {
 244        enum mv88e6xxx_policy_mapping mapping;
 245        enum mv88e6xxx_policy_action action;
 246        struct ethtool_rx_flow_spec fs;
 247        u8 addr[ETH_ALEN];
 248        int port;
 249        u16 vid;
 250};
 251
 252struct mv88e6xxx_vlan {
 253        u16     vid;
 254        bool    valid;
 255};
 256
 257struct mv88e6xxx_port {
 258        struct mv88e6xxx_chip *chip;
 259        int port;
 260        struct mv88e6xxx_vlan bridge_pvid;
 261        u64 serdes_stats[2];
 262        u64 atu_member_violation;
 263        u64 atu_miss_violation;
 264        u64 atu_full_violation;
 265        u64 vtu_member_violation;
 266        u64 vtu_miss_violation;
 267        phy_interface_t interface;
 268        u8 cmode;
 269        bool mirror_ingress;
 270        bool mirror_egress;
 271        unsigned int serdes_irq;
 272        char serdes_irq_name[64];
 273        struct devlink_region *region;
 274};
 275
 276enum mv88e6xxx_region_id {
 277        MV88E6XXX_REGION_GLOBAL1 = 0,
 278        MV88E6XXX_REGION_GLOBAL2,
 279        MV88E6XXX_REGION_ATU,
 280        MV88E6XXX_REGION_VTU,
 281        MV88E6XXX_REGION_PVT,
 282
 283        _MV88E6XXX_REGION_MAX,
 284};
 285
 286struct mv88e6xxx_region_priv {
 287        enum mv88e6xxx_region_id id;
 288};
 289
 290struct mv88e6xxx_chip {
 291        const struct mv88e6xxx_info *info;
 292
 293        /* Currently configured tagging protocol */
 294        enum dsa_tag_protocol tag_protocol;
 295
 296        /* The dsa_switch this private structure is related to */
 297        struct dsa_switch *ds;
 298
 299        /* The device this structure is associated to */
 300        struct device *dev;
 301
 302        /* This mutex protects the access to the switch registers */
 303        struct mutex reg_lock;
 304
 305        /* The MII bus and the address on the bus that is used to
 306         * communication with the switch
 307         */
 308        const struct mv88e6xxx_bus_ops *smi_ops;
 309        struct mii_bus *bus;
 310        int sw_addr;
 311
 312        /* Handles automatic disabling and re-enabling of the PHY
 313         * polling unit.
 314         */
 315        const struct mv88e6xxx_bus_ops *phy_ops;
 316        struct mutex            ppu_mutex;
 317        int                     ppu_disabled;
 318        struct work_struct      ppu_work;
 319        struct timer_list       ppu_timer;
 320
 321        /* This mutex serialises access to the statistics unit.
 322         * Hold this mutex over snapshot + dump sequences.
 323         */
 324        struct mutex    stats_mutex;
 325
 326        /* A switch may have a GPIO line tied to its reset pin. Parse
 327         * this from the device tree, and use it before performing
 328         * switch soft reset.
 329         */
 330        struct gpio_desc *reset;
 331
 332        /* set to size of eeprom if supported by the switch */
 333        u32 eeprom_len;
 334
 335        /* List of mdio busses */
 336        struct list_head mdios;
 337
 338        /* Policy Control List IDs and rules */
 339        struct idr policies;
 340
 341        /* There can be two interrupt controllers, which are chained
 342         * off a GPIO as interrupt source
 343         */
 344        struct mv88e6xxx_irq g1_irq;
 345        struct mv88e6xxx_irq g2_irq;
 346        int irq;
 347        char irq_name[64];
 348        int device_irq;
 349        char device_irq_name[64];
 350        int watchdog_irq;
 351        char watchdog_irq_name[64];
 352
 353        int atu_prob_irq;
 354        char atu_prob_irq_name[64];
 355        int vtu_prob_irq;
 356        char vtu_prob_irq_name[64];
 357        struct kthread_worker *kworker;
 358        struct kthread_delayed_work irq_poll_work;
 359
 360        /* GPIO resources */
 361        u8 gpio_data[2];
 362
 363        /* This cyclecounter abstracts the switch PTP time.
 364         * reg_lock must be held for any operation that read()s.
 365         */
 366        struct cyclecounter     tstamp_cc;
 367        struct timecounter      tstamp_tc;
 368        struct delayed_work     overflow_work;
 369
 370        struct ptp_clock        *ptp_clock;
 371        struct ptp_clock_info   ptp_clock_info;
 372        struct delayed_work     tai_event_work;
 373        struct ptp_pin_desc     pin_config[MV88E6XXX_MAX_GPIO];
 374        u16 trig_config;
 375        u16 evcap_config;
 376        u16 enable_count;
 377
 378        /* Current ingress and egress monitor ports */
 379        int egress_dest_port;
 380        int ingress_dest_port;
 381
 382        /* Per-port timestamping resources. */
 383        struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
 384
 385        /* Array of port structures. */
 386        struct mv88e6xxx_port ports[DSA_MAX_PORTS];
 387
 388        /* devlink regions */
 389        struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
 390};
 391
 392struct mv88e6xxx_bus_ops {
 393        int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 394        int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 395};
 396
 397struct mv88e6xxx_mdio_bus {
 398        struct mii_bus *bus;
 399        struct mv88e6xxx_chip *chip;
 400        struct list_head list;
 401        bool external;
 402};
 403
 404struct mv88e6xxx_ops {
 405        /* Switch Setup Errata, called early in the switch setup to
 406         * allow any errata actions to be performed
 407         */
 408        int (*setup_errata)(struct mv88e6xxx_chip *chip);
 409
 410        int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
 411        int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
 412
 413        /* Ingress Rate Limit unit (IRL) operations */
 414        int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
 415
 416        int (*get_eeprom)(struct mv88e6xxx_chip *chip,
 417                          struct ethtool_eeprom *eeprom, u8 *data);
 418        int (*set_eeprom)(struct mv88e6xxx_chip *chip,
 419                          struct ethtool_eeprom *eeprom, u8 *data);
 420
 421        int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
 422
 423        int (*phy_read)(struct mv88e6xxx_chip *chip,
 424                        struct mii_bus *bus,
 425                        int addr, int reg, u16 *val);
 426        int (*phy_write)(struct mv88e6xxx_chip *chip,
 427                         struct mii_bus *bus,
 428                         int addr, int reg, u16 val);
 429
 430        /* Priority Override Table operations */
 431        int (*pot_clear)(struct mv88e6xxx_chip *chip);
 432
 433        /* PHY Polling Unit (PPU) operations */
 434        int (*ppu_enable)(struct mv88e6xxx_chip *chip);
 435        int (*ppu_disable)(struct mv88e6xxx_chip *chip);
 436
 437        /* Switch Software Reset */
 438        int (*reset)(struct mv88e6xxx_chip *chip);
 439
 440        /* RGMII Receive/Transmit Timing Control
 441         * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
 442         */
 443        int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
 444                                    phy_interface_t mode);
 445
 446#define LINK_FORCED_DOWN        0
 447#define LINK_FORCED_UP          1
 448#define LINK_UNFORCED           -2
 449
 450        /* Port's MAC link state
 451         * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
 452         * or LINK_UNFORCED for normal link detection.
 453         */
 454        int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
 455
 456        /* Synchronise the port link state with that of the SERDES
 457         */
 458        int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
 459
 460#define PAUSE_ON                1
 461#define PAUSE_OFF               0
 462
 463        /* Enable/disable sending Pause */
 464        int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
 465                              int pause);
 466
 467#define SPEED_MAX               INT_MAX
 468#define SPEED_UNFORCED          -2
 469#define DUPLEX_UNFORCED         -2
 470
 471        /* Port's MAC speed (in Mbps) and MAC duplex mode
 472         *
 473         * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
 474         * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
 475         *
 476         * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
 477         * or DUPLEX_UNFORCED for normal duplex detection.
 478         */
 479        int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
 480                                     int speed, int duplex);
 481
 482        /* What interface mode should be used for maximum speed? */
 483        phy_interface_t (*port_max_speed_mode)(int port);
 484
 485        int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
 486
 487        int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
 488                               enum mv88e6xxx_policy_mapping mapping,
 489                               enum mv88e6xxx_policy_action action);
 490
 491        int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
 492                                   enum mv88e6xxx_frame_mode mode);
 493        int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
 494                                    bool unicast);
 495        int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
 496                                    bool multicast);
 497        int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
 498                                   u16 etype);
 499        int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
 500                                   size_t size);
 501
 502        int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
 503        int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
 504                                u8 out);
 505        int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
 506        int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
 507        int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
 508
 509        /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
 510         * Some chips allow this to be configured on specific ports.
 511         */
 512        int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
 513                              phy_interface_t mode);
 514        int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 515
 516        /* Some devices have a per port register indicating what is
 517         * the upstream port this port should forward to.
 518         */
 519        int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
 520                                      int upstream_port);
 521
 522        /* Snapshot the statistics for a port. The statistics can then
 523         * be read back a leisure but still with a consistent view.
 524         */
 525        int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
 526
 527        /* Set the histogram mode for statistics, when the control registers
 528         * are separated out of the STATS_OP register.
 529         */
 530        int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
 531
 532        /* Return the number of strings describing statistics */
 533        int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
 534        int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
 535        int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 536                               uint64_t *data);
 537        int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
 538        int (*set_egress_port)(struct mv88e6xxx_chip *chip,
 539                               enum mv88e6xxx_egress_direction direction,
 540                               int port);
 541
 542#define MV88E6XXX_CASCADE_PORT_NONE             0xe
 543#define MV88E6XXX_CASCADE_PORT_MULTIPLE         0xf
 544
 545        int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
 546
 547        const struct mv88e6xxx_irq_ops *watchdog_ops;
 548
 549        int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
 550
 551        /* Power on/off a SERDES interface */
 552        int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane,
 553                            bool up);
 554
 555        /* SERDES lane mapping */
 556        int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
 557
 558        int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
 559                                    int lane, struct phylink_link_state *state);
 560        int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
 561                                 int lane, unsigned int mode,
 562                                 phy_interface_t interface,
 563                                 const unsigned long *advertise);
 564        int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
 565                                     int lane);
 566        int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
 567                                  int lane, int speed, int duplex);
 568
 569        /* SERDES interrupt handling */
 570        unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
 571                                           int port);
 572        int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane,
 573                                 bool enable);
 574        irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
 575                                         int lane);
 576
 577        /* Statistics from the SERDES interface */
 578        int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
 579        int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
 580                                  uint8_t *data);
 581        int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 582                                uint64_t *data);
 583
 584        /* SERDES registers for ethtool */
 585        int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip,  int port);
 586        void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
 587                                void *_p);
 588
 589        /* Address Translation Unit operations */
 590        int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
 591        int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
 592
 593        /* VLAN Translation Unit operations */
 594        int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
 595                           struct mv88e6xxx_vtu_entry *entry);
 596        int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
 597                             struct mv88e6xxx_vtu_entry *entry);
 598
 599        /* GPIO operations */
 600        const struct mv88e6xxx_gpio_ops *gpio_ops;
 601
 602        /* Interface to the AVB/PTP registers */
 603        const struct mv88e6xxx_avb_ops *avb_ops;
 604
 605        /* Remote Management Unit operations */
 606        int (*rmu_disable)(struct mv88e6xxx_chip *chip);
 607
 608        /* Precision Time Protocol operations */
 609        const struct mv88e6xxx_ptp_ops *ptp_ops;
 610
 611        /* Phylink */
 612        void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
 613                                 unsigned long *mask,
 614                                 struct phylink_link_state *state);
 615
 616        /* Max Frame Size */
 617        int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
 618};
 619
 620struct mv88e6xxx_irq_ops {
 621        /* Action to be performed when the interrupt happens */
 622        int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
 623        /* Setup the hardware to generate the interrupt */
 624        int (*irq_setup)(struct mv88e6xxx_chip *chip);
 625        /* Reset the hardware to stop generating the interrupt */
 626        void (*irq_free)(struct mv88e6xxx_chip *chip);
 627};
 628
 629struct mv88e6xxx_gpio_ops {
 630        /* Get/set data on GPIO pin */
 631        int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
 632        int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
 633                        int value);
 634
 635        /* get/set GPIO direction */
 636        int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
 637        int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
 638                       bool input);
 639
 640        /* get/set GPIO pin control */
 641        int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 642                        int *func);
 643        int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 644                        int func);
 645};
 646
 647struct mv88e6xxx_avb_ops {
 648        /* Access port-scoped Precision Time Protocol registers */
 649        int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
 650                             u16 *data, int len);
 651        int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
 652                              u16 data);
 653
 654        /* Access global Precision Time Protocol registers */
 655        int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 656                        int len);
 657        int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 658
 659        /* Access global Time Application Interface registers */
 660        int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 661                        int len);
 662        int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 663};
 664
 665struct mv88e6xxx_ptp_ops {
 666        u64 (*clock_read)(const struct cyclecounter *cc);
 667        int (*ptp_enable)(struct ptp_clock_info *ptp,
 668                          struct ptp_clock_request *rq, int on);
 669        int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
 670                          enum ptp_pin_function func, unsigned int chan);
 671        void (*event_work)(struct work_struct *ugly);
 672        int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
 673        int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
 674        int (*global_enable)(struct mv88e6xxx_chip *chip);
 675        int (*global_disable)(struct mv88e6xxx_chip *chip);
 676        int n_ext_ts;
 677        int arr0_sts_reg;
 678        int arr1_sts_reg;
 679        int dep_sts_reg;
 680        u32 rx_filters;
 681        u32 cc_shift;
 682        u32 cc_mult;
 683        u32 cc_mult_num;
 684        u32 cc_mult_dem;
 685};
 686
 687#define STATS_TYPE_PORT         BIT(0)
 688#define STATS_TYPE_BANK0        BIT(1)
 689#define STATS_TYPE_BANK1        BIT(2)
 690
 691struct mv88e6xxx_hw_stat {
 692        char string[ETH_GSTRING_LEN];
 693        size_t size;
 694        int reg;
 695        int type;
 696};
 697
 698static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
 699{
 700        return chip->info->pvt;
 701}
 702
 703static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
 704{
 705        return !!chip->info->global2_addr;
 706}
 707
 708static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 709{
 710        return chip->info->num_databases;
 711}
 712
 713static inline unsigned int mv88e6xxx_num_macs(struct  mv88e6xxx_chip *chip)
 714{
 715        return chip->info->num_macs;
 716}
 717
 718static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
 719{
 720        return chip->info->num_ports;
 721}
 722
 723static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
 724{
 725        return chip->info->max_vid;
 726}
 727
 728static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
 729{
 730        return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
 731}
 732
 733static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
 734{
 735        return chip->info->num_gpio;
 736}
 737
 738static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
 739{
 740        return (chip->info->invalid_port_mask & BIT(port)) != 0;
 741}
 742
 743int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 744int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 745int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
 746                        u16 mask, u16 val);
 747int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 748                       int bit, int val);
 749struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
 750
 751static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
 752{
 753        mutex_lock(&chip->reg_lock);
 754}
 755
 756static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
 757{
 758        mutex_unlock(&chip->reg_lock);
 759}
 760
 761int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
 762
 763#endif /* _MV88E6XXX_CHIP_H */
 764