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11#include <linux/bitfield.h>
12#include <linux/interrupt.h>
13#include <linux/irqdomain.h>
14
15#include "chip.h"
16#include "global1.h"
17#include "global2.h"
18
19int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
20{
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val);
22}
23
24int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
25{
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val);
27}
28
29int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
30 bit, int val)
31{
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg,
33 bit, val);
34}
35
36
37
38static int mv88e6xxx_g2_int_source(struct mv88e6xxx_chip *chip, u16 *src)
39{
40
41 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_INT_SRC, src);
42}
43
44
45
46static int mv88e6xxx_g2_int_mask(struct mv88e6xxx_chip *chip, u16 mask)
47{
48 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_INT_MASK, mask);
49}
50
51
52
53static int mv88e6xxx_g2_mgmt_enable_2x(struct mv88e6xxx_chip *chip, u16 en2x)
54{
55 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_2X, en2x);
56}
57
58
59
60static int mv88e6xxx_g2_mgmt_enable_0x(struct mv88e6xxx_chip *chip, u16 en0x)
61{
62 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MGMT_EN_0X, en0x);
63}
64
65
66
67static int mv88e6xxx_g2_switch_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip,
68 bool enable)
69{
70 u16 val;
71 int err;
72
73 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SWITCH_MGMT, &val);
74 if (err)
75 return err;
76
77 if (enable)
78 val |= MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
79 else
80 val &= ~MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU;
81
82 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MGMT, val);
83}
84
85int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
86{
87 int err;
88
89
90
91
92 err = mv88e6xxx_g2_mgmt_enable_0x(chip, 0xffff);
93 if (err)
94 return err;
95
96 return mv88e6xxx_g2_switch_mgmt_rsvd2cpu(chip, true);
97}
98
99int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
100{
101 int err;
102
103
104
105
106 err = mv88e6xxx_g2_mgmt_enable_2x(chip, 0xffff);
107 if (err)
108 return err;
109
110 return mv88e6185_g2_mgmt_rsvd2cpu(chip);
111}
112
113
114
115int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
116 int port)
117{
118 u16 val = (target << 8) | (port & 0x1f);
119
120
121
122
123 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_DEVICE_MAPPING,
124 MV88E6XXX_G2_DEVICE_MAPPING_UPDATE | val);
125}
126
127
128
129int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
130 bool hash, u16 mask)
131{
132 u16 val = (num << 12) | (mask & mv88e6xxx_port_mask(chip));
133
134 if (hash)
135 val |= MV88E6XXX_G2_TRUNK_MASK_HASH;
136
137 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MASK,
138 MV88E6XXX_G2_TRUNK_MASK_UPDATE | val);
139}
140
141
142
143int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
144 u16 map)
145{
146 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
147 u16 val = (id << 11) | (map & port_mask);
148
149 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_TRUNK_MAPPING,
150 MV88E6XXX_G2_TRUNK_MAPPING_UPDATE | val);
151}
152
153int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
154{
155 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1;
156 int i, err;
157
158
159 for (i = 0; i < 8; ++i) {
160 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
161 if (err)
162 return err;
163 }
164
165
166 for (i = 0; i < 16; ++i) {
167 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
168 if (err)
169 return err;
170 }
171
172 return 0;
173}
174
175
176
177
178
179static int mv88e6xxx_g2_irl_wait(struct mv88e6xxx_chip *chip)
180{
181 int bit = __bf_shf(MV88E6XXX_G2_IRL_CMD_BUSY);
182
183 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_IRL_CMD, bit, 0);
184}
185
186static int mv88e6xxx_g2_irl_op(struct mv88e6xxx_chip *chip, u16 op, int port,
187 int res, int reg)
188{
189 int err;
190
191 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_IRL_CMD,
192 MV88E6XXX_G2_IRL_CMD_BUSY | op | (port << 8) |
193 (res << 5) | reg);
194 if (err)
195 return err;
196
197 return mv88e6xxx_g2_irl_wait(chip);
198}
199
200int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
201{
202 return mv88e6xxx_g2_irl_op(chip, MV88E6352_G2_IRL_CMD_OP_INIT_ALL, port,
203 0, 0);
204}
205
206int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port)
207{
208 return mv88e6xxx_g2_irl_op(chip, MV88E6390_G2_IRL_CMD_OP_INIT_ALL, port,
209 0, 0);
210}
211
212
213
214
215
216static int mv88e6xxx_g2_pvt_op_wait(struct mv88e6xxx_chip *chip)
217{
218 int bit = __bf_shf(MV88E6XXX_G2_PVT_ADDR_BUSY);
219
220 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_PVT_ADDR, bit, 0);
221}
222
223static int mv88e6xxx_g2_pvt_op(struct mv88e6xxx_chip *chip, int src_dev,
224 int src_port, u16 op)
225{
226 int err;
227
228
229
230
231 op |= MV88E6XXX_G2_PVT_ADDR_BUSY;
232 op |= (src_dev & 0x1f) << 4;
233 op |= (src_port & 0xf);
234
235 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_ADDR, op);
236 if (err)
237 return err;
238
239 return mv88e6xxx_g2_pvt_op_wait(chip);
240}
241
242int mv88e6xxx_g2_pvt_read(struct mv88e6xxx_chip *chip, int src_dev,
243 int src_port, u16 *data)
244{
245 int err;
246
247 err = mv88e6xxx_g2_pvt_op_wait(chip);
248 if (err)
249 return err;
250
251 err = mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
252 MV88E6XXX_G2_PVT_ADDR_OP_READ);
253 if (err)
254 return err;
255
256 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_PVT_DATA, data);
257}
258
259int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
260 int src_port, u16 data)
261{
262 int err;
263
264 err = mv88e6xxx_g2_pvt_op_wait(chip);
265 if (err)
266 return err;
267
268 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PVT_DATA, data);
269 if (err)
270 return err;
271
272 return mv88e6xxx_g2_pvt_op(chip, src_dev, src_port,
273 MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN);
274}
275
276
277
278static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
279 unsigned int pointer, u8 data)
280{
281 u16 val = (pointer << 8) | data;
282
283 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SWITCH_MAC,
284 MV88E6XXX_G2_SWITCH_MAC_UPDATE | val);
285}
286
287int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
288{
289 int i, err;
290
291 for (i = 0; i < 6; i++) {
292 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
293 if (err)
294 break;
295 }
296
297 return err;
298}
299
300
301
302int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin)
303{
304 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_ATU_STATS,
305 kind | bin);
306}
307
308int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats)
309{
310 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_ATU_STATS, stats);
311}
312
313
314
315static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
316 u8 data)
317{
318 u16 val = (pointer << 8) | (data & 0x7);
319
320 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_PRIO_OVERRIDE,
321 MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE | val);
322}
323
324int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
325{
326 int i, err;
327
328
329 for (i = 0; i < 16; i++) {
330 err = mv88e6xxx_g2_pot_write(chip, i, 0);
331 if (err)
332 break;
333 }
334
335 return err;
336}
337
338
339
340
341
342
343static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
344{
345 int bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_BUSY);
346 int err;
347
348 err = mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0);
349 if (err)
350 return err;
351
352 bit = __bf_shf(MV88E6XXX_G2_EEPROM_CMD_RUNNING);
353
354 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_EEPROM_CMD, bit, 0);
355}
356
357static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
358{
359 int err;
360
361 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_EEPROM_CMD,
362 MV88E6XXX_G2_EEPROM_CMD_BUSY | cmd);
363 if (err)
364 return err;
365
366 return mv88e6xxx_g2_eeprom_wait(chip);
367}
368
369static int mv88e6xxx_g2_eeprom_read8(struct mv88e6xxx_chip *chip,
370 u16 addr, u8 *data)
371{
372 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ;
373 int err;
374
375 err = mv88e6xxx_g2_eeprom_wait(chip);
376 if (err)
377 return err;
378
379 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
380 if (err)
381 return err;
382
383 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
384 if (err)
385 return err;
386
387 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &cmd);
388 if (err)
389 return err;
390
391 *data = cmd & 0xff;
392
393 return 0;
394}
395
396static int mv88e6xxx_g2_eeprom_write8(struct mv88e6xxx_chip *chip,
397 u16 addr, u8 data)
398{
399 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE |
400 MV88E6XXX_G2_EEPROM_CMD_WRITE_EN;
401 int err;
402
403 err = mv88e6xxx_g2_eeprom_wait(chip);
404 if (err)
405 return err;
406
407 err = mv88e6xxx_g2_write(chip, MV88E6390_G2_EEPROM_ADDR, addr);
408 if (err)
409 return err;
410
411 return mv88e6xxx_g2_eeprom_cmd(chip, cmd | data);
412}
413
414static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
415 u8 addr, u16 *data)
416{
417 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_READ | addr;
418 int err;
419
420 err = mv88e6xxx_g2_eeprom_wait(chip);
421 if (err)
422 return err;
423
424 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
425 if (err)
426 return err;
427
428 return mv88e6xxx_g2_read(chip, MV88E6352_G2_EEPROM_DATA, data);
429}
430
431static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
432 u8 addr, u16 data)
433{
434 u16 cmd = MV88E6XXX_G2_EEPROM_CMD_OP_WRITE | addr;
435 int err;
436
437 err = mv88e6xxx_g2_eeprom_wait(chip);
438 if (err)
439 return err;
440
441 err = mv88e6xxx_g2_write(chip, MV88E6352_G2_EEPROM_DATA, data);
442 if (err)
443 return err;
444
445 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
446}
447
448int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
449 struct ethtool_eeprom *eeprom, u8 *data)
450{
451 unsigned int offset = eeprom->offset;
452 unsigned int len = eeprom->len;
453 int err;
454
455 eeprom->len = 0;
456
457 while (len) {
458 err = mv88e6xxx_g2_eeprom_read8(chip, offset, data);
459 if (err)
460 return err;
461
462 eeprom->len++;
463 offset++;
464 data++;
465 len--;
466 }
467
468 return 0;
469}
470
471int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
472 struct ethtool_eeprom *eeprom, u8 *data)
473{
474 unsigned int offset = eeprom->offset;
475 unsigned int len = eeprom->len;
476 int err;
477
478 eeprom->len = 0;
479
480 while (len) {
481 err = mv88e6xxx_g2_eeprom_write8(chip, offset, *data);
482 if (err)
483 return err;
484
485 eeprom->len++;
486 offset++;
487 data++;
488 len--;
489 }
490
491 return 0;
492}
493
494int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
495 struct ethtool_eeprom *eeprom, u8 *data)
496{
497 unsigned int offset = eeprom->offset;
498 unsigned int len = eeprom->len;
499 u16 val;
500 int err;
501
502 eeprom->len = 0;
503
504 if (offset & 1) {
505 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
506 if (err)
507 return err;
508
509 *data++ = (val >> 8) & 0xff;
510
511 offset++;
512 len--;
513 eeprom->len++;
514 }
515
516 while (len >= 2) {
517 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
518 if (err)
519 return err;
520
521 *data++ = val & 0xff;
522 *data++ = (val >> 8) & 0xff;
523
524 offset += 2;
525 len -= 2;
526 eeprom->len += 2;
527 }
528
529 if (len) {
530 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
531 if (err)
532 return err;
533
534 *data++ = val & 0xff;
535
536 offset++;
537 len--;
538 eeprom->len++;
539 }
540
541 return 0;
542}
543
544int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
545 struct ethtool_eeprom *eeprom, u8 *data)
546{
547 unsigned int offset = eeprom->offset;
548 unsigned int len = eeprom->len;
549 u16 val;
550 int err;
551
552
553 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_EEPROM_CMD, &val);
554 if (err)
555 return err;
556
557 if (!(val & MV88E6XXX_G2_EEPROM_CMD_WRITE_EN))
558 return -EROFS;
559
560 eeprom->len = 0;
561
562 if (offset & 1) {
563 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
564 if (err)
565 return err;
566
567 val = (*data++ << 8) | (val & 0xff);
568
569 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
570 if (err)
571 return err;
572
573 offset++;
574 len--;
575 eeprom->len++;
576 }
577
578 while (len >= 2) {
579 val = *data++;
580 val |= *data++ << 8;
581
582 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
583 if (err)
584 return err;
585
586 offset += 2;
587 len -= 2;
588 eeprom->len += 2;
589 }
590
591 if (len) {
592 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
593 if (err)
594 return err;
595
596 val = (val & 0xff00) | *data++;
597
598 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
599 if (err)
600 return err;
601
602 offset++;
603 len--;
604 eeprom->len++;
605 }
606
607 return 0;
608}
609
610
611
612
613
614static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
615{
616 int bit = __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_BUSY);
617
618 return mv88e6xxx_g2_wait_bit(chip, MV88E6XXX_G2_SMI_PHY_CMD, bit, 0);
619}
620
621static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
622{
623 int err;
624
625 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_CMD,
626 MV88E6XXX_G2_SMI_PHY_CMD_BUSY | cmd);
627 if (err)
628 return err;
629
630 return mv88e6xxx_g2_smi_phy_wait(chip);
631}
632
633static int mv88e6xxx_g2_smi_phy_access(struct mv88e6xxx_chip *chip,
634 bool external, bool c45, u16 op, int dev,
635 int reg)
636{
637 u16 cmd = op;
638
639 if (external)
640 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL;
641 else
642 cmd |= MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL;
643
644 if (c45)
645 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_45;
646 else
647 cmd |= MV88E6XXX_G2_SMI_PHY_CMD_MODE_22;
648
649 dev <<= __bf_shf(MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK);
650 cmd |= dev & MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK;
651 cmd |= reg & MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK;
652
653 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
654}
655
656static int mv88e6xxx_g2_smi_phy_access_c22(struct mv88e6xxx_chip *chip,
657 bool external, u16 op, int dev,
658 int reg)
659{
660 return mv88e6xxx_g2_smi_phy_access(chip, external, false, op, dev, reg);
661}
662
663
664static int mv88e6xxx_g2_smi_phy_read_data_c22(struct mv88e6xxx_chip *chip,
665 bool external, int dev, int reg,
666 u16 *data)
667{
668 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA;
669 int err;
670
671 err = mv88e6xxx_g2_smi_phy_wait(chip);
672 if (err)
673 return err;
674
675 err = mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
676 if (err)
677 return err;
678
679 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
680}
681
682
683static int mv88e6xxx_g2_smi_phy_write_data_c22(struct mv88e6xxx_chip *chip,
684 bool external, int dev, int reg,
685 u16 data)
686{
687 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA;
688 int err;
689
690 err = mv88e6xxx_g2_smi_phy_wait(chip);
691 if (err)
692 return err;
693
694 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
695 if (err)
696 return err;
697
698 return mv88e6xxx_g2_smi_phy_access_c22(chip, external, op, dev, reg);
699}
700
701static int mv88e6xxx_g2_smi_phy_access_c45(struct mv88e6xxx_chip *chip,
702 bool external, u16 op, int port,
703 int dev)
704{
705 return mv88e6xxx_g2_smi_phy_access(chip, external, true, op, port, dev);
706}
707
708
709static int mv88e6xxx_g2_smi_phy_write_addr_c45(struct mv88e6xxx_chip *chip,
710 bool external, int port, int dev,
711 int addr)
712{
713 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR;
714 int err;
715
716 err = mv88e6xxx_g2_smi_phy_wait(chip);
717 if (err)
718 return err;
719
720 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, addr);
721 if (err)
722 return err;
723
724 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
725}
726
727
728static int mv88e6xxx_g2_smi_phy_read_data_c45(struct mv88e6xxx_chip *chip,
729 bool external, int port, int dev,
730 u16 *data)
731{
732 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA;
733 int err;
734
735 err = mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
736 if (err)
737 return err;
738
739 return mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
740}
741
742static int mv88e6xxx_g2_smi_phy_read_c45(struct mv88e6xxx_chip *chip,
743 bool external, int port, int reg,
744 u16 *data)
745{
746 int dev = (reg >> 16) & 0x1f;
747 int addr = reg & 0xffff;
748 int err;
749
750 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
751 addr);
752 if (err)
753 return err;
754
755 return mv88e6xxx_g2_smi_phy_read_data_c45(chip, external, port, dev,
756 data);
757}
758
759
760static int mv88e6xxx_g2_smi_phy_write_data_c45(struct mv88e6xxx_chip *chip,
761 bool external, int port, int dev,
762 u16 data)
763{
764 u16 op = MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA;
765 int err;
766
767 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SMI_PHY_DATA, data);
768 if (err)
769 return err;
770
771 return mv88e6xxx_g2_smi_phy_access_c45(chip, external, op, port, dev);
772}
773
774static int mv88e6xxx_g2_smi_phy_write_c45(struct mv88e6xxx_chip *chip,
775 bool external, int port, int reg,
776 u16 data)
777{
778 int dev = (reg >> 16) & 0x1f;
779 int addr = reg & 0xffff;
780 int err;
781
782 err = mv88e6xxx_g2_smi_phy_write_addr_c45(chip, external, port, dev,
783 addr);
784 if (err)
785 return err;
786
787 return mv88e6xxx_g2_smi_phy_write_data_c45(chip, external, port, dev,
788 data);
789}
790
791int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
792 int addr, int reg, u16 *val)
793{
794 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
795 bool external = mdio_bus->external;
796
797 if (reg & MII_ADDR_C45)
798 return mv88e6xxx_g2_smi_phy_read_c45(chip, external, addr, reg,
799 val);
800
801 return mv88e6xxx_g2_smi_phy_read_data_c22(chip, external, addr, reg,
802 val);
803}
804
805int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
806 int addr, int reg, u16 val)
807{
808 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
809 bool external = mdio_bus->external;
810
811 if (reg & MII_ADDR_C45)
812 return mv88e6xxx_g2_smi_phy_write_c45(chip, external, addr, reg,
813 val);
814
815 return mv88e6xxx_g2_smi_phy_write_data_c22(chip, external, addr, reg,
816 val);
817}
818
819
820static int mv88e6097_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
821{
822 u16 reg;
823
824 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
825
826 dev_info(chip->dev, "Watchdog event: 0x%04x", reg);
827
828 return IRQ_HANDLED;
829}
830
831static void mv88e6097_watchdog_free(struct mv88e6xxx_chip *chip)
832{
833 u16 reg;
834
835 mv88e6xxx_g2_read(chip, MV88E6352_G2_WDOG_CTL, ®);
836
837 reg &= ~(MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
838 MV88E6352_G2_WDOG_CTL_QC_ENABLE);
839
840 mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL, reg);
841}
842
843static int mv88e6097_watchdog_setup(struct mv88e6xxx_chip *chip)
844{
845 return mv88e6xxx_g2_write(chip, MV88E6352_G2_WDOG_CTL,
846 MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE |
847 MV88E6352_G2_WDOG_CTL_QC_ENABLE |
848 MV88E6352_G2_WDOG_CTL_SWRESET);
849}
850
851const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {
852 .irq_action = mv88e6097_watchdog_action,
853 .irq_setup = mv88e6097_watchdog_setup,
854 .irq_free = mv88e6097_watchdog_free,
855};
856
857static void mv88e6250_watchdog_free(struct mv88e6xxx_chip *chip)
858{
859 u16 reg;
860
861 mv88e6xxx_g2_read(chip, MV88E6250_G2_WDOG_CTL, ®);
862
863 reg &= ~(MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE |
864 MV88E6250_G2_WDOG_CTL_QC_ENABLE);
865
866 mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL, reg);
867}
868
869static int mv88e6250_watchdog_setup(struct mv88e6xxx_chip *chip)
870{
871 return mv88e6xxx_g2_write(chip, MV88E6250_G2_WDOG_CTL,
872 MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE |
873 MV88E6250_G2_WDOG_CTL_QC_ENABLE |
874 MV88E6250_G2_WDOG_CTL_SWRESET);
875}
876
877const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = {
878 .irq_action = mv88e6097_watchdog_action,
879 .irq_setup = mv88e6250_watchdog_setup,
880 .irq_free = mv88e6250_watchdog_free,
881};
882
883static int mv88e6390_watchdog_setup(struct mv88e6xxx_chip *chip)
884{
885 return mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
886 MV88E6390_G2_WDOG_CTL_UPDATE |
887 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE |
888 MV88E6390_G2_WDOG_CTL_CUT_THROUGH |
889 MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER |
890 MV88E6390_G2_WDOG_CTL_EGRESS |
891 MV88E6390_G2_WDOG_CTL_FORCE_IRQ);
892}
893
894static int mv88e6390_watchdog_action(struct mv88e6xxx_chip *chip, int irq)
895{
896 u16 reg;
897
898 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
899 MV88E6390_G2_WDOG_CTL_PTR_EVENT);
900 mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
901
902 dev_info(chip->dev, "Watchdog event: 0x%04x",
903 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
904
905 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
906 MV88E6390_G2_WDOG_CTL_PTR_HISTORY);
907 mv88e6xxx_g2_read(chip, MV88E6390_G2_WDOG_CTL, ®);
908
909 dev_info(chip->dev, "Watchdog history: 0x%04x",
910 reg & MV88E6390_G2_WDOG_CTL_DATA_MASK);
911
912
913 if (chip->info->ops->reset)
914 chip->info->ops->reset(chip);
915
916 mv88e6390_watchdog_setup(chip);
917
918 return IRQ_HANDLED;
919}
920
921static void mv88e6390_watchdog_free(struct mv88e6xxx_chip *chip)
922{
923 mv88e6xxx_g2_write(chip, MV88E6390_G2_WDOG_CTL,
924 MV88E6390_G2_WDOG_CTL_UPDATE |
925 MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE);
926}
927
928const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {
929 .irq_action = mv88e6390_watchdog_action,
930 .irq_setup = mv88e6390_watchdog_setup,
931 .irq_free = mv88e6390_watchdog_free,
932};
933
934static irqreturn_t mv88e6xxx_g2_watchdog_thread_fn(int irq, void *dev_id)
935{
936 struct mv88e6xxx_chip *chip = dev_id;
937 irqreturn_t ret = IRQ_NONE;
938
939 mv88e6xxx_reg_lock(chip);
940 if (chip->info->ops->watchdog_ops->irq_action)
941 ret = chip->info->ops->watchdog_ops->irq_action(chip, irq);
942 mv88e6xxx_reg_unlock(chip);
943
944 return ret;
945}
946
947static void mv88e6xxx_g2_watchdog_free(struct mv88e6xxx_chip *chip)
948{
949 mv88e6xxx_reg_lock(chip);
950 if (chip->info->ops->watchdog_ops->irq_free)
951 chip->info->ops->watchdog_ops->irq_free(chip);
952 mv88e6xxx_reg_unlock(chip);
953
954 free_irq(chip->watchdog_irq, chip);
955 irq_dispose_mapping(chip->watchdog_irq);
956}
957
958static int mv88e6xxx_g2_watchdog_setup(struct mv88e6xxx_chip *chip)
959{
960 int err;
961
962 chip->watchdog_irq = irq_find_mapping(chip->g2_irq.domain,
963 MV88E6XXX_G2_INT_SOURCE_WATCHDOG);
964 if (chip->watchdog_irq < 0)
965 return chip->watchdog_irq;
966
967 snprintf(chip->watchdog_irq_name, sizeof(chip->watchdog_irq_name),
968 "mv88e6xxx-%s-watchdog", dev_name(chip->dev));
969
970 err = request_threaded_irq(chip->watchdog_irq, NULL,
971 mv88e6xxx_g2_watchdog_thread_fn,
972 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
973 chip->watchdog_irq_name, chip);
974 if (err)
975 return err;
976
977 mv88e6xxx_reg_lock(chip);
978 if (chip->info->ops->watchdog_ops->irq_setup)
979 err = chip->info->ops->watchdog_ops->irq_setup(chip);
980 mv88e6xxx_reg_unlock(chip);
981
982 return err;
983}
984
985
986
987static int mv88e6xxx_g2_misc_5_bit_port(struct mv88e6xxx_chip *chip,
988 bool port_5_bit)
989{
990 u16 val;
991 int err;
992
993 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_MISC, &val);
994 if (err)
995 return err;
996
997 if (port_5_bit)
998 val |= MV88E6XXX_G2_MISC_5_BIT_PORT;
999 else
1000 val &= ~MV88E6XXX_G2_MISC_5_BIT_PORT;
1001
1002 return mv88e6xxx_g2_write(chip, MV88E6XXX_G2_MISC, val);
1003}
1004
1005int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
1006{
1007 return mv88e6xxx_g2_misc_5_bit_port(chip, false);
1008}
1009
1010static void mv88e6xxx_g2_irq_mask(struct irq_data *d)
1011{
1012 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1013 unsigned int n = d->hwirq;
1014
1015 chip->g2_irq.masked |= (1 << n);
1016}
1017
1018static void mv88e6xxx_g2_irq_unmask(struct irq_data *d)
1019{
1020 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1021 unsigned int n = d->hwirq;
1022
1023 chip->g2_irq.masked &= ~(1 << n);
1024}
1025
1026static irqreturn_t mv88e6xxx_g2_irq_thread_fn(int irq, void *dev_id)
1027{
1028 struct mv88e6xxx_chip *chip = dev_id;
1029 unsigned int nhandled = 0;
1030 unsigned int sub_irq;
1031 unsigned int n;
1032 int err;
1033 u16 reg;
1034
1035 mv88e6xxx_reg_lock(chip);
1036 err = mv88e6xxx_g2_int_source(chip, ®);
1037 mv88e6xxx_reg_unlock(chip);
1038 if (err)
1039 goto out;
1040
1041 for (n = 0; n < 16; ++n) {
1042 if (reg & (1 << n)) {
1043 sub_irq = irq_find_mapping(chip->g2_irq.domain, n);
1044 handle_nested_irq(sub_irq);
1045 ++nhandled;
1046 }
1047 }
1048out:
1049 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
1050}
1051
1052static void mv88e6xxx_g2_irq_bus_lock(struct irq_data *d)
1053{
1054 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1055
1056 mv88e6xxx_reg_lock(chip);
1057}
1058
1059static void mv88e6xxx_g2_irq_bus_sync_unlock(struct irq_data *d)
1060{
1061 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
1062 int err;
1063
1064 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1065 if (err)
1066 dev_err(chip->dev, "failed to mask interrupts\n");
1067
1068 mv88e6xxx_reg_unlock(chip);
1069}
1070
1071static const struct irq_chip mv88e6xxx_g2_irq_chip = {
1072 .name = "mv88e6xxx-g2",
1073 .irq_mask = mv88e6xxx_g2_irq_mask,
1074 .irq_unmask = mv88e6xxx_g2_irq_unmask,
1075 .irq_bus_lock = mv88e6xxx_g2_irq_bus_lock,
1076 .irq_bus_sync_unlock = mv88e6xxx_g2_irq_bus_sync_unlock,
1077};
1078
1079static int mv88e6xxx_g2_irq_domain_map(struct irq_domain *d,
1080 unsigned int irq,
1081 irq_hw_number_t hwirq)
1082{
1083 struct mv88e6xxx_chip *chip = d->host_data;
1084
1085 irq_set_chip_data(irq, d->host_data);
1086 irq_set_chip_and_handler(irq, &chip->g2_irq.chip, handle_level_irq);
1087 irq_set_noprobe(irq);
1088
1089 return 0;
1090}
1091
1092static const struct irq_domain_ops mv88e6xxx_g2_irq_domain_ops = {
1093 .map = mv88e6xxx_g2_irq_domain_map,
1094 .xlate = irq_domain_xlate_twocell,
1095};
1096
1097void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
1098{
1099 int irq, virq;
1100
1101 mv88e6xxx_g2_watchdog_free(chip);
1102
1103 free_irq(chip->device_irq, chip);
1104 irq_dispose_mapping(chip->device_irq);
1105
1106 for (irq = 0; irq < 16; irq++) {
1107 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1108 irq_dispose_mapping(virq);
1109 }
1110
1111 irq_domain_remove(chip->g2_irq.domain);
1112}
1113
1114int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
1115{
1116 int err, irq, virq;
1117
1118 chip->g2_irq.masked = ~0;
1119 mv88e6xxx_reg_lock(chip);
1120 err = mv88e6xxx_g2_int_mask(chip, ~chip->g2_irq.masked);
1121 mv88e6xxx_reg_unlock(chip);
1122 if (err)
1123 return err;
1124
1125 chip->g2_irq.domain = irq_domain_add_simple(
1126 chip->dev->of_node, 16, 0, &mv88e6xxx_g2_irq_domain_ops, chip);
1127 if (!chip->g2_irq.domain)
1128 return -ENOMEM;
1129
1130 for (irq = 0; irq < 16; irq++)
1131 irq_create_mapping(chip->g2_irq.domain, irq);
1132
1133 chip->g2_irq.chip = mv88e6xxx_g2_irq_chip;
1134
1135 chip->device_irq = irq_find_mapping(chip->g1_irq.domain,
1136 MV88E6XXX_G1_STS_IRQ_DEVICE);
1137 if (chip->device_irq < 0) {
1138 err = chip->device_irq;
1139 goto out;
1140 }
1141
1142 snprintf(chip->device_irq_name, sizeof(chip->device_irq_name),
1143 "mv88e6xxx-%s-g2", dev_name(chip->dev));
1144
1145 err = request_threaded_irq(chip->device_irq, NULL,
1146 mv88e6xxx_g2_irq_thread_fn,
1147 IRQF_ONESHOT, chip->device_irq_name, chip);
1148 if (err)
1149 goto out;
1150
1151 return mv88e6xxx_g2_watchdog_setup(chip);
1152
1153out:
1154 for (irq = 0; irq < 16; irq++) {
1155 virq = irq_find_mapping(chip->g2_irq.domain, irq);
1156 irq_dispose_mapping(virq);
1157 }
1158
1159 irq_domain_remove(chip->g2_irq.domain);
1160
1161 return err;
1162}
1163
1164int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
1165 struct mii_bus *bus)
1166{
1167 int phy, irq, err, err_phy;
1168
1169 for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
1170 irq = irq_find_mapping(chip->g2_irq.domain, phy);
1171 if (irq < 0) {
1172 err = irq;
1173 goto out;
1174 }
1175 bus->irq[chip->info->phy_base_addr + phy] = irq;
1176 }
1177 return 0;
1178out:
1179 err_phy = phy;
1180
1181 for (phy = 0; phy < err_phy; phy++)
1182 irq_dispose_mapping(bus->irq[phy]);
1183
1184 return err;
1185}
1186
1187void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
1188 struct mii_bus *bus)
1189{
1190 int phy;
1191
1192 for (phy = 0; phy < chip->info->num_internal_phys; phy++)
1193 irq_dispose_mapping(bus->irq[phy]);
1194}
1195
