LXR linux/drivers/net/dsa/mv88e6xxx/serdes.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
   4 *
   5 * Copyright (c) 2008 Marvell Semiconductor
   6 *
   7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   8 */
   9
  10#ifndef _MV88E6XXX_SERDES_H
  11#define _MV88E6XXX_SERDES_H
  12
  13#include "chip.h"
  14
  15#define MV88E6352_ADDR_SERDES           0x0f
  16#define MV88E6352_SERDES_PAGE_FIBER     0x01
  17#define MV88E6352_SERDES_IRQ            0x0b
  18#define MV88E6352_SERDES_INT_ENABLE     0x12
  19#define MV88E6352_SERDES_INT_SPEED_CHANGE       BIT(14)
  20#define MV88E6352_SERDES_INT_DUPLEX_CHANGE      BIT(13)
  21#define MV88E6352_SERDES_INT_PAGE_RX            BIT(12)
  22#define MV88E6352_SERDES_INT_AN_COMPLETE        BIT(11)
  23#define MV88E6352_SERDES_INT_LINK_CHANGE        BIT(10)
  24#define MV88E6352_SERDES_INT_SYMBOL_ERROR       BIT(9)
  25#define MV88E6352_SERDES_INT_FALSE_CARRIER      BIT(8)
  26#define MV88E6352_SERDES_INT_FIFO_OVER_UNDER    BIT(7)
  27#define MV88E6352_SERDES_INT_FIBRE_ENERGY       BIT(4)
  28#define MV88E6352_SERDES_INT_STATUS     0x13
  29
  30
  31#define MV88E6341_PORT5_LANE            0x15
  32
  33#define MV88E6390_PORT9_LANE0           0x09
  34#define MV88E6390_PORT9_LANE1           0x12
  35#define MV88E6390_PORT9_LANE2           0x13
  36#define MV88E6390_PORT9_LANE3           0x14
  37#define MV88E6390_PORT10_LANE0          0x0a
  38#define MV88E6390_PORT10_LANE1          0x15
  39#define MV88E6390_PORT10_LANE2          0x16
  40#define MV88E6390_PORT10_LANE3          0x17
  41
  42/* 10GBASE-R and 10GBASE-X4/X2 */
  43#define MV88E6390_10G_CTRL1             (0x1000 + MDIO_CTRL1)
  44#define MV88E6390_10G_STAT1             (0x1000 + MDIO_STAT1)
  45#define MV88E6393X_10G_INT_ENABLE       0x9000
  46#define MV88E6393X_10G_INT_LINK_CHANGE  BIT(2)
  47#define MV88E6393X_10G_INT_STATUS       0x9001
  48
  49/* 1000BASE-X and SGMII */
  50#define MV88E6390_SGMII_BMCR            (0x2000 + MII_BMCR)
  51#define MV88E6390_SGMII_BMSR            (0x2000 + MII_BMSR)
  52#define MV88E6390_SGMII_ADVERTISE       (0x2000 + MII_ADVERTISE)
  53#define MV88E6390_SGMII_LPA             (0x2000 + MII_LPA)
  54#define MV88E6390_SGMII_INT_ENABLE      0xa001
  55#define MV88E6390_SGMII_INT_SPEED_CHANGE        BIT(14)
  56#define MV88E6390_SGMII_INT_DUPLEX_CHANGE       BIT(13)
  57#define MV88E6390_SGMII_INT_PAGE_RX             BIT(12)
  58#define MV88E6390_SGMII_INT_AN_COMPLETE         BIT(11)
  59#define MV88E6390_SGMII_INT_LINK_DOWN           BIT(10)
  60#define MV88E6390_SGMII_INT_LINK_UP             BIT(9)
  61#define MV88E6390_SGMII_INT_SYMBOL_ERROR        BIT(8)
  62#define MV88E6390_SGMII_INT_FALSE_CARRIER       BIT(7)
  63#define MV88E6390_SGMII_INT_STATUS      0xa002
  64#define MV88E6390_SGMII_PHY_STATUS      0xa003
  65#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK   GENMASK(15, 14)
  66#define MV88E6390_SGMII_PHY_STATUS_SPEED_1000   0x8000
  67#define MV88E6390_SGMII_PHY_STATUS_SPEED_100    0x4000
  68#define MV88E6390_SGMII_PHY_STATUS_SPEED_10     0x0000
  69#define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL  BIT(13)
  70#define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
  71#define MV88E6390_SGMII_PHY_STATUS_LINK         BIT(10)
  72#define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE     BIT(3)
  73#define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE     BIT(2)
  74
  75/* Packet generator pad packet checker */
  76#define MV88E6390_PG_CONTROL            0xf010
  77#define MV88E6390_PG_CONTROL_ENABLE_PC          BIT(0)
  78
  79#define MV88E6393X_PORT0_LANE                   0x00
  80#define MV88E6393X_PORT9_LANE                   0x09
  81#define MV88E6393X_PORT10_LANE                  0x0a
  82
  83/* Port Operational Configuration */
  84#define MV88E6393X_SERDES_POC                   0xf002
  85#define MV88E6393X_SERDES_POC_PCS_1000BASEX     0x0000
  86#define MV88E6393X_SERDES_POC_PCS_2500BASEX     0x0001
  87#define MV88E6393X_SERDES_POC_PCS_SGMII_PHY     0x0002
  88#define MV88E6393X_SERDES_POC_PCS_SGMII_MAC     0x0003
  89#define MV88E6393X_SERDES_POC_PCS_5GBASER       0x0004
  90#define MV88E6393X_SERDES_POC_PCS_10GBASER      0x0005
  91#define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY   0x0006
  92#define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC   0x0007
  93#define MV88E6393X_SERDES_POC_PCS_MASK          0x0007
  94#define MV88E6393X_SERDES_POC_RESET             BIT(15)
  95#define MV88E6393X_SERDES_POC_PDOWN             BIT(5)
  96
  97#define MV88E6393X_ERRATA_4_8_REG               0xF074
  98#define MV88E6393X_ERRATA_4_8_BIT               BIT(14)
  99
 100int mv88e6185_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
 101int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
 102int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
 103int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
 104int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
 105int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
 106int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 107                                int lane, unsigned int mode,
 108                                phy_interface_t interface,
 109                                const unsigned long *advertise);
 110int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
 111                                int lane, unsigned int mode,
 112                                phy_interface_t interface,
 113                                const unsigned long *advertise);
 114int mv88e6185_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
 115                                   int lane, struct phylink_link_state *state);
 116int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
 117                                   int lane, struct phylink_link_state *state);
 118int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
 119                                   int lane, struct phylink_link_state *state);
 120int mv88e6393x_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
 121                                    int lane, struct phylink_link_state *state);
 122int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
 123                                    int lane);
 124int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
 125                                    int lane);
 126int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 127                                 int lane, int speed, int duplex);
 128int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
 129                                 int lane, int speed, int duplex);
 130unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
 131                                          int port);
 132unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
 133                                          int port);
 134int mv88e6185_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
 135                           bool up);
 136int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
 137                           bool on);
 138int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
 139                           bool on);
 140int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
 141                            bool on);
 142int mv88e6393x_serdes_setup_errata(struct mv88e6xxx_chip *chip);
 143int mv88e6097_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
 144                                bool enable);
 145int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
 146                                bool enable);
 147int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
 148                                bool enable);
 149int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port,
 150                                 int lane, bool enable);
 151irqreturn_t mv88e6097_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
 152                                        int lane);
 153irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
 154                                        int lane);
 155irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
 156                                        int lane);
 157irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
 158                                         int lane);
 159int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
 160int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
 161                                 int port, uint8_t *data);
 162int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
 163                               uint64_t *data);
 164int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
 165int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
 166                                 int port, uint8_t *data);
 167int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
 168                               uint64_t *data);
 169
 170int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
 171void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
 172int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
 173void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
 174
 175/* Return the (first) SERDES lane address a port is using, -errno otherwise. */
 176static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
 177                                            int port)
 178{
 179        if (!chip->info->ops->serdes_get_lane)
 180                return -EOPNOTSUPP;
 181
 182        return chip->info->ops->serdes_get_lane(chip, port);
 183}
 184
 185static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip,
 186                                            int port, int lane)
 187{
 188        if (!chip->info->ops->serdes_power)
 189                return -EOPNOTSUPP;
 190
 191        return chip->info->ops->serdes_power(chip, port, lane, true);
 192}
 193
 194static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip,
 195                                              int port, int lane)
 196{
 197        if (!chip->info->ops->serdes_power)
 198                return -EOPNOTSUPP;
 199
 200        return chip->info->ops->serdes_power(chip, port, lane, false);
 201}
 202
 203static inline unsigned int
 204mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
 205{
 206        if (!chip->info->ops->serdes_irq_mapping)
 207                return 0;
 208
 209        return chip->info->ops->serdes_irq_mapping(chip, port);
 210}
 211
 212static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip,
 213                                              int port, int lane)
 214{
 215        if (!chip->info->ops->serdes_irq_enable)
 216                return -EOPNOTSUPP;
 217
 218        return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
 219}
 220
 221static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip,
 222                                               int port, int lane)
 223{
 224        if (!chip->info->ops->serdes_irq_enable)
 225                return -EOPNOTSUPP;
 226
 227        return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
 228}
 229
 230static inline irqreturn_t
 231mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane)
 232{
 233        if (!chip->info->ops->serdes_irq_status)
 234                return IRQ_NONE;
 235
 236        return chip->info->ops->serdes_irq_status(chip, port, lane);
 237}
 238
 239#endif
 240