1
2
3
4
5#ifndef _SJA1105_H
6#define _SJA1105_H
7
8#include <linux/ptp_clock_kernel.h>
9#include <linux/timecounter.h>
10#include <linux/dsa/sja1105.h>
11#include <linux/dsa/8021q.h>
12#include <net/dsa.h>
13#include <linux/mutex.h>
14#include "sja1105_static_config.h"
15
16#define SJA1105ET_FDB_BIN_SIZE 4
17
18
19
20#define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10)
21#define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT
22
23typedef enum {
24 SPI_READ = 0,
25 SPI_WRITE = 1,
26} sja1105_spi_rw_mode_t;
27
28#include "sja1105_tas.h"
29#include "sja1105_ptp.h"
30
31enum sja1105_stats_area {
32 MAC,
33 HL1,
34 HL2,
35 ETHER,
36 __MAX_SJA1105_STATS_AREA,
37};
38
39
40struct sja1105_regs {
41 u64 device_id;
42 u64 prod_id;
43 u64 status;
44 u64 port_control;
45 u64 rgu;
46 u64 vl_status;
47 u64 config;
48 u64 rmii_pll1;
49 u64 ptppinst;
50 u64 ptppindur;
51 u64 ptp_control;
52 u64 ptpclkval;
53 u64 ptpclkrate;
54 u64 ptpclkcorp;
55 u64 ptpsyncts;
56 u64 ptpschtm;
57 u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS];
58 u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS];
59 u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS];
60 u64 pad_mii_id[SJA1105_MAX_NUM_PORTS];
61 u64 cgu_idiv[SJA1105_MAX_NUM_PORTS];
62 u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS];
63 u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS];
64 u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
65 u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS];
66 u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS];
67 u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS];
68 u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS];
69 u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS];
70 u64 mdio_100base_tx;
71 u64 mdio_100base_t1;
72 u64 pcs_base[SJA1105_MAX_NUM_PORTS];
73};
74
75struct sja1105_mdio_private {
76 struct sja1105_private *priv;
77};
78
79enum {
80 SJA1105_SPEED_AUTO,
81 SJA1105_SPEED_10MBPS,
82 SJA1105_SPEED_100MBPS,
83 SJA1105_SPEED_1000MBPS,
84 SJA1105_SPEED_2500MBPS,
85 SJA1105_SPEED_MAX,
86};
87
88enum sja1105_internal_phy_t {
89 SJA1105_NO_PHY = 0,
90 SJA1105_PHY_BASE_TX,
91 SJA1105_PHY_BASE_T1,
92};
93
94struct sja1105_info {
95 u64 device_id;
96
97
98
99
100 u64 part_no;
101
102
103
104
105 int ptp_ts_bits;
106
107
108
109 int ptpegr_ts_bytes;
110 int num_cbs_shapers;
111 int max_frame_mem;
112 int num_ports;
113 bool multiple_cascade_ports;
114 enum dsa_tag_protocol tag_proto;
115 const struct sja1105_dynamic_table_ops *dyn_ops;
116 const struct sja1105_table_ops *static_ops;
117 const struct sja1105_regs *regs;
118 bool can_limit_mcast_flood;
119 int (*reset_cmd)(struct dsa_switch *ds);
120 int (*setup_rgmii_delay)(const void *ctx, int port);
121
122 int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
123 const unsigned char *addr, u16 vid);
124 int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
125 const unsigned char *addr, u16 vid);
126 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
127 enum packing_op op);
128 bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
129 void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);
130 int (*clocking_setup)(struct sja1105_private *priv);
131 int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg);
132 int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val);
133 int (*disable_microcontroller)(struct sja1105_private *priv);
134 const char *name;
135 bool supports_mii[SJA1105_MAX_NUM_PORTS];
136 bool supports_rmii[SJA1105_MAX_NUM_PORTS];
137 bool supports_rgmii[SJA1105_MAX_NUM_PORTS];
138 bool supports_sgmii[SJA1105_MAX_NUM_PORTS];
139 bool supports_2500basex[SJA1105_MAX_NUM_PORTS];
140 enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS];
141 const u64 port_speed[SJA1105_SPEED_MAX];
142};
143
144enum sja1105_key_type {
145 SJA1105_KEY_BCAST,
146 SJA1105_KEY_TC,
147 SJA1105_KEY_VLAN_UNAWARE_VL,
148 SJA1105_KEY_VLAN_AWARE_VL,
149};
150
151struct sja1105_key {
152 enum sja1105_key_type type;
153
154 union {
155
156 struct {
157 int pcp;
158 } tc;
159
160
161
162 struct {
163 u64 dmac;
164 u16 vid;
165 u16 pcp;
166 } vl;
167 };
168};
169
170enum sja1105_rule_type {
171 SJA1105_RULE_BCAST_POLICER,
172 SJA1105_RULE_TC_POLICER,
173 SJA1105_RULE_VL,
174};
175
176enum sja1105_vl_type {
177 SJA1105_VL_NONCRITICAL,
178 SJA1105_VL_RATE_CONSTRAINED,
179 SJA1105_VL_TIME_TRIGGERED,
180};
181
182struct sja1105_rule {
183 struct list_head list;
184 unsigned long cookie;
185 unsigned long port_mask;
186 struct sja1105_key key;
187 enum sja1105_rule_type type;
188
189
190 union {
191
192 struct {
193 int sharindx;
194 } bcast_pol;
195
196
197 struct {
198 int sharindx;
199 } tc_pol;
200
201
202 struct {
203 enum sja1105_vl_type type;
204 unsigned long destports;
205 int sharindx;
206 int maxlen;
207 int ipv;
208 u64 base_time;
209 u64 cycle_time;
210 int num_entries;
211 struct action_gate_entry *entries;
212 struct flow_stats stats;
213 } vl;
214 };
215};
216
217struct sja1105_flow_block {
218 struct list_head rules;
219 bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
220 int num_virtual_links;
221};
222
223struct sja1105_private {
224 struct sja1105_static_config static_config;
225 bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS];
226 bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS];
227 phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS];
228 bool fixed_link[SJA1105_MAX_NUM_PORTS];
229 bool vlan_aware;
230 unsigned long ucast_egress_floods;
231 unsigned long bcast_egress_floods;
232 const struct sja1105_info *info;
233 size_t max_xfer_len;
234 struct gpio_desc *reset_gpio;
235 struct spi_device *spidev;
236 struct dsa_switch *ds;
237 u16 bridge_pvid[SJA1105_MAX_NUM_PORTS];
238 u16 tag_8021q_pvid[SJA1105_MAX_NUM_PORTS];
239 struct sja1105_flow_block flow_block;
240 struct sja1105_port ports[SJA1105_MAX_NUM_PORTS];
241
242
243
244 struct mutex mgmt_lock;
245 struct devlink_region **regions;
246 struct sja1105_cbs_entry *cbs;
247 struct mii_bus *mdio_base_t1;
248 struct mii_bus *mdio_base_tx;
249 struct mii_bus *mdio_pcs;
250 struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS];
251 struct sja1105_tagger_data tagger_data;
252 struct sja1105_ptp_data ptp_data;
253 struct sja1105_tas_data tas_data;
254};
255
256#include "sja1105_dynamic_config.h"
257
258struct sja1105_spi_message {
259 u64 access;
260 u64 read_count;
261 u64 address;
262};
263
264
265enum sja1105_reset_reason {
266 SJA1105_VLAN_FILTERING = 0,
267 SJA1105_RX_HWTSTAMPING,
268 SJA1105_AGEING_TIME,
269 SJA1105_SCHEDULING,
270 SJA1105_BEST_EFFORT_POLICING,
271 SJA1105_VIRTUAL_LINKS,
272};
273
274int sja1105_static_config_reload(struct sja1105_private *priv,
275 enum sja1105_reset_reason reason);
276int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
277 struct netlink_ext_ack *extack);
278void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
279
280
281int sja1105_mdiobus_register(struct dsa_switch *ds);
282void sja1105_mdiobus_unregister(struct dsa_switch *ds);
283int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
284int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
285int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);
286int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);
287
288
289int sja1105_devlink_setup(struct dsa_switch *ds);
290void sja1105_devlink_teardown(struct dsa_switch *ds);
291int sja1105_devlink_info_get(struct dsa_switch *ds,
292 struct devlink_info_req *req,
293 struct netlink_ext_ack *extack);
294
295
296int sja1105_xfer_buf(const struct sja1105_private *priv,
297 sja1105_spi_rw_mode_t rw, u64 reg_addr,
298 u8 *buf, size_t len);
299int sja1105_xfer_u32(const struct sja1105_private *priv,
300 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
301 struct ptp_system_timestamp *ptp_sts);
302int sja1105_xfer_u64(const struct sja1105_private *priv,
303 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
304 struct ptp_system_timestamp *ptp_sts);
305int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
306 void *config_buf, int buf_len);
307int sja1105_static_config_upload(struct sja1105_private *priv);
308int sja1105_inhibit_tx(const struct sja1105_private *priv,
309 unsigned long port_bitmap, bool tx_inhibited);
310
311extern const struct sja1105_info sja1105e_info;
312extern const struct sja1105_info sja1105t_info;
313extern const struct sja1105_info sja1105p_info;
314extern const struct sja1105_info sja1105q_info;
315extern const struct sja1105_info sja1105r_info;
316extern const struct sja1105_info sja1105s_info;
317extern const struct sja1105_info sja1110a_info;
318extern const struct sja1105_info sja1110b_info;
319extern const struct sja1105_info sja1110c_info;
320extern const struct sja1105_info sja1110d_info;
321
322
323
324typedef enum {
325 XMII_MAC = 0,
326 XMII_PHY = 1,
327} sja1105_mii_role_t;
328
329typedef enum {
330 XMII_MODE_MII = 0,
331 XMII_MODE_RMII = 1,
332 XMII_MODE_RGMII = 2,
333 XMII_MODE_SGMII = 3,
334} sja1105_phy_interface_t;
335
336int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
337int sja1110_setup_rgmii_delay(const void *ctx, int port);
338int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
339int sja1105_clocking_setup(struct sja1105_private *priv);
340int sja1110_disable_microcontroller(struct sja1105_private *priv);
341
342
343void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
344void sja1105_get_strings(struct dsa_switch *ds, int port,
345 u32 stringset, u8 *data);
346int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
347
348
349int sja1105_dynamic_config_read(struct sja1105_private *priv,
350 enum sja1105_blk_idx blk_idx,
351 int index, void *entry);
352int sja1105_dynamic_config_write(struct sja1105_private *priv,
353 enum sja1105_blk_idx blk_idx,
354 int index, void *entry, bool keep);
355
356enum sja1105_iotag {
357 SJA1105_C_TAG = 0,
358 SJA1105_S_TAG = 1,
359};
360
361enum sja1110_vlan_type {
362 SJA1110_VLAN_INVALID = 0,
363 SJA1110_VLAN_C_TAG = 1,
364 SJA1110_VLAN_S_TAG = 2,
365 SJA1110_VLAN_D_TAG = 3,
366};
367
368enum sja1110_shaper_type {
369 SJA1110_LEAKY_BUCKET_SHAPER = 0,
370 SJA1110_CBS_SHAPER = 1,
371};
372
373u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
374int sja1105et_fdb_add(struct dsa_switch *ds, int port,
375 const unsigned char *addr, u16 vid);
376int sja1105et_fdb_del(struct dsa_switch *ds, int port,
377 const unsigned char *addr, u16 vid);
378int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
379 const unsigned char *addr, u16 vid);
380int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
381 const unsigned char *addr, u16 vid);
382
383
384int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
385 struct flow_cls_offload *cls, bool ingress);
386int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
387 struct flow_cls_offload *cls, bool ingress);
388int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
389 struct flow_cls_offload *cls, bool ingress);
390void sja1105_flower_setup(struct dsa_switch *ds);
391void sja1105_flower_teardown(struct dsa_switch *ds);
392struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
393 unsigned long cookie);
394
395#endif
396
