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9#ifndef _8390_h
10#define _8390_h
11
12#include <linux/if_ether.h>
13#include <linux/ioport.h>
14#include <linux/irqreturn.h>
15#include <linux/skbuff.h>
16
17#define TX_PAGES 12
18
19
20struct e8390_pkt_hdr {
21 unsigned char status;
22 unsigned char next;
23 unsigned short count;
24};
25
26#ifdef CONFIG_NET_POLL_CONTROLLER
27void ei_poll(struct net_device *dev);
28void eip_poll(struct net_device *dev);
29#endif
30
31
32
33void NS8390_init(struct net_device *dev, int startp);
34int ei_open(struct net_device *dev);
35int ei_close(struct net_device *dev);
36irqreturn_t ei_interrupt(int irq, void *dev_id);
37void ei_tx_timeout(struct net_device *dev, unsigned int txqueue);
38netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev);
39void ei_set_multicast_list(struct net_device *dev);
40struct net_device_stats *ei_get_stats(struct net_device *dev);
41
42extern const struct net_device_ops ei_netdev_ops;
43
44struct net_device *__alloc_ei_netdev(int size);
45static inline struct net_device *alloc_ei_netdev(void)
46{
47 return __alloc_ei_netdev(0);
48}
49
50
51void NS8390p_init(struct net_device *dev, int startp);
52int eip_open(struct net_device *dev);
53int eip_close(struct net_device *dev);
54irqreturn_t eip_interrupt(int irq, void *dev_id);
55void eip_tx_timeout(struct net_device *dev, unsigned int txqueue);
56netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev);
57void eip_set_multicast_list(struct net_device *dev);
58struct net_device_stats *eip_get_stats(struct net_device *dev);
59
60extern const struct net_device_ops eip_netdev_ops;
61
62struct net_device *__alloc_eip_netdev(int size);
63static inline struct net_device *alloc_eip_netdev(void)
64{
65 return __alloc_eip_netdev(0);
66}
67
68
69struct ei_device {
70 const char *name;
71 void (*reset_8390)(struct net_device *dev);
72 void (*get_8390_hdr)(struct net_device *dev,
73 struct e8390_pkt_hdr *hdr, int ring_page);
74 void (*block_output)(struct net_device *dev, int count,
75 const unsigned char *buf, int start_page);
76 void (*block_input)(struct net_device *dev, int count,
77 struct sk_buff *skb, int ring_offset);
78 unsigned long rmem_start;
79 unsigned long rmem_end;
80 void __iomem *mem;
81 unsigned char mcfilter[8];
82 unsigned open:1;
83 unsigned word16:1;
84
85
86 unsigned bigendian:1;
87
88
89 unsigned txing:1;
90 unsigned irqlock:1;
91 unsigned dmaing:1;
92 unsigned char tx_start_page, rx_start_page, stop_page;
93 unsigned char current_page;
94 unsigned char interface_num;
95 unsigned char txqueue;
96 short tx1, tx2;
97 short lasttx;
98 unsigned char reg0;
99 unsigned char reg5;
100 unsigned char saved_irq;
101 u32 *reg_offset;
102 spinlock_t page_lock;
103 unsigned long priv;
104 u32 msg_enable;
105#ifdef AX88796_PLATFORM
106 unsigned char rxcr_base;
107#endif
108};
109
110
111#define MAX_SERVICE 12
112
113
114#define TX_TIMEOUT (20*HZ/100)
115
116#define ei_status (*(struct ei_device *)netdev_priv(dev))
117
118
119#define E8390_TX_IRQ_MASK 0xa
120#define E8390_RX_IRQ_MASK 0x5
121
122#ifdef AX88796_PLATFORM
123#define E8390_RXCONFIG (ei_status.rxcr_base | 0x04)
124#define E8390_RXOFF (ei_status.rxcr_base | 0x20)
125#else
126
127#define E8390_RXCONFIG 0x4
128
129#define E8390_RXOFF 0x20
130#endif
131
132
133#define E8390_TXCONFIG 0x00
134
135#define E8390_TXOFF 0x02
136
137
138
139#define E8390_STOP 0x01
140#define E8390_START 0x02
141#define E8390_TRANS 0x04
142#define E8390_RREAD 0x08
143#define E8390_RWRITE 0x10
144#define E8390_NODMA 0x20
145#define E8390_PAGE0 0x00
146#define E8390_PAGE1 0x40
147#define E8390_PAGE2 0x80
148
149
150
151
152
153
154#ifndef ei_inb
155#define ei_inb(_p) inb(_p)
156#define ei_outb(_v, _p) outb(_v, _p)
157#define ei_inb_p(_p) inb(_p)
158#define ei_outb_p(_v, _p) outb(_v, _p)
159#endif
160
161#ifndef EI_SHIFT
162#define EI_SHIFT(x) (x)
163#endif
164
165#define E8390_CMD EI_SHIFT(0x00)
166
167#define EN0_CLDALO EI_SHIFT(0x01)
168#define EN0_STARTPG EI_SHIFT(0x01)
169#define EN0_CLDAHI EI_SHIFT(0x02)
170#define EN0_STOPPG EI_SHIFT(0x02)
171#define EN0_BOUNDARY EI_SHIFT(0x03)
172#define EN0_TSR EI_SHIFT(0x04)
173#define EN0_TPSR EI_SHIFT(0x04)
174#define EN0_NCR EI_SHIFT(0x05)
175#define EN0_TCNTLO EI_SHIFT(0x05)
176#define EN0_FIFO EI_SHIFT(0x06)
177#define EN0_TCNTHI EI_SHIFT(0x06)
178#define EN0_ISR EI_SHIFT(0x07)
179#define EN0_CRDALO EI_SHIFT(0x08)
180#define EN0_RSARLO EI_SHIFT(0x08)
181#define EN0_CRDAHI EI_SHIFT(0x09)
182#define EN0_RSARHI EI_SHIFT(0x09)
183#define EN0_RCNTLO EI_SHIFT(0x0a)
184#define EN0_RCNTHI EI_SHIFT(0x0b)
185#define EN0_RSR EI_SHIFT(0x0c)
186#define EN0_RXCR EI_SHIFT(0x0c)
187#define EN0_TXCR EI_SHIFT(0x0d)
188#define EN0_COUNTER0 EI_SHIFT(0x0d)
189#define EN0_DCFG EI_SHIFT(0x0e)
190#define EN0_COUNTER1 EI_SHIFT(0x0e)
191#define EN0_IMR EI_SHIFT(0x0f)
192#define EN0_COUNTER2 EI_SHIFT(0x0f)
193
194
195#define ENISR_RX 0x01
196#define ENISR_TX 0x02
197#define ENISR_RX_ERR 0x04
198#define ENISR_TX_ERR 0x08
199#define ENISR_OVER 0x10
200#define ENISR_COUNTERS 0x20
201#define ENISR_RDC 0x40
202#define ENISR_RESET 0x80
203#define ENISR_ALL 0x3f
204
205
206#define ENDCFG_WTS 0x01
207#define ENDCFG_BOS 0x02
208
209
210#define EN1_PHYS EI_SHIFT(0x01)
211#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1)
212#define EN1_CURPAG EI_SHIFT(0x07)
213#define EN1_MULT EI_SHIFT(0x08)
214#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i)
215
216
217#define ENRSR_RXOK 0x01
218#define ENRSR_CRC 0x02
219#define ENRSR_FAE 0x04
220#define ENRSR_FO 0x08
221#define ENRSR_MPA 0x10
222#define ENRSR_PHY 0x20
223#define ENRSR_DIS 0x40
224#define ENRSR_DEF 0x80
225
226
227#define ENTSR_PTX 0x01
228#define ENTSR_ND 0x02
229#define ENTSR_COL 0x04
230#define ENTSR_ABT 0x08
231#define ENTSR_CRS 0x10
232#define ENTSR_FU 0x20
233#define ENTSR_CDH 0x40
234#define ENTSR_OWC 0x80
235
236#endif
237