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12#ifndef AQ_HW_H
13#define AQ_HW_H
14
15#include "aq_common.h"
16#include "aq_rss.h"
17#include "hw_atl/hw_atl_utils.h"
18
19#define AQ_HW_MAC_COUNTER_HZ 312500000ll
20#define AQ_HW_PHY_COUNTER_HZ 160000000ll
21
22enum aq_tc_mode {
23 AQ_TC_MODE_INVALID = -1,
24 AQ_TC_MODE_8TCS,
25 AQ_TC_MODE_4TCS,
26};
27
28#define AQ_RX_FIRST_LOC_FVLANID 0U
29#define AQ_RX_LAST_LOC_FVLANID 15U
30#define AQ_RX_FIRST_LOC_FETHERT 16U
31#define AQ_RX_LAST_LOC_FETHERT 31U
32#define AQ_RX_FIRST_LOC_FL3L4 32U
33#define AQ_RX_LAST_LOC_FL3L4 39U
34#define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4
35#define AQ_VLAN_MAX_FILTERS \
36 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U)
37#define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU
38
39#define AQ_FRAC_PER_NS 0x100000000LL
40
41
42#define AQ_MBPS_DIVISOR 125000
43
44
45struct aq_hw_caps_s {
46 u64 hw_features;
47 u64 link_speed_msk;
48 unsigned int hw_priv_flags;
49 u32 media_type;
50 u32 rxds_max;
51 u32 txds_max;
52 u32 rxds_min;
53 u32 txds_min;
54 u32 txhwb_alignment;
55 u32 irq_mask;
56 u32 vecs;
57 u32 mtu;
58 u32 mac_regs_count;
59 u32 hw_alive_check_addr;
60 u8 msix_irqs;
61 u8 tcs_max;
62 u8 rxd_alignment;
63 u8 rxd_size;
64 u8 txd_alignment;
65 u8 txd_size;
66 u8 tx_rings;
67 u8 rx_rings;
68 bool flow_control;
69 bool is_64_dma;
70 bool op64bit;
71 u32 quirks;
72 u32 priv_data_len;
73};
74
75struct aq_hw_link_status_s {
76 unsigned int mbps;
77 bool full_duplex;
78 u32 lp_link_speed_msk;
79 u32 lp_flow_control;
80};
81
82struct aq_stats_s {
83 u64 uprc;
84 u64 mprc;
85 u64 bprc;
86 u64 erpt;
87 u64 uptc;
88 u64 mptc;
89 u64 bptc;
90 u64 erpr;
91 u64 mbtc;
92 u64 bbtc;
93 u64 mbrc;
94 u64 bbrc;
95 u64 ubrc;
96 u64 ubtc;
97 u64 dpc;
98 u64 dma_pkt_rc;
99 u64 dma_pkt_tc;
100 u64 dma_oct_rc;
101 u64 dma_oct_tc;
102};
103
104#define AQ_HW_IRQ_INVALID 0U
105#define AQ_HW_IRQ_LEGACY 1U
106#define AQ_HW_IRQ_MSI 2U
107#define AQ_HW_IRQ_MSIX 3U
108
109#define AQ_HW_SERVICE_IRQS 1U
110
111#define AQ_HW_POWER_STATE_D0 0U
112#define AQ_HW_POWER_STATE_D3 3U
113
114#define AQ_HW_FLAG_STARTED 0x00000004U
115#define AQ_HW_FLAG_STOPPING 0x00000008U
116#define AQ_HW_FLAG_RESETTING 0x00000010U
117#define AQ_HW_FLAG_CLOSING 0x00000020U
118#define AQ_HW_PTP_AVAILABLE 0x01000000U
119#define AQ_HW_LINK_DOWN 0x04000000U
120#define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U
121#define AQ_HW_FLAG_ERR_HW 0x80000000U
122
123#define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG)
124
125#define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \
126 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \
127 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW)
128
129#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
130 AQ_NIC_LINK_DOWN)
131
132#define AQ_HW_MEDIA_TYPE_TP 1U
133#define AQ_HW_MEDIA_TYPE_FIBRE 2U
134
135#define AQ_HW_TXD_MULTIPLE 8U
136#define AQ_HW_RXD_MULTIPLE 8U
137
138#define AQ_HW_QUEUES_MAX 32U
139#define AQ_HW_MULTICAST_ADDRESS_MAX 32U
140
141#define AQ_HW_PTP_TC 2U
142
143#define AQ_HW_LED_BLINK 0x2U
144#define AQ_HW_LED_DEFAULT 0x0U
145
146#define AQ_HW_MEDIA_DETECT_CNT 6000
147
148enum aq_priv_flags {
149 AQ_HW_LOOPBACK_DMA_SYS,
150 AQ_HW_LOOPBACK_PKT_SYS,
151 AQ_HW_LOOPBACK_DMA_NET,
152 AQ_HW_LOOPBACK_PHYINT_SYS,
153 AQ_HW_LOOPBACK_PHYEXT_SYS,
154};
155
156#define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\
157 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\
158 BIT(AQ_HW_LOOPBACK_DMA_NET) |\
159 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\
160 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS))
161
162#define ATL_HW_CHIP_MIPS 0x00000001U
163#define ATL_HW_CHIP_TPO2 0x00000002U
164#define ATL_HW_CHIP_RPF2 0x00000004U
165#define ATL_HW_CHIP_MPI_AQ 0x00000010U
166#define ATL_HW_CHIP_ATLANTIC 0x00800000U
167#define ATL_HW_CHIP_REVISION_A0 0x01000000U
168#define ATL_HW_CHIP_REVISION_B0 0x02000000U
169#define ATL_HW_CHIP_REVISION_B1 0x04000000U
170#define ATL_HW_CHIP_ANTIGUA 0x08000000U
171
172#define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \
173 (_HW_)->chip_features))
174
175struct aq_hw_s {
176 atomic_t flags;
177 u8 rbl_enabled:1;
178 struct aq_nic_cfg_s *aq_nic_cfg;
179 const struct aq_fw_ops *aq_fw_ops;
180 void __iomem *mmio;
181 struct aq_hw_link_status_s aq_link_status;
182 struct hw_atl_utils_mbox mbox;
183 struct hw_atl_stats_s last_stats;
184 struct aq_stats_s curr_stats;
185 u64 speed;
186 u32 itr_tx;
187 u32 itr_rx;
188 unsigned int chip_features;
189 u32 fw_ver_actual;
190 atomic_t dpc;
191 u32 mbox_addr;
192 u32 rpc_addr;
193 u32 settings_addr;
194 u32 rpc_tid;
195 struct hw_atl_utils_fw_rpc rpc;
196 s64 ptp_clk_offset;
197 u16 phy_id;
198 void *priv;
199};
200
201struct aq_ring_s;
202struct aq_ring_param_s;
203struct sk_buff;
204struct aq_rx_filter_l3l4;
205
206struct aq_hw_ops {
207
208 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
209 unsigned int frags);
210
211 int (*hw_ring_rx_receive)(struct aq_hw_s *self,
212 struct aq_ring_s *aq_ring);
213
214 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
215 unsigned int sw_tail_old);
216
217 int (*hw_ring_tx_head_update)(struct aq_hw_s *self,
218 struct aq_ring_s *aq_ring);
219
220 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr);
221
222 int (*hw_soft_reset)(struct aq_hw_s *self);
223
224 int (*hw_prepare)(struct aq_hw_s *self,
225 const struct aq_fw_ops **fw_ops);
226
227 int (*hw_reset)(struct aq_hw_s *self);
228
229 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr);
230
231 int (*hw_start)(struct aq_hw_s *self);
232
233 int (*hw_stop)(struct aq_hw_s *self);
234
235 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
236 struct aq_ring_param_s *aq_ring_param);
237
238 int (*hw_ring_tx_start)(struct aq_hw_s *self,
239 struct aq_ring_s *aq_ring);
240
241 int (*hw_ring_tx_stop)(struct aq_hw_s *self,
242 struct aq_ring_s *aq_ring);
243
244 int (*hw_ring_rx_init)(struct aq_hw_s *self,
245 struct aq_ring_s *aq_ring,
246 struct aq_ring_param_s *aq_ring_param);
247
248 int (*hw_ring_rx_start)(struct aq_hw_s *self,
249 struct aq_ring_s *aq_ring);
250
251 int (*hw_ring_rx_stop)(struct aq_hw_s *self,
252 struct aq_ring_s *aq_ring);
253
254 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask);
255
256 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask);
257
258 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask);
259
260 int (*hw_packet_filter_set)(struct aq_hw_s *self,
261 unsigned int packet_filter);
262
263 int (*hw_filter_l3l4_set)(struct aq_hw_s *self,
264 struct aq_rx_filter_l3l4 *data);
265
266 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self,
267 struct aq_rx_filter_l3l4 *data);
268
269 int (*hw_filter_l2_set)(struct aq_hw_s *self,
270 struct aq_rx_filter_l2 *data);
271
272 int (*hw_filter_l2_clear)(struct aq_hw_s *self,
273 struct aq_rx_filter_l2 *data);
274
275 int (*hw_filter_vlan_set)(struct aq_hw_s *self,
276 struct aq_rx_filter_vlan *aq_vlans);
277
278 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable);
279
280 int (*hw_multicast_list_set)(struct aq_hw_s *self,
281 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX]
282 [ETH_ALEN],
283 u32 count);
284
285 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self);
286
287 int (*hw_rss_set)(struct aq_hw_s *self,
288 struct aq_rss_parameters *rss_params);
289
290 int (*hw_rss_hash_set)(struct aq_hw_s *self,
291 struct aq_rss_parameters *rss_params);
292
293 int (*hw_tc_rate_limit_set)(struct aq_hw_s *self);
294
295 int (*hw_get_regs)(struct aq_hw_s *self,
296 const struct aq_hw_caps_s *aq_hw_caps,
297 u32 *regs_buff);
298
299 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self);
300
301 u32 (*hw_get_fw_version)(struct aq_hw_s *self);
302
303 int (*hw_set_offload)(struct aq_hw_s *self,
304 struct aq_nic_cfg_s *aq_nic_cfg);
305
306 int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self,
307 struct aq_ring_s *aq_ring);
308
309 int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self,
310 struct aq_ring_s *ring);
311
312 void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp);
313
314 int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta);
315
316 int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta);
317
318 int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts);
319
320 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time);
321
322 int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start,
323 u32 period);
324
325 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index,
326 u32 enable);
327
328 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts);
329
330 u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len,
331 u64 *timestamp);
332
333 int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len,
334 u64 *timestamp);
335
336 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc);
337
338 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable);
339
340 int (*hw_get_mac_temp)(struct aq_hw_s *self, u32 *temp);
341};
342
343struct aq_fw_ops {
344 int (*init)(struct aq_hw_s *self);
345
346 int (*deinit)(struct aq_hw_s *self);
347
348 int (*reset)(struct aq_hw_s *self);
349
350 int (*renegotiate)(struct aq_hw_s *self);
351
352 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac);
353
354 int (*set_link_speed)(struct aq_hw_s *self, u32 speed);
355
356 int (*set_state)(struct aq_hw_s *self,
357 enum hal_atl_utils_fw_state_e state);
358
359 int (*update_link_status)(struct aq_hw_s *self);
360
361 int (*update_stats)(struct aq_hw_s *self);
362
363 int (*get_mac_temp)(struct aq_hw_s *self, int *temp);
364
365 int (*get_phy_temp)(struct aq_hw_s *self, int *temp);
366
367 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode);
368
369 int (*set_flow_control)(struct aq_hw_s *self);
370
371 int (*led_control)(struct aq_hw_s *self, u32 mode);
372
373 int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable);
374
375 int (*set_power)(struct aq_hw_s *self, unsigned int power_state,
376 u8 *mac);
377
378 int (*send_fw_request)(struct aq_hw_s *self,
379 const struct hw_fw_request_iface *fw_req,
380 size_t size);
381
382 void (*enable_ptp)(struct aq_hw_s *self, int enable);
383
384 void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj);
385
386 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed);
387
388 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate,
389 u32 *supported_rates);
390
391 int (*set_downshift)(struct aq_hw_s *self, u32 counter);
392
393 int (*set_media_detect)(struct aq_hw_s *self, bool enable);
394
395 u32 (*get_link_capabilities)(struct aq_hw_s *self);
396
397 int (*send_macsec_req)(struct aq_hw_s *self,
398 struct macsec_msg_fw_request *msg,
399 struct macsec_msg_fw_response *resp);
400};
401
402#endif
403
