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6#ifndef MSS_INGRESS_REGS_HEADER
7#define MSS_INGRESS_REGS_HEADER
8
9#define MSS_INGRESS_CTL_REGISTER_ADDR 0x0000800E
10#define MSS_INGRESS_LUT_ADDR_CTL_REGISTER_ADDR 0x00008080
11#define MSS_INGRESS_LUT_CTL_REGISTER_ADDR 0x00008081
12#define MSS_INGRESS_LUT_DATA_CTL_REGISTER_ADDR 0x000080A0
13
14struct mss_ingress_ctl_register {
15 union {
16 struct {
17 unsigned int soft_reset : 1;
18 unsigned int operation_point_to_point : 1;
19 unsigned int create_sci : 1;
20
21 unsigned int mask_short_length_error : 1;
22 unsigned int drop_kay_packet : 1;
23 unsigned int drop_igprc_miss : 1;
24
25 unsigned int check_icv : 1;
26 unsigned int clear_global_time : 1;
27 unsigned int clear_count : 1;
28 unsigned int high_prio : 1;
29 unsigned int remove_sectag : 1;
30 unsigned int global_validate_frames : 2;
31 unsigned int icv_lsb_8bytes_enabled : 1;
32 unsigned int reserved0 : 2;
33 } bits_0;
34 unsigned short word_0;
35 };
36 union {
37 struct {
38 unsigned int reserved0 : 16;
39 } bits_1;
40 unsigned short word_1;
41 };
42};
43
44struct mss_ingress_lut_addr_ctl_register {
45 union {
46 struct {
47 unsigned int lut_addr : 9;
48 unsigned int reserved0 : 3;
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60 unsigned int lut_select : 4;
61 } bits_0;
62 unsigned short word_0;
63 };
64};
65
66struct mss_ingress_lut_ctl_register {
67 union {
68 struct {
69 unsigned int reserved0 : 14;
70 unsigned int lut_read : 1;
71 unsigned int lut_write : 1;
72 } bits_0;
73 unsigned short word_0;
74 };
75};
76
77#endif
78