LXR linux/drivers/net/ethernet/atheros/atl1e/atl1e.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
   4 * Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
   5 *
   6 * Derived from Intel e1000 driver
   7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
   8 */
   9
  10#ifndef _ATL1E_H_
  11#define _ATL1E_H_
  12
  13#include <linux/interrupt.h>
  14#include <linux/types.h>
  15#include <linux/errno.h>
  16#include <linux/module.h>
  17#include <linux/pci.h>
  18#include <linux/netdevice.h>
  19#include <linux/etherdevice.h>
  20#include <linux/skbuff.h>
  21#include <linux/ioport.h>
  22#include <linux/slab.h>
  23#include <linux/list.h>
  24#include <linux/delay.h>
  25#include <linux/sched.h>
  26#include <linux/in.h>
  27#include <linux/ip.h>
  28#include <linux/ipv6.h>
  29#include <linux/udp.h>
  30#include <linux/mii.h>
  31#include <linux/io.h>
  32#include <linux/vmalloc.h>
  33#include <linux/pagemap.h>
  34#include <linux/tcp.h>
  35#include <linux/ethtool.h>
  36#include <linux/if_vlan.h>
  37#include <linux/workqueue.h>
  38#include <net/checksum.h>
  39#include <net/ip6_checksum.h>
  40
  41#include "atl1e_hw.h"
  42
  43#define PCI_REG_COMMAND  0x04    /* PCI Command Register */
  44#define CMD_IO_SPACE     0x0001
  45#define CMD_MEMORY_SPACE 0x0002
  46#define CMD_BUS_MASTER   0x0004
  47
  48#define BAR_0   0
  49#define BAR_1   1
  50#define BAR_5   5
  51
  52/* Wake Up Filter Control */
  53#define AT_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  54#define AT_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  55#define AT_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  56#define AT_WUFC_MC   0x00000008 /* Multicast Wakeup Enable */
  57#define AT_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  58
  59#define SPEED_0            0xffff
  60#define HALF_DUPLEX        1
  61#define FULL_DUPLEX        2
  62
  63/* Error Codes */
  64#define AT_ERR_EEPROM      1
  65#define AT_ERR_PHY         2
  66#define AT_ERR_CONFIG      3
  67#define AT_ERR_PARAM       4
  68#define AT_ERR_MAC_TYPE    5
  69#define AT_ERR_PHY_TYPE    6
  70#define AT_ERR_PHY_SPEED   7
  71#define AT_ERR_PHY_RES     8
  72#define AT_ERR_TIMEOUT     9
  73
  74#define MAX_JUMBO_FRAME_SIZE 0x2000
  75
  76#define AT_VLAN_TAG_TO_TPD_TAG(_vlan, _tpd)    \
  77        _tpd = (((_vlan) << (4)) | (((_vlan) >> 13) & 7) |\
  78                 (((_vlan) >> 9) & 8))
  79
  80#define AT_TPD_TAG_TO_VLAN_TAG(_tpd, _vlan)    \
  81        _vlan = (((_tpd) >> 8) | (((_tpd) & 0x77) << 9) |\
  82                   (((_tdp) & 0x88) << 5))
  83
  84#define AT_MAX_RECEIVE_QUEUE    4
  85#define AT_PAGE_NUM_PER_QUEUE   2
  86
  87#define AT_DMA_HI_ADDR_MASK     0xffffffff00000000ULL
  88#define AT_DMA_LO_ADDR_MASK     0x00000000ffffffffULL
  89
  90#define AT_TX_WATCHDOG  (5 * HZ)
  91#define AT_MAX_INT_WORK         10
  92#define AT_TWSI_EEPROM_TIMEOUT  100
  93#define AT_HW_MAX_IDLE_DELAY    10
  94#define AT_SUSPEND_LINK_TIMEOUT 28
  95
  96#define AT_REGS_LEN     75
  97#define AT_EEPROM_LEN   512
  98#define AT_ADV_MASK     (ADVERTISE_10_HALF  |\
  99                         ADVERTISE_10_FULL  |\
 100                         ADVERTISE_100_HALF |\
 101                         ADVERTISE_100_FULL |\
 102                         ADVERTISE_1000_FULL)
 103
 104/* tpd word 2 */
 105#define TPD_BUFLEN_MASK         0x3FFF
 106#define TPD_BUFLEN_SHIFT        0
 107#define TPD_DMAINT_MASK         0x0001
 108#define TPD_DMAINT_SHIFT        14
 109#define TPD_PKTNT_MASK          0x0001
 110#define TPD_PKTINT_SHIFT        15
 111#define TPD_VLANTAG_MASK        0xFFFF
 112#define TPD_VLAN_SHIFT          16
 113
 114/* tpd word 3 bits 0:4 */
 115#define TPD_EOP_MASK            0x0001
 116#define TPD_EOP_SHIFT           0
 117#define TPD_IP_VERSION_MASK     0x0001
 118#define TPD_IP_VERSION_SHIFT    1       /* 0 : IPV4, 1 : IPV6 */
 119#define TPD_INS_VL_TAG_MASK     0x0001
 120#define TPD_INS_VL_TAG_SHIFT    2
 121#define TPD_CC_SEGMENT_EN_MASK  0x0001
 122#define TPD_CC_SEGMENT_EN_SHIFT 3
 123#define TPD_SEGMENT_EN_MASK     0x0001
 124#define TPD_SEGMENT_EN_SHIFT    4
 125
 126/* tdp word 3 bits 5:7 if ip version is 0 */
 127#define TPD_IP_CSUM_MASK        0x0001
 128#define TPD_IP_CSUM_SHIFT       5
 129#define TPD_TCP_CSUM_MASK       0x0001
 130#define TPD_TCP_CSUM_SHIFT      6
 131#define TPD_UDP_CSUM_MASK       0x0001
 132#define TPD_UDP_CSUM_SHIFT      7
 133
 134/* tdp word 3 bits 5:7 if ip version is 1 */
 135#define TPD_V6_IPHLLO_MASK      0x0007
 136#define TPD_V6_IPHLLO_SHIFT     7
 137
 138/* tpd word 3 bits 8:9 bit */
 139#define TPD_VL_TAGGED_MASK      0x0001
 140#define TPD_VL_TAGGED_SHIFT     8
 141#define TPD_ETHTYPE_MASK        0x0001
 142#define TPD_ETHTYPE_SHIFT       9
 143
 144/* tdp word 3 bits 10:13 if ip version is 0 */
 145#define TDP_V4_IPHL_MASK        0x000F
 146#define TPD_V4_IPHL_SHIFT       10
 147
 148/* tdp word 3 bits 10:13 if ip version is 1 */
 149#define TPD_V6_IPHLHI_MASK      0x000F
 150#define TPD_V6_IPHLHI_SHIFT     10
 151
 152/* tpd word 3 bit 14:31 if segment enabled */
 153#define TPD_TCPHDRLEN_MASK      0x000F
 154#define TPD_TCPHDRLEN_SHIFT     14
 155#define TPD_HDRFLAG_MASK        0x0001
 156#define TPD_HDRFLAG_SHIFT       18
 157#define TPD_MSS_MASK            0x1FFF
 158#define TPD_MSS_SHIFT           19
 159
 160/* tdp word 3 bit 16:31 if custom csum enabled */
 161#define TPD_PLOADOFFSET_MASK    0x00FF
 162#define TPD_PLOADOFFSET_SHIFT   16
 163#define TPD_CCSUMOFFSET_MASK    0x00FF
 164#define TPD_CCSUMOFFSET_SHIFT   24
 165
 166struct atl1e_tpd_desc {
 167        __le64 buffer_addr;
 168        __le32 word2;
 169        __le32 word3;
 170};
 171
 172/* how about 0x2000 */
 173#define MAX_TX_BUF_LEN      0x2000
 174#define MAX_TX_BUF_SHIFT    13
 175#define MAX_TSO_SEG_SIZE    0x3c00
 176
 177/* rrs word 1 bit 0:31 */
 178#define RRS_RX_CSUM_MASK        0xFFFF
 179#define RRS_RX_CSUM_SHIFT       0
 180#define RRS_PKT_SIZE_MASK       0x3FFF
 181#define RRS_PKT_SIZE_SHIFT      16
 182#define RRS_CPU_NUM_MASK        0x0003
 183#define RRS_CPU_NUM_SHIFT       30
 184
 185#define RRS_IS_RSS_IPV4         0x0001
 186#define RRS_IS_RSS_IPV4_TCP     0x0002
 187#define RRS_IS_RSS_IPV6         0x0004
 188#define RRS_IS_RSS_IPV6_TCP     0x0008
 189#define RRS_IS_IPV6             0x0010
 190#define RRS_IS_IP_FRAG          0x0020
 191#define RRS_IS_IP_DF            0x0040
 192#define RRS_IS_802_3            0x0080
 193#define RRS_IS_VLAN_TAG         0x0100
 194#define RRS_IS_ERR_FRAME        0x0200
 195#define RRS_IS_IPV4             0x0400
 196#define RRS_IS_UDP              0x0800
 197#define RRS_IS_TCP              0x1000
 198#define RRS_IS_BCAST            0x2000
 199#define RRS_IS_MCAST            0x4000
 200#define RRS_IS_PAUSE            0x8000
 201
 202#define RRS_ERR_BAD_CRC         0x0001
 203#define RRS_ERR_CODE            0x0002
 204#define RRS_ERR_DRIBBLE         0x0004
 205#define RRS_ERR_RUNT            0x0008
 206#define RRS_ERR_RX_OVERFLOW     0x0010
 207#define RRS_ERR_TRUNC           0x0020
 208#define RRS_ERR_IP_CSUM         0x0040
 209#define RRS_ERR_L4_CSUM         0x0080
 210#define RRS_ERR_LENGTH          0x0100
 211#define RRS_ERR_DES_ADDR        0x0200
 212
 213struct atl1e_recv_ret_status {
 214        u16 seq_num;
 215        u16 hash_lo;
 216        __le32  word1;
 217        u16 pkt_flag;
 218        u16 err_flag;
 219        u16 hash_hi;
 220        u16 vtag;
 221};
 222
 223enum atl1e_dma_req_block {
 224        atl1e_dma_req_128 = 0,
 225        atl1e_dma_req_256 = 1,
 226        atl1e_dma_req_512 = 2,
 227        atl1e_dma_req_1024 = 3,
 228        atl1e_dma_req_2048 = 4,
 229        atl1e_dma_req_4096 = 5
 230};
 231
 232enum atl1e_rrs_type {
 233        atl1e_rrs_disable = 0,
 234        atl1e_rrs_ipv4 = 1,
 235        atl1e_rrs_ipv4_tcp = 2,
 236        atl1e_rrs_ipv6 = 4,
 237        atl1e_rrs_ipv6_tcp = 8
 238};
 239
 240enum atl1e_nic_type {
 241        athr_l1e = 0,
 242        athr_l2e_revA = 1,
 243        athr_l2e_revB = 2
 244};
 245
 246struct atl1e_hw_stats {
 247        /* rx */
 248        unsigned long rx_ok;          /* The number of good packet received. */
 249        unsigned long rx_bcast;       /* The number of good broadcast packet received. */
 250        unsigned long rx_mcast;       /* The number of good multicast packet received. */
 251        unsigned long rx_pause;       /* The number of Pause packet received. */
 252        unsigned long rx_ctrl;        /* The number of Control packet received other than Pause frame. */
 253        unsigned long rx_fcs_err;     /* The number of packets with bad FCS. */
 254        unsigned long rx_len_err;     /* The number of packets with mismatch of length field and actual size. */
 255        unsigned long rx_byte_cnt;    /* The number of bytes of good packet received. FCS is NOT included. */
 256        unsigned long rx_runt;        /* The number of packets received that are less than 64 byte long and with good FCS. */
 257        unsigned long rx_frag;        /* The number of packets received that are less than 64 byte long and with bad FCS. */
 258        unsigned long rx_sz_64;       /* The number of good and bad packets received that are 64 byte long. */
 259        unsigned long rx_sz_65_127;   /* The number of good and bad packets received that are between 65 and 127-byte long. */
 260        unsigned long rx_sz_128_255;  /* The number of good and bad packets received that are between 128 and 255-byte long. */
 261        unsigned long rx_sz_256_511;  /* The number of good and bad packets received that are between 256 and 511-byte long. */
 262        unsigned long rx_sz_512_1023; /* The number of good and bad packets received that are between 512 and 1023-byte long. */
 263        unsigned long rx_sz_1024_1518;    /* The number of good and bad packets received that are between 1024 and 1518-byte long. */
 264        unsigned long rx_sz_1519_max; /* The number of good and bad packets received that are between 1519-byte and MTU. */
 265        unsigned long rx_sz_ov;       /* The number of good and bad packets received that are more than MTU size truncated by Selene. */
 266        unsigned long rx_rxf_ov;      /* The number of frame dropped due to occurrence of RX FIFO overflow. */
 267        unsigned long rx_rrd_ov;      /* The number of frame dropped due to occurrence of RRD overflow. */
 268        unsigned long rx_align_err;   /* Alignment Error */
 269        unsigned long rx_bcast_byte_cnt;  /* The byte count of broadcast packet received, excluding FCS. */
 270        unsigned long rx_mcast_byte_cnt;  /* The byte count of multicast packet received, excluding FCS. */
 271        unsigned long rx_err_addr;    /* The number of packets dropped due to address filtering. */
 272
 273        /* tx */
 274        unsigned long tx_ok;      /* The number of good packet transmitted. */
 275        unsigned long tx_bcast;       /* The number of good broadcast packet transmitted. */
 276        unsigned long tx_mcast;       /* The number of good multicast packet transmitted. */
 277        unsigned long tx_pause;       /* The number of Pause packet transmitted. */
 278        unsigned long tx_exc_defer;   /* The number of packets transmitted with excessive deferral. */
 279        unsigned long tx_ctrl;        /* The number of packets transmitted is a control frame, excluding Pause frame. */
 280        unsigned long tx_defer;       /* The number of packets transmitted that is deferred. */
 281        unsigned long tx_byte_cnt;    /* The number of bytes of data transmitted. FCS is NOT included. */
 282        unsigned long tx_sz_64;       /* The number of good and bad packets transmitted that are 64 byte long. */
 283        unsigned long tx_sz_65_127;   /* The number of good and bad packets transmitted that are between 65 and 127-byte long. */
 284        unsigned long tx_sz_128_255;  /* The number of good and bad packets transmitted that are between 128 and 255-byte long. */
 285        unsigned long tx_sz_256_511;  /* The number of good and bad packets transmitted that are between 256 and 511-byte long. */
 286        unsigned long tx_sz_512_1023; /* The number of good and bad packets transmitted that are between 512 and 1023-byte long. */
 287        unsigned long tx_sz_1024_1518;    /* The number of good and bad packets transmitted that are between 1024 and 1518-byte long. */
 288        unsigned long tx_sz_1519_max; /* The number of good and bad packets transmitted that are between 1519-byte and MTU. */
 289        unsigned long tx_1_col;       /* The number of packets subsequently transmitted successfully with a single prior collision. */
 290        unsigned long tx_2_col;       /* The number of packets subsequently transmitted successfully with multiple prior collisions. */
 291        unsigned long tx_late_col;    /* The number of packets transmitted with late collisions. */
 292        unsigned long tx_abort_col;   /* The number of transmit packets aborted due to excessive collisions. */
 293        unsigned long tx_underrun;    /* The number of transmit packets aborted due to transmit FIFO underrun, or TRD FIFO underrun */
 294        unsigned long tx_rd_eop;      /* The number of times that read beyond the EOP into the next frame area when TRD was not written timely */
 295        unsigned long tx_len_err;     /* The number of transmit packets with length field does NOT match the actual frame size. */
 296        unsigned long tx_trunc;       /* The number of transmit packets truncated due to size exceeding MTU. */
 297        unsigned long tx_bcast_byte;  /* The byte count of broadcast packet transmitted, excluding FCS. */
 298        unsigned long tx_mcast_byte;  /* The byte count of multicast packet transmitted, excluding FCS. */
 299};
 300
 301struct atl1e_hw {
 302        u8 __iomem      *hw_addr;            /* inner register address */
 303        resource_size_t mem_rang;
 304        struct atl1e_adapter *adapter;
 305        enum atl1e_nic_type  nic_type;
 306        u16 device_id;
 307        u16 vendor_id;
 308        u16 subsystem_id;
 309        u16 subsystem_vendor_id;
 310        u8  revision_id;
 311        u16 pci_cmd_word;
 312        u8 mac_addr[ETH_ALEN];
 313        u8 perm_mac_addr[ETH_ALEN];
 314        u8 preamble_len;
 315        u16 max_frame_size;
 316        u16 rx_jumbo_th;
 317        u16 tx_jumbo_th;
 318
 319        u16 media_type;
 320#define MEDIA_TYPE_AUTO_SENSOR  0
 321#define MEDIA_TYPE_100M_FULL    1
 322#define MEDIA_TYPE_100M_HALF    2
 323#define MEDIA_TYPE_10M_FULL     3
 324#define MEDIA_TYPE_10M_HALF     4
 325
 326        u16 autoneg_advertised;
 327#define ADVERTISE_10_HALF               0x0001
 328#define ADVERTISE_10_FULL               0x0002
 329#define ADVERTISE_100_HALF              0x0004
 330#define ADVERTISE_100_FULL              0x0008
 331#define ADVERTISE_1000_HALF             0x0010 /* Not used, just FYI */
 332#define ADVERTISE_1000_FULL             0x0020
 333        u16 mii_autoneg_adv_reg;
 334        u16 mii_1000t_ctrl_reg;
 335
 336        u16 imt;        /* Interrupt Moderator timer ( 2us resolution) */
 337        u16 ict;        /* Interrupt Clear timer (2us resolution) */
 338        u32 smb_timer;
 339        u16 rrd_thresh; /* Threshold of number of RRD produced to trigger
 340                          interrupt request */
 341        u16 tpd_thresh;
 342        u16 rx_count_down; /* 2us resolution */
 343        u16 tx_count_down;
 344
 345        u8 tpd_burst;   /* Number of TPD to prefetch in cache-aligned burst. */
 346        enum atl1e_rrs_type rrs_type;
 347        u32 base_cpu;
 348        u32 indirect_tab;
 349
 350        enum atl1e_dma_req_block dmar_block;
 351        enum atl1e_dma_req_block dmaw_block;
 352        u8 dmaw_dly_cnt;
 353        u8 dmar_dly_cnt;
 354
 355        bool phy_configured;
 356        bool re_autoneg;
 357        bool emi_ca;
 358};
 359
 360/*
 361 * wrapper around a pointer to a socket buffer,
 362 * so a DMA handle can be stored along with the buffer
 363 */
 364struct atl1e_tx_buffer {
 365        struct sk_buff *skb;
 366        u16 flags;
 367#define ATL1E_TX_PCIMAP_SINGLE          0x0001
 368#define ATL1E_TX_PCIMAP_PAGE            0x0002
 369#define ATL1E_TX_PCIMAP_TYPE_MASK       0x0003
 370        u16 length;
 371        dma_addr_t dma;
 372};
 373
 374#define ATL1E_SET_PCIMAP_TYPE(tx_buff, type) do {               \
 375        ((tx_buff)->flags) &= ~ATL1E_TX_PCIMAP_TYPE_MASK;       \
 376        ((tx_buff)->flags) |= (type);                           \
 377        } while (0)
 378
 379struct atl1e_rx_page {
 380        dma_addr_t      dma;    /* receive rage DMA address */
 381        u8              *addr;   /* receive rage virtual address */
 382        dma_addr_t      write_offset_dma;  /* the DMA address which contain the
 383                                              receive data offset in the page */
 384        u32             *write_offset_addr; /* the virtaul address which contain
 385                                             the receive data offset in the page */
 386        u32             read_offset;       /* the offset where we have read */
 387};
 388
 389struct atl1e_rx_page_desc {
 390        struct atl1e_rx_page   rx_page[AT_PAGE_NUM_PER_QUEUE];
 391        u8  rx_using;
 392        u16 rx_nxseq;
 393};
 394
 395/* transmit packet descriptor (tpd) ring */
 396struct atl1e_tx_ring {
 397        struct atl1e_tpd_desc *desc;  /* descriptor ring virtual address  */
 398        dma_addr_t         dma;    /* descriptor ring physical address */
 399        u16                count;  /* the count of transmit rings  */
 400        rwlock_t           tx_lock;
 401        u16                next_to_use;
 402        atomic_t           next_to_clean;
 403        struct atl1e_tx_buffer *tx_buffer;
 404        dma_addr_t         cmb_dma;
 405        u32                *cmb;
 406};
 407
 408/* receive packet descriptor ring */
 409struct atl1e_rx_ring {
 410        void            *desc;
 411        dma_addr_t      dma;
 412        int             size;
 413        u32             page_size; /* bytes length of rxf page */
 414        u32             real_page_size; /* real_page_size = page_size + jumbo + aliagn */
 415        struct atl1e_rx_page_desc       rx_page_desc[AT_MAX_RECEIVE_QUEUE];
 416};
 417
 418/* board specific private data structure */
 419struct atl1e_adapter {
 420        struct net_device   *netdev;
 421        struct pci_dev      *pdev;
 422        struct napi_struct  napi;
 423        struct mii_if_info  mii;    /* MII interface info */
 424        struct atl1e_hw        hw;
 425        struct atl1e_hw_stats  hw_stats;
 426
 427        u32 wol;
 428        u16 link_speed;
 429        u16 link_duplex;
 430
 431        spinlock_t mdio_lock;
 432        atomic_t irq_sem;
 433
 434        struct work_struct reset_task;
 435        struct work_struct link_chg_task;
 436        struct timer_list watchdog_timer;
 437        struct timer_list phy_config_timer;
 438
 439        /* All Descriptor memory */
 440        dma_addr_t      ring_dma;
 441        void            *ring_vir_addr;
 442        u32             ring_size;
 443
 444        struct atl1e_tx_ring tx_ring;
 445        struct atl1e_rx_ring rx_ring;
 446        int num_rx_queues;
 447        unsigned long flags;
 448#define __AT_TESTING        0x0001
 449#define __AT_RESETTING      0x0002
 450#define __AT_DOWN           0x0003
 451
 452        u32 bd_number;     /* board number;*/
 453        u32 pci_state[16];
 454        u32 *config_space;
 455};
 456
 457#define AT_WRITE_REG(a, reg, value) ( \
 458                writel((value), ((a)->hw_addr + reg)))
 459
 460#define AT_WRITE_FLUSH(a) (\
 461                readl((a)->hw_addr))
 462
 463#define AT_READ_REG(a, reg) ( \
 464                readl((a)->hw_addr + reg))
 465
 466#define AT_WRITE_REGB(a, reg, value) (\
 467                writeb((value), ((a)->hw_addr + reg)))
 468
 469#define AT_READ_REGB(a, reg) (\
 470                readb((a)->hw_addr + reg))
 471
 472#define AT_WRITE_REGW(a, reg, value) (\
 473                writew((value), ((a)->hw_addr + reg)))
 474
 475#define AT_READ_REGW(a, reg) (\
 476                readw((a)->hw_addr + reg))
 477
 478#define AT_WRITE_REG_ARRAY(a, reg, offset, value) ( \
 479                writel((value), (((a)->hw_addr + reg) + ((offset) << 2))))
 480
 481#define AT_READ_REG_ARRAY(a, reg, offset) ( \
 482                readl(((a)->hw_addr + reg) + ((offset) << 2)))
 483
 484extern char atl1e_driver_name[];
 485
 486void atl1e_check_options(struct atl1e_adapter *adapter);
 487int atl1e_up(struct atl1e_adapter *adapter);
 488void atl1e_down(struct atl1e_adapter *adapter);
 489void atl1e_reinit_locked(struct atl1e_adapter *adapter);
 490s32 atl1e_reset_hw(struct atl1e_hw *hw);
 491void atl1e_set_ethtool_ops(struct net_device *netdev);
 492#endif /* _ATL1_E_H_ */
 493