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20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/ethtool.h>
23#include <linux/netdevice.h>
24#include <linux/types.h>
25#include <linux/sched.h>
26#include <linux/crc32.h>
27#include "bnx2x.h"
28#include "bnx2x_cmn.h"
29#include "bnx2x_dump.h"
30#include "bnx2x_init.h"
31
32
33
34
35
36#define MAX_QUEUE_NAME_LEN 4
37static const struct {
38 long offset;
39 int size;
40 char string[ETH_GSTRING_LEN];
41} bnx2x_q_stats_arr[] = {
42 { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 8, "[%s]: rx_ucast_packets" },
45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 8, "[%s]: rx_mcast_packets" },
47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 8, "[%s]: rx_bcast_packets" },
49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
50 { Q_STATS_OFFSET32(rx_err_discard_pkt),
51 4, "[%s]: rx_phy_ip_err_discards"},
52 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 4, "[%s]: rx_skb_alloc_discard" },
54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
55 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
57{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
58 8, "[%s]: tx_ucast_packets" },
59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 8, "[%s]: tx_mcast_packets" },
61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
62 8, "[%s]: tx_bcast_packets" },
63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 8, "[%s]: tpa_aggregations" },
65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 8, "[%s]: tpa_aggregated_frames"},
67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 4, "[%s]: driver_filtered_tx_pkt" }
70};
71
72#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
73
74static const struct {
75 long offset;
76 int size;
77 bool is_port_stat;
78 char string[ETH_GSTRING_LEN];
79} bnx2x_stats_arr[] = {
80 { STATS_OFFSET32(total_bytes_received_hi),
81 8, false, "rx_bytes" },
82 { STATS_OFFSET32(error_bytes_received_hi),
83 8, false, "rx_error_bytes" },
84 { STATS_OFFSET32(total_unicast_packets_received_hi),
85 8, false, "rx_ucast_packets" },
86 { STATS_OFFSET32(total_multicast_packets_received_hi),
87 8, false, "rx_mcast_packets" },
88 { STATS_OFFSET32(total_broadcast_packets_received_hi),
89 8, false, "rx_bcast_packets" },
90 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
91 8, true, "rx_crc_errors" },
92 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
93 8, true, "rx_align_errors" },
94 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
95 8, true, "rx_undersize_packets" },
96 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
97 8, true, "rx_oversize_packets" },
98{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
99 8, true, "rx_fragments" },
100 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
101 8, true, "rx_jabbers" },
102 { STATS_OFFSET32(no_buff_discard_hi),
103 8, false, "rx_discards" },
104 { STATS_OFFSET32(mac_filter_discard),
105 4, true, "rx_filtered_packets" },
106 { STATS_OFFSET32(mf_tag_discard),
107 4, true, "rx_mf_tag_discard" },
108 { STATS_OFFSET32(pfc_frames_received_hi),
109 8, true, "pfc_frames_received" },
110 { STATS_OFFSET32(pfc_frames_sent_hi),
111 8, true, "pfc_frames_sent" },
112 { STATS_OFFSET32(brb_drop_hi),
113 8, true, "rx_brb_discard" },
114 { STATS_OFFSET32(brb_truncate_hi),
115 8, true, "rx_brb_truncate" },
116 { STATS_OFFSET32(pause_frames_received_hi),
117 8, true, "rx_pause_frames" },
118 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
119 8, true, "rx_mac_ctrl_frames" },
120 { STATS_OFFSET32(nig_timer_max),
121 4, true, "rx_constant_pause_events" },
122{ STATS_OFFSET32(rx_err_discard_pkt),
123 4, false, "rx_phy_ip_err_discards"},
124 { STATS_OFFSET32(rx_skb_alloc_failed),
125 4, false, "rx_skb_alloc_discard" },
126 { STATS_OFFSET32(hw_csum_err),
127 4, false, "rx_csum_offload_errors" },
128 { STATS_OFFSET32(driver_xoff),
129 4, false, "tx_exhaustion_events" },
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, false, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, true, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, false, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, false, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, false, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, true, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, true, "tx_carrier_errors" },
144{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, true, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, true, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, true, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, true, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, true, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, true, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, true, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, true, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, true, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, true, "tx_256_to_511_byte_packets" },
164{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, true, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, true, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, true, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
171 8, true, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, false, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, false, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
177 8, false, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, false, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, false, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, false, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi),
185 4, true, "Tx LPI entry count"},
186 { STATS_OFFSET32(ptp_skip_tx_ts),
187 4, false, "ptp_skipped_tx_tstamp" },
188};
189
190#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
191
192static int bnx2x_get_port_type(struct bnx2x *bp)
193{
194 int port_type;
195 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
196 switch (bp->link_params.phy[phy_idx].media_type) {
197 case ETH_PHY_SFPP_10G_FIBER:
198 case ETH_PHY_SFP_1G_FIBER:
199 case ETH_PHY_XFP_FIBER:
200 case ETH_PHY_KR:
201 case ETH_PHY_CX4:
202 port_type = PORT_FIBRE;
203 break;
204 case ETH_PHY_DA_TWINAX:
205 port_type = PORT_DA;
206 break;
207 case ETH_PHY_BASE_T:
208 port_type = PORT_TP;
209 break;
210 case ETH_PHY_NOT_PRESENT:
211 port_type = PORT_NONE;
212 break;
213 case ETH_PHY_UNSPECIFIED:
214 default:
215 port_type = PORT_OTHER;
216 break;
217 }
218 return port_type;
219}
220
221static int bnx2x_get_vf_link_ksettings(struct net_device *dev,
222 struct ethtool_link_ksettings *cmd)
223{
224 struct bnx2x *bp = netdev_priv(dev);
225 u32 supported, advertising;
226
227 ethtool_convert_link_mode_to_legacy_u32(&supported,
228 cmd->link_modes.supported);
229 ethtool_convert_link_mode_to_legacy_u32(&advertising,
230 cmd->link_modes.advertising);
231
232 if (bp->state == BNX2X_STATE_OPEN) {
233 if (test_bit(BNX2X_LINK_REPORT_FD,
234 &bp->vf_link_vars.link_report_flags))
235 cmd->base.duplex = DUPLEX_FULL;
236 else
237 cmd->base.duplex = DUPLEX_HALF;
238
239 cmd->base.speed = bp->vf_link_vars.line_speed;
240 } else {
241 cmd->base.duplex = DUPLEX_UNKNOWN;
242 cmd->base.speed = SPEED_UNKNOWN;
243 }
244
245 cmd->base.port = PORT_OTHER;
246 cmd->base.phy_address = 0;
247 cmd->base.autoneg = AUTONEG_DISABLE;
248
249 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
250 " supported 0x%x advertising 0x%x speed %u\n"
251 " duplex %d port %d phy_address %d\n"
252 " autoneg %d\n",
253 cmd->base.cmd, supported, advertising,
254 cmd->base.speed,
255 cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
256 cmd->base.autoneg);
257
258 return 0;
259}
260
261static int bnx2x_get_link_ksettings(struct net_device *dev,
262 struct ethtool_link_ksettings *cmd)
263{
264 struct bnx2x *bp = netdev_priv(dev);
265 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
266 u32 media_type;
267 u32 supported, advertising, lp_advertising;
268
269 ethtool_convert_link_mode_to_legacy_u32(&lp_advertising,
270 cmd->link_modes.lp_advertising);
271
272
273 supported = bp->port.supported[cfg_idx] |
274 (bp->port.supported[cfg_idx ^ 1] &
275 (SUPPORTED_TP | SUPPORTED_FIBRE));
276 advertising = bp->port.advertising[cfg_idx];
277 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
278 if (media_type == ETH_PHY_SFP_1G_FIBER) {
279 supported &= ~(SUPPORTED_10000baseT_Full);
280 advertising &= ~(ADVERTISED_10000baseT_Full);
281 }
282
283 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
284 !(bp->flags & MF_FUNC_DIS)) {
285 cmd->base.duplex = bp->link_vars.duplex;
286
287 if (IS_MF(bp) && !BP_NOMCP(bp))
288 cmd->base.speed = bnx2x_get_mf_speed(bp);
289 else
290 cmd->base.speed = bp->link_vars.line_speed;
291 } else {
292 cmd->base.duplex = DUPLEX_UNKNOWN;
293 cmd->base.speed = SPEED_UNKNOWN;
294 }
295
296 cmd->base.port = bnx2x_get_port_type(bp);
297
298 cmd->base.phy_address = bp->mdio.prtad;
299
300 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
301 cmd->base.autoneg = AUTONEG_ENABLE;
302 else
303 cmd->base.autoneg = AUTONEG_DISABLE;
304
305
306 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
307 u32 status = bp->link_vars.link_status;
308
309 lp_advertising |= ADVERTISED_Autoneg;
310 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
311 lp_advertising |= ADVERTISED_Pause;
312 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
313 lp_advertising |= ADVERTISED_Asym_Pause;
314
315 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
316 lp_advertising |= ADVERTISED_10baseT_Half;
317 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
318 lp_advertising |= ADVERTISED_10baseT_Full;
319 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
320 lp_advertising |= ADVERTISED_100baseT_Half;
321 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
322 lp_advertising |= ADVERTISED_100baseT_Full;
323 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
324 lp_advertising |= ADVERTISED_1000baseT_Half;
325 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
326 if (media_type == ETH_PHY_KR) {
327 lp_advertising |=
328 ADVERTISED_1000baseKX_Full;
329 } else {
330 lp_advertising |=
331 ADVERTISED_1000baseT_Full;
332 }
333 }
334 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
335 lp_advertising |= ADVERTISED_2500baseX_Full;
336 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
337 if (media_type == ETH_PHY_KR) {
338 lp_advertising |=
339 ADVERTISED_10000baseKR_Full;
340 } else {
341 lp_advertising |=
342 ADVERTISED_10000baseT_Full;
343 }
344 }
345 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
346 lp_advertising |= ADVERTISED_20000baseKR2_Full;
347 }
348
349 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
350 supported);
351 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
352 advertising);
353 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.lp_advertising,
354 lp_advertising);
355
356 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
357 " supported 0x%x advertising 0x%x speed %u\n"
358 " duplex %d port %d phy_address %d\n"
359 " autoneg %d\n",
360 cmd->base.cmd, supported, advertising,
361 cmd->base.speed,
362 cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
363 cmd->base.autoneg);
364
365 return 0;
366}
367
368static int bnx2x_set_link_ksettings(struct net_device *dev,
369 const struct ethtool_link_ksettings *cmd)
370{
371 struct bnx2x *bp = netdev_priv(dev);
372 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
373 u32 speed, phy_idx;
374 u32 supported;
375 u8 duplex = cmd->base.duplex;
376
377 ethtool_convert_link_mode_to_legacy_u32(&supported,
378 cmd->link_modes.supported);
379 ethtool_convert_link_mode_to_legacy_u32(&advertising,
380 cmd->link_modes.advertising);
381
382 if (IS_MF_SD(bp))
383 return 0;
384
385 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
386 " supported 0x%x advertising 0x%x speed %u\n"
387 " duplex %d port %d phy_address %d\n"
388 " autoneg %d\n",
389 cmd->base.cmd, supported, advertising,
390 cmd->base.speed,
391 cmd->base.duplex, cmd->base.port, cmd->base.phy_address,
392 cmd->base.autoneg);
393
394 speed = cmd->base.speed;
395
396
397 if (duplex == DUPLEX_UNKNOWN)
398 duplex = DUPLEX_FULL;
399
400 if (IS_MF_SI(bp)) {
401 u32 part;
402 u32 line_speed = bp->link_vars.line_speed;
403
404
405 if (!line_speed)
406 line_speed = 10000;
407
408 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
409 DP(BNX2X_MSG_ETHTOOL,
410 "To set speed BC %X or higher is required, please upgrade BC\n",
411 REQ_BC_VER_4_SET_MF_BW);
412 return -EINVAL;
413 }
414
415 part = (speed * 100) / line_speed;
416
417 if (line_speed < speed || !part) {
418 DP(BNX2X_MSG_ETHTOOL,
419 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
420 return -EINVAL;
421 }
422
423 if (bp->state != BNX2X_STATE_OPEN)
424
425 bp->pending_max = part;
426 else
427 bnx2x_update_max_mf_config(bp, part);
428
429 return 0;
430 }
431
432 cfg_idx = bnx2x_get_link_cfg_idx(bp);
433 old_multi_phy_config = bp->link_params.multi_phy_config;
434 if (cmd->base.port != bnx2x_get_port_type(bp)) {
435 switch (cmd->base.port) {
436 case PORT_TP:
437 if (!(bp->port.supported[0] & SUPPORTED_TP ||
438 bp->port.supported[1] & SUPPORTED_TP)) {
439 DP(BNX2X_MSG_ETHTOOL,
440 "Unsupported port type\n");
441 return -EINVAL;
442 }
443 bp->link_params.multi_phy_config &=
444 ~PORT_HW_CFG_PHY_SELECTION_MASK;
445 if (bp->link_params.multi_phy_config &
446 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
447 bp->link_params.multi_phy_config |=
448 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
449 else
450 bp->link_params.multi_phy_config |=
451 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
452 break;
453 case PORT_FIBRE:
454 case PORT_DA:
455 case PORT_NONE:
456 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
457 bp->port.supported[1] & SUPPORTED_FIBRE)) {
458 DP(BNX2X_MSG_ETHTOOL,
459 "Unsupported port type\n");
460 return -EINVAL;
461 }
462 bp->link_params.multi_phy_config &=
463 ~PORT_HW_CFG_PHY_SELECTION_MASK;
464 if (bp->link_params.multi_phy_config &
465 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
466 bp->link_params.multi_phy_config |=
467 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
468 else
469 bp->link_params.multi_phy_config |=
470 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
471 break;
472 default:
473 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
474 return -EINVAL;
475 }
476 }
477
478 new_multi_phy_config = bp->link_params.multi_phy_config;
479
480 cfg_idx = bnx2x_get_link_cfg_idx(bp);
481
482 bp->link_params.multi_phy_config = old_multi_phy_config;
483 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
484
485 if (cmd->base.autoneg == AUTONEG_ENABLE) {
486 u32 an_supported_speed = bp->port.supported[cfg_idx];
487 if (bp->link_params.phy[EXT_PHY1].type ==
488 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
489 an_supported_speed |= (SUPPORTED_100baseT_Half |
490 SUPPORTED_100baseT_Full);
491 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
492 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
493 return -EINVAL;
494 }
495
496
497 if (advertising & ~an_supported_speed) {
498 DP(BNX2X_MSG_ETHTOOL,
499 "Advertisement parameters are not supported\n");
500 return -EINVAL;
501 }
502
503 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
504 bp->link_params.req_duplex[cfg_idx] = duplex;
505 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
506 advertising);
507 if (advertising) {
508
509 bp->link_params.speed_cap_mask[cfg_idx] = 0;
510 if (advertising & ADVERTISED_10baseT_Half) {
511 bp->link_params.speed_cap_mask[cfg_idx] |=
512 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
513 }
514 if (advertising & ADVERTISED_10baseT_Full)
515 bp->link_params.speed_cap_mask[cfg_idx] |=
516 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
517
518 if (advertising & ADVERTISED_100baseT_Full)
519 bp->link_params.speed_cap_mask[cfg_idx] |=
520 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
521
522 if (advertising & ADVERTISED_100baseT_Half) {
523 bp->link_params.speed_cap_mask[cfg_idx] |=
524 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
525 }
526 if (advertising & ADVERTISED_1000baseT_Half) {
527 bp->link_params.speed_cap_mask[cfg_idx] |=
528 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
529 }
530 if (advertising & (ADVERTISED_1000baseT_Full |
531 ADVERTISED_1000baseKX_Full))
532 bp->link_params.speed_cap_mask[cfg_idx] |=
533 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
534
535 if (advertising & (ADVERTISED_10000baseT_Full |
536 ADVERTISED_10000baseKX4_Full |
537 ADVERTISED_10000baseKR_Full))
538 bp->link_params.speed_cap_mask[cfg_idx] |=
539 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
540
541 if (advertising & ADVERTISED_20000baseKR2_Full)
542 bp->link_params.speed_cap_mask[cfg_idx] |=
543 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
544 }
545 } else {
546
547 switch (speed) {
548 case SPEED_10:
549 if (duplex == DUPLEX_FULL) {
550 if (!(bp->port.supported[cfg_idx] &
551 SUPPORTED_10baseT_Full)) {
552 DP(BNX2X_MSG_ETHTOOL,
553 "10M full not supported\n");
554 return -EINVAL;
555 }
556
557 advertising = (ADVERTISED_10baseT_Full |
558 ADVERTISED_TP);
559 } else {
560 if (!(bp->port.supported[cfg_idx] &
561 SUPPORTED_10baseT_Half)) {
562 DP(BNX2X_MSG_ETHTOOL,
563 "10M half not supported\n");
564 return -EINVAL;
565 }
566
567 advertising = (ADVERTISED_10baseT_Half |
568 ADVERTISED_TP);
569 }
570 break;
571
572 case SPEED_100:
573 if (duplex == DUPLEX_FULL) {
574 if (!(bp->port.supported[cfg_idx] &
575 SUPPORTED_100baseT_Full)) {
576 DP(BNX2X_MSG_ETHTOOL,
577 "100M full not supported\n");
578 return -EINVAL;
579 }
580
581 advertising = (ADVERTISED_100baseT_Full |
582 ADVERTISED_TP);
583 } else {
584 if (!(bp->port.supported[cfg_idx] &
585 SUPPORTED_100baseT_Half)) {
586 DP(BNX2X_MSG_ETHTOOL,
587 "100M half not supported\n");
588 return -EINVAL;
589 }
590
591 advertising = (ADVERTISED_100baseT_Half |
592 ADVERTISED_TP);
593 }
594 break;
595
596 case SPEED_1000:
597 if (duplex != DUPLEX_FULL) {
598 DP(BNX2X_MSG_ETHTOOL,
599 "1G half not supported\n");
600 return -EINVAL;
601 }
602
603 if (bp->port.supported[cfg_idx] &
604 SUPPORTED_1000baseT_Full) {
605 advertising = (ADVERTISED_1000baseT_Full |
606 ADVERTISED_TP);
607
608 } else if (bp->port.supported[cfg_idx] &
609 SUPPORTED_1000baseKX_Full) {
610 advertising = ADVERTISED_1000baseKX_Full;
611 } else {
612 DP(BNX2X_MSG_ETHTOOL,
613 "1G full not supported\n");
614 return -EINVAL;
615 }
616
617 break;
618
619 case SPEED_2500:
620 if (duplex != DUPLEX_FULL) {
621 DP(BNX2X_MSG_ETHTOOL,
622 "2.5G half not supported\n");
623 return -EINVAL;
624 }
625
626 if (!(bp->port.supported[cfg_idx]
627 & SUPPORTED_2500baseX_Full)) {
628 DP(BNX2X_MSG_ETHTOOL,
629 "2.5G full not supported\n");
630 return -EINVAL;
631 }
632
633 advertising = (ADVERTISED_2500baseX_Full |
634 ADVERTISED_TP);
635 break;
636
637 case SPEED_10000:
638 if (duplex != DUPLEX_FULL) {
639 DP(BNX2X_MSG_ETHTOOL,
640 "10G half not supported\n");
641 return -EINVAL;
642 }
643 phy_idx = bnx2x_get_cur_phy_idx(bp);
644 if ((bp->port.supported[cfg_idx] &
645 SUPPORTED_10000baseT_Full) &&
646 (bp->link_params.phy[phy_idx].media_type !=
647 ETH_PHY_SFP_1G_FIBER)) {
648 advertising = (ADVERTISED_10000baseT_Full |
649 ADVERTISED_FIBRE);
650 } else if (bp->port.supported[cfg_idx] &
651 SUPPORTED_10000baseKR_Full) {
652 advertising = (ADVERTISED_10000baseKR_Full |
653 ADVERTISED_FIBRE);
654 } else {
655 DP(BNX2X_MSG_ETHTOOL,
656 "10G full not supported\n");
657 return -EINVAL;
658 }
659
660 break;
661
662 default:
663 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
664 return -EINVAL;
665 }
666
667 bp->link_params.req_line_speed[cfg_idx] = speed;
668 bp->link_params.req_duplex[cfg_idx] = duplex;
669 bp->port.advertising[cfg_idx] = advertising;
670 }
671
672 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
673 " req_duplex %d advertising 0x%x\n",
674 bp->link_params.req_line_speed[cfg_idx],
675 bp->link_params.req_duplex[cfg_idx],
676 bp->port.advertising[cfg_idx]);
677
678
679 bp->link_params.multi_phy_config = new_multi_phy_config;
680 if (netif_running(dev)) {
681 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
682 bnx2x_force_link_reset(bp);
683 bnx2x_link_set(bp);
684 }
685
686 return 0;
687}
688
689#define DUMP_ALL_PRESETS 0x1FFF
690#define DUMP_MAX_PRESETS 13
691
692static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
693{
694 if (CHIP_IS_E1(bp))
695 return dump_num_registers[0][preset-1];
696 else if (CHIP_IS_E1H(bp))
697 return dump_num_registers[1][preset-1];
698 else if (CHIP_IS_E2(bp))
699 return dump_num_registers[2][preset-1];
700 else if (CHIP_IS_E3A0(bp))
701 return dump_num_registers[3][preset-1];
702 else if (CHIP_IS_E3B0(bp))
703 return dump_num_registers[4][preset-1];
704 else
705 return 0;
706}
707
708static int __bnx2x_get_regs_len(struct bnx2x *bp)
709{
710 u32 preset_idx;
711 int regdump_len = 0;
712
713
714 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
715 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
716
717 return regdump_len;
718}
719
720static int bnx2x_get_regs_len(struct net_device *dev)
721{
722 struct bnx2x *bp = netdev_priv(dev);
723 int regdump_len = 0;
724
725 if (IS_VF(bp))
726 return 0;
727
728 regdump_len = __bnx2x_get_regs_len(bp);
729 regdump_len *= 4;
730 regdump_len += sizeof(struct dump_header);
731
732 return regdump_len;
733}
734
735#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
736#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
737#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
738#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
739#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
740
741#define IS_REG_IN_PRESET(presets, idx) \
742 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
743
744
745static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
746{
747 if (CHIP_IS_E2(bp))
748 return page_vals_e2;
749 else if (CHIP_IS_E3(bp))
750 return page_vals_e3;
751 else
752 return NULL;
753}
754
755static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
756{
757 if (CHIP_IS_E2(bp))
758 return PAGE_MODE_VALUES_E2;
759 else if (CHIP_IS_E3(bp))
760 return PAGE_MODE_VALUES_E3;
761 else
762 return 0;
763}
764
765static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
766{
767 if (CHIP_IS_E2(bp))
768 return page_write_regs_e2;
769 else if (CHIP_IS_E3(bp))
770 return page_write_regs_e3;
771 else
772 return NULL;
773}
774
775static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
776{
777 if (CHIP_IS_E2(bp))
778 return PAGE_WRITE_REGS_E2;
779 else if (CHIP_IS_E3(bp))
780 return PAGE_WRITE_REGS_E3;
781 else
782 return 0;
783}
784
785static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
786{
787 if (CHIP_IS_E2(bp))
788 return page_read_regs_e2;
789 else if (CHIP_IS_E3(bp))
790 return page_read_regs_e3;
791 else
792 return NULL;
793}
794
795static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
796{
797 if (CHIP_IS_E2(bp))
798 return PAGE_READ_REGS_E2;
799 else if (CHIP_IS_E3(bp))
800 return PAGE_READ_REGS_E3;
801 else
802 return 0;
803}
804
805static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
806 const struct reg_addr *reg_info)
807{
808 if (CHIP_IS_E1(bp))
809 return IS_E1_REG(reg_info->chips);
810 else if (CHIP_IS_E1H(bp))
811 return IS_E1H_REG(reg_info->chips);
812 else if (CHIP_IS_E2(bp))
813 return IS_E2_REG(reg_info->chips);
814 else if (CHIP_IS_E3A0(bp))
815 return IS_E3A0_REG(reg_info->chips);
816 else if (CHIP_IS_E3B0(bp))
817 return IS_E3B0_REG(reg_info->chips);
818 else
819 return false;
820}
821
822static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
823 const struct wreg_addr *wreg_info)
824{
825 if (CHIP_IS_E1(bp))
826 return IS_E1_REG(wreg_info->chips);
827 else if (CHIP_IS_E1H(bp))
828 return IS_E1H_REG(wreg_info->chips);
829 else if (CHIP_IS_E2(bp))
830 return IS_E2_REG(wreg_info->chips);
831 else if (CHIP_IS_E3A0(bp))
832 return IS_E3A0_REG(wreg_info->chips);
833 else if (CHIP_IS_E3B0(bp))
834 return IS_E3B0_REG(wreg_info->chips);
835 else
836 return false;
837}
838
839
840
841
842
843
844
845
846
847
848
849
850
851static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
852{
853 u32 i, j, k, n;
854
855
856 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
857
858 int num_pages = __bnx2x_get_page_reg_num(bp);
859
860 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
861
862 int write_num = __bnx2x_get_page_write_num(bp);
863
864 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
865
866 int read_num = __bnx2x_get_page_read_num(bp);
867 u32 addr, size;
868
869 for (i = 0; i < num_pages; i++) {
870 for (j = 0; j < write_num; j++) {
871 REG_WR(bp, write_addr[j], page_addr[i]);
872
873 for (k = 0; k < read_num; k++) {
874 if (IS_REG_IN_PRESET(read_addr[k].presets,
875 preset)) {
876 size = read_addr[k].size;
877 for (n = 0; n < size; n++) {
878 addr = read_addr[k].addr + n*4;
879 *p++ = REG_RD(bp, addr);
880 }
881 }
882 }
883 }
884 }
885}
886
887static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
888{
889 u32 i, j, addr;
890 const struct wreg_addr *wreg_addr_p = NULL;
891
892 if (CHIP_IS_E1(bp))
893 wreg_addr_p = &wreg_addr_e1;
894 else if (CHIP_IS_E1H(bp))
895 wreg_addr_p = &wreg_addr_e1h;
896 else if (CHIP_IS_E2(bp))
897 wreg_addr_p = &wreg_addr_e2;
898 else if (CHIP_IS_E3A0(bp))
899 wreg_addr_p = &wreg_addr_e3;
900 else if (CHIP_IS_E3B0(bp))
901 wreg_addr_p = &wreg_addr_e3b0;
902
903
904 for (i = 0; i < IDLE_REGS_COUNT; i++) {
905 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
906 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
907 for (j = 0; j < idle_reg_addrs[i].size; j++)
908 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
909 }
910 }
911
912
913 for (i = 0; i < REGS_COUNT; i++) {
914 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) &&
915 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
916 for (j = 0; j < reg_addrs[i].size; j++)
917 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
918 }
919 }
920
921
922 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
923 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
924 for (i = 0; i < wreg_addr_p->size; i++) {
925 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
926
927
928
929
930 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
931 addr = *(wreg_addr_p->read_regs);
932 *p++ = REG_RD(bp, addr + j*4);
933 }
934 }
935 }
936
937
938 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
939
940 bnx2x_read_pages_regs(bp, p, preset);
941 }
942
943 return 0;
944}
945
946static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
947{
948 u32 preset_idx;
949
950
951 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
952
953 if ((preset_idx == 2) ||
954 (preset_idx == 5) ||
955 (preset_idx == 8) ||
956 (preset_idx == 11))
957 continue;
958 __bnx2x_get_preset_regs(bp, p, preset_idx);
959 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
960 }
961}
962
963static void bnx2x_get_regs(struct net_device *dev,
964 struct ethtool_regs *regs, void *_p)
965{
966 u32 *p = _p;
967 struct bnx2x *bp = netdev_priv(dev);
968 struct dump_header dump_hdr = {0};
969
970 regs->version = 2;
971 memset(p, 0, regs->len);
972
973 if (!netif_running(bp->dev))
974 return;
975
976
977
978
979
980
981 bnx2x_disable_blocks_parity(bp);
982
983 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
984 dump_hdr.preset = DUMP_ALL_PRESETS;
985 dump_hdr.version = BNX2X_DUMP_VERSION;
986
987
988 if (CHIP_IS_E1(bp)) {
989 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
990 } else if (CHIP_IS_E1H(bp)) {
991 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
992 } else if (CHIP_IS_E2(bp)) {
993 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
994 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
995 } else if (CHIP_IS_E3A0(bp)) {
996 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
997 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
998 } else if (CHIP_IS_E3B0(bp)) {
999 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1000 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1001 }
1002
1003 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1004 p += dump_hdr.header_size + 1;
1005
1006
1007
1008
1009 BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
1010
1011
1012 __bnx2x_get_regs(bp, p);
1013
1014
1015 bnx2x_clear_blocks_parity(bp);
1016 bnx2x_enable_blocks_parity(bp);
1017}
1018
1019static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
1020{
1021 struct bnx2x *bp = netdev_priv(dev);
1022 int regdump_len = 0;
1023
1024 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1025 regdump_len *= 4;
1026 regdump_len += sizeof(struct dump_header);
1027
1028 return regdump_len;
1029}
1030
1031static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1032{
1033 struct bnx2x *bp = netdev_priv(dev);
1034
1035
1036 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1037 return -EINVAL;
1038
1039 bp->dump_preset_idx = val->flag;
1040 return 0;
1041}
1042
1043static int bnx2x_get_dump_flag(struct net_device *dev,
1044 struct ethtool_dump *dump)
1045{
1046 struct bnx2x *bp = netdev_priv(dev);
1047
1048 dump->version = BNX2X_DUMP_VERSION;
1049 dump->flag = bp->dump_preset_idx;
1050
1051 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1052 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1053 bp->dump_preset_idx, dump->len);
1054 return 0;
1055}
1056
1057static int bnx2x_get_dump_data(struct net_device *dev,
1058 struct ethtool_dump *dump,
1059 void *buffer)
1060{
1061 u32 *p = buffer;
1062 struct bnx2x *bp = netdev_priv(dev);
1063 struct dump_header dump_hdr = {0};
1064
1065
1066
1067
1068
1069
1070 bnx2x_disable_blocks_parity(bp);
1071
1072 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1073 dump_hdr.preset = bp->dump_preset_idx;
1074 dump_hdr.version = BNX2X_DUMP_VERSION;
1075
1076 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1077
1078
1079 if (CHIP_IS_E1(bp)) {
1080 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1081 } else if (CHIP_IS_E1H(bp)) {
1082 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1083 } else if (CHIP_IS_E2(bp)) {
1084 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1085 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1086 } else if (CHIP_IS_E3A0(bp)) {
1087 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1088 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1089 } else if (CHIP_IS_E3B0(bp)) {
1090 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1091 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1092 }
1093
1094 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1095 p += dump_hdr.header_size + 1;
1096
1097
1098 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1099
1100
1101 bnx2x_clear_blocks_parity(bp);
1102 bnx2x_enable_blocks_parity(bp);
1103
1104 return 0;
1105}
1106
1107static void bnx2x_get_drvinfo(struct net_device *dev,
1108 struct ethtool_drvinfo *info)
1109{
1110 struct bnx2x *bp = netdev_priv(dev);
1111 char version[ETHTOOL_FWVERS_LEN];
1112 int ext_dev_info_offset;
1113 u32 mbi;
1114
1115 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1116
1117 if (SHMEM2_HAS(bp, extended_dev_info_shared_addr)) {
1118 ext_dev_info_offset = SHMEM2_RD(bp,
1119 extended_dev_info_shared_addr);
1120 mbi = REG_RD(bp, ext_dev_info_offset +
1121 offsetof(struct extended_dev_info_shared_cfg,
1122 mbi_version));
1123 if (mbi) {
1124 memset(version, 0, sizeof(version));
1125 snprintf(version, ETHTOOL_FWVERS_LEN, "mbi %d.%d.%d ",
1126 (mbi & 0xff000000) >> 24,
1127 (mbi & 0x00ff0000) >> 16,
1128 (mbi & 0x0000ff00) >> 8);
1129 strlcpy(info->fw_version, version,
1130 sizeof(info->fw_version));
1131 }
1132 }
1133
1134 memset(version, 0, sizeof(version));
1135 bnx2x_fill_fw_str(bp, version, ETHTOOL_FWVERS_LEN);
1136 strlcat(info->fw_version, version, sizeof(info->fw_version));
1137
1138 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1139}
1140
1141static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1142{
1143 struct bnx2x *bp = netdev_priv(dev);
1144
1145 if (bp->flags & NO_WOL_FLAG) {
1146 wol->supported = 0;
1147 wol->wolopts = 0;
1148 } else {
1149 wol->supported = WAKE_MAGIC;
1150 if (bp->wol)
1151 wol->wolopts = WAKE_MAGIC;
1152 else
1153 wol->wolopts = 0;
1154 }
1155 memset(&wol->sopass, 0, sizeof(wol->sopass));
1156}
1157
1158static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1159{
1160 struct bnx2x *bp = netdev_priv(dev);
1161
1162 if (wol->wolopts & ~WAKE_MAGIC) {
1163 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1164 return -EINVAL;
1165 }
1166
1167 if (wol->wolopts & WAKE_MAGIC) {
1168 if (bp->flags & NO_WOL_FLAG) {
1169 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1170 return -EINVAL;
1171 }
1172 bp->wol = 1;
1173 } else
1174 bp->wol = 0;
1175
1176 if (SHMEM2_HAS(bp, curr_cfg))
1177 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1178
1179 return 0;
1180}
1181
1182static u32 bnx2x_get_msglevel(struct net_device *dev)
1183{
1184 struct bnx2x *bp = netdev_priv(dev);
1185
1186 return bp->msg_enable;
1187}
1188
1189static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1190{
1191 struct bnx2x *bp = netdev_priv(dev);
1192
1193 if (capable(CAP_NET_ADMIN)) {
1194
1195 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1196 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1197 bp->msg_enable = level;
1198 }
1199}
1200
1201static int bnx2x_nway_reset(struct net_device *dev)
1202{
1203 struct bnx2x *bp = netdev_priv(dev);
1204
1205 if (!bp->port.pmf)
1206 return 0;
1207
1208 if (netif_running(dev)) {
1209 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1210 bnx2x_force_link_reset(bp);
1211 bnx2x_link_set(bp);
1212 }
1213
1214 return 0;
1215}
1216
1217static u32 bnx2x_get_link(struct net_device *dev)
1218{
1219 struct bnx2x *bp = netdev_priv(dev);
1220
1221 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1222 return 0;
1223
1224 if (IS_VF(bp))
1225 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1226 &bp->vf_link_vars.link_report_flags);
1227
1228 return bp->link_vars.link_up;
1229}
1230
1231static int bnx2x_get_eeprom_len(struct net_device *dev)
1232{
1233 struct bnx2x *bp = netdev_priv(dev);
1234
1235 return bp->common.flash_size;
1236}
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1252{
1253 int port = BP_PORT(bp);
1254 int count, i;
1255 u32 val;
1256
1257
1258 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1259
1260
1261 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1262 if (CHIP_REV_IS_SLOW(bp))
1263 count *= 100;
1264
1265
1266 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1267 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1268
1269 for (i = 0; i < count*10; i++) {
1270 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1271 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1272 break;
1273
1274 udelay(5);
1275 }
1276
1277 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1278 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1279 "cannot get access to nvram interface\n");
1280 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1281 return -EBUSY;
1282 }
1283
1284 return 0;
1285}
1286
1287static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1288{
1289 int port = BP_PORT(bp);
1290 int count, i;
1291 u32 val;
1292
1293
1294 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1295 if (CHIP_REV_IS_SLOW(bp))
1296 count *= 100;
1297
1298
1299 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1300 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1301
1302 for (i = 0; i < count*10; i++) {
1303 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1304 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1305 break;
1306
1307 udelay(5);
1308 }
1309
1310 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1311 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1312 "cannot free access to nvram interface\n");
1313 return -EBUSY;
1314 }
1315
1316
1317 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1318 return 0;
1319}
1320
1321static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1322{
1323 u32 val;
1324
1325 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1326
1327
1328 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1329 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1330 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1331}
1332
1333static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1334{
1335 u32 val;
1336
1337 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1338
1339
1340 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1341 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1342 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1343}
1344
1345static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1346 u32 cmd_flags)
1347{
1348 int count, i, rc;
1349 u32 val;
1350
1351
1352 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1353
1354
1355 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1356
1357
1358 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1359 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1360
1361
1362 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1363
1364
1365 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1366 if (CHIP_REV_IS_SLOW(bp))
1367 count *= 100;
1368
1369
1370 *ret_val = 0;
1371 rc = -EBUSY;
1372 for (i = 0; i < count; i++) {
1373 udelay(5);
1374 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1375
1376 if (val & MCPR_NVM_COMMAND_DONE) {
1377 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1378
1379
1380
1381
1382 *ret_val = cpu_to_be32(val);
1383 rc = 0;
1384 break;
1385 }
1386 }
1387 if (rc == -EBUSY)
1388 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1389 "nvram read timeout expired\n");
1390 return rc;
1391}
1392
1393int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1394 int buf_size)
1395{
1396 int rc;
1397 u32 cmd_flags;
1398 __be32 val;
1399
1400 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1401 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1402 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1403 offset, buf_size);
1404 return -EINVAL;
1405 }
1406
1407 if (offset + buf_size > bp->common.flash_size) {
1408 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1409 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1410 offset, buf_size, bp->common.flash_size);
1411 return -EINVAL;
1412 }
1413
1414
1415 rc = bnx2x_acquire_nvram_lock(bp);
1416 if (rc)
1417 return rc;
1418
1419
1420 bnx2x_enable_nvram_access(bp);
1421
1422
1423 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1424 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1425 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1426 memcpy(ret_buf, &val, 4);
1427
1428
1429 offset += sizeof(u32);
1430 ret_buf += sizeof(u32);
1431 buf_size -= sizeof(u32);
1432 cmd_flags = 0;
1433 }
1434
1435 if (rc == 0) {
1436 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1437 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1438 memcpy(ret_buf, &val, 4);
1439 }
1440
1441
1442 bnx2x_disable_nvram_access(bp);
1443 bnx2x_release_nvram_lock(bp);
1444
1445 return rc;
1446}
1447
1448static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1449 int buf_size)
1450{
1451 int rc;
1452
1453 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1454
1455 if (!rc) {
1456 __be32 *be = (__be32 *)buf;
1457
1458 while ((buf_size -= 4) >= 0)
1459 *buf++ = be32_to_cpu(*be++);
1460 }
1461
1462 return rc;
1463}
1464
1465static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1466{
1467 int rc = 1;
1468 u16 pm = 0;
1469 struct net_device *dev = pci_get_drvdata(bp->pdev);
1470
1471 if (bp->pdev->pm_cap)
1472 rc = pci_read_config_word(bp->pdev,
1473 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1474
1475 if ((rc && !netif_running(dev)) ||
1476 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1477 return false;
1478
1479 return true;
1480}
1481
1482static int bnx2x_get_eeprom(struct net_device *dev,
1483 struct ethtool_eeprom *eeprom, u8 *eebuf)
1484{
1485 struct bnx2x *bp = netdev_priv(dev);
1486
1487 if (!bnx2x_is_nvm_accessible(bp)) {
1488 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1489 "cannot access eeprom when the interface is down\n");
1490 return -EAGAIN;
1491 }
1492
1493 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1494 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1495 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1496 eeprom->len, eeprom->len);
1497
1498
1499
1500 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1501}
1502
1503static int bnx2x_get_module_eeprom(struct net_device *dev,
1504 struct ethtool_eeprom *ee,
1505 u8 *data)
1506{
1507 struct bnx2x *bp = netdev_priv(dev);
1508 int rc = -EINVAL, phy_idx;
1509 u8 *user_data = data;
1510 unsigned int start_addr = ee->offset, xfer_size = 0;
1511
1512 if (!bnx2x_is_nvm_accessible(bp)) {
1513 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1514 "cannot access eeprom when the interface is down\n");
1515 return -EAGAIN;
1516 }
1517
1518 phy_idx = bnx2x_get_cur_phy_idx(bp);
1519
1520
1521 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1522
1523 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1524 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1525 else
1526 xfer_size = ee->len;
1527 bnx2x_acquire_phy_lock(bp);
1528 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1529 &bp->link_params,
1530 I2C_DEV_ADDR_A0,
1531 start_addr,
1532 xfer_size,
1533 user_data);
1534 bnx2x_release_phy_lock(bp);
1535 if (rc) {
1536 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1537
1538 return -EINVAL;
1539 }
1540 user_data += xfer_size;
1541 start_addr += xfer_size;
1542 }
1543
1544
1545 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1546 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1547 xfer_size = ee->len - xfer_size;
1548
1549 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1550 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1551 start_addr -= ETH_MODULE_SFF_8079_LEN;
1552 bnx2x_acquire_phy_lock(bp);
1553 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1554 &bp->link_params,
1555 I2C_DEV_ADDR_A2,
1556 start_addr,
1557 xfer_size,
1558 user_data);
1559 bnx2x_release_phy_lock(bp);
1560 if (rc) {
1561 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1562 return -EINVAL;
1563 }
1564 }
1565 return rc;
1566}
1567
1568static int bnx2x_get_module_info(struct net_device *dev,
1569 struct ethtool_modinfo *modinfo)
1570{
1571 struct bnx2x *bp = netdev_priv(dev);
1572 int phy_idx, rc;
1573 u8 sff8472_comp, diag_type;
1574
1575 if (!bnx2x_is_nvm_accessible(bp)) {
1576 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1577 "cannot access eeprom when the interface is down\n");
1578 return -EAGAIN;
1579 }
1580 phy_idx = bnx2x_get_cur_phy_idx(bp);
1581 bnx2x_acquire_phy_lock(bp);
1582 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1583 &bp->link_params,
1584 I2C_DEV_ADDR_A0,
1585 SFP_EEPROM_SFF_8472_COMP_ADDR,
1586 SFP_EEPROM_SFF_8472_COMP_SIZE,
1587 &sff8472_comp);
1588 bnx2x_release_phy_lock(bp);
1589 if (rc) {
1590 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1591 return -EINVAL;
1592 }
1593
1594 bnx2x_acquire_phy_lock(bp);
1595 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1596 &bp->link_params,
1597 I2C_DEV_ADDR_A0,
1598 SFP_EEPROM_DIAG_TYPE_ADDR,
1599 SFP_EEPROM_DIAG_TYPE_SIZE,
1600 &diag_type);
1601 bnx2x_release_phy_lock(bp);
1602 if (rc) {
1603 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1604 return -EINVAL;
1605 }
1606
1607 if (!sff8472_comp ||
1608 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ) ||
1609 !(diag_type & SFP_EEPROM_DDM_IMPLEMENTED)) {
1610 modinfo->type = ETH_MODULE_SFF_8079;
1611 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1612 } else {
1613 modinfo->type = ETH_MODULE_SFF_8472;
1614 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1615 }
1616 return 0;
1617}
1618
1619static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1620 u32 cmd_flags)
1621{
1622 int count, i, rc;
1623
1624
1625 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1626
1627
1628 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1629
1630
1631 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1632
1633
1634 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1635 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1636
1637
1638 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1639
1640
1641 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1642 if (CHIP_REV_IS_SLOW(bp))
1643 count *= 100;
1644
1645
1646 rc = -EBUSY;
1647 for (i = 0; i < count; i++) {
1648 udelay(5);
1649 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1650 if (val & MCPR_NVM_COMMAND_DONE) {
1651 rc = 0;
1652 break;
1653 }
1654 }
1655
1656 if (rc == -EBUSY)
1657 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1658 "nvram write timeout expired\n");
1659 return rc;
1660}
1661
1662#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1663
1664static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1665 int buf_size)
1666{
1667 int rc;
1668 u32 cmd_flags, align_offset, val;
1669 __be32 val_be;
1670
1671 if (offset + buf_size > bp->common.flash_size) {
1672 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1673 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1674 offset, buf_size, bp->common.flash_size);
1675 return -EINVAL;
1676 }
1677
1678
1679 rc = bnx2x_acquire_nvram_lock(bp);
1680 if (rc)
1681 return rc;
1682
1683
1684 bnx2x_enable_nvram_access(bp);
1685
1686 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1687 align_offset = (offset & ~0x03);
1688 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1689
1690 if (rc == 0) {
1691
1692
1693
1694 val = be32_to_cpu(val_be);
1695
1696 val &= ~le32_to_cpu((__force __le32)
1697 (0xff << BYTE_OFFSET(offset)));
1698 val |= le32_to_cpu((__force __le32)
1699 (*data_buf << BYTE_OFFSET(offset)));
1700
1701 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1702 cmd_flags);
1703 }
1704
1705
1706 bnx2x_disable_nvram_access(bp);
1707 bnx2x_release_nvram_lock(bp);
1708
1709 return rc;
1710}
1711
1712static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1713 int buf_size)
1714{
1715 int rc;
1716 u32 cmd_flags;
1717 u32 val;
1718 u32 written_so_far;
1719
1720 if (buf_size == 1)
1721 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1722
1723 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1724 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1725 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1726 offset, buf_size);
1727 return -EINVAL;
1728 }
1729
1730 if (offset + buf_size > bp->common.flash_size) {
1731 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1732 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1733 offset, buf_size, bp->common.flash_size);
1734 return -EINVAL;
1735 }
1736
1737
1738 rc = bnx2x_acquire_nvram_lock(bp);
1739 if (rc)
1740 return rc;
1741
1742
1743 bnx2x_enable_nvram_access(bp);
1744
1745 written_so_far = 0;
1746 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1747 while ((written_so_far < buf_size) && (rc == 0)) {
1748 if (written_so_far == (buf_size - sizeof(u32)))
1749 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1750 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1751 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1752 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1753 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1754
1755 memcpy(&val, data_buf, 4);
1756
1757
1758
1759
1760
1761
1762
1763 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1764
1765
1766 offset += sizeof(u32);
1767 data_buf += sizeof(u32);
1768 written_so_far += sizeof(u32);
1769
1770
1771
1772
1773 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1774 (written_so_far < buf_size)) {
1775 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1776 "Releasing NVM lock after offset 0x%x\n",
1777 (u32)(offset - sizeof(u32)));
1778 bnx2x_release_nvram_lock(bp);
1779 usleep_range(1000, 2000);
1780 rc = bnx2x_acquire_nvram_lock(bp);
1781 if (rc)
1782 return rc;
1783 }
1784
1785 cmd_flags = 0;
1786 }
1787
1788
1789 bnx2x_disable_nvram_access(bp);
1790 bnx2x_release_nvram_lock(bp);
1791
1792 return rc;
1793}
1794
1795static int bnx2x_set_eeprom(struct net_device *dev,
1796 struct ethtool_eeprom *eeprom, u8 *eebuf)
1797{
1798 struct bnx2x *bp = netdev_priv(dev);
1799 int port = BP_PORT(bp);
1800 int rc = 0;
1801 u32 ext_phy_config;
1802
1803 if (!bnx2x_is_nvm_accessible(bp)) {
1804 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1805 "cannot access eeprom when the interface is down\n");
1806 return -EAGAIN;
1807 }
1808
1809 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1810 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1811 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1812 eeprom->len, eeprom->len);
1813
1814
1815
1816
1817 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1818 !bp->port.pmf) {
1819 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1820 "wrong magic or interface is not pmf\n");
1821 return -EINVAL;
1822 }
1823
1824 ext_phy_config =
1825 SHMEM_RD(bp,
1826 dev_info.port_hw_config[port].external_phy_config);
1827
1828 if (eeprom->magic == 0x50485950) {
1829
1830 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1831
1832 bnx2x_acquire_phy_lock(bp);
1833 rc |= bnx2x_link_reset(&bp->link_params,
1834 &bp->link_vars, 0);
1835 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1836 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1837 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1838 MISC_REGISTERS_GPIO_HIGH, port);
1839 bnx2x_release_phy_lock(bp);
1840 bnx2x_link_report(bp);
1841
1842 } else if (eeprom->magic == 0x50485952) {
1843
1844 if (bp->state == BNX2X_STATE_OPEN) {
1845 bnx2x_acquire_phy_lock(bp);
1846 rc |= bnx2x_link_reset(&bp->link_params,
1847 &bp->link_vars, 1);
1848
1849 rc |= bnx2x_phy_init(&bp->link_params,
1850 &bp->link_vars);
1851 bnx2x_release_phy_lock(bp);
1852 bnx2x_calc_fc_adv(bp);
1853 }
1854 } else if (eeprom->magic == 0x53985943) {
1855
1856 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1857 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1858
1859
1860 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1861 MISC_REGISTERS_GPIO_LOW, port);
1862
1863 bnx2x_acquire_phy_lock(bp);
1864
1865 bnx2x_sfx7101_sp_sw_reset(bp,
1866 &bp->link_params.phy[EXT_PHY1]);
1867
1868
1869 msleep(500);
1870 bnx2x_ext_phy_hw_reset(bp, port);
1871 msleep(500);
1872 bnx2x_release_phy_lock(bp);
1873 }
1874 } else
1875 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1876
1877 return rc;
1878}
1879
1880static int bnx2x_get_coalesce(struct net_device *dev,
1881 struct ethtool_coalesce *coal,
1882 struct kernel_ethtool_coalesce *kernel_coal,
1883 struct netlink_ext_ack *extack)
1884{
1885 struct bnx2x *bp = netdev_priv(dev);
1886
1887 memset(coal, 0, sizeof(struct ethtool_coalesce));
1888
1889 coal->rx_coalesce_usecs = bp->rx_ticks;
1890 coal->tx_coalesce_usecs = bp->tx_ticks;
1891
1892 return 0;
1893}
1894
1895static int bnx2x_set_coalesce(struct net_device *dev,
1896 struct ethtool_coalesce *coal,
1897 struct kernel_ethtool_coalesce *kernel_coal,
1898 struct netlink_ext_ack *extack)
1899{
1900 struct bnx2x *bp = netdev_priv(dev);
1901
1902 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1903 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1904 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1905
1906 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1907 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1908 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1909
1910 if (netif_running(dev))
1911 bnx2x_update_coalesce(bp);
1912
1913 return 0;
1914}
1915
1916static void bnx2x_get_ringparam(struct net_device *dev,
1917 struct ethtool_ringparam *ering)
1918{
1919 struct bnx2x *bp = netdev_priv(dev);
1920
1921 ering->rx_max_pending = MAX_RX_AVAIL;
1922
1923
1924
1925
1926
1927
1928
1929 if (bp->rx_ring_size)
1930 ering->rx_pending = bp->rx_ring_size;
1931 else if (BNX2X_NUM_RX_QUEUES(bp))
1932 ering->rx_pending = MAX_RX_AVAIL / BNX2X_NUM_RX_QUEUES(bp);
1933 else
1934 ering->rx_pending = MAX_RX_AVAIL;
1935
1936 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1937 ering->tx_pending = bp->tx_ring_size;
1938}
1939
1940static int bnx2x_set_ringparam(struct net_device *dev,
1941 struct ethtool_ringparam *ering)
1942{
1943 struct bnx2x *bp = netdev_priv(dev);
1944
1945 DP(BNX2X_MSG_ETHTOOL,
1946 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1947 ering->rx_pending, ering->tx_pending);
1948
1949 if (pci_num_vf(bp->pdev)) {
1950 DP(BNX2X_MSG_IOV,
1951 "VFs are enabled, can not change ring parameters\n");
1952 return -EPERM;
1953 }
1954
1955 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1956 DP(BNX2X_MSG_ETHTOOL,
1957 "Handling parity error recovery. Try again later\n");
1958 return -EAGAIN;
1959 }
1960
1961 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1962 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1963 MIN_RX_SIZE_TPA)) ||
1964 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1965 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1966 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1967 return -EINVAL;
1968 }
1969
1970 bp->rx_ring_size = ering->rx_pending;
1971 bp->tx_ring_size = ering->tx_pending;
1972
1973 return bnx2x_reload_if_running(dev);
1974}
1975
1976static void bnx2x_get_pauseparam(struct net_device *dev,
1977 struct ethtool_pauseparam *epause)
1978{
1979 struct bnx2x *bp = netdev_priv(dev);
1980 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1981 int cfg_reg;
1982
1983 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1984 BNX2X_FLOW_CTRL_AUTO);
1985
1986 if (!epause->autoneg)
1987 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1988 else
1989 cfg_reg = bp->link_params.req_fc_auto_adv;
1990
1991 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1992 BNX2X_FLOW_CTRL_RX);
1993 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1994 BNX2X_FLOW_CTRL_TX);
1995
1996 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1997 " autoneg %d rx_pause %d tx_pause %d\n",
1998 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1999}
2000
2001static int bnx2x_set_pauseparam(struct net_device *dev,
2002 struct ethtool_pauseparam *epause)
2003{
2004 struct bnx2x *bp = netdev_priv(dev);
2005 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2006 if (IS_MF(bp))
2007 return 0;
2008
2009 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
2010 " autoneg %d rx_pause %d tx_pause %d\n",
2011 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
2012
2013 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
2014
2015 if (epause->rx_pause)
2016 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
2017
2018 if (epause->tx_pause)
2019 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
2020
2021 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
2022 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
2023
2024 if (epause->autoneg) {
2025 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
2026 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
2027 return -EINVAL;
2028 }
2029
2030 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
2031 bp->link_params.req_flow_ctrl[cfg_idx] =
2032 BNX2X_FLOW_CTRL_AUTO;
2033 }
2034 bp->link_params.req_fc_auto_adv = 0;
2035 if (epause->rx_pause)
2036 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
2037
2038 if (epause->tx_pause)
2039 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
2040
2041 if (!bp->link_params.req_fc_auto_adv)
2042 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
2043 }
2044
2045 DP(BNX2X_MSG_ETHTOOL,
2046 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
2047
2048 if (netif_running(dev)) {
2049 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2050 bnx2x_force_link_reset(bp);
2051 bnx2x_link_set(bp);
2052 }
2053
2054 return 0;
2055}
2056
2057static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2058 "register_test (offline) ",
2059 "memory_test (offline) ",
2060 "int_loopback_test (offline)",
2061 "ext_loopback_test (offline)",
2062 "nvram_test (online) ",
2063 "interrupt_test (online) ",
2064 "link_test (online) "
2065};
2066
2067enum {
2068 BNX2X_PRI_FLAG_ISCSI,
2069 BNX2X_PRI_FLAG_FCOE,
2070 BNX2X_PRI_FLAG_STORAGE,
2071 BNX2X_PRI_FLAG_LEN,
2072};
2073
2074static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2075 "iSCSI offload support",
2076 "FCoE offload support",
2077 "Storage only interface"
2078};
2079
2080static u32 bnx2x_eee_to_adv(u32 eee_adv)
2081{
2082 u32 modes = 0;
2083
2084 if (eee_adv & SHMEM_EEE_100M_ADV)
2085 modes |= ADVERTISED_100baseT_Full;
2086 if (eee_adv & SHMEM_EEE_1G_ADV)
2087 modes |= ADVERTISED_1000baseT_Full;
2088 if (eee_adv & SHMEM_EEE_10G_ADV)
2089 modes |= ADVERTISED_10000baseT_Full;
2090
2091 return modes;
2092}
2093
2094static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2095{
2096 u32 eee_adv = 0;
2097 if (modes & ADVERTISED_100baseT_Full)
2098 eee_adv |= SHMEM_EEE_100M_ADV;
2099 if (modes & ADVERTISED_1000baseT_Full)
2100 eee_adv |= SHMEM_EEE_1G_ADV;
2101 if (modes & ADVERTISED_10000baseT_Full)
2102 eee_adv |= SHMEM_EEE_10G_ADV;
2103
2104 return eee_adv << shift;
2105}
2106
2107static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2108{
2109 struct bnx2x *bp = netdev_priv(dev);
2110 u32 eee_cfg;
2111
2112 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2113 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2114 return -EOPNOTSUPP;
2115 }
2116
2117 eee_cfg = bp->link_vars.eee_status;
2118
2119 edata->supported =
2120 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2121 SHMEM_EEE_SUPPORTED_SHIFT);
2122
2123 edata->advertised =
2124 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2125 SHMEM_EEE_ADV_STATUS_SHIFT);
2126 edata->lp_advertised =
2127 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2128 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2129
2130
2131 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2132
2133 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2134 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2135 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2136
2137 return 0;
2138}
2139
2140static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2141{
2142 struct bnx2x *bp = netdev_priv(dev);
2143 u32 eee_cfg;
2144 u32 advertised;
2145
2146 if (IS_MF(bp))
2147 return 0;
2148
2149 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2150 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2151 return -EOPNOTSUPP;
2152 }
2153
2154 eee_cfg = bp->link_vars.eee_status;
2155
2156 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2157 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2158 return -EOPNOTSUPP;
2159 }
2160
2161 advertised = bnx2x_adv_to_eee(edata->advertised,
2162 SHMEM_EEE_ADV_STATUS_SHIFT);
2163 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2164 DP(BNX2X_MSG_ETHTOOL,
2165 "Direct manipulation of EEE advertisement is not supported\n");
2166 return -EINVAL;
2167 }
2168
2169 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2170 DP(BNX2X_MSG_ETHTOOL,
2171 "Maximal Tx Lpi timer supported is %x(u)\n",
2172 EEE_MODE_TIMER_MASK);
2173 return -EINVAL;
2174 }
2175 if (edata->tx_lpi_enabled &&
2176 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2177 DP(BNX2X_MSG_ETHTOOL,
2178 "Minimal Tx Lpi timer supported is %d(u)\n",
2179 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2180 return -EINVAL;
2181 }
2182
2183
2184 if (edata->eee_enabled)
2185 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2186 else
2187 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2188
2189 if (edata->tx_lpi_enabled)
2190 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2191 else
2192 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2193
2194 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2195 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2196 EEE_MODE_TIMER_MASK) |
2197 EEE_MODE_OVERRIDE_NVRAM |
2198 EEE_MODE_OUTPUT_TIME;
2199
2200
2201 if (netif_running(dev)) {
2202 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2203 bnx2x_force_link_reset(bp);
2204 bnx2x_link_set(bp);
2205 }
2206
2207 return 0;
2208}
2209
2210enum {
2211 BNX2X_CHIP_E1_OFST = 0,
2212 BNX2X_CHIP_E1H_OFST,
2213 BNX2X_CHIP_E2_OFST,
2214 BNX2X_CHIP_E3_OFST,
2215 BNX2X_CHIP_E3B0_OFST,
2216 BNX2X_CHIP_MAX_OFST
2217};
2218
2219#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2220#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2221#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2222#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2223#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2224
2225#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2226#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2227
2228static int bnx2x_test_registers(struct bnx2x *bp)
2229{
2230 int idx, i, rc = -ENODEV;
2231 u32 wr_val = 0, hw;
2232 int port = BP_PORT(bp);
2233 static const struct {
2234 u32 hw;
2235 u32 offset0;
2236 u32 offset1;
2237 u32 mask;
2238 } reg_tbl[] = {
2239 { BNX2X_CHIP_MASK_ALL,
2240 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2241 { BNX2X_CHIP_MASK_ALL,
2242 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2243 { BNX2X_CHIP_MASK_E1X,
2244 HC_REG_AGG_INT_0, 4, 0x000003ff },
2245 { BNX2X_CHIP_MASK_ALL,
2246 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2247 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2248 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2249 { BNX2X_CHIP_MASK_E3B0,
2250 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2251 { BNX2X_CHIP_MASK_ALL,
2252 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2253 { BNX2X_CHIP_MASK_ALL,
2254 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2255 { BNX2X_CHIP_MASK_ALL,
2256 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2257 { BNX2X_CHIP_MASK_ALL,
2258 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2259 { BNX2X_CHIP_MASK_ALL,
2260 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2261 { BNX2X_CHIP_MASK_ALL,
2262 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2263 { BNX2X_CHIP_MASK_ALL,
2264 QM_REG_CONNNUM_0, 4, 0x000fffff },
2265 { BNX2X_CHIP_MASK_ALL,
2266 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2267 { BNX2X_CHIP_MASK_ALL,
2268 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2269 { BNX2X_CHIP_MASK_ALL,
2270 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2271 { BNX2X_CHIP_MASK_ALL,
2272 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2273 { BNX2X_CHIP_MASK_ALL,
2274 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2275 { BNX2X_CHIP_MASK_ALL,
2276 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2277 { BNX2X_CHIP_MASK_ALL,
2278 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2279 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2280 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2281 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2282 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2283 { BNX2X_CHIP_MASK_ALL,
2284 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2285 { BNX2X_CHIP_MASK_ALL,
2286 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2287 { BNX2X_CHIP_MASK_ALL,
2288 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2289 { BNX2X_CHIP_MASK_ALL,
2290 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2291 { BNX2X_CHIP_MASK_ALL,
2292 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2293 { BNX2X_CHIP_MASK_ALL,
2294 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2295 { BNX2X_CHIP_MASK_ALL,
2296 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2297 { BNX2X_CHIP_MASK_ALL,
2298 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2299 { BNX2X_CHIP_MASK_ALL,
2300 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2301 { BNX2X_CHIP_MASK_ALL,
2302 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2303 { BNX2X_CHIP_MASK_ALL,
2304 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2305 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2306 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2307 { BNX2X_CHIP_MASK_ALL,
2308 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2309 { BNX2X_CHIP_MASK_ALL,
2310 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2311 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2312 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2313 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2314 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2315
2316 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2317 };
2318
2319 if (!bnx2x_is_nvm_accessible(bp)) {
2320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2321 "cannot access eeprom when the interface is down\n");
2322 return rc;
2323 }
2324
2325 if (CHIP_IS_E1(bp))
2326 hw = BNX2X_CHIP_MASK_E1;
2327 else if (CHIP_IS_E1H(bp))
2328 hw = BNX2X_CHIP_MASK_E1H;
2329 else if (CHIP_IS_E2(bp))
2330 hw = BNX2X_CHIP_MASK_E2;
2331 else if (CHIP_IS_E3B0(bp))
2332 hw = BNX2X_CHIP_MASK_E3B0;
2333 else
2334 hw = BNX2X_CHIP_MASK_E3;
2335
2336
2337
2338
2339 for (idx = 0; idx < 2; idx++) {
2340
2341 switch (idx) {
2342 case 0:
2343 wr_val = 0;
2344 break;
2345 case 1:
2346 wr_val = 0xffffffff;
2347 break;
2348 }
2349
2350 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2351 u32 offset, mask, save_val, val;
2352 if (!(hw & reg_tbl[i].hw))
2353 continue;
2354
2355 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2356 mask = reg_tbl[i].mask;
2357
2358 save_val = REG_RD(bp, offset);
2359
2360 REG_WR(bp, offset, wr_val & mask);
2361
2362 val = REG_RD(bp, offset);
2363
2364
2365 REG_WR(bp, offset, save_val);
2366
2367
2368 if ((val & mask) != (wr_val & mask)) {
2369 DP(BNX2X_MSG_ETHTOOL,
2370 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2371 offset, val, wr_val, mask);
2372 goto test_reg_exit;
2373 }
2374 }
2375 }
2376
2377 rc = 0;
2378
2379test_reg_exit:
2380 return rc;
2381}
2382
2383static int bnx2x_test_memory(struct bnx2x *bp)
2384{
2385 int i, j, rc = -ENODEV;
2386 u32 val, index;
2387 static const struct {
2388 u32 offset;
2389 int size;
2390 } mem_tbl[] = {
2391 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2392 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2393 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2394 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2395 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2396 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2397 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2398
2399 { 0xffffffff, 0 }
2400 };
2401
2402 static const struct {
2403 char *name;
2404 u32 offset;
2405 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2406 } prty_tbl[] = {
2407 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2408 {0x3ffc0, 0, 0, 0} },
2409 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2410 {0x2, 0x2, 0, 0} },
2411 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2412 {0, 0, 0, 0} },
2413 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2414 {0x3ffc0, 0, 0, 0} },
2415 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2416 {0x3ffc0, 0, 0, 0} },
2417 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2418 {0x3ffc1, 0, 0, 0} },
2419
2420 { NULL, 0xffffffff, {0, 0, 0, 0} }
2421 };
2422
2423 if (!bnx2x_is_nvm_accessible(bp)) {
2424 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2425 "cannot access eeprom when the interface is down\n");
2426 return rc;
2427 }
2428
2429 if (CHIP_IS_E1(bp))
2430 index = BNX2X_CHIP_E1_OFST;
2431 else if (CHIP_IS_E1H(bp))
2432 index = BNX2X_CHIP_E1H_OFST;
2433 else if (CHIP_IS_E2(bp))
2434 index = BNX2X_CHIP_E2_OFST;
2435 else
2436 index = BNX2X_CHIP_E3_OFST;
2437
2438
2439 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2440 val = REG_RD(bp, prty_tbl[i].offset);
2441 if (val & ~(prty_tbl[i].hw_mask[index])) {
2442 DP(BNX2X_MSG_ETHTOOL,
2443 "%s is 0x%x\n", prty_tbl[i].name, val);
2444 goto test_mem_exit;
2445 }
2446 }
2447
2448
2449 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2450 for (j = 0; j < mem_tbl[i].size; j++)
2451 REG_RD(bp, mem_tbl[i].offset + j*4);
2452
2453
2454 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2455 val = REG_RD(bp, prty_tbl[i].offset);
2456 if (val & ~(prty_tbl[i].hw_mask[index])) {
2457 DP(BNX2X_MSG_ETHTOOL,
2458 "%s is 0x%x\n", prty_tbl[i].name, val);
2459 goto test_mem_exit;
2460 }
2461 }
2462
2463 rc = 0;
2464
2465test_mem_exit:
2466 return rc;
2467}
2468
2469static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2470{
2471 int cnt = 1400;
2472
2473 if (link_up) {
2474 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2475 msleep(20);
2476
2477 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2478 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2479
2480 cnt = 1400;
2481 while (!bp->link_vars.link_up && cnt--)
2482 msleep(20);
2483
2484 if (cnt <= 0 && !bp->link_vars.link_up)
2485 DP(BNX2X_MSG_ETHTOOL,
2486 "Timeout waiting for link init\n");
2487 }
2488}
2489
2490static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2491{
2492 unsigned int pkt_size, num_pkts, i;
2493 struct sk_buff *skb;
2494 unsigned char *packet;
2495 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2496 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2497 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2498 u16 tx_start_idx, tx_idx;
2499 u16 rx_start_idx, rx_idx;
2500 u16 pkt_prod, bd_prod;
2501 struct sw_tx_bd *tx_buf;
2502 struct eth_tx_start_bd *tx_start_bd;
2503 dma_addr_t mapping;
2504 union eth_rx_cqe *cqe;
2505 u8 cqe_fp_flags, cqe_fp_type;
2506 struct sw_rx_bd *rx_buf;
2507 u16 len;
2508 int rc = -ENODEV;
2509 u8 *data;
2510 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2511 txdata->txq_index);
2512
2513
2514 switch (loopback_mode) {
2515 case BNX2X_PHY_LOOPBACK:
2516 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2517 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2518 return -EINVAL;
2519 }
2520 break;
2521 case BNX2X_MAC_LOOPBACK:
2522 if (CHIP_IS_E3(bp)) {
2523 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2524 if (bp->port.supported[cfg_idx] &
2525 (SUPPORTED_10000baseT_Full |
2526 SUPPORTED_20000baseMLD2_Full |
2527 SUPPORTED_20000baseKR2_Full))
2528 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2529 else
2530 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2531 } else
2532 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2533
2534 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2535 break;
2536 case BNX2X_EXT_LOOPBACK:
2537 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2538 DP(BNX2X_MSG_ETHTOOL,
2539 "Can't configure external loopback\n");
2540 return -EINVAL;
2541 }
2542 break;
2543 default:
2544 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2545 return -EINVAL;
2546 }
2547
2548
2549 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2550 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2551 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2552 if (!skb) {
2553 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2554 rc = -ENOMEM;
2555 goto test_loopback_exit;
2556 }
2557 packet = skb_put(skb, pkt_size);
2558 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2559 eth_zero_addr(packet + ETH_ALEN);
2560 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2561 for (i = ETH_HLEN; i < pkt_size; i++)
2562 packet[i] = (unsigned char) (i & 0xff);
2563 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2564 skb_headlen(skb), DMA_TO_DEVICE);
2565 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2566 rc = -ENOMEM;
2567 dev_kfree_skb(skb);
2568 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2569 goto test_loopback_exit;
2570 }
2571
2572
2573 num_pkts = 0;
2574 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2575 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2576
2577 netdev_tx_sent_queue(txq, skb->len);
2578
2579 pkt_prod = txdata->tx_pkt_prod++;
2580 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2581 tx_buf->first_bd = txdata->tx_bd_prod;
2582 tx_buf->skb = skb;
2583 tx_buf->flags = 0;
2584
2585 bd_prod = TX_BD(txdata->tx_bd_prod);
2586 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2587 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2588 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2589 tx_start_bd->nbd = cpu_to_le16(2);
2590 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2591 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2592 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2593 SET_FLAG(tx_start_bd->general_data,
2594 ETH_TX_START_BD_HDR_NBDS,
2595 1);
2596 SET_FLAG(tx_start_bd->general_data,
2597 ETH_TX_START_BD_PARSE_NBDS,
2598 0);
2599
2600
2601 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2602
2603 if (CHIP_IS_E1x(bp)) {
2604 u16 global_data = 0;
2605 struct eth_tx_parse_bd_e1x *pbd_e1x =
2606 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2607 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2608 SET_FLAG(global_data,
2609 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2610 pbd_e1x->global_data = cpu_to_le16(global_data);
2611 } else {
2612 u32 parsing_data = 0;
2613 struct eth_tx_parse_bd_e2 *pbd_e2 =
2614 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2615 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2616 SET_FLAG(parsing_data,
2617 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2618 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2619 }
2620 wmb();
2621
2622 txdata->tx_db.data.prod += 2;
2623
2624 wmb();
2625 DOORBELL_RELAXED(bp, txdata->cid, txdata->tx_db.raw);
2626
2627 barrier();
2628
2629 num_pkts++;
2630 txdata->tx_bd_prod += 2;
2631
2632 udelay(100);
2633
2634 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2635 if (tx_idx != tx_start_idx + num_pkts)
2636 goto test_loopback_exit;
2637
2638
2639
2640
2641
2642 if (bp->common.int_block == INT_BLOCK_IGU) {
2643
2644
2645
2646
2647 local_bh_disable();
2648 bnx2x_tx_int(bp, txdata);
2649 local_bh_enable();
2650 }
2651
2652 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2653 if (rx_idx != rx_start_idx + num_pkts)
2654 goto test_loopback_exit;
2655
2656 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2657 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2658 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2659 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2660 goto test_loopback_rx_exit;
2661
2662 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2663 if (len != pkt_size)
2664 goto test_loopback_rx_exit;
2665
2666 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2667 dma_sync_single_for_cpu(&bp->pdev->dev,
2668 dma_unmap_addr(rx_buf, mapping),
2669 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2670 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2671 for (i = ETH_HLEN; i < pkt_size; i++)
2672 if (*(data + i) != (unsigned char) (i & 0xff))
2673 goto test_loopback_rx_exit;
2674
2675 rc = 0;
2676
2677test_loopback_rx_exit:
2678
2679 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2680 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2681 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2682 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2683
2684
2685 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2686 fp_rx->rx_sge_prod);
2687
2688test_loopback_exit:
2689 bp->link_params.loopback_mode = LOOPBACK_NONE;
2690
2691 return rc;
2692}
2693
2694static int bnx2x_test_loopback(struct bnx2x *bp)
2695{
2696 int rc = 0, res;
2697
2698 if (BP_NOMCP(bp))
2699 return rc;
2700
2701 if (!netif_running(bp->dev))
2702 return BNX2X_LOOPBACK_FAILED;
2703
2704 bnx2x_netif_stop(bp, 1);
2705 bnx2x_acquire_phy_lock(bp);
2706
2707 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2708 if (res) {
2709 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2710 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2711 }
2712
2713 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2714 if (res) {
2715 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2716 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2717 }
2718
2719 bnx2x_release_phy_lock(bp);
2720 bnx2x_netif_start(bp);
2721
2722 return rc;
2723}
2724
2725static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2726{
2727 int rc;
2728 u8 is_serdes =
2729 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2730
2731 if (BP_NOMCP(bp))
2732 return -ENODEV;
2733
2734 if (!netif_running(bp->dev))
2735 return BNX2X_EXT_LOOPBACK_FAILED;
2736
2737 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2738 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2739 if (rc) {
2740 DP(BNX2X_MSG_ETHTOOL,
2741 "Can't perform self-test, nic_load (for external lb) failed\n");
2742 return -ENODEV;
2743 }
2744 bnx2x_wait_for_link(bp, 1, is_serdes);
2745
2746 bnx2x_netif_stop(bp, 1);
2747
2748 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2749 if (rc)
2750 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2751
2752 bnx2x_netif_start(bp);
2753
2754 return rc;
2755}
2756
2757struct code_entry {
2758 u32 sram_start_addr;
2759 u32 code_attribute;
2760#define CODE_IMAGE_TYPE_MASK 0xf0800003
2761#define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2762#define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2763#define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2764 u32 nvm_start_addr;
2765};
2766
2767#define CODE_ENTRY_MAX 16
2768#define CODE_ENTRY_EXTENDED_DIR_IDX 15
2769#define MAX_IMAGES_IN_EXTENDED_DIR 64
2770#define NVRAM_DIR_OFFSET 0x14
2771
2772#define EXTENDED_DIR_EXISTS(code) \
2773 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2774 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2775
2776#define CRC32_RESIDUAL 0xdebb20e3
2777#define CRC_BUFF_SIZE 256
2778
2779static int bnx2x_nvram_crc(struct bnx2x *bp,
2780 int offset,
2781 int size,
2782 u8 *buff)
2783{
2784 u32 crc = ~0;
2785 int rc = 0, done = 0;
2786
2787 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2788 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2789
2790 while (done < size) {
2791 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2792
2793 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2794
2795 if (rc)
2796 return rc;
2797
2798 crc = crc32_le(crc, buff, count);
2799 done += count;
2800 }
2801
2802 if (crc != CRC32_RESIDUAL)
2803 rc = -EINVAL;
2804
2805 return rc;
2806}
2807
2808static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2809 struct code_entry *entry,
2810 u8 *buff)
2811{
2812 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2813 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2814 int rc;
2815
2816
2817 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2818 return 0;
2819
2820 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2821 if (rc)
2822 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2823 "image %x has failed crc test (rc %d)\n", type, rc);
2824
2825 return rc;
2826}
2827
2828static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2829{
2830 int rc;
2831 struct code_entry entry;
2832
2833 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2834 if (rc)
2835 return rc;
2836
2837 return bnx2x_test_nvram_dir(bp, &entry, buff);
2838}
2839
2840static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2841{
2842 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2843 struct code_entry entry;
2844 int i;
2845
2846 rc = bnx2x_nvram_read32(bp,
2847 dir_offset +
2848 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2849 (u32 *)&entry, sizeof(entry));
2850 if (rc)
2851 return rc;
2852
2853 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2854 return 0;
2855
2856 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2857 &cnt, sizeof(u32));
2858 if (rc)
2859 return rc;
2860
2861 dir_offset = entry.nvm_start_addr + 8;
2862
2863 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2864 rc = bnx2x_test_dir_entry(bp, dir_offset +
2865 sizeof(struct code_entry) * i,
2866 buff);
2867 if (rc)
2868 return rc;
2869 }
2870
2871 return 0;
2872}
2873
2874static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2875{
2876 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2877 int i;
2878
2879 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2880
2881 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2882 rc = bnx2x_test_dir_entry(bp, dir_offset +
2883 sizeof(struct code_entry) * i,
2884 buff);
2885 if (rc)
2886 return rc;
2887 }
2888
2889 return bnx2x_test_nvram_ext_dirs(bp, buff);
2890}
2891
2892struct crc_pair {
2893 int offset;
2894 int size;
2895};
2896
2897static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2898 const struct crc_pair *nvram_tbl, u8 *buf)
2899{
2900 int i;
2901
2902 for (i = 0; nvram_tbl[i].size; i++) {
2903 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2904 nvram_tbl[i].size, buf);
2905 if (rc) {
2906 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2907 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2908 i, rc);
2909 return rc;
2910 }
2911 }
2912
2913 return 0;
2914}
2915
2916static int bnx2x_test_nvram(struct bnx2x *bp)
2917{
2918 static const struct crc_pair nvram_tbl[] = {
2919 { 0, 0x14 },
2920 { 0x14, 0xec },
2921 { 0x100, 0x350 },
2922 { 0x450, 0xf0 },
2923 { 0x640, 0x64 },
2924 { 0x708, 0x70 },
2925 { 0, 0 }
2926 };
2927 static const struct crc_pair nvram_tbl2[] = {
2928 { 0x7e8, 0x350 },
2929 { 0xb38, 0xf0 },
2930 { 0, 0 }
2931 };
2932
2933 u8 *buf;
2934 int rc;
2935 u32 magic;
2936
2937 if (BP_NOMCP(bp))
2938 return 0;
2939
2940 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2941 if (!buf) {
2942 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2943 rc = -ENOMEM;
2944 goto test_nvram_exit;
2945 }
2946
2947 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2948 if (rc) {
2949 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2950 "magic value read (rc %d)\n", rc);
2951 goto test_nvram_exit;
2952 }
2953
2954 if (magic != 0x669955aa) {
2955 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2956 "wrong magic value (0x%08x)\n", magic);
2957 rc = -ENODEV;
2958 goto test_nvram_exit;
2959 }
2960
2961 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2962 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2963 if (rc)
2964 goto test_nvram_exit;
2965
2966 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2967 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2968 SHARED_HW_CFG_HIDE_PORT1;
2969
2970 if (!hide) {
2971 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2972 "Port 1 CRC test-set\n");
2973 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2974 if (rc)
2975 goto test_nvram_exit;
2976 }
2977 }
2978
2979 rc = bnx2x_test_nvram_dirs(bp, buf);
2980
2981test_nvram_exit:
2982 kfree(buf);
2983 return rc;
2984}
2985
2986
2987static int bnx2x_test_intr(struct bnx2x *bp)
2988{
2989 struct bnx2x_queue_state_params params = {NULL};
2990
2991 if (!netif_running(bp->dev)) {
2992 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2993 "cannot access eeprom when the interface is down\n");
2994 return -ENODEV;
2995 }
2996
2997 params.q_obj = &bp->sp_objs->q_obj;
2998 params.cmd = BNX2X_Q_CMD_EMPTY;
2999
3000 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
3001
3002 return bnx2x_queue_state_change(bp, ¶ms);
3003}
3004
3005static void bnx2x_self_test(struct net_device *dev,
3006 struct ethtool_test *etest, u64 *buf)
3007{
3008 struct bnx2x *bp = netdev_priv(dev);
3009 u8 is_serdes, link_up;
3010 int rc, cnt = 0;
3011
3012 if (pci_num_vf(bp->pdev)) {
3013 DP(BNX2X_MSG_IOV,
3014 "VFs are enabled, can not perform self test\n");
3015 return;
3016 }
3017
3018 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
3019 netdev_err(bp->dev,
3020 "Handling parity error recovery. Try again later\n");
3021 etest->flags |= ETH_TEST_FL_FAILED;
3022 return;
3023 }
3024
3025 DP(BNX2X_MSG_ETHTOOL,
3026 "Self-test command parameters: offline = %d, external_lb = %d\n",
3027 (etest->flags & ETH_TEST_FL_OFFLINE),
3028 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
3029
3030 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
3031
3032 if (bnx2x_test_nvram(bp) != 0) {
3033 if (!IS_MF(bp))
3034 buf[4] = 1;
3035 else
3036 buf[0] = 1;
3037 etest->flags |= ETH_TEST_FL_FAILED;
3038 }
3039
3040 if (!netif_running(dev)) {
3041 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
3042 return;
3043 }
3044
3045 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
3046 link_up = bp->link_vars.link_up;
3047
3048 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
3049 int port = BP_PORT(bp);
3050 u32 val;
3051
3052
3053 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
3054
3055 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3056
3057 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3058 rc = bnx2x_nic_load(bp, LOAD_DIAG);
3059 if (rc) {
3060 etest->flags |= ETH_TEST_FL_FAILED;
3061 DP(BNX2X_MSG_ETHTOOL,
3062 "Can't perform self-test, nic_load (for offline) failed\n");
3063 return;
3064 }
3065
3066
3067 bnx2x_wait_for_link(bp, 1, is_serdes);
3068
3069 if (bnx2x_test_registers(bp) != 0) {
3070 buf[0] = 1;
3071 etest->flags |= ETH_TEST_FL_FAILED;
3072 }
3073 if (bnx2x_test_memory(bp) != 0) {
3074 buf[1] = 1;
3075 etest->flags |= ETH_TEST_FL_FAILED;
3076 }
3077
3078 buf[2] = bnx2x_test_loopback(bp);
3079 if (buf[2] != 0)
3080 etest->flags |= ETH_TEST_FL_FAILED;
3081
3082 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3083 buf[3] = bnx2x_test_ext_loopback(bp);
3084 if (buf[3] != 0)
3085 etest->flags |= ETH_TEST_FL_FAILED;
3086 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3087 }
3088
3089 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3090
3091
3092 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3093 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3094 if (rc) {
3095 etest->flags |= ETH_TEST_FL_FAILED;
3096 DP(BNX2X_MSG_ETHTOOL,
3097 "Can't perform self-test, nic_load (for online) failed\n");
3098 return;
3099 }
3100
3101 bnx2x_wait_for_link(bp, link_up, is_serdes);
3102 }
3103
3104 if (bnx2x_test_intr(bp) != 0) {
3105 if (!IS_MF(bp))
3106 buf[5] = 1;
3107 else
3108 buf[1] = 1;
3109 etest->flags |= ETH_TEST_FL_FAILED;
3110 }
3111
3112 if (link_up) {
3113 cnt = 100;
3114 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3115 msleep(20);
3116 }
3117
3118 if (!cnt) {
3119 if (!IS_MF(bp))
3120 buf[6] = 1;
3121 else
3122 buf[2] = 1;
3123 etest->flags |= ETH_TEST_FL_FAILED;
3124 }
3125}
3126
3127#define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat)
3128#define HIDE_PORT_STAT(bp) IS_VF(bp)
3129
3130
3131
3132
3133static int bnx2x_num_stat_queues(struct bnx2x *bp)
3134{
3135 return BNX2X_NUM_ETH_QUEUES(bp);
3136}
3137
3138static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3139{
3140 struct bnx2x *bp = netdev_priv(dev);
3141 int i, num_strings = 0;
3142
3143 switch (stringset) {
3144 case ETH_SS_STATS:
3145 if (is_multi(bp)) {
3146 num_strings = bnx2x_num_stat_queues(bp) *
3147 BNX2X_NUM_Q_STATS;
3148 } else
3149 num_strings = 0;
3150 if (HIDE_PORT_STAT(bp)) {
3151 for (i = 0; i < BNX2X_NUM_STATS; i++)
3152 if (!IS_PORT_STAT(i))
3153 num_strings++;
3154 } else
3155 num_strings += BNX2X_NUM_STATS;
3156
3157 return num_strings;
3158
3159 case ETH_SS_TEST:
3160 return BNX2X_NUM_TESTS(bp);
3161
3162 case ETH_SS_PRIV_FLAGS:
3163 return BNX2X_PRI_FLAG_LEN;
3164
3165 default:
3166 return -EINVAL;
3167 }
3168}
3169
3170static u32 bnx2x_get_private_flags(struct net_device *dev)
3171{
3172 struct bnx2x *bp = netdev_priv(dev);
3173 u32 flags = 0;
3174
3175 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3176 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3177 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3178
3179 return flags;
3180}
3181
3182static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3183{
3184 struct bnx2x *bp = netdev_priv(dev);
3185 int i, j, k, start;
3186 char queue_name[MAX_QUEUE_NAME_LEN+1];
3187
3188 switch (stringset) {
3189 case ETH_SS_STATS:
3190 k = 0;
3191 if (is_multi(bp)) {
3192 for_each_eth_queue(bp, i) {
3193 memset(queue_name, 0, sizeof(queue_name));
3194 snprintf(queue_name, sizeof(queue_name),
3195 "%d", i);
3196 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3197 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3198 ETH_GSTRING_LEN,
3199 bnx2x_q_stats_arr[j].string,
3200 queue_name);
3201 k += BNX2X_NUM_Q_STATS;
3202 }
3203 }
3204
3205 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3206 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3207 continue;
3208 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3209 bnx2x_stats_arr[i].string);
3210 j++;
3211 }
3212
3213 break;
3214
3215 case ETH_SS_TEST:
3216
3217 if (!IS_MF(bp))
3218 start = 0;
3219 else
3220 start = 4;
3221 memcpy(buf, bnx2x_tests_str_arr + start,
3222 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3223 break;
3224
3225 case ETH_SS_PRIV_FLAGS:
3226 memcpy(buf, bnx2x_private_arr,
3227 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3228 break;
3229 }
3230}
3231
3232static void bnx2x_get_ethtool_stats(struct net_device *dev,
3233 struct ethtool_stats *stats, u64 *buf)
3234{
3235 struct bnx2x *bp = netdev_priv(dev);
3236 u32 *hw_stats, *offset;
3237 int i, j, k = 0;
3238
3239 if (is_multi(bp)) {
3240 for_each_eth_queue(bp, i) {
3241 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3242 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3243 if (bnx2x_q_stats_arr[j].size == 0) {
3244
3245 buf[k + j] = 0;
3246 continue;
3247 }
3248 offset = (hw_stats +
3249 bnx2x_q_stats_arr[j].offset);
3250 if (bnx2x_q_stats_arr[j].size == 4) {
3251
3252 buf[k + j] = (u64) *offset;
3253 continue;
3254 }
3255
3256 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3257 }
3258 k += BNX2X_NUM_Q_STATS;
3259 }
3260 }
3261
3262 hw_stats = (u32 *)&bp->eth_stats;
3263 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3264 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3265 continue;
3266 if (bnx2x_stats_arr[i].size == 0) {
3267
3268 buf[k + j] = 0;
3269 j++;
3270 continue;
3271 }
3272 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3273 if (bnx2x_stats_arr[i].size == 4) {
3274
3275 buf[k + j] = (u64) *offset;
3276 j++;
3277 continue;
3278 }
3279
3280 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3281 j++;
3282 }
3283}
3284
3285static int bnx2x_set_phys_id(struct net_device *dev,
3286 enum ethtool_phys_id_state state)
3287{
3288 struct bnx2x *bp = netdev_priv(dev);
3289
3290 if (!bnx2x_is_nvm_accessible(bp)) {
3291 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3292 "cannot access eeprom when the interface is down\n");
3293 return -EAGAIN;
3294 }
3295
3296 switch (state) {
3297 case ETHTOOL_ID_ACTIVE:
3298 return 1;
3299
3300 case ETHTOOL_ID_ON:
3301 bnx2x_acquire_phy_lock(bp);
3302 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3303 LED_MODE_ON, SPEED_1000);
3304 bnx2x_release_phy_lock(bp);
3305 break;
3306
3307 case ETHTOOL_ID_OFF:
3308 bnx2x_acquire_phy_lock(bp);
3309 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3310 LED_MODE_FRONT_PANEL_OFF, 0);
3311 bnx2x_release_phy_lock(bp);
3312 break;
3313
3314 case ETHTOOL_ID_INACTIVE:
3315 bnx2x_acquire_phy_lock(bp);
3316 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3317 LED_MODE_OPER,
3318 bp->link_vars.line_speed);
3319 bnx2x_release_phy_lock(bp);
3320 }
3321
3322 return 0;
3323}
3324
3325static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3326{
3327 switch (info->flow_type) {
3328 case TCP_V4_FLOW:
3329 case TCP_V6_FLOW:
3330 info->data = RXH_IP_SRC | RXH_IP_DST |
3331 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3332 break;
3333 case UDP_V4_FLOW:
3334 if (bp->rss_conf_obj.udp_rss_v4)
3335 info->data = RXH_IP_SRC | RXH_IP_DST |
3336 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3337 else
3338 info->data = RXH_IP_SRC | RXH_IP_DST;
3339 break;
3340 case UDP_V6_FLOW:
3341 if (bp->rss_conf_obj.udp_rss_v6)
3342 info->data = RXH_IP_SRC | RXH_IP_DST |
3343 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3344 else
3345 info->data = RXH_IP_SRC | RXH_IP_DST;
3346 break;
3347 case IPV4_FLOW:
3348 case IPV6_FLOW:
3349 info->data = RXH_IP_SRC | RXH_IP_DST;
3350 break;
3351 default:
3352 info->data = 0;
3353 break;
3354 }
3355
3356 return 0;
3357}
3358
3359static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3360 u32 *rules __always_unused)
3361{
3362 struct bnx2x *bp = netdev_priv(dev);
3363
3364 switch (info->cmd) {
3365 case ETHTOOL_GRXRINGS:
3366 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3367 return 0;
3368 case ETHTOOL_GRXFH:
3369 return bnx2x_get_rss_flags(bp, info);
3370 default:
3371 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3372 return -EOPNOTSUPP;
3373 }
3374}
3375
3376static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3377{
3378 int udp_rss_requested;
3379
3380 DP(BNX2X_MSG_ETHTOOL,
3381 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3382 info->flow_type, info->data);
3383
3384 switch (info->flow_type) {
3385 case TCP_V4_FLOW:
3386 case TCP_V6_FLOW:
3387
3388 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3389 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3390 DP(BNX2X_MSG_ETHTOOL,
3391 "Command parameters not supported\n");
3392 return -EINVAL;
3393 }
3394 return 0;
3395
3396 case UDP_V4_FLOW:
3397 case UDP_V6_FLOW:
3398
3399 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3400 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3401 udp_rss_requested = 1;
3402 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3403 udp_rss_requested = 0;
3404 else
3405 return -EINVAL;
3406
3407 if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3408 DP(BNX2X_MSG_ETHTOOL,
3409 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3410 return -EINVAL;
3411 }
3412
3413 if ((info->flow_type == UDP_V4_FLOW) &&
3414 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3415 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3416 DP(BNX2X_MSG_ETHTOOL,
3417 "rss re-configured, UDP 4-tupple %s\n",
3418 udp_rss_requested ? "enabled" : "disabled");
3419 if (bp->state == BNX2X_STATE_OPEN)
3420 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3421 true);
3422 } else if ((info->flow_type == UDP_V6_FLOW) &&
3423 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3424 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3425 DP(BNX2X_MSG_ETHTOOL,
3426 "rss re-configured, UDP 4-tupple %s\n",
3427 udp_rss_requested ? "enabled" : "disabled");
3428 if (bp->state == BNX2X_STATE_OPEN)
3429 return bnx2x_rss(bp, &bp->rss_conf_obj, false,
3430 true);
3431 }
3432 return 0;
3433
3434 case IPV4_FLOW:
3435 case IPV6_FLOW:
3436
3437 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3438 DP(BNX2X_MSG_ETHTOOL,
3439 "Command parameters not supported\n");
3440 return -EINVAL;
3441 }
3442 return 0;
3443
3444 case SCTP_V4_FLOW:
3445 case AH_ESP_V4_FLOW:
3446 case AH_V4_FLOW:
3447 case ESP_V4_FLOW:
3448 case SCTP_V6_FLOW:
3449 case AH_ESP_V6_FLOW:
3450 case AH_V6_FLOW:
3451 case ESP_V6_FLOW:
3452 case IP_USER_FLOW:
3453 case ETHER_FLOW:
3454
3455 if (info->data) {
3456 DP(BNX2X_MSG_ETHTOOL,
3457 "Command parameters not supported\n");
3458 return -EINVAL;
3459 }
3460 return 0;
3461
3462 default:
3463 return -EINVAL;
3464 }
3465}
3466
3467static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3468{
3469 struct bnx2x *bp = netdev_priv(dev);
3470
3471 switch (info->cmd) {
3472 case ETHTOOL_SRXFH:
3473 return bnx2x_set_rss_flags(bp, info);
3474 default:
3475 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3476 return -EOPNOTSUPP;
3477 }
3478}
3479
3480static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3481{
3482 return T_ETH_INDIRECTION_TABLE_SIZE;
3483}
3484
3485static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3486 u8 *hfunc)
3487{
3488 struct bnx2x *bp = netdev_priv(dev);
3489 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3490 size_t i;
3491
3492 if (hfunc)
3493 *hfunc = ETH_RSS_HASH_TOP;
3494 if (!indir)
3495 return 0;
3496
3497
3498 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3510 indir[i] = ind_table[i] - bp->fp->cl_id;
3511
3512 return 0;
3513}
3514
3515static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3516 const u8 *key, const u8 hfunc)
3517{
3518 struct bnx2x *bp = netdev_priv(dev);
3519 size_t i;
3520
3521
3522
3523
3524 if (key ||
3525 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3526 return -EOPNOTSUPP;
3527
3528 if (!indir)
3529 return 0;
3530
3531 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3542 }
3543
3544 if (bp->state == BNX2X_STATE_OPEN)
3545 return bnx2x_config_rss_eth(bp, false);
3546
3547 return 0;
3548}
3549
3550
3551
3552
3553
3554
3555
3556static void bnx2x_get_channels(struct net_device *dev,
3557 struct ethtool_channels *channels)
3558{
3559 struct bnx2x *bp = netdev_priv(dev);
3560
3561 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3562 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3563}
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3575{
3576 bnx2x_disable_msi(bp);
3577 bp->num_ethernet_queues = num_rss;
3578 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3579 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3580 bnx2x_set_int_mode(bp);
3581}
3582
3583
3584
3585
3586
3587
3588
3589static int bnx2x_set_channels(struct net_device *dev,
3590 struct ethtool_channels *channels)
3591{
3592 struct bnx2x *bp = netdev_priv(dev);
3593
3594 DP(BNX2X_MSG_ETHTOOL,
3595 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3596 channels->rx_count, channels->tx_count, channels->other_count,
3597 channels->combined_count);
3598
3599 if (pci_num_vf(bp->pdev)) {
3600 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3601 return -EPERM;
3602 }
3603
3604
3605
3606
3607 if (channels->rx_count || channels->tx_count || channels->other_count
3608 || (channels->combined_count == 0) ||
3609 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3610 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3611 return -EINVAL;
3612 }
3613
3614
3615 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3616 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3617 return 0;
3618 }
3619
3620
3621
3622
3623
3624 if (unlikely(!netif_running(dev))) {
3625 bnx2x_change_num_queues(bp, channels->combined_count);
3626 return 0;
3627 }
3628 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3629 bnx2x_change_num_queues(bp, channels->combined_count);
3630 return bnx2x_nic_load(bp, LOAD_NORMAL);
3631}
3632
3633static int bnx2x_get_ts_info(struct net_device *dev,
3634 struct ethtool_ts_info *info)
3635{
3636 struct bnx2x *bp = netdev_priv(dev);
3637
3638 if (bp->flags & PTP_SUPPORTED) {
3639 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3640 SOF_TIMESTAMPING_RX_SOFTWARE |
3641 SOF_TIMESTAMPING_SOFTWARE |
3642 SOF_TIMESTAMPING_TX_HARDWARE |
3643 SOF_TIMESTAMPING_RX_HARDWARE |
3644 SOF_TIMESTAMPING_RAW_HARDWARE;
3645
3646 if (bp->ptp_clock)
3647 info->phc_index = ptp_clock_index(bp->ptp_clock);
3648 else
3649 info->phc_index = -1;
3650
3651 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3652 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3653 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3654 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3655
3656 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3657
3658 return 0;
3659 }
3660
3661 return ethtool_op_get_ts_info(dev, info);
3662}
3663
3664static const struct ethtool_ops bnx2x_ethtool_ops = {
3665 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3666 .get_drvinfo = bnx2x_get_drvinfo,
3667 .get_regs_len = bnx2x_get_regs_len,
3668 .get_regs = bnx2x_get_regs,
3669 .get_dump_flag = bnx2x_get_dump_flag,
3670 .get_dump_data = bnx2x_get_dump_data,
3671 .set_dump = bnx2x_set_dump,
3672 .get_wol = bnx2x_get_wol,
3673 .set_wol = bnx2x_set_wol,
3674 .get_msglevel = bnx2x_get_msglevel,
3675 .set_msglevel = bnx2x_set_msglevel,
3676 .nway_reset = bnx2x_nway_reset,
3677 .get_link = bnx2x_get_link,
3678 .get_eeprom_len = bnx2x_get_eeprom_len,
3679 .get_eeprom = bnx2x_get_eeprom,
3680 .set_eeprom = bnx2x_set_eeprom,
3681 .get_coalesce = bnx2x_get_coalesce,
3682 .set_coalesce = bnx2x_set_coalesce,
3683 .get_ringparam = bnx2x_get_ringparam,
3684 .set_ringparam = bnx2x_set_ringparam,
3685 .get_pauseparam = bnx2x_get_pauseparam,
3686 .set_pauseparam = bnx2x_set_pauseparam,
3687 .self_test = bnx2x_self_test,
3688 .get_sset_count = bnx2x_get_sset_count,
3689 .get_priv_flags = bnx2x_get_private_flags,
3690 .get_strings = bnx2x_get_strings,
3691 .set_phys_id = bnx2x_set_phys_id,
3692 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3693 .get_rxnfc = bnx2x_get_rxnfc,
3694 .set_rxnfc = bnx2x_set_rxnfc,
3695 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3696 .get_rxfh = bnx2x_get_rxfh,
3697 .set_rxfh = bnx2x_set_rxfh,
3698 .get_channels = bnx2x_get_channels,
3699 .set_channels = bnx2x_set_channels,
3700 .get_module_info = bnx2x_get_module_info,
3701 .get_module_eeprom = bnx2x_get_module_eeprom,
3702 .get_eee = bnx2x_get_eee,
3703 .set_eee = bnx2x_set_eee,
3704 .get_ts_info = bnx2x_get_ts_info,
3705 .get_link_ksettings = bnx2x_get_link_ksettings,
3706 .set_link_ksettings = bnx2x_set_link_ksettings,
3707};
3708
3709static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3710 .get_drvinfo = bnx2x_get_drvinfo,
3711 .get_msglevel = bnx2x_get_msglevel,
3712 .set_msglevel = bnx2x_set_msglevel,
3713 .get_link = bnx2x_get_link,
3714 .get_coalesce = bnx2x_get_coalesce,
3715 .get_ringparam = bnx2x_get_ringparam,
3716 .set_ringparam = bnx2x_set_ringparam,
3717 .get_sset_count = bnx2x_get_sset_count,
3718 .get_strings = bnx2x_get_strings,
3719 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3720 .get_rxnfc = bnx2x_get_rxnfc,
3721 .set_rxnfc = bnx2x_set_rxnfc,
3722 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3723 .get_rxfh = bnx2x_get_rxfh,
3724 .set_rxfh = bnx2x_set_rxfh,
3725 .get_channels = bnx2x_get_channels,
3726 .set_channels = bnx2x_set_channels,
3727 .get_link_ksettings = bnx2x_get_vf_link_ksettings,
3728};
3729
3730void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3731{
3732 netdev->ethtool_ops = (IS_PF(bp)) ?
3733 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3734}
3735
