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11#ifndef BNX2X_HSI_H
12#define BNX2X_HSI_H
13
14#include "bnx2x_fw_defs.h"
15#include "bnx2x_mfw_req.h"
16
17#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
18
19struct license_key {
20 u32 reserved[6];
21
22 u32 max_iscsi_conn;
23#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25#define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
26#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
27
28 u32 reserved_a;
29
30 u32 max_fcoe_conn;
31#define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33#define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
34#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
35
36 u32 reserved_b[4];
37};
38
39
40
41
42#define PIN_CFG_NA 0x00000000
43#define PIN_CFG_GPIO0_P0 0x00000001
44#define PIN_CFG_GPIO1_P0 0x00000002
45#define PIN_CFG_GPIO2_P0 0x00000003
46#define PIN_CFG_GPIO3_P0 0x00000004
47#define PIN_CFG_GPIO0_P1 0x00000005
48#define PIN_CFG_GPIO1_P1 0x00000006
49#define PIN_CFG_GPIO2_P1 0x00000007
50#define PIN_CFG_GPIO3_P1 0x00000008
51#define PIN_CFG_EPIO0 0x00000009
52#define PIN_CFG_EPIO1 0x0000000a
53#define PIN_CFG_EPIO2 0x0000000b
54#define PIN_CFG_EPIO3 0x0000000c
55#define PIN_CFG_EPIO4 0x0000000d
56#define PIN_CFG_EPIO5 0x0000000e
57#define PIN_CFG_EPIO6 0x0000000f
58#define PIN_CFG_EPIO7 0x00000010
59#define PIN_CFG_EPIO8 0x00000011
60#define PIN_CFG_EPIO9 0x00000012
61#define PIN_CFG_EPIO10 0x00000013
62#define PIN_CFG_EPIO11 0x00000014
63#define PIN_CFG_EPIO12 0x00000015
64#define PIN_CFG_EPIO13 0x00000016
65#define PIN_CFG_EPIO14 0x00000017
66#define PIN_CFG_EPIO15 0x00000018
67#define PIN_CFG_EPIO16 0x00000019
68#define PIN_CFG_EPIO17 0x0000001a
69#define PIN_CFG_EPIO18 0x0000001b
70#define PIN_CFG_EPIO19 0x0000001c
71#define PIN_CFG_EPIO20 0x0000001d
72#define PIN_CFG_EPIO21 0x0000001e
73#define PIN_CFG_EPIO22 0x0000001f
74#define PIN_CFG_EPIO23 0x00000020
75#define PIN_CFG_EPIO24 0x00000021
76#define PIN_CFG_EPIO25 0x00000022
77#define PIN_CFG_EPIO26 0x00000023
78#define PIN_CFG_EPIO27 0x00000024
79#define PIN_CFG_EPIO28 0x00000025
80#define PIN_CFG_EPIO29 0x00000026
81#define PIN_CFG_EPIO30 0x00000027
82#define PIN_CFG_EPIO31 0x00000028
83
84
85#define EPIO_CFG_NA 0x00000000
86#define EPIO_CFG_EPIO0 0x00000001
87#define EPIO_CFG_EPIO1 0x00000002
88#define EPIO_CFG_EPIO2 0x00000003
89#define EPIO_CFG_EPIO3 0x00000004
90#define EPIO_CFG_EPIO4 0x00000005
91#define EPIO_CFG_EPIO5 0x00000006
92#define EPIO_CFG_EPIO6 0x00000007
93#define EPIO_CFG_EPIO7 0x00000008
94#define EPIO_CFG_EPIO8 0x00000009
95#define EPIO_CFG_EPIO9 0x0000000a
96#define EPIO_CFG_EPIO10 0x0000000b
97#define EPIO_CFG_EPIO11 0x0000000c
98#define EPIO_CFG_EPIO12 0x0000000d
99#define EPIO_CFG_EPIO13 0x0000000e
100#define EPIO_CFG_EPIO14 0x0000000f
101#define EPIO_CFG_EPIO15 0x00000010
102#define EPIO_CFG_EPIO16 0x00000011
103#define EPIO_CFG_EPIO17 0x00000012
104#define EPIO_CFG_EPIO18 0x00000013
105#define EPIO_CFG_EPIO19 0x00000014
106#define EPIO_CFG_EPIO20 0x00000015
107#define EPIO_CFG_EPIO21 0x00000016
108#define EPIO_CFG_EPIO22 0x00000017
109#define EPIO_CFG_EPIO23 0x00000018
110#define EPIO_CFG_EPIO24 0x00000019
111#define EPIO_CFG_EPIO25 0x0000001a
112#define EPIO_CFG_EPIO26 0x0000001b
113#define EPIO_CFG_EPIO27 0x0000001c
114#define EPIO_CFG_EPIO28 0x0000001d
115#define EPIO_CFG_EPIO29 0x0000001e
116#define EPIO_CFG_EPIO30 0x0000001f
117#define EPIO_CFG_EPIO31 0x00000020
118
119struct mac_addr {
120 u32 upper;
121 u32 lower;
122};
123
124struct shared_hw_cfg {
125
126 u8 part_num[16];
127
128 u32 config;
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
131 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
132 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
133 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
134
135 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
136
137 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
138
139 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
140 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
141
142 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
143 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
144
145
146 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
147 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
148 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
149 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
150
151
152 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
153
154
155 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
156
157
158 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
159
160 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
161 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
162 #define SHARED_HW_CFG_LED_MAC1 0x00000000
163 #define SHARED_HW_CFG_LED_PHY1 0x00010000
164 #define SHARED_HW_CFG_LED_PHY2 0x00020000
165 #define SHARED_HW_CFG_LED_PHY3 0x00030000
166 #define SHARED_HW_CFG_LED_MAC2 0x00040000
167 #define SHARED_HW_CFG_LED_PHY4 0x00050000
168 #define SHARED_HW_CFG_LED_PHY5 0x00060000
169 #define SHARED_HW_CFG_LED_PHY6 0x00070000
170 #define SHARED_HW_CFG_LED_MAC3 0x00080000
171 #define SHARED_HW_CFG_LED_PHY7 0x00090000
172 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
173 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
174 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
175 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
176 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
177 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
178
179
180 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
181 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
182 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
183 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
184 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
185 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
186 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
187 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
188
189 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
190 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
191 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
192
193 #define SHARED_HW_CFG_ATC_MASK 0x80000000
194 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
195 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
196
197 u32 config2;
198
199 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
200 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
201
202 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
203 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
204
205
206
207 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
208 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
209
210 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
211 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
212 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
213
214 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
215
216 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
217 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
218 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
219
220
221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
222 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
223 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
224
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
229 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
230 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
231
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237
238
239 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
240 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
241 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
242 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
243 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
244
245
246 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
250 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
251 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
252
253
254
255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
256 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
257 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
258
259 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
260 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
261 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
262
263 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
264 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
265 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
266
267
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
275
276
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
284
285 u32 config_3;
286 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
287 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
288 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
289 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
290
291 u32 ump_nc_si_config;
292 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
293 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
294 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
298
299 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
300 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
301
302 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
303 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
304 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
306
307 u32 board;
308 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
309 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
310 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
311 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
312
313 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
314 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
315
316 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
317 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
318
319 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
320 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
321
322 u32 wc_lane_config;
323 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
324 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
325 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
333
334
335 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
336 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
337 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
338 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
339
340 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
341 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
342 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
343 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
344
345
346 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
347 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
348 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
354};
355
356
357
358
359
360struct port_hw_cfg {
361
362 u32 pci_id;
363 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
364 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
365
366 u32 pci_sub_id;
367 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
368 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
369
370 u32 power_dissipated;
371 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
372 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
373 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
374 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
375 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
376 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
377 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
378 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
379
380 u32 power_consumed;
381 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
382 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
383 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
384 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
385 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
386 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
387 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
388 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
389
390 u32 mac_upper;
391 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
392 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
393 u32 mac_lower;
394
395 u32 iscsi_mac_upper;
396 u32 iscsi_mac_lower;
397
398 u32 rdma_mac_upper;
399 u32 rdma_mac_lower;
400
401 u32 serdes_config;
402 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
403 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
404
405 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
406 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
407
408
409
410 u32 pf_config;
411 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
412 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
413
414
415 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
416 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
417
418 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
419 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
420
421 u32 vf_config;
422 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
423 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
424
425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
426 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
427
428 u32 mf_pci_id;
429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
431
432
433 u32 sfp_ctrl;
434 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
435 #define PORT_HW_CFG_TX_LASER_SHIFT 0
436 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
437 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
438 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
439 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
440 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
441
442
443 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
444 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
449 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
450
451
452
453 u32 e3_sfp_ctrl;
454 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
455 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
456
457
458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
459 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
460
461
462
463 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
464 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
465
466
467
468 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
469 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
470
471
472
473
474
475 u32 e3_cmn_pin_cfg;
476 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
477 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
478
479
480
481 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
482 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
483
484
485
486
487
488 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
489 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
490
491
492
493 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
494 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
495
496
497
498
499
500
501 u32 e3_cmn_pin_cfg1;
502 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
503 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
504
505
506 u32 generic_features;
507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
511
512
513
514
515
516 u32 sfi_tap_values;
517 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
518 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
519
520
521
522
523
524 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
525 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
526
527 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
528 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
529
530
531 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
532 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
533
534
535 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
536 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
537
538 u32 reserved0[5];
539
540 u32 aeu_int_mask;
541
542 u32 media_type;
543 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
544 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
545
546 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
547 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
548
549 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
550 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
551
552
553
554
555
556
557 u16 xgxs_config_rx[4];
558 u16 xgxs_config_tx[4];
559
560
561 u32 fcoe_fip_mac_upper;
562 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
563 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
564 u32 fcoe_fip_mac_lower;
565
566 u32 fcoe_wwn_port_name_upper;
567 u32 fcoe_wwn_port_name_lower;
568
569 u32 fcoe_wwn_node_name_upper;
570 u32 fcoe_wwn_node_name_lower;
571
572 u32 Reserved1[49];
573
574
575
576 u32 xgbt_phy_cfg;
577 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
578 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
579
580 u32 default_cfg;
581 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
582 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
583 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
584 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
585 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
586 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
587
588 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
589 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
590 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
591 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
592 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
593 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
594
595 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
596 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
597 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
598 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
599 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
600 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
601
602 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
603 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
604 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
605 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
606 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
607 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
608
609
610
611
612
613
614
615 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
616 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
617 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
618 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
619 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
620 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
621 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
622 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
623 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
624 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
625 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
626 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
627
628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
631 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
632 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
633 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
634 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
635 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
636 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
637 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
639
640
641 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
642 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
643 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
644 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
645
646
647 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
648 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
649 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
650 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
651
652
653 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
654 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
655 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
656 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
657 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
658 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
659 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
660 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
661
662
663 u32 speed_capability_mask2;
664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
666 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
674
675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
677 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
678 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
679 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
680 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
681 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
682 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
685
686
687
688
689
690
691 u32 multi_phy_config;
692 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
693 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
694 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
695 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
696 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
697 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
698 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
699
700
701
702 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
703 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
704 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
705 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
706
707
708
709 u32 external_phy_config2;
710 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
711 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
712
713
714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
728 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
729 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
730 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
731 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
732 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200
735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
737
738
739
740
741 u16 xgxs_config2_rx[4];
742 u16 xgxs_config2_tx[4];
743
744 u32 lane_config;
745 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
746 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
747
748 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
749
750 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
751
752 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
753
754 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
755 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
756 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
757 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
758 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
759 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
760 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
761
762
763 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
764 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
765 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
766
767
768 u32 external_phy_config;
769 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
770 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
771
772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
786 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
787 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
788 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
789 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200
793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
796
797 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
798 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
799
800 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
801 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
802 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
803 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
804 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
805 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
806
807 u32 speed_capability_mask;
808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
809 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
810 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
811 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
812 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
813 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
814 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
815 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
816 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
817 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
818 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
819
820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
821 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
822 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
823 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
824 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
825 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
826 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
827 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
828 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
829 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
830 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
831
832
833 u32 backup_mac_upper;
834 u32 backup_mac_lower;
835
836};
837
838
839
840
841
842struct shared_feat_cfg {
843
844 u32 config;
845 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
846
847
848 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
849 0x00000002
850 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
851 0x00000000
852 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
853 0x00000002
854
855 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
856 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
857 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
858
859 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
860 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
861
862
863
864 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
865 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
866 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
867 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
868 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
869 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
870 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
871 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
872 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
873 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
874
875
876
877 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
878 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
879
880
881 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
882 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
883
884};
885
886
887
888
889
890struct port_feat_cfg {
891
892 u32 config;
893 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
894 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
895 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
896 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
897 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
898 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
899 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
900 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
901 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
902 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
903 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
904 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
905 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
906 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
907 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
908 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
909 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
910 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
911 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
912 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
913 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
914 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
915 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
916 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
917 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
918 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
919 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
920 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
921 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
922 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
923 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
924 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
925 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
926 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
927 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
928 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
929
930 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
931 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
932 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
933
934 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
935 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
936 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
937
938 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
939 #define PORT_FEATURE_EN_SIZE_SHIFT 24
940 #define PORT_FEATURE_WOL_ENABLED 0x01000000
941 #define PORT_FEATURE_MBA_ENABLED 0x02000000
942 #define PORT_FEATURE_MFW_ENABLED 0x04000000
943
944
945 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
946 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
947 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
948
949
950
951 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
952 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
953 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
954 0x00000000
955 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
956 0x20000000
957 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
958 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
959
960 u32 wol_config;
961
962 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
963 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
964 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
965 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
966 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
967 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
968 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
969 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
970 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
971
972 u32 mba_config;
973 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
974 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
975 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
976 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
977 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
978 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
979 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
980 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
981
982 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
983 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
984
985 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
986 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
987 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
988 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
989 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
990 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
996 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
997 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
998 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
999 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
1000 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
1001 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
1002 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
1003 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
1004 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
1005 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
1006 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
1007 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
1008 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
1009 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
1010 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
1011 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
1012 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
1013 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1014 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1015 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1016 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1017 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
1018 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
1019 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1020 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
1021 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
1022 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
1023 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
1024 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
1025 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
1026 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
1027 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
1028 u32 bmc_config;
1029 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
1030 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
1031 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
1032
1033 u32 mba_vlan_cfg;
1034 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
1035 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1036 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1037
1038 u32 resource_cfg;
1039 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
1040 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1041 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1042 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1043 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1044
1045 u32 smbus_config;
1046 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1047 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1048
1049 u32 vf_config;
1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1055 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1056 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1057 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1058 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1059 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1060 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1061 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1062 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1063 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1064 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1065 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1066 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1067 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1068
1069 u32 link_config;
1070 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1071 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1072
1073 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1074
1075 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1076 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1077 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1078
1079 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1080 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1081 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1082 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1083 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1084 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1085 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1086 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1087 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1088 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1089 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1090
1091 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1092 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1093 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1094 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1095 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1096 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1097 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1098
1099
1100
1101 u32 mfw_wol_link_cfg;
1102
1103
1104
1105 u32 link_config2;
1106
1107
1108
1109 u32 mfw_wol_link_cfg2;
1110
1111
1112
1113 u32 eee_power_mode;
1114 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1115 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1116 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1117 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1118 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1119 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1120
1121
1122 u32 Reserved2[16];
1123};
1124
1125
1126
1127
1128
1129struct shm_dev_info {
1130
1131 u32 bc_rev;
1132
1133 struct shared_hw_cfg shared_hw_config;
1134
1135 struct port_hw_cfg port_hw_config[PORT_MAX];
1136
1137 struct shared_feat_cfg shared_feature_config;
1138
1139 struct port_feat_cfg port_feature_config[PORT_MAX];
1140
1141};
1142
1143struct extended_dev_info_shared_cfg {
1144 u32 reserved[18];
1145 u32 mbi_version;
1146 u32 mbi_date;
1147};
1148
1149#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1150 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1151#endif
1152
1153#define FUNC_0 0
1154#define FUNC_1 1
1155#define FUNC_2 2
1156#define FUNC_3 3
1157#define FUNC_4 4
1158#define FUNC_5 5
1159#define FUNC_6 6
1160#define FUNC_7 7
1161#define E1_FUNC_MAX 2
1162#define E1H_FUNC_MAX 8
1163#define E2_FUNC_MAX 4
1164
1165#define VN_0 0
1166#define VN_1 1
1167#define VN_2 2
1168#define VN_3 3
1169#define E1VN_MAX 1
1170#define E1HVN_MAX 4
1171
1172#define E2_VF_MAX 64
1173
1174
1175
1176#define DRV_PULSE_PERIOD_MS 250
1177
1178
1179
1180
1181
1182
1183#define FW_ACK_TIME_OUT_MS 5000
1184
1185#define FW_ACK_POLL_TIME_MS 1
1186
1187#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1188
1189#define MFW_TRACE_SIGNATURE 0x54524342
1190
1191
1192
1193
1194struct drv_port_mb {
1195
1196 u32 link_status;
1197
1198
1199 #define LINK_STATUS_NONE (0<<0)
1200 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1201 #define LINK_STATUS_LINK_UP 0x00000001
1202 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1203 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1204 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1205 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1206 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1207 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1208 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1209 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1210 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1211 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1212 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1213 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1214 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1215 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1216 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1217 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1218 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1219
1220 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1221 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1222
1223 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1224 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1225 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1226
1227 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1228 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1229 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1230 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1231 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1232 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1233 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1234
1235 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1236 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1237
1238 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1239 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1240
1241 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1242 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1243 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1244 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1245 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1246
1247 #define LINK_STATUS_SERDES_LINK 0x00100000
1248
1249 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1250 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1251 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1252 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1253
1254 #define LINK_STATUS_PFC_ENABLED 0x20000000
1255
1256 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1257 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1258
1259 u32 port_stx;
1260
1261 u32 stat_nig_timer;
1262
1263
1264 u32 ext_phy_fw_version;
1265
1266};
1267
1268
1269struct drv_func_mb {
1270
1271 u32 drv_mb_header;
1272 #define DRV_MSG_CODE_MASK 0xffff0000
1273 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1274 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1275 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1276 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1277 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1278 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1279 #define DRV_MSG_CODE_DCC_OK 0x30000000
1280 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1281 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1282 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1283 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1284 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1285 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1286 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1287 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1288 #define DRV_MSG_CODE_OEM_OK 0x00010000
1289 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
1290 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
1291 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
1292
1293
1294
1295
1296
1297 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1298 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1299 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1300 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1301 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1302 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1303 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1304 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1305 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1306 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1307
1308 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1309 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1310 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1311
1312 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1313
1314 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1315 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1316 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1317 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1318 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1319
1320 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1321 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1322
1323 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1324
1325 #define DRV_MSG_CODE_RMMOD 0xdb000000
1326 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
1327
1328 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1329 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1330 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1331
1332 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1333
1334 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1335 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1336
1337 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1338 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1339 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1340 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1341
1342 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1343
1344 u32 drv_mb_param;
1345 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1346 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1347
1348 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1349
1350 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1351 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1352
1353 u32 fw_mb_header;
1354 #define FW_MSG_CODE_MASK 0xffff0000
1355 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1356 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1357 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1358
1359 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1360 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1361
1362 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1363 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1364 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1365 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1366 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1367 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1368 #define FW_MSG_CODE_DCC_DONE 0x30100000
1369 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1370 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1371 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1372 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1373 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1374 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1375 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1376 #define FW_MSG_CODE_NO_KEY 0x80f00000
1377 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1378 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1379 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1380 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1381 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1382 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1383 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1384 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1385 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1386 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1387 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1388
1389 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1390 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1391 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1392 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1393 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1394
1395 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1396 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1397
1398 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1399
1400 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000
1401
1402 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1403 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1404
1405 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1406
1407 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1408 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1409 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1410 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1411
1412 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1413
1414 u32 fw_mb_param;
1415
1416 u32 drv_pulse_mb;
1417 #define DRV_PULSE_SEQ_MASK 0x00007fff
1418 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1419
1420
1421
1422
1423 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1424
1425
1426
1427
1428
1429
1430 u32 mcp_pulse_mb;
1431 #define MCP_PULSE_SEQ_MASK 0x00007fff
1432 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1433
1434
1435 #define MCP_EVENT_MASK 0xffff0000
1436 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1437
1438 u32 iscsi_boot_signature;
1439 u32 iscsi_boot_block_offset;
1440
1441 u32 drv_status;
1442 #define DRV_STATUS_PMF 0x00000001
1443 #define DRV_STATUS_VF_DISABLED 0x00000002
1444 #define DRV_STATUS_SET_MF_BW 0x00000004
1445 #define DRV_STATUS_LINK_EVENT 0x00000008
1446
1447 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
1448 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
1449 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
1450
1451 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
1452
1453 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1454 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1455 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1456 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1457 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1458 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1459 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1460
1461 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1462 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1463 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1464 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1465 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1466 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1467 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1468
1469 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1470
1471 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1472
1473 u32 virt_mac_upper;
1474 #define VIRT_MAC_SIGN_MASK 0xffff0000
1475 #define VIRT_MAC_SIGNATURE 0x564d0000
1476 u32 virt_mac_lower;
1477
1478};
1479
1480
1481
1482
1483
1484
1485#define MGMTFW_STATE_WORD_SIZE 110
1486
1487struct mgmtfw_state {
1488 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1489};
1490
1491
1492
1493
1494
1495struct shared_mf_cfg {
1496
1497 u32 clp_mb;
1498 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1499
1500 #define SHARED_MF_CLP_EXIT 0x00000001
1501
1502 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1503
1504};
1505
1506struct port_mf_cfg {
1507
1508 u32 dynamic_cfg;
1509 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1510 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1511 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1512
1513 u32 reserved[1];
1514
1515};
1516
1517struct func_mf_cfg {
1518
1519 u32 config;
1520
1521
1522 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1523
1524 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1525 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1526 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1527 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1528 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1529 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1530 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1531
1532 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1533 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1534
1535
1536
1537 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1538 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1539 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1540
1541
1542
1543 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1544 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1545 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1546 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1547 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1548 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1549
1550 u32 mac_upper;
1551 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1552 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1553 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1554 u32 mac_lower;
1555 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1556
1557 u32 e1hov_tag;
1558 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1559 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1560 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1561
1562
1563 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1564 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1565
1566 u32 afex_config;
1567 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1568 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1569 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1570 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1571 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1572 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1573 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1574
1575 u32 reserved;
1576};
1577
1578enum mf_cfg_afex_vlan_mode {
1579 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1580 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1581 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1582};
1583
1584
1585struct func_ext_cfg {
1586 u32 func_cfg;
1587 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
1588 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1589 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1590 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1591 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1592 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1593 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
1594
1595 u32 iscsi_mac_addr_upper;
1596 u32 iscsi_mac_addr_lower;
1597
1598 u32 fcoe_mac_addr_upper;
1599 u32 fcoe_mac_addr_lower;
1600
1601 u32 fcoe_wwn_port_name_upper;
1602 u32 fcoe_wwn_port_name_lower;
1603
1604 u32 fcoe_wwn_node_name_upper;
1605 u32 fcoe_wwn_node_name_lower;
1606
1607 u32 preserve_data;
1608 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1609 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1610 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1611 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1612 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1613 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1614};
1615
1616struct mf_cfg {
1617
1618 struct shared_mf_cfg shared_mf_config;
1619
1620 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1621
1622 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
1623
1624
1625
1626
1627 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
1628};
1629
1630
1631
1632
1633struct shmem_region {
1634
1635 u32 validity_map[PORT_MAX];
1636 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1637 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1638
1639 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1640 #define SHR_MEM_VALIDITY_MB 0x00200000
1641 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1642 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1643
1644 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1645 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1646 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1647 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1648
1649 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1650 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1651 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1652 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1653 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1654 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1655
1656 struct shm_dev_info dev_info;
1657
1658 struct license_key drv_lic_key[PORT_MAX];
1659
1660
1661 u32 fw_info_fio_offset;
1662 struct mgmtfw_state mgmtfw_state;
1663
1664 struct drv_port_mb port_mb[PORT_MAX];
1665
1666#ifdef BMAPI
1667
1668
1669 struct drv_func_mb func_mb[1];
1670#else
1671
1672 struct drv_func_mb func_mb[];
1673#endif
1674
1675};
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692struct fw_flr_ack {
1693 u32 pf_ack;
1694 u32 vf_ack[1];
1695 u32 iov_dis_ack;
1696};
1697
1698struct fw_flr_mb {
1699 u32 aggint;
1700 u32 opgen_addr;
1701 struct fw_flr_ack ack;
1702};
1703
1704struct eee_remote_vals {
1705 u32 tx_tw;
1706 u32 rx_tw;
1707};
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1720#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1747 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1748 (((i)%((fb)/(eb))) * (eb)))
1749
1750#define SHMEM_ARRAY_GET(a, i, eb, fb) \
1751 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1752 SHMEM_ARRAY_MASK(eb))
1753
1754#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1755do { \
1756 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1757 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1758 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1759 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1760} while (0)
1761
1762
1763
1764#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1765#define DCBX_PRI_PG_BITWIDTH 4
1766#define DCBX_PRI_PG_FBITS 8
1767#define DCBX_PRI_PG_GET(a, i) \
1768 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1769#define DCBX_PRI_PG_SET(a, i, val) \
1770 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1771#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1772#define DCBX_BW_PG_BITWIDTH 8
1773#define DCBX_PG_BW_GET(a, i) \
1774 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1775#define DCBX_PG_BW_SET(a, i, val) \
1776 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1777#define DCBX_STRICT_PRI_PG 15
1778#define DCBX_MAX_APP_PROTOCOL 16
1779#define FCOE_APP_IDX 0
1780#define ISCSI_APP_IDX 1
1781#define PREDEFINED_APP_IDX_MAX 2
1782
1783
1784
1785struct dcbx_ets_feature {
1786
1787
1788
1789
1790 u32 enabled;
1791 u32 pg_bw_tbl[2];
1792 u32 pri_pg_tbl[1];
1793};
1794
1795
1796struct dcbx_pfc_feature {
1797#ifdef __BIG_ENDIAN
1798 u8 pri_en_bitmap;
1799 #define DCBX_PFC_PRI_0 0x01
1800 #define DCBX_PFC_PRI_1 0x02
1801 #define DCBX_PFC_PRI_2 0x04
1802 #define DCBX_PFC_PRI_3 0x08
1803 #define DCBX_PFC_PRI_4 0x10
1804 #define DCBX_PFC_PRI_5 0x20
1805 #define DCBX_PFC_PRI_6 0x40
1806 #define DCBX_PFC_PRI_7 0x80
1807 u8 pfc_caps;
1808 u8 reserved;
1809 u8 enabled;
1810#elif defined(__LITTLE_ENDIAN)
1811 u8 enabled;
1812 u8 reserved;
1813 u8 pfc_caps;
1814 u8 pri_en_bitmap;
1815 #define DCBX_PFC_PRI_0 0x01
1816 #define DCBX_PFC_PRI_1 0x02
1817 #define DCBX_PFC_PRI_2 0x04
1818 #define DCBX_PFC_PRI_3 0x08
1819 #define DCBX_PFC_PRI_4 0x10
1820 #define DCBX_PFC_PRI_5 0x20
1821 #define DCBX_PFC_PRI_6 0x40
1822 #define DCBX_PFC_PRI_7 0x80
1823#endif
1824};
1825
1826struct dcbx_app_priority_entry {
1827#ifdef __BIG_ENDIAN
1828 u16 app_id;
1829 u8 pri_bitmap;
1830 u8 appBitfield;
1831 #define DCBX_APP_ENTRY_VALID 0x01
1832 #define DCBX_APP_ENTRY_SF_MASK 0xF0
1833 #define DCBX_APP_ENTRY_SF_SHIFT 4
1834 #define DCBX_APP_SF_ETH_TYPE 0x10
1835 #define DCBX_APP_SF_PORT 0x20
1836 #define DCBX_APP_SF_UDP 0x40
1837 #define DCBX_APP_SF_DEFAULT 0x80
1838#elif defined(__LITTLE_ENDIAN)
1839 u8 appBitfield;
1840 #define DCBX_APP_ENTRY_VALID 0x01
1841 #define DCBX_APP_ENTRY_SF_MASK 0xF0
1842 #define DCBX_APP_ENTRY_SF_SHIFT 4
1843 #define DCBX_APP_ENTRY_VALID 0x01
1844 #define DCBX_APP_SF_ETH_TYPE 0x10
1845 #define DCBX_APP_SF_PORT 0x20
1846 #define DCBX_APP_SF_UDP 0x40
1847 #define DCBX_APP_SF_DEFAULT 0x80
1848 u8 pri_bitmap;
1849 u16 app_id;
1850#endif
1851};
1852
1853
1854
1855struct dcbx_app_priority_feature {
1856#ifdef __BIG_ENDIAN
1857 u8 reserved;
1858 u8 default_pri;
1859 u8 tc_supported;
1860 u8 enabled;
1861#elif defined(__LITTLE_ENDIAN)
1862 u8 enabled;
1863 u8 tc_supported;
1864 u8 default_pri;
1865 u8 reserved;
1866#endif
1867 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1868};
1869
1870
1871struct dcbx_features {
1872
1873 struct dcbx_ets_feature ets;
1874
1875 struct dcbx_pfc_feature pfc;
1876
1877 struct dcbx_app_priority_feature app;
1878};
1879
1880
1881
1882struct lldp_params {
1883#ifdef __BIG_ENDIAN
1884 u8 msg_fast_tx_interval;
1885 u8 msg_tx_hold;
1886 u8 msg_tx_interval;
1887 u8 admin_status;
1888 #define LLDP_TX_ONLY 0x01
1889 #define LLDP_RX_ONLY 0x02
1890 #define LLDP_TX_RX 0x03
1891 #define LLDP_DISABLED 0x04
1892 u8 reserved1;
1893 u8 tx_fast;
1894 u8 tx_crd_max;
1895 u8 tx_crd;
1896#elif defined(__LITTLE_ENDIAN)
1897 u8 admin_status;
1898 #define LLDP_TX_ONLY 0x01
1899 #define LLDP_RX_ONLY 0x02
1900 #define LLDP_TX_RX 0x03
1901 #define LLDP_DISABLED 0x04
1902 u8 msg_tx_interval;
1903 u8 msg_tx_hold;
1904 u8 msg_fast_tx_interval;
1905 u8 tx_crd;
1906 u8 tx_crd_max;
1907 u8 tx_fast;
1908 u8 reserved1;
1909#endif
1910 #define REM_CHASSIS_ID_STAT_LEN 4
1911 #define REM_PORT_ID_STAT_LEN 4
1912
1913 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1914
1915 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1916};
1917
1918struct lldp_dcbx_stat {
1919 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1920 #define LOCAL_PORT_ID_STAT_LEN 2
1921
1922 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1923
1924 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1925
1926 u32 num_tx_dcbx_pkts;
1927
1928 u32 num_rx_dcbx_pkts;
1929};
1930
1931
1932struct lldp_admin_mib {
1933 u32 ver_cfg_flags;
1934 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1935 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1936 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1937 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1938 #define DCBX_ETS_RECO_VALID 0x00000010
1939 #define DCBX_ETS_WILLING 0x00000020
1940 #define DCBX_PFC_WILLING 0x00000040
1941 #define DCBX_APP_WILLING 0x00000080
1942 #define DCBX_VERSION_CEE 0x00000100
1943 #define DCBX_VERSION_IEEE 0x00000200
1944 #define DCBX_DCBX_ENABLED 0x00000400
1945 #define DCBX_CEE_VERSION_MASK 0x0000f000
1946 #define DCBX_CEE_VERSION_SHIFT 12
1947 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1948 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1949 struct dcbx_features features;
1950};
1951
1952
1953struct lldp_remote_mib {
1954 u32 prefix_seq_num;
1955 u32 flags;
1956 #define DCBX_ETS_TLV_RX 0x00000001
1957 #define DCBX_PFC_TLV_RX 0x00000002
1958 #define DCBX_APP_TLV_RX 0x00000004
1959 #define DCBX_ETS_RX_ERROR 0x00000010
1960 #define DCBX_PFC_RX_ERROR 0x00000020
1961 #define DCBX_APP_RX_ERROR 0x00000040
1962 #define DCBX_ETS_REM_WILLING 0x00000100
1963 #define DCBX_PFC_REM_WILLING 0x00000200
1964 #define DCBX_APP_REM_WILLING 0x00000400
1965 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1966 #define DCBX_REMOTE_MIB_VALID 0x00002000
1967 struct dcbx_features features;
1968 u32 suffix_seq_num;
1969};
1970
1971
1972struct lldp_local_mib {
1973 u32 prefix_seq_num;
1974
1975 u32 error;
1976 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1977 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1978 #define DCBX_LOCAL_APP_ERROR 0x00000004
1979 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1980 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1981 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1982 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1983 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1984 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1985 struct dcbx_features features;
1986 u32 suffix_seq_num;
1987};
1988
1989
1990
1991
1992
1993#define SHMEM_LINK_CONFIG_SIZE 2
1994struct shmem_lfa {
1995 u32 req_duplex;
1996 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
1997 #define REQ_DUPLEX_PHY0_SHIFT 0
1998 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
1999 #define REQ_DUPLEX_PHY1_SHIFT 16
2000 u32 req_flow_ctrl;
2001 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
2002 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
2003 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
2004 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
2005 u32 req_line_speed;
2006 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
2007 #define REQ_LINE_SPD_PHY0_SHIFT 0
2008 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
2009 #define REQ_LINE_SPD_PHY1_SHIFT 16
2010 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
2011 u32 additional_config;
2012 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
2013 #define REQ_FC_AUTO_ADV0_SHIFT 0
2014 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
2015 u32 lfa_sts;
2016 #define LFA_LINK_FLAP_REASON_OFFSET 0
2017 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
2018 #define LFA_LINK_DOWN 0x1
2019 #define LFA_LOOPBACK_ENABLED 0x2
2020 #define LFA_DUPLEX_MISMATCH 0x3
2021 #define LFA_MFW_IS_TOO_OLD 0x4
2022 #define LFA_LINK_SPEED_MISMATCH 0x5
2023 #define LFA_FLOW_CTRL_MISMATCH 0x6
2024 #define LFA_SPEED_CAP_MISMATCH 0x7
2025 #define LFA_DCC_LFA_DISABLED 0x8
2026 #define LFA_EEE_MISMATCH 0x9
2027
2028 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
2029 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
2030
2031 #define LINK_FLAP_COUNT_OFFSET 16
2032 #define LINK_FLAP_COUNT_MASK 0x00ff0000
2033
2034 #define LFA_FLAGS_MASK 0xff000000
2035 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
2036};
2037
2038
2039
2040
2041
2042struct os_drv_ver {
2043#define DRV_VER_NOT_LOADED 0
2044
2045
2046#define DRV_PERS_ETHERNET 0
2047#define DRV_PERS_ISCSI 1
2048#define DRV_PERS_FCOE 2
2049
2050
2051#define MAX_DRV_PERS 3
2052 u32 versions[MAX_DRV_PERS];
2053};
2054
2055struct ncsi_oem_fcoe_features {
2056 u32 fcoe_features1;
2057 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
2058 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
2059
2060 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
2061 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
2062
2063 u32 fcoe_features2;
2064 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
2065 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
2066
2067 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
2068 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
2069
2070 u32 fcoe_features3;
2071 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
2072 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
2073
2074 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
2075 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
2076
2077 u32 fcoe_features4;
2078 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
2079 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
2080};
2081
2082enum curr_cfg_method_e {
2083 CURR_CFG_MET_NONE = 0,
2084 CURR_CFG_MET_OS = 1,
2085 CURR_CFG_MET_VENDOR_SPEC = 2,
2086};
2087
2088#define FC_NPIV_WWPN_SIZE 8
2089#define FC_NPIV_WWNN_SIZE 8
2090struct bdn_npiv_settings {
2091 u8 npiv_wwpn[FC_NPIV_WWPN_SIZE];
2092 u8 npiv_wwnn[FC_NPIV_WWNN_SIZE];
2093};
2094
2095struct bdn_fc_npiv_cfg {
2096
2097 u32 hdr;
2098 u32 num_of_npiv;
2099};
2100
2101#define MAX_NUMBER_NPIV 64
2102struct bdn_fc_npiv_tbl {
2103 struct bdn_fc_npiv_cfg fc_npiv_cfg;
2104 struct bdn_npiv_settings settings[MAX_NUMBER_NPIV];
2105};
2106
2107struct mdump_driver_info {
2108 u32 epoc;
2109 u32 drv_ver;
2110 u32 fw_ver;
2111
2112 u32 valid_dump;
2113 #define FIRST_DUMP_VALID (1 << 0)
2114 #define SECOND_DUMP_VALID (1 << 1)
2115
2116 u32 flags;
2117 #define ENABLE_ALL_TRIGGERS (0x7fffffff)
2118 #define TRIGGER_MDUMP_ONCE (1 << 31)
2119};
2120
2121struct ncsi_oem_data {
2122 u32 driver_version[4];
2123 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2124};
2125
2126struct shmem2_region {
2127
2128 u32 size;
2129
2130 u32 dcc_support;
2131 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2132 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2133 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2134 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2135 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2136 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2137
2138 u32 ext_phy_fw_version2[PORT_MAX];
2139
2140
2141
2142
2143
2144 u32 mf_cfg_addr;
2145 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2146
2147 struct fw_flr_mb flr_mb;
2148 u32 dcbx_lldp_params_offset;
2149 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2150 u32 dcbx_neg_res_offset;
2151 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2152 u32 dcbx_remote_mib_offset;
2153 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2154
2155
2156
2157
2158
2159
2160 u32 other_shmem_base_addr;
2161 u32 other_shmem2_base_addr;
2162
2163
2164
2165
2166 u32 mcp_vf_disabled[E2_VF_MAX / 32];
2167
2168
2169
2170
2171
2172 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32];
2173
2174 u32 dcbx_lldp_dcbx_stat_offset;
2175 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186 u32 edebug_driver_if[2];
2187 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2188 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2189 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2190
2191 u32 nvm_retain_bitmap_addr;
2192
2193
2194 u32 afex_driver_support;
2195 #define SHMEM_AFEX_VERSION_MASK 0x100f
2196 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2197 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2198
2199
2200 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2201
2202
2203
2204
2205 u32 afex_param1_to_driver[E2_FUNC_MAX];
2206 u32 afex_param2_to_driver[E2_FUNC_MAX];
2207
2208 u32 swim_base_addr;
2209 u32 swim_funcs;
2210 u32 swim_main_cb;
2211
2212
2213
2214
2215 u32 afex_profiles_enabled[2];
2216
2217
2218 u32 drv_flags;
2219 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2220 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2221 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2222
2223 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2224 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2225 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2226
2227 u32 extended_dev_info_shared_addr;
2228 u32 ncsi_oem_data_addr;
2229
2230 u32 ocsd_host_addr;
2231 u32 ocbb_host_addr;
2232 u32 ocsd_req_update_interval;
2233 u32 temperature_in_half_celsius;
2234 u32 glob_struct_in_host;
2235
2236 u32 dcbx_neg_res_ext_offset;
2237#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2238
2239 u32 drv_capabilities_flag[E2_FUNC_MAX];
2240#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2241#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2242#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2243#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2244#define DRV_FLAGS_MTU_MASK 0xffff0000
2245#define DRV_FLAGS_MTU_SHIFT 16
2246
2247 u32 extended_dev_info_shared_cfg_size;
2248
2249 u32 dcbx_en[PORT_MAX];
2250
2251
2252 u32 multi_thread_data_offset;
2253
2254
2255 u32 drv_info_host_addr_lo;
2256 u32 drv_info_host_addr_hi;
2257
2258
2259 u32 drv_info_control;
2260#define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2261#define DRV_INFO_CONTROL_VER_SHIFT 0
2262#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2263#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2264 u32 ibft_host_addr;
2265 struct eee_remote_vals eee_remote_vals[PORT_MAX];
2266 u32 reserved[E2_FUNC_MAX];
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283 u32 eee_status[PORT_MAX];
2284 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2285 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2286 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2287 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2288 #define SHMEM_EEE_100M_ADV (1<<0)
2289 #define SHMEM_EEE_1G_ADV (1<<1)
2290 #define SHMEM_EEE_10G_ADV (1<<2)
2291 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2292 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2293 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2294 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2295 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2296 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2297 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2298
2299 u32 sizeof_port_stats;
2300
2301
2302 u32 lfa_host_addr[PORT_MAX];
2303 u32 reserved1;
2304
2305 u32 reserved2;
2306 u32 reserved3;
2307 u32 reserved4;
2308 u32 link_attr_sync[PORT_MAX];
2309 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
2310 #define LINK_ATTR_84858 0x00000002
2311 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
2312 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
2313 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
2314 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
2315 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
2316
2317 u32 reserved5[2];
2318 u32 link_change_count[PORT_MAX];
2319 #define LINK_CHANGE_COUNT_MASK 0xff
2320
2321 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX];
2322
2323
2324 u32 mfw_drv_indication;
2325
2326
2327#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
2328 union {
2329 u8 storage_boot_prog[E2_FUNC_MAX];
2330 #define STORAGE_BOOT_PROG_MASK 0x000000FF
2331 #define STORAGE_BOOT_PROG_NONE 0x00000000
2332 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
2333 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
2334 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
2335 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
2336 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
2337 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
2338 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
2339 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
2340 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
2341
2342 u32 oem_i2c_data_addr;
2343 };
2344
2345
2346
2347
2348
2349
2350 u32 c2s_pcp_map_lower[E2_FUNC_MAX];
2351
2352
2353
2354
2355
2356 u32 c2s_pcp_map_upper[E2_FUNC_MAX];
2357
2358
2359 u32 c2s_pcp_map_default[E2_FUNC_MAX];
2360
2361
2362 u32 fc_npiv_nvram_tbl_addr[PORT_MAX];
2363
2364
2365 enum curr_cfg_method_e curr_cfg;
2366
2367
2368
2369
2370 u32 netproc_fw_ver;
2371
2372
2373 u32 clp_ver;
2374
2375 u32 pcie_bus_num;
2376
2377 u32 sriov_switch_mode;
2378 #define SRIOV_SWITCH_MODE_NONE 0x0
2379 #define SRIOV_SWITCH_MODE_VEB 0x1
2380 #define SRIOV_SWITCH_MODE_VEPA 0x2
2381
2382 u8 rsrv2[E2_FUNC_MAX];
2383
2384 u32 img_inv_table_addr;
2385
2386 u32 mtu_size[E2_FUNC_MAX];
2387
2388 u32 os_driver_state[E2_FUNC_MAX];
2389 #define OS_DRIVER_STATE_NOT_LOADED 0
2390 #define OS_DRIVER_STATE_LOADING 1
2391 #define OS_DRIVER_STATE_DISABLED 2
2392 #define OS_DRIVER_STATE_ACTIVE 3
2393
2394
2395 struct mdump_driver_info drv_info;
2396};
2397
2398
2399struct emac_stats {
2400 u32 rx_stat_ifhcinoctets;
2401 u32 rx_stat_ifhcinbadoctets;
2402 u32 rx_stat_etherstatsfragments;
2403 u32 rx_stat_ifhcinucastpkts;
2404 u32 rx_stat_ifhcinmulticastpkts;
2405 u32 rx_stat_ifhcinbroadcastpkts;
2406 u32 rx_stat_dot3statsfcserrors;
2407 u32 rx_stat_dot3statsalignmenterrors;
2408 u32 rx_stat_dot3statscarriersenseerrors;
2409 u32 rx_stat_xonpauseframesreceived;
2410 u32 rx_stat_xoffpauseframesreceived;
2411 u32 rx_stat_maccontrolframesreceived;
2412 u32 rx_stat_xoffstateentered;
2413 u32 rx_stat_dot3statsframestoolong;
2414 u32 rx_stat_etherstatsjabbers;
2415 u32 rx_stat_etherstatsundersizepkts;
2416 u32 rx_stat_etherstatspkts64octets;
2417 u32 rx_stat_etherstatspkts65octetsto127octets;
2418 u32 rx_stat_etherstatspkts128octetsto255octets;
2419 u32 rx_stat_etherstatspkts256octetsto511octets;
2420 u32 rx_stat_etherstatspkts512octetsto1023octets;
2421 u32 rx_stat_etherstatspkts1024octetsto1522octets;
2422 u32 rx_stat_etherstatspktsover1522octets;
2423
2424 u32 rx_stat_falsecarriererrors;
2425
2426 u32 tx_stat_ifhcoutoctets;
2427 u32 tx_stat_ifhcoutbadoctets;
2428 u32 tx_stat_etherstatscollisions;
2429 u32 tx_stat_outxonsent;
2430 u32 tx_stat_outxoffsent;
2431 u32 tx_stat_flowcontroldone;
2432 u32 tx_stat_dot3statssinglecollisionframes;
2433 u32 tx_stat_dot3statsmultiplecollisionframes;
2434 u32 tx_stat_dot3statsdeferredtransmissions;
2435 u32 tx_stat_dot3statsexcessivecollisions;
2436 u32 tx_stat_dot3statslatecollisions;
2437 u32 tx_stat_ifhcoutucastpkts;
2438 u32 tx_stat_ifhcoutmulticastpkts;
2439 u32 tx_stat_ifhcoutbroadcastpkts;
2440 u32 tx_stat_etherstatspkts64octets;
2441 u32 tx_stat_etherstatspkts65octetsto127octets;
2442 u32 tx_stat_etherstatspkts128octetsto255octets;
2443 u32 tx_stat_etherstatspkts256octetsto511octets;
2444 u32 tx_stat_etherstatspkts512octetsto1023octets;
2445 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2446 u32 tx_stat_etherstatspktsover1522octets;
2447 u32 tx_stat_dot3statsinternalmactransmiterrors;
2448};
2449
2450
2451struct bmac1_stats {
2452 u32 tx_stat_gtpkt_lo;
2453 u32 tx_stat_gtpkt_hi;
2454 u32 tx_stat_gtxpf_lo;
2455 u32 tx_stat_gtxpf_hi;
2456 u32 tx_stat_gtfcs_lo;
2457 u32 tx_stat_gtfcs_hi;
2458 u32 tx_stat_gtmca_lo;
2459 u32 tx_stat_gtmca_hi;
2460 u32 tx_stat_gtbca_lo;
2461 u32 tx_stat_gtbca_hi;
2462 u32 tx_stat_gtfrg_lo;
2463 u32 tx_stat_gtfrg_hi;
2464 u32 tx_stat_gtovr_lo;
2465 u32 tx_stat_gtovr_hi;
2466 u32 tx_stat_gt64_lo;
2467 u32 tx_stat_gt64_hi;
2468 u32 tx_stat_gt127_lo;
2469 u32 tx_stat_gt127_hi;
2470 u32 tx_stat_gt255_lo;
2471 u32 tx_stat_gt255_hi;
2472 u32 tx_stat_gt511_lo;
2473 u32 tx_stat_gt511_hi;
2474 u32 tx_stat_gt1023_lo;
2475 u32 tx_stat_gt1023_hi;
2476 u32 tx_stat_gt1518_lo;
2477 u32 tx_stat_gt1518_hi;
2478 u32 tx_stat_gt2047_lo;
2479 u32 tx_stat_gt2047_hi;
2480 u32 tx_stat_gt4095_lo;
2481 u32 tx_stat_gt4095_hi;
2482 u32 tx_stat_gt9216_lo;
2483 u32 tx_stat_gt9216_hi;
2484 u32 tx_stat_gt16383_lo;
2485 u32 tx_stat_gt16383_hi;
2486 u32 tx_stat_gtmax_lo;
2487 u32 tx_stat_gtmax_hi;
2488 u32 tx_stat_gtufl_lo;
2489 u32 tx_stat_gtufl_hi;
2490 u32 tx_stat_gterr_lo;
2491 u32 tx_stat_gterr_hi;
2492 u32 tx_stat_gtbyt_lo;
2493 u32 tx_stat_gtbyt_hi;
2494
2495 u32 rx_stat_gr64_lo;
2496 u32 rx_stat_gr64_hi;
2497 u32 rx_stat_gr127_lo;
2498 u32 rx_stat_gr127_hi;
2499 u32 rx_stat_gr255_lo;
2500 u32 rx_stat_gr255_hi;
2501 u32 rx_stat_gr511_lo;
2502 u32 rx_stat_gr511_hi;
2503 u32 rx_stat_gr1023_lo;
2504 u32 rx_stat_gr1023_hi;
2505 u32 rx_stat_gr1518_lo;
2506 u32 rx_stat_gr1518_hi;
2507 u32 rx_stat_gr2047_lo;
2508 u32 rx_stat_gr2047_hi;
2509 u32 rx_stat_gr4095_lo;
2510 u32 rx_stat_gr4095_hi;
2511 u32 rx_stat_gr9216_lo;
2512 u32 rx_stat_gr9216_hi;
2513 u32 rx_stat_gr16383_lo;
2514 u32 rx_stat_gr16383_hi;
2515 u32 rx_stat_grmax_lo;
2516 u32 rx_stat_grmax_hi;
2517 u32 rx_stat_grpkt_lo;
2518 u32 rx_stat_grpkt_hi;
2519 u32 rx_stat_grfcs_lo;
2520 u32 rx_stat_grfcs_hi;
2521 u32 rx_stat_grmca_lo;
2522 u32 rx_stat_grmca_hi;
2523 u32 rx_stat_grbca_lo;
2524 u32 rx_stat_grbca_hi;
2525 u32 rx_stat_grxcf_lo;
2526 u32 rx_stat_grxcf_hi;
2527 u32 rx_stat_grxpf_lo;
2528 u32 rx_stat_grxpf_hi;
2529 u32 rx_stat_grxuo_lo;
2530 u32 rx_stat_grxuo_hi;
2531 u32 rx_stat_grjbr_lo;
2532 u32 rx_stat_grjbr_hi;
2533 u32 rx_stat_grovr_lo;
2534 u32 rx_stat_grovr_hi;
2535 u32 rx_stat_grflr_lo;
2536 u32 rx_stat_grflr_hi;
2537 u32 rx_stat_grmeg_lo;
2538 u32 rx_stat_grmeg_hi;
2539 u32 rx_stat_grmeb_lo;
2540 u32 rx_stat_grmeb_hi;
2541 u32 rx_stat_grbyt_lo;
2542 u32 rx_stat_grbyt_hi;
2543 u32 rx_stat_grund_lo;
2544 u32 rx_stat_grund_hi;
2545 u32 rx_stat_grfrg_lo;
2546 u32 rx_stat_grfrg_hi;
2547 u32 rx_stat_grerb_lo;
2548 u32 rx_stat_grerb_hi;
2549 u32 rx_stat_grfre_lo;
2550 u32 rx_stat_grfre_hi;
2551 u32 rx_stat_gripj_lo;
2552 u32 rx_stat_gripj_hi;
2553};
2554
2555struct bmac2_stats {
2556 u32 tx_stat_gtpk_lo;
2557 u32 tx_stat_gtpk_hi;
2558 u32 tx_stat_gtxpf_lo;
2559 u32 tx_stat_gtxpf_hi;
2560 u32 tx_stat_gtpp_lo;
2561 u32 tx_stat_gtpp_hi;
2562 u32 tx_stat_gtfcs_lo;
2563 u32 tx_stat_gtfcs_hi;
2564 u32 tx_stat_gtuca_lo;
2565 u32 tx_stat_gtuca_hi;
2566 u32 tx_stat_gtmca_lo;
2567 u32 tx_stat_gtmca_hi;
2568 u32 tx_stat_gtbca_lo;
2569 u32 tx_stat_gtbca_hi;
2570 u32 tx_stat_gtovr_lo;
2571 u32 tx_stat_gtovr_hi;
2572 u32 tx_stat_gtfrg_lo;
2573 u32 tx_stat_gtfrg_hi;
2574 u32 tx_stat_gtpkt1_lo;
2575 u32 tx_stat_gtpkt1_hi;
2576 u32 tx_stat_gt64_lo;
2577 u32 tx_stat_gt64_hi;
2578 u32 tx_stat_gt127_lo;
2579 u32 tx_stat_gt127_hi;
2580 u32 tx_stat_gt255_lo;
2581 u32 tx_stat_gt255_hi;
2582 u32 tx_stat_gt511_lo;
2583 u32 tx_stat_gt511_hi;
2584 u32 tx_stat_gt1023_lo;
2585 u32 tx_stat_gt1023_hi;
2586 u32 tx_stat_gt1518_lo;
2587 u32 tx_stat_gt1518_hi;
2588 u32 tx_stat_gt2047_lo;
2589 u32 tx_stat_gt2047_hi;
2590 u32 tx_stat_gt4095_lo;
2591 u32 tx_stat_gt4095_hi;
2592 u32 tx_stat_gt9216_lo;
2593 u32 tx_stat_gt9216_hi;
2594 u32 tx_stat_gt16383_lo;
2595 u32 tx_stat_gt16383_hi;
2596 u32 tx_stat_gtmax_lo;
2597 u32 tx_stat_gtmax_hi;
2598 u32 tx_stat_gtufl_lo;
2599 u32 tx_stat_gtufl_hi;
2600 u32 tx_stat_gterr_lo;
2601 u32 tx_stat_gterr_hi;
2602 u32 tx_stat_gtbyt_lo;
2603 u32 tx_stat_gtbyt_hi;
2604
2605 u32 rx_stat_gr64_lo;
2606 u32 rx_stat_gr64_hi;
2607 u32 rx_stat_gr127_lo;
2608 u32 rx_stat_gr127_hi;
2609 u32 rx_stat_gr255_lo;
2610 u32 rx_stat_gr255_hi;
2611 u32 rx_stat_gr511_lo;
2612 u32 rx_stat_gr511_hi;
2613 u32 rx_stat_gr1023_lo;
2614 u32 rx_stat_gr1023_hi;
2615 u32 rx_stat_gr1518_lo;
2616 u32 rx_stat_gr1518_hi;
2617 u32 rx_stat_gr2047_lo;
2618 u32 rx_stat_gr2047_hi;
2619 u32 rx_stat_gr4095_lo;
2620 u32 rx_stat_gr4095_hi;
2621 u32 rx_stat_gr9216_lo;
2622 u32 rx_stat_gr9216_hi;
2623 u32 rx_stat_gr16383_lo;
2624 u32 rx_stat_gr16383_hi;
2625 u32 rx_stat_grmax_lo;
2626 u32 rx_stat_grmax_hi;
2627 u32 rx_stat_grpkt_lo;
2628 u32 rx_stat_grpkt_hi;
2629 u32 rx_stat_grfcs_lo;
2630 u32 rx_stat_grfcs_hi;
2631 u32 rx_stat_gruca_lo;
2632 u32 rx_stat_gruca_hi;
2633 u32 rx_stat_grmca_lo;
2634 u32 rx_stat_grmca_hi;
2635 u32 rx_stat_grbca_lo;
2636 u32 rx_stat_grbca_hi;
2637 u32 rx_stat_grxpf_lo;
2638 u32 rx_stat_grxpf_hi;
2639 u32 rx_stat_grpp_lo;
2640 u32 rx_stat_grpp_hi;
2641 u32 rx_stat_grxuo_lo;
2642 u32 rx_stat_grxuo_hi;
2643 u32 rx_stat_grjbr_lo;
2644 u32 rx_stat_grjbr_hi;
2645 u32 rx_stat_grovr_lo;
2646 u32 rx_stat_grovr_hi;
2647 u32 rx_stat_grxcf_lo;
2648 u32 rx_stat_grxcf_hi;
2649 u32 rx_stat_grflr_lo;
2650 u32 rx_stat_grflr_hi;
2651 u32 rx_stat_grpok_lo;
2652 u32 rx_stat_grpok_hi;
2653 u32 rx_stat_grmeg_lo;
2654 u32 rx_stat_grmeg_hi;
2655 u32 rx_stat_grmeb_lo;
2656 u32 rx_stat_grmeb_hi;
2657 u32 rx_stat_grbyt_lo;
2658 u32 rx_stat_grbyt_hi;
2659 u32 rx_stat_grund_lo;
2660 u32 rx_stat_grund_hi;
2661 u32 rx_stat_grfrg_lo;
2662 u32 rx_stat_grfrg_hi;
2663 u32 rx_stat_grerb_lo;
2664 u32 rx_stat_grerb_hi;
2665 u32 rx_stat_grfre_lo;
2666 u32 rx_stat_grfre_hi;
2667 u32 rx_stat_gripj_lo;
2668 u32 rx_stat_gripj_hi;
2669};
2670
2671struct mstat_stats {
2672 struct {
2673
2674
2675
2676 u32 tx_gtxpok_lo;
2677 u32 tx_gtxpok_hi;
2678 u32 tx_gtxpf_lo;
2679 u32 tx_gtxpf_hi;
2680 u32 tx_gtxpp_lo;
2681 u32 tx_gtxpp_hi;
2682 u32 tx_gtfcs_lo;
2683 u32 tx_gtfcs_hi;
2684 u32 tx_gtuca_lo;
2685 u32 tx_gtuca_hi;
2686 u32 tx_gtmca_lo;
2687 u32 tx_gtmca_hi;
2688 u32 tx_gtgca_lo;
2689 u32 tx_gtgca_hi;
2690 u32 tx_gtpkt_lo;
2691 u32 tx_gtpkt_hi;
2692 u32 tx_gt64_lo;
2693 u32 tx_gt64_hi;
2694 u32 tx_gt127_lo;
2695 u32 tx_gt127_hi;
2696 u32 tx_gt255_lo;
2697 u32 tx_gt255_hi;
2698 u32 tx_gt511_lo;
2699 u32 tx_gt511_hi;
2700 u32 tx_gt1023_lo;
2701 u32 tx_gt1023_hi;
2702 u32 tx_gt1518_lo;
2703 u32 tx_gt1518_hi;
2704 u32 tx_gt2047_lo;
2705 u32 tx_gt2047_hi;
2706 u32 tx_gt4095_lo;
2707 u32 tx_gt4095_hi;
2708 u32 tx_gt9216_lo;
2709 u32 tx_gt9216_hi;
2710 u32 tx_gt16383_lo;
2711 u32 tx_gt16383_hi;
2712 u32 tx_gtufl_lo;
2713 u32 tx_gtufl_hi;
2714 u32 tx_gterr_lo;
2715 u32 tx_gterr_hi;
2716 u32 tx_gtbyt_lo;
2717 u32 tx_gtbyt_hi;
2718 u32 tx_collisions_lo;
2719 u32 tx_collisions_hi;
2720 u32 tx_singlecollision_lo;
2721 u32 tx_singlecollision_hi;
2722 u32 tx_multiplecollisions_lo;
2723 u32 tx_multiplecollisions_hi;
2724 u32 tx_deferred_lo;
2725 u32 tx_deferred_hi;
2726 u32 tx_excessivecollisions_lo;
2727 u32 tx_excessivecollisions_hi;
2728 u32 tx_latecollisions_lo;
2729 u32 tx_latecollisions_hi;
2730 } stats_tx;
2731
2732 struct {
2733 u32 rx_gr64_lo;
2734 u32 rx_gr64_hi;
2735 u32 rx_gr127_lo;
2736 u32 rx_gr127_hi;
2737 u32 rx_gr255_lo;
2738 u32 rx_gr255_hi;
2739 u32 rx_gr511_lo;
2740 u32 rx_gr511_hi;
2741 u32 rx_gr1023_lo;
2742 u32 rx_gr1023_hi;
2743 u32 rx_gr1518_lo;
2744 u32 rx_gr1518_hi;
2745 u32 rx_gr2047_lo;
2746 u32 rx_gr2047_hi;
2747 u32 rx_gr4095_lo;
2748 u32 rx_gr4095_hi;
2749 u32 rx_gr9216_lo;
2750 u32 rx_gr9216_hi;
2751 u32 rx_gr16383_lo;
2752 u32 rx_gr16383_hi;
2753 u32 rx_grpkt_lo;
2754 u32 rx_grpkt_hi;
2755 u32 rx_grfcs_lo;
2756 u32 rx_grfcs_hi;
2757 u32 rx_gruca_lo;
2758 u32 rx_gruca_hi;
2759 u32 rx_grmca_lo;
2760 u32 rx_grmca_hi;
2761 u32 rx_grbca_lo;
2762 u32 rx_grbca_hi;
2763 u32 rx_grxpf_lo;
2764 u32 rx_grxpf_hi;
2765 u32 rx_grxpp_lo;
2766 u32 rx_grxpp_hi;
2767 u32 rx_grxuo_lo;
2768 u32 rx_grxuo_hi;
2769 u32 rx_grovr_lo;
2770 u32 rx_grovr_hi;
2771 u32 rx_grxcf_lo;
2772 u32 rx_grxcf_hi;
2773 u32 rx_grflr_lo;
2774 u32 rx_grflr_hi;
2775 u32 rx_grpok_lo;
2776 u32 rx_grpok_hi;
2777 u32 rx_grbyt_lo;
2778 u32 rx_grbyt_hi;
2779 u32 rx_grund_lo;
2780 u32 rx_grund_hi;
2781 u32 rx_grfrg_lo;
2782 u32 rx_grfrg_hi;
2783 u32 rx_grerb_lo;
2784 u32 rx_grerb_hi;
2785 u32 rx_grfre_lo;
2786 u32 rx_grfre_hi;
2787
2788 u32 rx_alignmenterrors_lo;
2789 u32 rx_alignmenterrors_hi;
2790 u32 rx_falsecarrier_lo;
2791 u32 rx_falsecarrier_hi;
2792 u32 rx_llfcmsgcnt_lo;
2793 u32 rx_llfcmsgcnt_hi;
2794 } stats_rx;
2795};
2796
2797union mac_stats {
2798 struct emac_stats emac_stats;
2799 struct bmac1_stats bmac1_stats;
2800 struct bmac2_stats bmac2_stats;
2801 struct mstat_stats mstat_stats;
2802};
2803
2804
2805struct mac_stx {
2806
2807 u32 rx_stat_ifhcinbadoctets_hi;
2808 u32 rx_stat_ifhcinbadoctets_lo;
2809
2810
2811 u32 tx_stat_ifhcoutbadoctets_hi;
2812 u32 tx_stat_ifhcoutbadoctets_lo;
2813
2814
2815 u32 rx_stat_dot3statsfcserrors_hi;
2816 u32 rx_stat_dot3statsfcserrors_lo;
2817
2818 u32 rx_stat_dot3statsalignmenterrors_hi;
2819 u32 rx_stat_dot3statsalignmenterrors_lo;
2820
2821 u32 rx_stat_dot3statscarriersenseerrors_hi;
2822 u32 rx_stat_dot3statscarriersenseerrors_lo;
2823
2824 u32 rx_stat_falsecarriererrors_hi;
2825 u32 rx_stat_falsecarriererrors_lo;
2826
2827
2828 u32 rx_stat_etherstatsundersizepkts_hi;
2829 u32 rx_stat_etherstatsundersizepkts_lo;
2830
2831 u32 rx_stat_dot3statsframestoolong_hi;
2832 u32 rx_stat_dot3statsframestoolong_lo;
2833
2834
2835 u32 rx_stat_etherstatsfragments_hi;
2836 u32 rx_stat_etherstatsfragments_lo;
2837
2838 u32 rx_stat_etherstatsjabbers_hi;
2839 u32 rx_stat_etherstatsjabbers_lo;
2840
2841
2842 u32 rx_stat_maccontrolframesreceived_hi;
2843 u32 rx_stat_maccontrolframesreceived_lo;
2844 u32 rx_stat_mac_xpf_hi;
2845 u32 rx_stat_mac_xpf_lo;
2846 u32 rx_stat_mac_xcf_hi;
2847 u32 rx_stat_mac_xcf_lo;
2848
2849
2850 u32 rx_stat_xoffstateentered_hi;
2851 u32 rx_stat_xoffstateentered_lo;
2852
2853 u32 rx_stat_xonpauseframesreceived_hi;
2854 u32 rx_stat_xonpauseframesreceived_lo;
2855
2856 u32 rx_stat_xoffpauseframesreceived_hi;
2857 u32 rx_stat_xoffpauseframesreceived_lo;
2858
2859 u32 tx_stat_outxonsent_hi;
2860 u32 tx_stat_outxonsent_lo;
2861
2862 u32 tx_stat_outxoffsent_hi;
2863 u32 tx_stat_outxoffsent_lo;
2864
2865 u32 tx_stat_flowcontroldone_hi;
2866 u32 tx_stat_flowcontroldone_lo;
2867
2868
2869 u32 tx_stat_etherstatscollisions_hi;
2870 u32 tx_stat_etherstatscollisions_lo;
2871
2872 u32 tx_stat_dot3statssinglecollisionframes_hi;
2873 u32 tx_stat_dot3statssinglecollisionframes_lo;
2874
2875 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2876 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2877
2878 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2879 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2880
2881 u32 tx_stat_dot3statsexcessivecollisions_hi;
2882 u32 tx_stat_dot3statsexcessivecollisions_lo;
2883
2884 u32 tx_stat_dot3statslatecollisions_hi;
2885 u32 tx_stat_dot3statslatecollisions_lo;
2886
2887
2888 u32 tx_stat_etherstatspkts64octets_hi;
2889 u32 tx_stat_etherstatspkts64octets_lo;
2890
2891 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2892 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2893
2894 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2895 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2896
2897 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2898 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2899
2900 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2901 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2902
2903 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2904 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2905
2906 u32 tx_stat_etherstatspktsover1522octets_hi;
2907 u32 tx_stat_etherstatspktsover1522octets_lo;
2908 u32 tx_stat_mac_2047_hi;
2909 u32 tx_stat_mac_2047_lo;
2910 u32 tx_stat_mac_4095_hi;
2911 u32 tx_stat_mac_4095_lo;
2912 u32 tx_stat_mac_9216_hi;
2913 u32 tx_stat_mac_9216_lo;
2914 u32 tx_stat_mac_16383_hi;
2915 u32 tx_stat_mac_16383_lo;
2916
2917
2918 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2919 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2920
2921
2922 u32 tx_stat_mac_ufl_hi;
2923 u32 tx_stat_mac_ufl_lo;
2924};
2925
2926
2927#define MAC_STX_IDX_MAX 2
2928
2929struct host_port_stats {
2930 u32 host_port_stats_counter;
2931
2932 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2933
2934 u32 brb_drop_hi;
2935 u32 brb_drop_lo;
2936
2937 u32 not_used;
2938 u32 pfc_frames_tx_hi;
2939 u32 pfc_frames_tx_lo;
2940 u32 pfc_frames_rx_hi;
2941 u32 pfc_frames_rx_lo;
2942
2943 u32 eee_lpi_count_hi;
2944 u32 eee_lpi_count_lo;
2945};
2946
2947
2948struct host_func_stats {
2949 u32 host_func_stats_start;
2950
2951 u32 total_bytes_received_hi;
2952 u32 total_bytes_received_lo;
2953
2954 u32 total_bytes_transmitted_hi;
2955 u32 total_bytes_transmitted_lo;
2956
2957 u32 total_unicast_packets_received_hi;
2958 u32 total_unicast_packets_received_lo;
2959
2960 u32 total_multicast_packets_received_hi;
2961 u32 total_multicast_packets_received_lo;
2962
2963 u32 total_broadcast_packets_received_hi;
2964 u32 total_broadcast_packets_received_lo;
2965
2966 u32 total_unicast_packets_transmitted_hi;
2967 u32 total_unicast_packets_transmitted_lo;
2968
2969 u32 total_multicast_packets_transmitted_hi;
2970 u32 total_multicast_packets_transmitted_lo;
2971
2972 u32 total_broadcast_packets_transmitted_hi;
2973 u32 total_broadcast_packets_transmitted_lo;
2974
2975 u32 valid_bytes_received_hi;
2976 u32 valid_bytes_received_lo;
2977
2978 u32 host_func_stats_end;
2979};
2980
2981
2982#define VICSTATST_UIF_INDEX 2
2983
2984
2985
2986
2987
2988
2989struct afex_stats {
2990 u32 tx_unicast_frames_hi;
2991 u32 tx_unicast_frames_lo;
2992 u32 tx_unicast_bytes_hi;
2993 u32 tx_unicast_bytes_lo;
2994 u32 tx_multicast_frames_hi;
2995 u32 tx_multicast_frames_lo;
2996 u32 tx_multicast_bytes_hi;
2997 u32 tx_multicast_bytes_lo;
2998 u32 tx_broadcast_frames_hi;
2999 u32 tx_broadcast_frames_lo;
3000 u32 tx_broadcast_bytes_hi;
3001 u32 tx_broadcast_bytes_lo;
3002 u32 tx_frames_discarded_hi;
3003 u32 tx_frames_discarded_lo;
3004 u32 tx_frames_dropped_hi;
3005 u32 tx_frames_dropped_lo;
3006
3007 u32 rx_unicast_frames_hi;
3008 u32 rx_unicast_frames_lo;
3009 u32 rx_unicast_bytes_hi;
3010 u32 rx_unicast_bytes_lo;
3011 u32 rx_multicast_frames_hi;
3012 u32 rx_multicast_frames_lo;
3013 u32 rx_multicast_bytes_hi;
3014 u32 rx_multicast_bytes_lo;
3015 u32 rx_broadcast_frames_hi;
3016 u32 rx_broadcast_frames_lo;
3017 u32 rx_broadcast_bytes_hi;
3018 u32 rx_broadcast_bytes_lo;
3019 u32 rx_frames_discarded_hi;
3020 u32 rx_frames_discarded_lo;
3021 u32 rx_frames_dropped_hi;
3022 u32 rx_frames_dropped_lo;
3023};
3024
3025#define BCM_5710_FW_MAJOR_VERSION 7
3026#define BCM_5710_FW_MINOR_VERSION 13
3027#define BCM_5710_FW_REVISION_VERSION 15
3028#define BCM_5710_FW_ENGINEERING_VERSION 0
3029#define BCM_5710_FW_COMPILE_FLAGS 1
3030
3031
3032
3033
3034
3035struct atten_sp_status_block {
3036 __le32 attn_bits;
3037 __le32 attn_bits_ack;
3038 u8 status_block_id;
3039 u8 reserved0;
3040 __le16 attn_bits_index;
3041 __le32 reserved1;
3042};
3043
3044
3045
3046
3047
3048struct cstorm_eth_ag_context {
3049 u32 __reserved0[10];
3050};
3051
3052
3053
3054
3055
3056struct dmae_command {
3057 u32 opcode;
3058#define DMAE_COMMAND_SRC (0x1<<0)
3059#define DMAE_COMMAND_SRC_SHIFT 0
3060#define DMAE_COMMAND_DST (0x3<<1)
3061#define DMAE_COMMAND_DST_SHIFT 1
3062#define DMAE_COMMAND_C_DST (0x1<<3)
3063#define DMAE_COMMAND_C_DST_SHIFT 3
3064#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
3065#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
3066#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
3067#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
3068#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
3069#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
3070#define DMAE_COMMAND_ENDIANITY (0x3<<9)
3071#define DMAE_COMMAND_ENDIANITY_SHIFT 9
3072#define DMAE_COMMAND_PORT (0x1<<11)
3073#define DMAE_COMMAND_PORT_SHIFT 11
3074#define DMAE_COMMAND_CRC_RESET (0x1<<12)
3075#define DMAE_COMMAND_CRC_RESET_SHIFT 12
3076#define DMAE_COMMAND_SRC_RESET (0x1<<13)
3077#define DMAE_COMMAND_SRC_RESET_SHIFT 13
3078#define DMAE_COMMAND_DST_RESET (0x1<<14)
3079#define DMAE_COMMAND_DST_RESET_SHIFT 14
3080#define DMAE_COMMAND_E1HVN (0x3<<15)
3081#define DMAE_COMMAND_E1HVN_SHIFT 15
3082#define DMAE_COMMAND_DST_VN (0x3<<17)
3083#define DMAE_COMMAND_DST_VN_SHIFT 17
3084#define DMAE_COMMAND_C_FUNC (0x1<<19)
3085#define DMAE_COMMAND_C_FUNC_SHIFT 19
3086#define DMAE_COMMAND_ERR_POLICY (0x3<<20)
3087#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
3088#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
3089#define DMAE_COMMAND_RESERVED0_SHIFT 22
3090 u32 src_addr_lo;
3091 u32 src_addr_hi;
3092 u32 dst_addr_lo;
3093 u32 dst_addr_hi;
3094#if defined(__BIG_ENDIAN)
3095 u16 opcode_iov;
3096#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
3097#define DMAE_COMMAND_SRC_VFID_SHIFT 0
3098#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
3099#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
3100#define DMAE_COMMAND_RESERVED1 (0x1<<7)
3101#define DMAE_COMMAND_RESERVED1_SHIFT 7
3102#define DMAE_COMMAND_DST_VFID (0x3F<<8)
3103#define DMAE_COMMAND_DST_VFID_SHIFT 8
3104#define DMAE_COMMAND_DST_VFPF (0x1<<14)
3105#define DMAE_COMMAND_DST_VFPF_SHIFT 14
3106#define DMAE_COMMAND_RESERVED2 (0x1<<15)
3107#define DMAE_COMMAND_RESERVED2_SHIFT 15
3108 u16 len;
3109#elif defined(__LITTLE_ENDIAN)
3110 u16 len;
3111 u16 opcode_iov;
3112#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
3113#define DMAE_COMMAND_SRC_VFID_SHIFT 0
3114#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
3115#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
3116#define DMAE_COMMAND_RESERVED1 (0x1<<7)
3117#define DMAE_COMMAND_RESERVED1_SHIFT 7
3118#define DMAE_COMMAND_DST_VFID (0x3F<<8)
3119#define DMAE_COMMAND_DST_VFID_SHIFT 8
3120#define DMAE_COMMAND_DST_VFPF (0x1<<14)
3121#define DMAE_COMMAND_DST_VFPF_SHIFT 14
3122#define DMAE_COMMAND_RESERVED2 (0x1<<15)
3123#define DMAE_COMMAND_RESERVED2_SHIFT 15
3124#endif
3125 u32 comp_addr_lo;
3126 u32 comp_addr_hi;
3127 u32 comp_val;
3128 u32 crc32;
3129 u32 crc32_c;
3130#if defined(__BIG_ENDIAN)
3131 u16 crc16_c;
3132 u16 crc16;
3133#elif defined(__LITTLE_ENDIAN)
3134 u16 crc16;
3135 u16 crc16_c;
3136#endif
3137#if defined(__BIG_ENDIAN)
3138 u16 reserved3;
3139 u16 crc_t10;
3140#elif defined(__LITTLE_ENDIAN)
3141 u16 crc_t10;
3142 u16 reserved3;
3143#endif
3144#if defined(__BIG_ENDIAN)
3145 u16 xsum8;
3146 u16 xsum16;
3147#elif defined(__LITTLE_ENDIAN)
3148 u16 xsum16;
3149 u16 xsum8;
3150#endif
3151};
3152
3153
3154
3155
3156
3157struct doorbell_hdr {
3158 u8 header;
3159#define DOORBELL_HDR_RX (0x1<<0)
3160#define DOORBELL_HDR_RX_SHIFT 0
3161#define DOORBELL_HDR_DB_TYPE (0x1<<1)
3162#define DOORBELL_HDR_DB_TYPE_SHIFT 1
3163#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
3164#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
3165#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
3166#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
3167};
3168
3169
3170
3171
3172struct eth_tx_doorbell {
3173#if defined(__BIG_ENDIAN)
3174 u16 npackets;
3175 u8 params;
3176#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3177#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3178#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3179#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3180#define ETH_TX_DOORBELL_SPARE (0x1<<7)
3181#define ETH_TX_DOORBELL_SPARE_SHIFT 7
3182 struct doorbell_hdr hdr;
3183#elif defined(__LITTLE_ENDIAN)
3184 struct doorbell_hdr hdr;
3185 u8 params;
3186#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3187#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3188#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3189#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3190#define ETH_TX_DOORBELL_SPARE (0x1<<7)
3191#define ETH_TX_DOORBELL_SPARE_SHIFT 7
3192 u16 npackets;
3193#endif
3194};
3195
3196
3197
3198
3199
3200struct hc_status_block_e1x {
3201 __le16 index_values[HC_SB_MAX_INDICES_E1X];
3202 __le16 running_index[HC_SB_MAX_SM];
3203 __le32 rsrv[11];
3204};
3205
3206
3207
3208
3209struct host_hc_status_block_e1x {
3210 struct hc_status_block_e1x sb;
3211};
3212
3213
3214
3215
3216
3217struct hc_status_block_e2 {
3218 __le16 index_values[HC_SB_MAX_INDICES_E2];
3219 __le16 running_index[HC_SB_MAX_SM];
3220 __le32 reserved[11];
3221};
3222
3223
3224
3225
3226struct host_hc_status_block_e2 {
3227 struct hc_status_block_e2 sb;
3228};
3229
3230
3231
3232
3233
3234struct hc_sp_status_block {
3235 __le16 index_values[HC_SP_SB_MAX_INDICES];
3236 __le16 running_index;
3237 __le16 rsrv;
3238 u32 rsrv1;
3239};
3240
3241
3242
3243
3244struct host_sp_status_block {
3245 struct atten_sp_status_block atten_status_block;
3246 struct hc_sp_status_block sp_sb;
3247};
3248
3249
3250
3251
3252
3253struct igu_ack_register {
3254#if defined(__BIG_ENDIAN)
3255 u16 sb_id_and_flags;
3256#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3257#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3258#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3259#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3260#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3261#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3262#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3263#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3264#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3265#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3266 u16 status_block_index;
3267#elif defined(__LITTLE_ENDIAN)
3268 u16 status_block_index;
3269 u16 sb_id_and_flags;
3270#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3271#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3272#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3273#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3274#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3275#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3276#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3277#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3278#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3279#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3280#endif
3281};
3282
3283
3284
3285
3286
3287struct igu_backward_compatible {
3288 u32 sb_id_and_flags;
3289#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3290#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3291#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3292#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3293#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3294#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3295#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3296#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3297#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3298#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3299#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3300#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3301 u32 reserved_2;
3302};
3303
3304
3305
3306
3307
3308struct igu_regular {
3309 u32 sb_id_and_flags;
3310#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3311#define IGU_REGULAR_SB_INDEX_SHIFT 0
3312#define IGU_REGULAR_RESERVED0 (0x1<<20)
3313#define IGU_REGULAR_RESERVED0_SHIFT 20
3314#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3315#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3316#define IGU_REGULAR_BUPDATE (0x1<<24)
3317#define IGU_REGULAR_BUPDATE_SHIFT 24
3318#define IGU_REGULAR_ENABLE_INT (0x3<<25)
3319#define IGU_REGULAR_ENABLE_INT_SHIFT 25
3320#define IGU_REGULAR_RESERVED_1 (0x1<<27)
3321#define IGU_REGULAR_RESERVED_1_SHIFT 27
3322#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3323#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3324#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3325#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3326#define IGU_REGULAR_BCLEANUP (0x1<<31)
3327#define IGU_REGULAR_BCLEANUP_SHIFT 31
3328 u32 reserved_2;
3329};
3330
3331
3332
3333
3334union igu_consprod_reg {
3335 struct igu_regular regular;
3336 struct igu_backward_compatible backward_compatible;
3337};
3338
3339
3340
3341
3342
3343enum igu_ctrl_cmd {
3344 IGU_CTRL_CMD_TYPE_RD,
3345 IGU_CTRL_CMD_TYPE_WR,
3346 MAX_IGU_CTRL_CMD
3347};
3348
3349
3350
3351
3352
3353struct igu_ctrl_reg {
3354 u32 ctrl_data;
3355#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3356#define IGU_CTRL_REG_ADDRESS_SHIFT 0
3357#define IGU_CTRL_REG_FID (0x7F<<12)
3358#define IGU_CTRL_REG_FID_SHIFT 12
3359#define IGU_CTRL_REG_RESERVED (0x1<<19)
3360#define IGU_CTRL_REG_RESERVED_SHIFT 19
3361#define IGU_CTRL_REG_TYPE (0x1<<20)
3362#define IGU_CTRL_REG_TYPE_SHIFT 20
3363#define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3364#define IGU_CTRL_REG_UNUSED_SHIFT 21
3365};
3366
3367
3368
3369
3370
3371enum igu_int_cmd {
3372 IGU_INT_ENABLE,
3373 IGU_INT_DISABLE,
3374 IGU_INT_NOP,
3375 IGU_INT_NOP2,
3376 MAX_IGU_INT_CMD
3377};
3378
3379
3380
3381
3382
3383enum igu_seg_access {
3384 IGU_SEG_ACCESS_NORM,
3385 IGU_SEG_ACCESS_DEF,
3386 IGU_SEG_ACCESS_ATTN,
3387 MAX_IGU_SEG_ACCESS
3388};
3389
3390
3391
3392
3393
3394struct parsing_flags {
3395 __le16 flags;
3396#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3397#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3398#define PARSING_FLAGS_VLAN (0x1<<1)
3399#define PARSING_FLAGS_VLAN_SHIFT 1
3400#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3401#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3402#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3403#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3404#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3405#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3406#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3407#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3408#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3409#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3410#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3411#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3412#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3413#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3414#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3415#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3416#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3417#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3418#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3419#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3420#define PARSING_FLAGS_RESERVED0 (0x3<<14)
3421#define PARSING_FLAGS_RESERVED0_SHIFT 14
3422};
3423
3424
3425
3426
3427
3428enum prs_flags_ack_type {
3429 PRS_FLAG_PUREACK_PIGGY,
3430 PRS_FLAG_PUREACK_PURE,
3431 MAX_PRS_FLAGS_ACK_TYPE
3432};
3433
3434
3435
3436
3437
3438enum prs_flags_eth_addr_type {
3439 PRS_FLAG_ETHTYPE_NON_UNICAST,
3440 PRS_FLAG_ETHTYPE_UNICAST,
3441 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3442};
3443
3444
3445
3446
3447
3448enum prs_flags_over_eth {
3449 PRS_FLAG_OVERETH_UNKNOWN,
3450 PRS_FLAG_OVERETH_IPV4,
3451 PRS_FLAG_OVERETH_IPV6,
3452 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3453 MAX_PRS_FLAGS_OVER_ETH
3454};
3455
3456
3457
3458
3459
3460enum prs_flags_over_ip {
3461 PRS_FLAG_OVERIP_UNKNOWN,
3462 PRS_FLAG_OVERIP_TCP,
3463 PRS_FLAG_OVERIP_UDP,
3464 MAX_PRS_FLAGS_OVER_IP
3465};
3466
3467
3468
3469
3470
3471struct sdm_op_gen {
3472 __le32 command;
3473#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3474#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3475#define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3476#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3477#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3478#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3479#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3480#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3481#define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3482#define SDM_OP_GEN_RESERVED_SHIFT 17
3483};
3484
3485
3486
3487
3488
3489struct timers_block_context {
3490 u32 __reserved_0;
3491 u32 __reserved_1;
3492 u32 __reserved_2;
3493 u32 flags;
3494#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3495#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3496#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3497#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3498#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3499#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3500};
3501
3502
3503
3504
3505
3506struct tstorm_eth_ag_context {
3507 u32 __reserved0[14];
3508};
3509
3510
3511
3512
3513
3514struct ustorm_eth_ag_context {
3515 u32 __reserved0;
3516#if defined(__BIG_ENDIAN)
3517 u8 cdu_usage;
3518 u8 __reserved2;
3519 u16 __reserved1;
3520#elif defined(__LITTLE_ENDIAN)
3521 u16 __reserved1;
3522 u8 __reserved2;
3523 u8 cdu_usage;
3524#endif
3525 u32 __reserved3[6];
3526};
3527
3528
3529
3530
3531
3532struct xstorm_eth_ag_context {
3533 u32 reserved0;
3534#if defined(__BIG_ENDIAN)
3535 u8 cdu_reserved;
3536 u8 reserved2;
3537 u16 reserved1;
3538#elif defined(__LITTLE_ENDIAN)
3539 u16 reserved1;
3540 u8 reserved2;
3541 u8 cdu_reserved;
3542#endif
3543 u32 reserved3[30];
3544};
3545
3546
3547
3548
3549
3550struct doorbell {
3551#if defined(__BIG_ENDIAN)
3552 u16 zero_fill2;
3553 u8 zero_fill1;
3554 struct doorbell_hdr header;
3555#elif defined(__LITTLE_ENDIAN)
3556 struct doorbell_hdr header;
3557 u8 zero_fill1;
3558 u16 zero_fill2;
3559#endif
3560};
3561
3562
3563
3564
3565
3566struct doorbell_set_prod {
3567#if defined(__BIG_ENDIAN)
3568 u16 prod;
3569 u8 zero_fill1;
3570 struct doorbell_hdr header;
3571#elif defined(__LITTLE_ENDIAN)
3572 struct doorbell_hdr header;
3573 u8 zero_fill1;
3574 u16 prod;
3575#endif
3576};
3577
3578
3579struct regpair {
3580 __le32 lo;
3581 __le32 hi;
3582};
3583
3584struct regpair_native {
3585 u32 lo;
3586 u32 hi;
3587};
3588
3589
3590
3591
3592enum classify_rule {
3593 CLASSIFY_RULE_OPCODE_MAC,
3594 CLASSIFY_RULE_OPCODE_VLAN,
3595 CLASSIFY_RULE_OPCODE_PAIR,
3596 CLASSIFY_RULE_OPCODE_IMAC_VNI,
3597 MAX_CLASSIFY_RULE
3598};
3599
3600
3601
3602
3603
3604enum classify_rule_action_type {
3605 CLASSIFY_RULE_REMOVE,
3606 CLASSIFY_RULE_ADD,
3607 MAX_CLASSIFY_RULE_ACTION_TYPE
3608};
3609
3610
3611
3612
3613
3614struct client_init_general_data {
3615 u8 client_id;
3616 u8 statistics_counter_id;
3617 u8 statistics_en_flg;
3618 u8 is_fcoe_flg;
3619 u8 activate_flg;
3620 u8 sp_client_id;
3621 __le16 mtu;
3622 u8 statistics_zero_flg;
3623 u8 func_id;
3624 u8 cos;
3625 u8 traffic_type;
3626 u8 fp_hsi_ver;
3627 u8 reserved0[3];
3628};
3629
3630
3631
3632
3633
3634struct client_init_rx_data {
3635 u8 tpa_en;
3636#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3637#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3638#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3639#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3640#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3641#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3642#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE (0x1<<3)
3643#define CLIENT_INIT_RX_DATA_TPA_OVER_VLAN_DISABLE_SHIFT 3
3644#define CLIENT_INIT_RX_DATA_RESERVED5 (0xF<<4)
3645#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 4
3646 u8 vmqueue_mode_en_flg;
3647 u8 extra_data_over_sgl_en_flg;
3648 u8 cache_line_alignment_log_size;
3649 u8 enable_dynamic_hc;
3650 u8 max_sges_for_packet;
3651 u8 client_qzone_id;
3652 u8 drop_ip_cs_err_flg;
3653 u8 drop_tcp_cs_err_flg;
3654 u8 drop_ttl0_flg;
3655 u8 drop_udp_cs_err_flg;
3656 u8 inner_vlan_removal_enable_flg;
3657 u8 outer_vlan_removal_enable_flg;
3658 u8 status_block_id;
3659 u8 rx_sb_index_number;
3660 u8 dont_verify_rings_pause_thr_flg;
3661 u8 max_tpa_queues;
3662 u8 silent_vlan_removal_flg;
3663 __le16 max_bytes_on_bd;
3664 __le16 sge_buff_size;
3665 u8 approx_mcast_engine_id;
3666 u8 rss_engine_id;
3667 struct regpair bd_page_base;
3668 struct regpair sge_page_base;
3669 struct regpair cqe_page_base;
3670 u8 is_leading_rss;
3671 u8 is_approx_mcast;
3672 __le16 max_agg_size;
3673 __le16 state;
3674#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3675#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3676#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3677#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3678#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3679#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3680#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3681#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3682#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3683#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3684#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3685#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3686#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3687#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3688#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3689#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3690 __le16 cqe_pause_thr_low;
3691 __le16 cqe_pause_thr_high;
3692 __le16 bd_pause_thr_low;
3693 __le16 bd_pause_thr_high;
3694 __le16 sge_pause_thr_low;
3695 __le16 sge_pause_thr_high;
3696 __le16 rx_cos_mask;
3697 __le16 silent_vlan_value;
3698 __le16 silent_vlan_mask;
3699 u8 handle_ptp_pkts_flg;
3700 u8 reserved6[3];
3701 __le32 reserved7;
3702};
3703
3704
3705
3706
3707struct client_init_tx_data {
3708 u8 enforce_security_flg;
3709 u8 tx_status_block_id;
3710 u8 tx_sb_index_number;
3711 u8 tss_leading_client_id;
3712 u8 tx_switching_flg;
3713 u8 anti_spoofing_flg;
3714 __le16 default_vlan;
3715 struct regpair tx_bd_page_base;
3716 __le16 state;
3717#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3718#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3719#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3720#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3721#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3722#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3723#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3724#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3725#define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
3726#define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
3727 u8 default_vlan_flg;
3728 u8 force_default_pri_flg;
3729 u8 tunnel_lso_inc_ip_id;
3730 u8 refuse_outband_vlan_flg;
3731 u8 tunnel_non_lso_pcsum_location;
3732 u8 tunnel_non_lso_outer_ip_csum_location;
3733};
3734
3735
3736
3737
3738struct client_init_ramrod_data {
3739 struct client_init_general_data general;
3740 struct client_init_rx_data rx;
3741 struct client_init_tx_data tx;
3742};
3743
3744
3745
3746
3747
3748struct client_update_ramrod_data {
3749 u8 client_id;
3750 u8 func_id;
3751 u8 inner_vlan_removal_enable_flg;
3752 u8 inner_vlan_removal_change_flg;
3753 u8 outer_vlan_removal_enable_flg;
3754 u8 outer_vlan_removal_change_flg;
3755 u8 anti_spoofing_enable_flg;
3756 u8 anti_spoofing_change_flg;
3757 u8 activate_flg;
3758 u8 activate_change_flg;
3759 __le16 default_vlan;
3760 u8 default_vlan_enable_flg;
3761 u8 default_vlan_change_flg;
3762 __le16 silent_vlan_value;
3763 __le16 silent_vlan_mask;
3764 u8 silent_vlan_removal_flg;
3765 u8 silent_vlan_change_flg;
3766 u8 refuse_outband_vlan_flg;
3767 u8 refuse_outband_vlan_change_flg;
3768 u8 tx_switching_flg;
3769 u8 tx_switching_change_flg;
3770 u8 handle_ptp_pkts_flg;
3771 u8 handle_ptp_pkts_change_flg;
3772 __le16 reserved1;
3773 __le32 echo;
3774};
3775
3776
3777
3778
3779
3780struct cstorm_eth_st_context {
3781 u32 __reserved0[4];
3782};
3783
3784
3785struct double_regpair {
3786 u32 regpair0_lo;
3787 u32 regpair0_hi;
3788 u32 regpair1_lo;
3789 u32 regpair1_hi;
3790};
3791
3792
3793enum eth_2nd_parse_bd_type {
3794 ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
3795 MAX_ETH_2ND_PARSE_BD_TYPE
3796};
3797
3798
3799
3800
3801enum eth_addr_type {
3802 UNKNOWN_ADDRESS,
3803 UNICAST_ADDRESS,
3804 MULTICAST_ADDRESS,
3805 BROADCAST_ADDRESS,
3806 MAX_ETH_ADDR_TYPE
3807};
3808
3809
3810
3811
3812
3813struct eth_classify_cmd_header {
3814 u8 cmd_general_data;
3815#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3816#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3817#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3818#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3819#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3820#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3821#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3822#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3823#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3824#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3825 u8 func_id;
3826 u8 client_id;
3827 u8 reserved1;
3828};
3829
3830
3831
3832
3833
3834struct eth_classify_header {
3835 u8 rule_cnt;
3836 u8 warning_on_error;
3837 __le16 reserved1;
3838 __le32 echo;
3839};
3840
3841
3842
3843
3844struct eth_classify_imac_vni_cmd {
3845 struct eth_classify_cmd_header header;
3846 __le32 vni;
3847 __le16 imac_lsb;
3848 __le16 imac_mid;
3849 __le16 imac_msb;
3850 __le16 reserved1;
3851};
3852
3853
3854
3855
3856struct eth_classify_mac_cmd {
3857 struct eth_classify_cmd_header header;
3858 __le16 reserved0;
3859 __le16 inner_mac;
3860 __le16 mac_lsb;
3861 __le16 mac_mid;
3862 __le16 mac_msb;
3863 __le16 reserved1;
3864};
3865
3866
3867
3868
3869
3870struct eth_classify_pair_cmd {
3871 struct eth_classify_cmd_header header;
3872 __le16 reserved0;
3873 __le16 inner_mac;
3874 __le16 mac_lsb;
3875 __le16 mac_mid;
3876 __le16 mac_msb;
3877 __le16 vlan;
3878};
3879
3880
3881
3882
3883
3884struct eth_classify_vlan_cmd {
3885 struct eth_classify_cmd_header header;
3886 __le32 reserved0;
3887 __le32 reserved1;
3888 __le16 reserved2;
3889 __le16 vlan;
3890};
3891
3892
3893
3894
3895
3896
3897
3898
3899union eth_classify_rule_cmd {
3900 struct eth_classify_mac_cmd mac;
3901 struct eth_classify_vlan_cmd vlan;
3902 struct eth_classify_pair_cmd pair;
3903 struct eth_classify_imac_vni_cmd imac_vni;
3904};
3905
3906
3907
3908
3909struct eth_classify_rules_ramrod_data {
3910 struct eth_classify_header header;
3911 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3912};
3913
3914
3915
3916
3917
3918struct eth_common_ramrod_data {
3919 __le32 client_id;
3920 __le32 reserved1;
3921};
3922
3923
3924
3925
3926
3927struct ustorm_eth_st_context {
3928 u32 reserved0[52];
3929};
3930
3931
3932
3933
3934struct tstorm_eth_st_context {
3935 u32 __reserved0[28];
3936};
3937
3938
3939
3940
3941struct xstorm_eth_st_context {
3942 u32 reserved0[60];
3943};
3944
3945
3946
3947
3948struct eth_context {
3949 struct ustorm_eth_st_context ustorm_st_context;
3950 struct tstorm_eth_st_context tstorm_st_context;
3951 struct xstorm_eth_ag_context xstorm_ag_context;
3952 struct tstorm_eth_ag_context tstorm_ag_context;
3953 struct cstorm_eth_ag_context cstorm_ag_context;
3954 struct ustorm_eth_ag_context ustorm_ag_context;
3955 struct timers_block_context timers_context;
3956 struct xstorm_eth_st_context xstorm_st_context;
3957 struct cstorm_eth_st_context cstorm_st_context;
3958};
3959
3960
3961
3962
3963
3964union eth_sgl_or_raw_data {
3965 __le16 sgl[8];
3966 u32 raw_data[4];
3967};
3968
3969
3970
3971
3972struct eth_end_agg_rx_cqe {
3973 u8 type_error_flags;
3974#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3975#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3976#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3977#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3978#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3979#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3980 u8 reserved1;
3981 u8 queue_index;
3982 u8 reserved2;
3983 __le32 timestamp_delta;
3984 __le16 num_of_coalesced_segs;
3985 __le16 pkt_len;
3986 u8 pure_ack_count;
3987 u8 reserved3;
3988 __le16 reserved4;
3989 union eth_sgl_or_raw_data sgl_or_raw_data;
3990 __le32 reserved5[8];
3991};
3992
3993
3994
3995
3996
3997struct eth_fast_path_rx_cqe {
3998 u8 type_error_flags;
3999#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
4000#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
4001#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
4002#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
4003#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
4004#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
4005#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
4006#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
4007#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
4008#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
4009#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
4010#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
4011#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
4012#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
4013 u8 status_flags;
4014#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
4015#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
4016#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
4017#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
4018#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
4019#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
4020#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
4021#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
4022#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
4023#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
4024#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
4025#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
4026 u8 queue_index;
4027 u8 placement_offset;
4028 __le32 rss_hash_result;
4029 __le16 vlan_tag;
4030 __le16 pkt_len_or_gro_seg_len;
4031 __le16 len_on_bd;
4032 struct parsing_flags pars_flags;
4033 union eth_sgl_or_raw_data sgl_or_raw_data;
4034 u8 tunn_type;
4035 u8 tunn_inner_hdrs_offset;
4036 __le16 reserved1;
4037 __le32 tunn_tenant_id;
4038 __le32 padding[5];
4039 u32 marker;
4040};
4041
4042
4043
4044
4045
4046struct eth_filter_rules_cmd {
4047 u8 cmd_general_data;
4048#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
4049#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
4050#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
4051#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
4052#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
4053#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
4054 u8 func_id;
4055 u8 client_id;
4056 u8 reserved1;
4057 __le16 state;
4058#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
4059#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
4060#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
4061#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
4062#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
4063#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
4064#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
4065#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
4066#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
4067#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
4068#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
4069#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
4070#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
4071#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
4072#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
4073#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
4074 __le16 reserved3;
4075 struct regpair reserved4;
4076};
4077
4078
4079
4080
4081
4082struct eth_filter_rules_ramrod_data {
4083 struct eth_classify_header header;
4084 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
4085};
4086
4087
4088enum eth_fp_hsi_ver {
4089 ETH_FP_HSI_VER_0,
4090 ETH_FP_HSI_VER_1,
4091 ETH_FP_HSI_VER_2,
4092 MAX_ETH_FP_HSI_VER
4093};
4094
4095
4096
4097
4098struct eth_general_rules_ramrod_data {
4099 struct eth_classify_header header;
4100 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
4101};
4102
4103
4104
4105
4106
4107struct eth_halt_ramrod_data {
4108 __le32 client_id;
4109 __le32 reserved0;
4110};
4111
4112
4113
4114
4115
4116struct eth_mac_addresses {
4117#if defined(__BIG_ENDIAN)
4118 __le16 dst_mid;
4119 __le16 dst_lo;
4120#elif defined(__LITTLE_ENDIAN)
4121 __le16 dst_lo;
4122 __le16 dst_mid;
4123#endif
4124#if defined(__BIG_ENDIAN)
4125 __le16 src_lo;
4126 __le16 dst_hi;
4127#elif defined(__LITTLE_ENDIAN)
4128 __le16 dst_hi;
4129 __le16 src_lo;
4130#endif
4131#if defined(__BIG_ENDIAN)
4132 __le16 src_hi;
4133 __le16 src_mid;
4134#elif defined(__LITTLE_ENDIAN)
4135 __le16 src_mid;
4136 __le16 src_hi;
4137#endif
4138};
4139
4140
4141struct eth_tunnel_data {
4142 __le16 dst_lo;
4143 __le16 dst_mid;
4144 __le16 dst_hi;
4145 __le16 fw_ip_hdr_csum;
4146 __le16 pseudo_csum;
4147 u8 ip_hdr_start_inner_w;
4148 u8 flags;
4149#define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0)
4150#define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
4151#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
4152#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
4153};
4154
4155
4156
4157
4158union eth_mac_addr_or_tunnel_data {
4159 struct eth_mac_addresses mac_addr;
4160 struct eth_tunnel_data tunnel_data;
4161};
4162
4163
4164struct eth_multicast_rules_cmd {
4165 u8 cmd_general_data;
4166#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
4167#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
4168#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
4169#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
4170#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
4171#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
4172#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
4173#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
4174 u8 func_id;
4175 u8 bin_id;
4176 u8 engine_id;
4177 __le32 reserved2;
4178 struct regpair reserved3;
4179};
4180
4181
4182
4183
4184struct eth_multicast_rules_ramrod_data {
4185 struct eth_classify_header header;
4186 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
4187};
4188
4189
4190
4191
4192struct ramrod_data {
4193 __le32 data_lo;
4194 __le32 data_hi;
4195};
4196
4197
4198
4199
4200union eth_ramrod_data {
4201 struct ramrod_data general;
4202};
4203
4204
4205
4206
4207
4208enum eth_rss_hash_type {
4209 DEFAULT_HASH_TYPE,
4210 IPV4_HASH_TYPE,
4211 TCP_IPV4_HASH_TYPE,
4212 IPV6_HASH_TYPE,
4213 TCP_IPV6_HASH_TYPE,
4214 VLAN_PRI_HASH_TYPE,
4215 E1HOV_PRI_HASH_TYPE,
4216 DSCP_HASH_TYPE,
4217 MAX_ETH_RSS_HASH_TYPE
4218};
4219
4220
4221
4222
4223
4224enum eth_rss_mode {
4225 ETH_RSS_MODE_DISABLED,
4226 ETH_RSS_MODE_REGULAR,
4227 ETH_RSS_MODE_VLAN_PRI,
4228 ETH_RSS_MODE_E1HOV_PRI,
4229 ETH_RSS_MODE_IP_DSCP,
4230 MAX_ETH_RSS_MODE
4231};
4232
4233
4234
4235
4236
4237struct eth_rss_update_ramrod_data {
4238 u8 rss_engine_id;
4239 u8 rss_mode;
4240 __le16 capabilities;
4241#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
4242#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4243#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
4244#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
4245#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
4246#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
4247#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
4248#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
4249#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
4250#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
4251#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
4252#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
4253#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
4254#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
4255#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
4256#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
4257#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8)
4258#define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
4259#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9)
4260#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
4261#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10)
4262#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
4263 u8 rss_result_mask;
4264 u8 reserved3;
4265 __le16 reserved4;
4266 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
4267 __le32 rss_key[T_ETH_RSS_KEY];
4268 __le32 echo;
4269 __le32 reserved5;
4270};
4271
4272
4273
4274
4275
4276struct eth_rx_bd {
4277 __le32 addr_lo;
4278 __le32 addr_hi;
4279};
4280
4281
4282
4283
4284
4285struct common_ramrod_eth_rx_cqe {
4286 u8 ramrod_type;
4287#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4288#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4289#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4290#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4291#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4292#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4293 u8 conn_type;
4294 __le16 reserved1;
4295 __le32 conn_and_cmd_data;
4296#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4297#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4298#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4299#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4300 struct ramrod_data protocol_data;
4301 __le32 echo;
4302 __le32 reserved2[11];
4303};
4304
4305
4306
4307
4308struct eth_rx_cqe_next_page {
4309 __le32 addr_lo;
4310 __le32 addr_hi;
4311 __le32 reserved[14];
4312};
4313
4314
4315
4316
4317union eth_rx_cqe {
4318 struct eth_fast_path_rx_cqe fast_path_cqe;
4319 struct common_ramrod_eth_rx_cqe ramrod_cqe;
4320 struct eth_rx_cqe_next_page next_page_cqe;
4321 struct eth_end_agg_rx_cqe end_agg_cqe;
4322};
4323
4324
4325
4326
4327
4328enum eth_rx_cqe_type {
4329 RX_ETH_CQE_TYPE_ETH_FASTPATH,
4330 RX_ETH_CQE_TYPE_ETH_RAMROD,
4331 RX_ETH_CQE_TYPE_ETH_START_AGG,
4332 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4333 MAX_ETH_RX_CQE_TYPE
4334};
4335
4336
4337
4338
4339
4340enum eth_rx_fp_sel {
4341 ETH_FP_CQE_REGULAR,
4342 ETH_FP_CQE_RAW,
4343 MAX_ETH_RX_FP_SEL
4344};
4345
4346
4347
4348
4349
4350struct eth_rx_sge {
4351 __le32 addr_lo;
4352 __le32 addr_hi;
4353};
4354
4355
4356
4357
4358
4359struct spe_hdr {
4360 __le32 conn_and_cmd_data;
4361#define SPE_HDR_CID (0xFFFFFF<<0)
4362#define SPE_HDR_CID_SHIFT 0
4363#define SPE_HDR_CMD_ID (0xFF<<24)
4364#define SPE_HDR_CMD_ID_SHIFT 24
4365 __le16 type;
4366#define SPE_HDR_CONN_TYPE (0xFF<<0)
4367#define SPE_HDR_CONN_TYPE_SHIFT 0
4368#define SPE_HDR_FUNCTION_ID (0xFF<<8)
4369#define SPE_HDR_FUNCTION_ID_SHIFT 8
4370 __le16 reserved1;
4371};
4372
4373
4374
4375
4376union eth_specific_data {
4377 u8 protocol_data[8];
4378 struct regpair client_update_ramrod_data;
4379 struct regpair client_init_ramrod_init_data;
4380 struct eth_halt_ramrod_data halt_ramrod_data;
4381 struct regpair update_data_addr;
4382 struct eth_common_ramrod_data common_ramrod_data;
4383 struct regpair classify_cfg_addr;
4384 struct regpair filter_cfg_addr;
4385 struct regpair mcast_cfg_addr;
4386};
4387
4388
4389
4390
4391struct eth_spe {
4392 struct spe_hdr hdr;
4393 union eth_specific_data data;
4394};
4395
4396
4397
4398
4399
4400enum eth_spqe_cmd_id {
4401 RAMROD_CMD_ID_ETH_UNUSED,
4402 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4403 RAMROD_CMD_ID_ETH_HALT,
4404 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4405 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4406 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4407 RAMROD_CMD_ID_ETH_EMPTY,
4408 RAMROD_CMD_ID_ETH_TERMINATE,
4409 RAMROD_CMD_ID_ETH_TPA_UPDATE,
4410 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4411 RAMROD_CMD_ID_ETH_FILTER_RULES,
4412 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4413 RAMROD_CMD_ID_ETH_RSS_UPDATE,
4414 RAMROD_CMD_ID_ETH_SET_MAC,
4415 MAX_ETH_SPQE_CMD_ID
4416};
4417
4418
4419
4420
4421
4422enum eth_tpa_update_command {
4423 TPA_UPDATE_NONE_COMMAND,
4424 TPA_UPDATE_ENABLE_COMMAND,
4425 TPA_UPDATE_DISABLE_COMMAND,
4426 MAX_ETH_TPA_UPDATE_COMMAND
4427};
4428
4429
4430
4431
4432enum eth_tunnel_lso_inc_ip_id {
4433 EXT_HEADER,
4434 INT_HEADER,
4435 MAX_ETH_TUNNEL_LSO_INC_IP_ID
4436};
4437
4438
4439
4440
4441enum eth_tunnel_non_lso_csum_location {
4442 CSUM_ON_PKT,
4443 CSUM_ON_BD,
4444 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
4445};
4446
4447enum eth_tunn_type {
4448 TUNN_TYPE_NONE,
4449 TUNN_TYPE_VXLAN,
4450 TUNN_TYPE_L2_GRE,
4451 TUNN_TYPE_IPV4_GRE,
4452 TUNN_TYPE_IPV6_GRE,
4453 TUNN_TYPE_L2_GENEVE,
4454 TUNN_TYPE_IPV4_GENEVE,
4455 TUNN_TYPE_IPV6_GENEVE,
4456 MAX_ETH_TUNN_TYPE
4457};
4458
4459
4460
4461
4462struct eth_tx_bd {
4463 __le32 addr_lo;
4464 __le32 addr_hi;
4465 __le16 total_pkt_bytes;
4466 __le16 nbytes;
4467 u8 reserved[4];
4468};
4469
4470
4471
4472
4473
4474struct eth_tx_bd_flags {
4475 u8 as_bitfield;
4476#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4477#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4478#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4479#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4480#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4481#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4482#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4483#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4484#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4485#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4486#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4487#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4488#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4489#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4490};
4491
4492
4493
4494
4495struct eth_tx_start_bd {
4496 __le32 addr_lo;
4497 __le32 addr_hi;
4498 __le16 nbd;
4499 __le16 nbytes;
4500 __le16 vlan_or_ethertype;
4501 struct eth_tx_bd_flags bd_flags;
4502 u8 general_data;
4503#define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
4504#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4505#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
4506#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
4507#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4508#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4509#define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4510#define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4511#define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
4512#define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
4513};
4514
4515
4516
4517
4518struct eth_tx_parse_bd_e1x {
4519 __le16 global_data;
4520#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4521#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4522#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4523#define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4524#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4525#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4526#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4527#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4528#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4529#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4530#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4531#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4532 u8 tcp_flags;
4533#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4534#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4535#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4536#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4537#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4538#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4539#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4540#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4541#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4542#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4543#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4544#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4545#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4546#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4547#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4548#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4549 u8 ip_hlen_w;
4550 __le16 total_hlen_w;
4551 __le16 tcp_pseudo_csum;
4552 __le16 lso_mss;
4553 __le16 ip_id;
4554 __le32 tcp_send_seq;
4555};
4556
4557
4558
4559
4560struct eth_tx_parse_bd_e2 {
4561 union eth_mac_addr_or_tunnel_data data;
4562 __le32 parsing_data;
4563#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
4564#define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4565#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4566#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4567#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4568#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4569#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4570#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4571#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4572#define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4573};
4574
4575
4576
4577
4578struct eth_tx_parse_2nd_bd {
4579 __le16 global_data;
4580#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
4581#define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4582#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
4583#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
4584#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
4585#define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
4586#define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
4587#define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
4588#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
4589#define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
4590#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
4591#define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
4592#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
4593#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
4594 u8 bd_type;
4595#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
4596#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
4597#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
4598#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
4599 u8 reserved3;
4600 u8 tcp_flags;
4601#define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
4602#define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4603#define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
4604#define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
4605#define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
4606#define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
4607#define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
4608#define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
4609#define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
4610#define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
4611#define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
4612#define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
4613#define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
4614#define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
4615#define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
4616#define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
4617 u8 reserved4;
4618 u8 tunnel_udp_hdr_start_w;
4619 u8 fw_ip_hdr_to_payload_w;
4620 __le16 fw_ip_csum_wo_len_flags_frag;
4621 __le16 hw_ip_id;
4622 __le32 tcp_send_seq;
4623};
4624
4625
4626struct eth_tx_next_bd {
4627 __le32 addr_lo;
4628 __le32 addr_hi;
4629 u8 reserved[8];
4630};
4631
4632
4633
4634
4635union eth_tx_bd_types {
4636 struct eth_tx_start_bd start_bd;
4637 struct eth_tx_bd reg_bd;
4638 struct eth_tx_parse_bd_e1x parse_bd_e1x;
4639 struct eth_tx_parse_bd_e2 parse_bd_e2;
4640 struct eth_tx_parse_2nd_bd parse_2nd_bd;
4641 struct eth_tx_next_bd next_bd;
4642};
4643
4644
4645
4646
4647struct eth_tx_bds_array {
4648 union eth_tx_bd_types bds[13];
4649};
4650
4651
4652
4653
4654
4655enum eth_tx_vlan_type {
4656 X_ETH_NO_VLAN,
4657 X_ETH_OUTBAND_VLAN,
4658 X_ETH_INBAND_VLAN,
4659 X_ETH_FW_ADDED_VLAN,
4660 MAX_ETH_TX_VLAN_TYPE
4661};
4662
4663
4664
4665
4666
4667enum eth_vlan_filter_mode {
4668 ETH_VLAN_FILTER_ANY_VLAN,
4669 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4670 ETH_VLAN_FILTER_CLASSIFY,
4671 MAX_ETH_VLAN_FILTER_MODE
4672};
4673
4674
4675
4676
4677
4678struct mac_configuration_hdr {
4679 u8 length;
4680 u8 offset;
4681 __le16 client_id;
4682 __le32 echo;
4683};
4684
4685
4686
4687
4688struct mac_configuration_entry {
4689 __le16 lsb_mac_addr;
4690 __le16 middle_mac_addr;
4691 __le16 msb_mac_addr;
4692 __le16 vlan_id;
4693 u8 pf_id;
4694 u8 flags;
4695#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4696#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4697#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4698#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4699#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4700#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4701#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4702#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4703#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4704#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4705#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4706#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4707 __le16 reserved0;
4708 __le32 clients_bit_vector;
4709};
4710
4711
4712
4713
4714struct mac_configuration_cmd {
4715 struct mac_configuration_hdr hdr;
4716 struct mac_configuration_entry config_table[64];
4717};
4718
4719
4720
4721
4722
4723enum set_mac_action_type {
4724 T_ETH_MAC_COMMAND_INVALIDATE,
4725 T_ETH_MAC_COMMAND_SET,
4726 MAX_SET_MAC_ACTION_TYPE
4727};
4728
4729
4730
4731
4732
4733enum tpa_mode {
4734 TPA_LRO,
4735 TPA_GRO,
4736 MAX_TPA_MODE};
4737
4738
4739
4740
4741
4742struct tpa_update_ramrod_data {
4743 u8 update_ipv4;
4744 u8 update_ipv6;
4745 u8 client_id;
4746 u8 max_tpa_queues;
4747 u8 max_sges_for_packet;
4748 u8 complete_on_both_clients;
4749 u8 dont_verify_rings_pause_thr_flg;
4750 u8 tpa_mode;
4751 __le16 sge_buff_size;
4752 __le16 max_agg_size;
4753 __le32 sge_page_base_lo;
4754 __le32 sge_page_base_hi;
4755 __le16 sge_pause_thr_low;
4756 __le16 sge_pause_thr_high;
4757 u8 tpa_over_vlan_disable;
4758 u8 reserved[7];
4759};
4760
4761
4762
4763
4764
4765struct tstorm_eth_approximate_match_multicast_filtering {
4766 u32 mcast_add_hash_bit_array[8];
4767};
4768
4769
4770
4771
4772
4773struct tstorm_eth_function_common_config {
4774 __le16 config_flags;
4775#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4776#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4777#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4778#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4779#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4780#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4781#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4782#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4783#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4784#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4785#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4786#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4787#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4788#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4789 u8 rss_result_mask;
4790 u8 reserved1;
4791 __le16 vlan_id[2];
4792};
4793
4794
4795
4796
4797
4798struct tstorm_eth_mac_filter_config {
4799 u32 ucast_drop_all;
4800 u32 ucast_accept_all;
4801 u32 mcast_drop_all;
4802 u32 mcast_accept_all;
4803 u32 bcast_accept_all;
4804 u32 vlan_filter[2];
4805 u32 unmatched_unicast;
4806};
4807
4808
4809
4810
4811
4812struct tx_queue_init_ramrod_data {
4813 struct client_init_general_data general;
4814 struct client_init_tx_data tx;
4815};
4816
4817
4818
4819
4820
4821struct ustorm_eth_rx_producers {
4822#if defined(__BIG_ENDIAN)
4823 u16 bd_prod;
4824 u16 cqe_prod;
4825#elif defined(__LITTLE_ENDIAN)
4826 u16 cqe_prod;
4827 u16 bd_prod;
4828#endif
4829#if defined(__BIG_ENDIAN)
4830 u16 reserved;
4831 u16 sge_prod;
4832#elif defined(__LITTLE_ENDIAN)
4833 u16 sge_prod;
4834 u16 reserved;
4835#endif
4836};
4837
4838
4839
4840
4841
4842struct fcoe_rx_stat_params_section0 {
4843 __le32 fcoe_rx_pkt_cnt;
4844 __le32 fcoe_rx_byte_cnt;
4845};
4846
4847
4848
4849
4850
4851struct fcoe_rx_stat_params_section1 {
4852 __le32 fcoe_ver_cnt;
4853 __le32 fcoe_rx_drop_pkt_cnt;
4854};
4855
4856
4857
4858
4859
4860struct fcoe_rx_stat_params_section2 {
4861 __le32 fc_crc_cnt;
4862 __le32 eofa_del_cnt;
4863 __le32 miss_frame_cnt;
4864 __le32 seq_timeout_cnt;
4865 __le32 drop_seq_cnt;
4866 __le32 fcoe_rx_drop_pkt_cnt;
4867 __le32 fcp_rx_pkt_cnt;
4868 __le32 reserved0;
4869};
4870
4871
4872
4873
4874
4875struct fcoe_tx_stat_params {
4876 __le32 fcoe_tx_pkt_cnt;
4877 __le32 fcoe_tx_byte_cnt;
4878 __le32 fcp_tx_pkt_cnt;
4879 __le32 reserved0;
4880};
4881
4882
4883
4884
4885struct fcoe_statistics_params {
4886 struct fcoe_tx_stat_params tx_stat;
4887 struct fcoe_rx_stat_params_section0 rx_stat0;
4888 struct fcoe_rx_stat_params_section1 rx_stat1;
4889 struct fcoe_rx_stat_params_section2 rx_stat2;
4890};
4891
4892
4893
4894
4895
4896struct afex_vif_list_ramrod_data {
4897 u8 afex_vif_list_command;
4898 u8 func_bit_map;
4899 __le16 vif_list_index;
4900 u8 func_to_clear;
4901 u8 echo;
4902 __le16 reserved1;
4903};
4904
4905struct c2s_pri_trans_table_entry {
4906 u8 val[MAX_VLAN_PRIORITIES];
4907};
4908
4909
4910
4911
4912struct cfc_del_event_data {
4913 __le32 cid;
4914 __le32 reserved0;
4915 __le32 reserved1;
4916};
4917
4918
4919
4920
4921
4922struct cmng_flags_per_port {
4923 u32 cmng_enables;
4924#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4925#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4926#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4927#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4928#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4929#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4930#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4931#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4932#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4933#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4934 u32 __reserved1;
4935};
4936
4937
4938
4939
4940
4941struct rate_shaping_vars_per_port {
4942 u32 rs_periodic_timeout;
4943 u32 rs_threshold;
4944};
4945
4946
4947
4948
4949struct fairness_vars_per_port {
4950 u32 upper_bound;
4951 u32 fair_threshold;
4952 u32 fairness_timeout;
4953 u32 size_thr;
4954};
4955
4956
4957
4958
4959struct safc_struct_per_port {
4960#if defined(__BIG_ENDIAN)
4961 u16 __reserved1;
4962 u8 __reserved0;
4963 u8 safc_timeout_usec;
4964#elif defined(__LITTLE_ENDIAN)
4965 u8 safc_timeout_usec;
4966 u8 __reserved0;
4967 u16 __reserved1;
4968#endif
4969 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4970 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4971};
4972
4973
4974
4975
4976struct cmng_struct_per_port {
4977 struct rate_shaping_vars_per_port rs_vars;
4978 struct fairness_vars_per_port fair_vars;
4979 struct safc_struct_per_port safc_vars;
4980 struct cmng_flags_per_port flags;
4981};
4982
4983
4984
4985
4986struct rate_shaping_counter {
4987 u32 quota;
4988#if defined(__BIG_ENDIAN)
4989 u16 __reserved0;
4990 u16 rate;
4991#elif defined(__LITTLE_ENDIAN)
4992 u16 rate;
4993 u16 __reserved0;
4994#endif
4995};
4996
4997
4998
4999
5000struct rate_shaping_vars_per_vn {
5001 struct rate_shaping_counter vn_counter;
5002};
5003
5004
5005
5006
5007struct fairness_vars_per_vn {
5008 u32 cos_credit_delta[MAX_COS_NUMBER];
5009 u32 vn_credit_delta;
5010 u32 __reserved0;
5011};
5012
5013
5014
5015
5016struct cmng_vnic {
5017 struct rate_shaping_vars_per_vn vnic_max_rate[4];
5018 struct fairness_vars_per_vn vnic_min_rate[4];
5019};
5020
5021
5022
5023
5024struct cmng_init {
5025 struct cmng_struct_per_port port;
5026 struct cmng_vnic vnic;
5027};
5028
5029
5030
5031
5032
5033struct cmng_init_input {
5034 u32 port_rate;
5035 u16 vnic_min_rate[4];
5036 u16 vnic_max_rate[4];
5037 u16 cos_min_rate[MAX_COS_NUMBER];
5038 u16 cos_to_pause_mask[MAX_COS_NUMBER];
5039 struct cmng_flags_per_port flags;
5040};
5041
5042
5043
5044
5045
5046enum common_spqe_cmd_id {
5047 RAMROD_CMD_ID_COMMON_UNUSED,
5048 RAMROD_CMD_ID_COMMON_FUNCTION_START,
5049 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
5050 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
5051 RAMROD_CMD_ID_COMMON_CFC_DEL,
5052 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
5053 RAMROD_CMD_ID_COMMON_STAT_QUERY,
5054 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
5055 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
5056 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
5057 RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
5058 MAX_COMMON_SPQE_CMD_ID
5059};
5060
5061
5062
5063
5064enum connection_type {
5065 ETH_CONNECTION_TYPE,
5066 TOE_CONNECTION_TYPE,
5067 RDMA_CONNECTION_TYPE,
5068 ISCSI_CONNECTION_TYPE,
5069 FCOE_CONNECTION_TYPE,
5070 RESERVED_CONNECTION_TYPE_0,
5071 RESERVED_CONNECTION_TYPE_1,
5072 RESERVED_CONNECTION_TYPE_2,
5073 NONE_CONNECTION_TYPE,
5074 MAX_CONNECTION_TYPE
5075};
5076
5077
5078
5079
5080
5081enum cos_mode {
5082 OVERRIDE_COS,
5083 STATIC_COS,
5084 FW_WRR,
5085 MAX_COS_MODE
5086};
5087
5088
5089
5090
5091
5092struct hc_dynamic_drv_counter {
5093 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
5094};
5095
5096
5097
5098
5099struct cstorm_queue_zone_data {
5100 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
5101 struct regpair reserved[2];
5102};
5103
5104
5105
5106
5107
5108struct vf_pf_channel_zone_data {
5109 u32 msg_addr_lo;
5110 u32 msg_addr_hi;
5111};
5112
5113
5114
5115
5116struct non_trigger_vf_zone {
5117 struct vf_pf_channel_zone_data vf_pf_channel;
5118};
5119
5120
5121
5122
5123struct vf_pf_channel_zone_trigger {
5124 u8 addr_valid;
5125};
5126
5127
5128
5129
5130struct trigger_vf_zone {
5131 struct vf_pf_channel_zone_trigger vf_pf_channel;
5132 u8 reserved0;
5133 u16 reserved1;
5134 u32 reserved2;
5135};
5136
5137
5138
5139
5140struct cstorm_vf_zone_data {
5141 struct non_trigger_vf_zone non_trigger;
5142 struct trigger_vf_zone trigger;
5143};
5144
5145
5146
5147
5148
5149struct dynamic_hc_sm_config {
5150 u32 threshold[3];
5151 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
5152 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
5153 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
5154 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
5155 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
5156};
5157
5158
5159
5160
5161struct dynamic_hc_config {
5162 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
5163};
5164
5165
5166struct e2_integ_data {
5167#if defined(__BIG_ENDIAN)
5168 u8 flags;
5169#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5170#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5171#define E2_INTEG_DATA_LB_TX (0x1<<1)
5172#define E2_INTEG_DATA_LB_TX_SHIFT 1
5173#define E2_INTEG_DATA_COS_TX (0x1<<2)
5174#define E2_INTEG_DATA_COS_TX_SHIFT 2
5175#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5176#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5177#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5178#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5179#define E2_INTEG_DATA_RESERVED (0x7<<5)
5180#define E2_INTEG_DATA_RESERVED_SHIFT 5
5181 u8 cos;
5182 u8 voq;
5183 u8 pbf_queue;
5184#elif defined(__LITTLE_ENDIAN)
5185 u8 pbf_queue;
5186 u8 voq;
5187 u8 cos;
5188 u8 flags;
5189#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
5190#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
5191#define E2_INTEG_DATA_LB_TX (0x1<<1)
5192#define E2_INTEG_DATA_LB_TX_SHIFT 1
5193#define E2_INTEG_DATA_COS_TX (0x1<<2)
5194#define E2_INTEG_DATA_COS_TX_SHIFT 2
5195#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
5196#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
5197#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
5198#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
5199#define E2_INTEG_DATA_RESERVED (0x7<<5)
5200#define E2_INTEG_DATA_RESERVED_SHIFT 5
5201#endif
5202#if defined(__BIG_ENDIAN)
5203 u16 reserved3;
5204 u8 reserved2;
5205 u8 ramEn;
5206#elif defined(__LITTLE_ENDIAN)
5207 u8 ramEn;
5208 u8 reserved2;
5209 u16 reserved3;
5210#endif
5211};
5212
5213
5214
5215
5216
5217struct eth_event_data {
5218 __le32 echo;
5219 __le32 reserved0;
5220 __le32 reserved1;
5221};
5222
5223
5224
5225
5226
5227struct vf_pf_event_data {
5228 u8 vf_id;
5229 u8 reserved0;
5230 __le16 reserved1;
5231 __le32 msg_addr_lo;
5232 __le32 msg_addr_hi;
5233};
5234
5235
5236
5237
5238struct vf_flr_event_data {
5239 u8 vf_id;
5240 u8 reserved0;
5241 __le16 reserved1;
5242 __le32 reserved2;
5243 __le32 reserved3;
5244};
5245
5246
5247
5248
5249struct malicious_vf_event_data {
5250 u8 vf_id;
5251 u8 err_id;
5252 __le16 reserved1;
5253 __le32 reserved2;
5254 __le32 reserved3;
5255};
5256
5257
5258
5259
5260struct vif_list_event_data {
5261 u8 func_bit_map;
5262 u8 echo;
5263 __le16 reserved0;
5264 __le32 reserved1;
5265 __le32 reserved2;
5266};
5267
5268
5269struct function_update_event_data {
5270 u8 echo;
5271 u8 reserved;
5272 __le16 reserved0;
5273 __le32 reserved1;
5274 __le32 reserved2;
5275};
5276
5277
5278
5279union event_data {
5280 struct vf_pf_event_data vf_pf_event;
5281 struct eth_event_data eth_event;
5282 struct cfc_del_event_data cfc_del_event;
5283 struct vf_flr_event_data vf_flr_event;
5284 struct malicious_vf_event_data malicious_vf_event;
5285 struct vif_list_event_data vif_list_event;
5286 struct function_update_event_data function_update_event;
5287};
5288
5289
5290
5291
5292
5293struct event_ring_data {
5294 struct regpair_native base_addr;
5295#if defined(__BIG_ENDIAN)
5296 u8 index_id;
5297 u8 sb_id;
5298 u16 producer;
5299#elif defined(__LITTLE_ENDIAN)
5300 u16 producer;
5301 u8 sb_id;
5302 u8 index_id;
5303#endif
5304 u32 reserved0;
5305};
5306
5307
5308
5309
5310
5311struct event_ring_msg {
5312 u8 opcode;
5313 u8 error;
5314 u16 reserved1;
5315 union event_data data;
5316};
5317
5318
5319
5320
5321struct event_ring_next {
5322 struct regpair addr;
5323 u32 reserved[2];
5324};
5325
5326
5327
5328
5329union event_ring_elem {
5330 struct event_ring_msg message;
5331 struct event_ring_next next_page;
5332};
5333
5334
5335
5336
5337
5338enum event_ring_opcode {
5339 EVENT_RING_OPCODE_VF_PF_CHANNEL,
5340 EVENT_RING_OPCODE_FUNCTION_START,
5341 EVENT_RING_OPCODE_FUNCTION_STOP,
5342 EVENT_RING_OPCODE_CFC_DEL,
5343 EVENT_RING_OPCODE_CFC_DEL_WB,
5344 EVENT_RING_OPCODE_STAT_QUERY,
5345 EVENT_RING_OPCODE_STOP_TRAFFIC,
5346 EVENT_RING_OPCODE_START_TRAFFIC,
5347 EVENT_RING_OPCODE_VF_FLR,
5348 EVENT_RING_OPCODE_MALICIOUS_VF,
5349 EVENT_RING_OPCODE_FORWARD_SETUP,
5350 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
5351 EVENT_RING_OPCODE_FUNCTION_UPDATE,
5352 EVENT_RING_OPCODE_AFEX_VIF_LISTS,
5353 EVENT_RING_OPCODE_SET_MAC,
5354 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
5355 EVENT_RING_OPCODE_FILTERS_RULES,
5356 EVENT_RING_OPCODE_MULTICAST_RULES,
5357 EVENT_RING_OPCODE_SET_TIMESYNC,
5358 MAX_EVENT_RING_OPCODE
5359};
5360
5361
5362
5363
5364enum fairness_mode {
5365 FAIRNESS_COS_WRR_MODE,
5366 FAIRNESS_COS_ETS_MODE,
5367 MAX_FAIRNESS_MODE
5368};
5369
5370
5371
5372
5373
5374struct priority_cos {
5375 u8 priority;
5376 u8 cos;
5377 __le16 reserved1;
5378};
5379
5380
5381
5382
5383struct flow_control_configuration {
5384 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5385 u8 dcb_enabled;
5386 u8 dcb_version;
5387 u8 dont_add_pri_0_en;
5388 u8 reserved1;
5389 __le32 reserved2;
5390 u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
5391};
5392
5393
5394
5395
5396
5397struct function_start_data {
5398 u8 function_mode;
5399 u8 allow_npar_tx_switching;
5400 __le16 sd_vlan_tag;
5401 __le16 vif_id;
5402 u8 path_id;
5403 u8 network_cos_mode;
5404 u8 dmae_cmd_id;
5405 u8 no_added_tags;
5406 __le16 reserved0;
5407 __le32 reserved1;
5408 u8 inner_clss_vxlan;
5409 u8 inner_clss_l2gre;
5410 u8 inner_clss_l2geneve;
5411 u8 inner_rss;
5412 __le16 vxlan_dst_port;
5413 __le16 geneve_dst_port;
5414 u8 sd_accept_mf_clss_fail;
5415 u8 sd_accept_mf_clss_fail_match_ethtype;
5416 __le16 sd_accept_mf_clss_fail_ethtype;
5417 __le16 sd_vlan_eth_type;
5418 u8 sd_vlan_force_pri_flg;
5419 u8 sd_vlan_force_pri_val;
5420 u8 c2s_pri_tt_valid;
5421 u8 c2s_pri_default;
5422 u8 tx_vlan_filtering_enable;
5423 u8 tx_vlan_filtering_use_pvid;
5424 u8 reserved2[4];
5425 struct c2s_pri_trans_table_entry c2s_pri_trans_table;
5426};
5427
5428struct function_update_data {
5429 u8 vif_id_change_flg;
5430 u8 afex_default_vlan_change_flg;
5431 u8 allowed_priorities_change_flg;
5432 u8 network_cos_mode_change_flg;
5433 __le16 vif_id;
5434 __le16 afex_default_vlan;
5435 u8 allowed_priorities;
5436 u8 network_cos_mode;
5437 u8 lb_mode_en_change_flg;
5438 u8 lb_mode_en;
5439 u8 tx_switch_suspend_change_flg;
5440 u8 tx_switch_suspend;
5441 u8 echo;
5442 u8 update_tunn_cfg_flg;
5443 u8 inner_clss_vxlan;
5444 u8 inner_clss_l2gre;
5445 u8 inner_clss_l2geneve;
5446 u8 inner_rss;
5447 __le16 vxlan_dst_port;
5448 __le16 geneve_dst_port;
5449 u8 sd_vlan_force_pri_change_flg;
5450 u8 sd_vlan_force_pri_flg;
5451 u8 sd_vlan_force_pri_val;
5452 u8 sd_vlan_tag_change_flg;
5453 u8 sd_vlan_eth_type_change_flg;
5454 u8 reserved1;
5455 __le16 sd_vlan_tag;
5456 __le16 sd_vlan_eth_type;
5457 u8 tx_vlan_filtering_pvid_change_flg;
5458 u8 reserved0;
5459 __le32 reserved2;
5460};
5461
5462
5463
5464
5465struct fw_version {
5466#if defined(__BIG_ENDIAN)
5467 u8 engineering;
5468 u8 revision;
5469 u8 minor;
5470 u8 major;
5471#elif defined(__LITTLE_ENDIAN)
5472 u8 major;
5473 u8 minor;
5474 u8 revision;
5475 u8 engineering;
5476#endif
5477 u32 flags;
5478#define FW_VERSION_OPTIMIZED (0x1<<0)
5479#define FW_VERSION_OPTIMIZED_SHIFT 0
5480#define FW_VERSION_BIG_ENDIEN (0x1<<1)
5481#define FW_VERSION_BIG_ENDIEN_SHIFT 1
5482#define FW_VERSION_CHIP_VERSION (0x3<<2)
5483#define FW_VERSION_CHIP_VERSION_SHIFT 2
5484#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5485#define __FW_VERSION_RESERVED_SHIFT 4
5486};
5487
5488
5489
5490
5491struct hc_dynamic_sb_drv_counters {
5492 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5493};
5494
5495
5496
5497
5498
5499struct hc_index_data {
5500#if defined(__BIG_ENDIAN)
5501 u8 flags;
5502#define HC_INDEX_DATA_SM_ID (0x1<<0)
5503#define HC_INDEX_DATA_SM_ID_SHIFT 0
5504#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5505#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5506#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5507#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5508#define HC_INDEX_DATA_RESERVE (0x1F<<3)
5509#define HC_INDEX_DATA_RESERVE_SHIFT 3
5510 u8 timeout;
5511#elif defined(__LITTLE_ENDIAN)
5512 u8 timeout;
5513 u8 flags;
5514#define HC_INDEX_DATA_SM_ID (0x1<<0)
5515#define HC_INDEX_DATA_SM_ID_SHIFT 0
5516#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5517#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5518#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5519#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5520#define HC_INDEX_DATA_RESERVE (0x1F<<3)
5521#define HC_INDEX_DATA_RESERVE_SHIFT 3
5522#endif
5523};
5524
5525
5526
5527
5528
5529struct hc_status_block_sm {
5530#if defined(__BIG_ENDIAN)
5531 u8 igu_seg_id;
5532 u8 igu_sb_id;
5533 u8 timer_value;
5534 u8 __flags;
5535#elif defined(__LITTLE_ENDIAN)
5536 u8 __flags;
5537 u8 timer_value;
5538 u8 igu_sb_id;
5539 u8 igu_seg_id;
5540#endif
5541 u32 time_to_expire;
5542};
5543
5544
5545
5546
5547struct pci_entity {
5548#if defined(__BIG_ENDIAN)
5549 u8 vf_valid;
5550 u8 vf_id;
5551 u8 vnic_id;
5552 u8 pf_id;
5553#elif defined(__LITTLE_ENDIAN)
5554 u8 pf_id;
5555 u8 vnic_id;
5556 u8 vf_id;
5557 u8 vf_valid;
5558#endif
5559};
5560
5561
5562
5563
5564struct hc_sb_data {
5565 struct regpair_native host_sb_addr;
5566 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5567 struct pci_entity p_func;
5568#if defined(__BIG_ENDIAN)
5569 u8 rsrv0;
5570 u8 state;
5571 u8 dhc_qzone_id;
5572 u8 same_igu_sb_1b;
5573#elif defined(__LITTLE_ENDIAN)
5574 u8 same_igu_sb_1b;
5575 u8 dhc_qzone_id;
5576 u8 state;
5577 u8 rsrv0;
5578#endif
5579 struct regpair_native rsrv1[2];
5580};
5581
5582
5583
5584
5585
5586enum hc_segment {
5587 HC_REGULAR_SEGMENT,
5588 HC_DEFAULT_SEGMENT,
5589 MAX_HC_SEGMENT
5590};
5591
5592
5593
5594
5595
5596struct hc_sp_status_block_data {
5597 struct regpair_native host_sb_addr;
5598#if defined(__BIG_ENDIAN)
5599 u8 rsrv1;
5600 u8 state;
5601 u8 igu_seg_id;
5602 u8 igu_sb_id;
5603#elif defined(__LITTLE_ENDIAN)
5604 u8 igu_sb_id;
5605 u8 igu_seg_id;
5606 u8 state;
5607 u8 rsrv1;
5608#endif
5609 struct pci_entity p_func;
5610};
5611
5612
5613
5614
5615
5616struct hc_status_block_data_e1x {
5617 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5618 struct hc_sb_data common;
5619};
5620
5621
5622
5623
5624
5625struct hc_status_block_data_e2 {
5626 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5627 struct hc_sb_data common;
5628};
5629
5630
5631
5632
5633
5634enum igu_mode {
5635 HC_IGU_BC_MODE,
5636 HC_IGU_NBC_MODE,
5637 MAX_IGU_MODE
5638};
5639
5640
5641
5642
5643enum inner_clss_type {
5644 INNER_CLSS_DISABLED,
5645 INNER_CLSS_USE_VLAN,
5646 INNER_CLSS_USE_VNI,
5647 MAX_INNER_CLSS_TYPE};
5648
5649
5650
5651
5652enum ip_ver {
5653 IP_V4,
5654 IP_V6,
5655 MAX_IP_VER
5656};
5657
5658
5659
5660
5661enum malicious_vf_error_id {
5662 MALICIOUS_VF_NO_ERROR,
5663 VF_PF_CHANNEL_NOT_READY,
5664 ETH_ILLEGAL_BD_LENGTHS,
5665 ETH_PACKET_TOO_SHORT,
5666 ETH_PAYLOAD_TOO_BIG,
5667 ETH_ILLEGAL_ETH_TYPE,
5668 ETH_ILLEGAL_LSO_HDR_LEN,
5669 ETH_TOO_MANY_BDS,
5670 ETH_ZERO_HDR_NBDS,
5671 ETH_START_BD_NOT_SET,
5672 ETH_ILLEGAL_PARSE_NBDS,
5673 ETH_IPV6_AND_CHECKSUM,
5674 ETH_VLAN_FLG_INCORRECT,
5675 ETH_ILLEGAL_LSO_MSS,
5676 ETH_TUNNEL_NOT_SUPPORTED,
5677 MAX_MALICIOUS_VF_ERROR_ID
5678};
5679
5680
5681
5682
5683enum mf_mode {
5684 SINGLE_FUNCTION,
5685 MULTI_FUNCTION_SD,
5686 MULTI_FUNCTION_SI,
5687 MULTI_FUNCTION_AFEX,
5688 MAX_MF_MODE
5689};
5690
5691
5692
5693
5694struct tstorm_per_pf_stats {
5695 struct regpair rcv_error_bytes;
5696};
5697
5698
5699
5700
5701struct per_pf_stats {
5702 struct tstorm_per_pf_stats tstorm_pf_statistics;
5703};
5704
5705
5706
5707
5708
5709struct tstorm_per_port_stats {
5710 __le32 mac_discard;
5711 __le32 mac_filter_discard;
5712 __le32 brb_truncate_discard;
5713 __le32 mf_tag_discard;
5714 __le32 packet_drop;
5715 __le32 reserved;
5716};
5717
5718
5719
5720
5721struct per_port_stats {
5722 struct tstorm_per_port_stats tstorm_port_statistics;
5723};
5724
5725
5726
5727
5728
5729struct tstorm_per_queue_stats {
5730 struct regpair rcv_ucast_bytes;
5731 __le32 rcv_ucast_pkts;
5732 __le32 checksum_discard;
5733 struct regpair rcv_bcast_bytes;
5734 __le32 rcv_bcast_pkts;
5735 __le32 pkts_too_big_discard;
5736 struct regpair rcv_mcast_bytes;
5737 __le32 rcv_mcast_pkts;
5738 __le32 ttl0_discard;
5739 __le16 no_buff_discard;
5740 __le16 reserved0;
5741 __le32 reserved1;
5742};
5743
5744
5745
5746
5747struct ustorm_per_queue_stats {
5748 struct regpair ucast_no_buff_bytes;
5749 struct regpair mcast_no_buff_bytes;
5750 struct regpair bcast_no_buff_bytes;
5751 __le32 ucast_no_buff_pkts;
5752 __le32 mcast_no_buff_pkts;
5753 __le32 bcast_no_buff_pkts;
5754 __le32 coalesced_pkts;
5755 struct regpair coalesced_bytes;
5756 __le32 coalesced_events;
5757 __le32 coalesced_aborts;
5758};
5759
5760
5761
5762
5763struct xstorm_per_queue_stats {
5764 struct regpair ucast_bytes_sent;
5765 struct regpair mcast_bytes_sent;
5766 struct regpair bcast_bytes_sent;
5767 __le32 ucast_pkts_sent;
5768 __le32 mcast_pkts_sent;
5769 __le32 bcast_pkts_sent;
5770 __le32 error_drop_pkts;
5771};
5772
5773
5774
5775
5776struct per_queue_stats {
5777 struct tstorm_per_queue_stats tstorm_queue_statistics;
5778 struct ustorm_per_queue_stats ustorm_queue_statistics;
5779 struct xstorm_per_queue_stats xstorm_queue_statistics;
5780};
5781
5782
5783
5784
5785
5786struct pram_fw_version {
5787 u8 major;
5788 u8 minor;
5789 u8 revision;
5790 u8 engineering;
5791 u8 flags;
5792#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5793#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5794#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5795#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5796#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5797#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5798#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5799#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5800#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5801#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5802};
5803
5804
5805
5806
5807
5808union protocol_common_specific_data {
5809 u8 protocol_data[8];
5810 struct regpair phy_address;
5811 struct regpair mac_config_addr;
5812 struct afex_vif_list_ramrod_data afex_vif_list_data;
5813};
5814
5815
5816
5817
5818struct protocol_common_spe {
5819 struct spe_hdr hdr;
5820 union protocol_common_specific_data data;
5821};
5822
5823
5824struct set_timesync_ramrod_data {
5825 u8 drift_adjust_cmd;
5826 u8 offset_cmd;
5827 u8 add_sub_drift_adjust_value;
5828 u8 drift_adjust_value;
5829 u32 drift_adjust_period;
5830 struct regpair offset_delta;
5831};
5832
5833
5834
5835
5836struct slow_path_element {
5837 struct spe_hdr hdr;
5838 struct regpair protocol_data;
5839};
5840
5841
5842
5843
5844
5845struct stats_counter {
5846 __le16 xstats_counter;
5847 __le16 reserved0;
5848 __le32 reserved1;
5849 __le16 tstats_counter;
5850 __le16 reserved2;
5851 __le32 reserved3;
5852 __le16 ustats_counter;
5853 __le16 reserved4;
5854 __le32 reserved5;
5855 __le16 cstats_counter;
5856 __le16 reserved6;
5857 __le32 reserved7;
5858};
5859
5860
5861
5862
5863
5864struct stats_query_entry {
5865 u8 kind;
5866 u8 index;
5867 __le16 funcID;
5868 __le32 reserved;
5869 struct regpair address;
5870};
5871
5872
5873
5874
5875struct stats_query_cmd_group {
5876 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5877};
5878
5879
5880
5881
5882
5883struct stats_query_header {
5884 u8 cmd_num;
5885 u8 reserved0;
5886 __le16 drv_stats_counter;
5887 __le32 reserved1;
5888 struct regpair stats_counters_addrs;
5889};
5890
5891
5892
5893
5894
5895enum stats_query_type {
5896 STATS_TYPE_QUEUE,
5897 STATS_TYPE_PORT,
5898 STATS_TYPE_PF,
5899 STATS_TYPE_TOE,
5900 STATS_TYPE_FCOE,
5901 MAX_STATS_QUERY_TYPE
5902};
5903
5904
5905
5906
5907
5908enum status_block_state {
5909 SB_DISABLED,
5910 SB_ENABLED,
5911 SB_CLEANED,
5912 MAX_STATUS_BLOCK_STATE
5913};
5914
5915
5916
5917
5918
5919enum storm_id {
5920 USTORM_ID,
5921 CSTORM_ID,
5922 XSTORM_ID,
5923 TSTORM_ID,
5924 ATTENTION_ID,
5925 MAX_STORM_ID
5926};
5927
5928
5929
5930
5931
5932enum traffic_type {
5933 LLFC_TRAFFIC_TYPE_NW,
5934 LLFC_TRAFFIC_TYPE_FCOE,
5935 LLFC_TRAFFIC_TYPE_ISCSI,
5936 MAX_TRAFFIC_TYPE
5937};
5938
5939
5940
5941
5942
5943struct tstorm_queue_zone_data {
5944 struct regpair reserved[4];
5945};
5946
5947
5948
5949
5950
5951struct tstorm_vf_zone_data {
5952 struct regpair reserved;
5953};
5954
5955
5956enum ts_add_sub_value {
5957 TS_SUB_VALUE,
5958 TS_ADD_VALUE,
5959 MAX_TS_ADD_SUB_VALUE
5960};
5961
5962
5963enum ts_drift_adjust_cmd {
5964 TS_DRIFT_ADJUST_KEEP,
5965 TS_DRIFT_ADJUST_SET,
5966 TS_DRIFT_ADJUST_RESET,
5967 MAX_TS_DRIFT_ADJUST_CMD
5968};
5969
5970
5971enum ts_offset_cmd {
5972 TS_OFFSET_KEEP,
5973 TS_OFFSET_INC,
5974 TS_OFFSET_DEC,
5975 MAX_TS_OFFSET_CMD
5976};
5977
5978
5979struct ustorm_queue_zone_data {
5980 struct ustorm_eth_rx_producers eth_rx_producers;
5981 struct regpair reserved[3];
5982};
5983
5984
5985
5986
5987
5988struct ustorm_vf_zone_data {
5989 struct regpair reserved;
5990};
5991
5992
5993
5994
5995
5996struct vf_pf_channel_data {
5997#if defined(__BIG_ENDIAN)
5998 u16 reserved0;
5999 u8 valid;
6000 u8 state;
6001#elif defined(__LITTLE_ENDIAN)
6002 u8 state;
6003 u8 valid;
6004 u16 reserved0;
6005#endif
6006 u32 reserved1;
6007};
6008
6009
6010
6011
6012
6013enum vf_pf_channel_state {
6014 VF_PF_CHANNEL_STATE_READY,
6015 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
6016 MAX_VF_PF_CHANNEL_STATE
6017};
6018
6019
6020
6021
6022
6023enum vif_list_rule_kind {
6024 VIF_LIST_RULE_SET,
6025 VIF_LIST_RULE_GET,
6026 VIF_LIST_RULE_CLEAR_ALL,
6027 VIF_LIST_RULE_CLEAR_FUNC,
6028 MAX_VIF_LIST_RULE_KIND
6029};
6030
6031
6032
6033
6034
6035struct xstorm_queue_zone_data {
6036 struct regpair reserved[4];
6037};
6038
6039
6040
6041
6042
6043struct xstorm_vf_zone_data {
6044 struct regpair reserved;
6045};
6046
6047#endif
6048