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9#include <linux/kernel.h>
10#include <linux/errno.h>
11#include <linux/pci.h>
12#include <linux/netdevice.h>
13#include <linux/etherdevice.h>
14#include <linux/ptp_clock_kernel.h>
15#include <linux/net_tstamp.h>
16#include <linux/timecounter.h>
17#include <linux/timekeeping.h>
18#include <linux/ptp_classify.h>
19#include "bnxt_hsi.h"
20#include "bnxt.h"
21#include "bnxt_hwrm.h"
22#include "bnxt_ptp.h"
23
24int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
25{
26 unsigned int ptp_class;
27 struct ptp_header *hdr;
28
29 ptp_class = ptp_classify_raw(skb);
30
31 switch (ptp_class & PTP_CLASS_VMASK) {
32 case PTP_CLASS_V1:
33 case PTP_CLASS_V2:
34 hdr = ptp_parse_header(skb, ptp_class);
35 if (!hdr)
36 return -EINVAL;
37
38 *hdr_off = (u8 *)hdr - skb->data;
39 *seq_id = ntohs(hdr->sequence_id);
40 return 0;
41 default:
42 return -ERANGE;
43 }
44}
45
46static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
47 const struct timespec64 *ts)
48{
49 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
50 ptp_info);
51 u64 ns = timespec64_to_ns(ts);
52
53 spin_lock_bh(&ptp->ptp_lock);
54 timecounter_init(&ptp->tc, &ptp->cc, ns);
55 spin_unlock_bh(&ptp->ptp_lock);
56 return 0;
57}
58
59
60static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
61 u64 *ns)
62{
63 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
64
65 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
66 return -EIO;
67
68 ptp_read_system_prets(sts);
69 *ns = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
70 ptp_read_system_postts(sts);
71 *ns |= (u64)readl(bp->bar0 + ptp->refclk_mapped_regs[1]) << 32;
72 return 0;
73}
74
75static void bnxt_ptp_get_current_time(struct bnxt *bp)
76{
77 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
78
79 if (!ptp)
80 return;
81 spin_lock_bh(&ptp->ptp_lock);
82 WRITE_ONCE(ptp->old_time, ptp->current_time);
83 bnxt_refclk_read(bp, NULL, &ptp->current_time);
84 spin_unlock_bh(&ptp->ptp_lock);
85}
86
87static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)
88{
89 struct hwrm_port_ts_query_output *resp;
90 struct hwrm_port_ts_query_input *req;
91 int rc;
92
93 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
94 if (rc)
95 return rc;
96
97 req->flags = cpu_to_le32(flags);
98 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
99 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
100 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
101 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid);
102 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off);
103 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT);
104 }
105 resp = hwrm_req_hold(bp, req);
106
107 rc = hwrm_req_send(bp, req);
108 if (!rc)
109 *ts = le64_to_cpu(resp->ptp_msg_ts);
110 hwrm_req_drop(bp, req);
111 return rc;
112}
113
114static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
115 struct timespec64 *ts,
116 struct ptp_system_timestamp *sts)
117{
118 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
119 ptp_info);
120 u64 ns, cycles;
121 int rc;
122
123 spin_lock_bh(&ptp->ptp_lock);
124 rc = bnxt_refclk_read(ptp->bp, sts, &cycles);
125 if (rc) {
126 spin_unlock_bh(&ptp->ptp_lock);
127 return rc;
128 }
129 ns = timecounter_cyc2time(&ptp->tc, cycles);
130 spin_unlock_bh(&ptp->ptp_lock);
131 *ts = ns_to_timespec64(ns);
132
133 return 0;
134}
135
136static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
137{
138 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
139 ptp_info);
140
141 spin_lock_bh(&ptp->ptp_lock);
142 timecounter_adjtime(&ptp->tc, delta);
143 spin_unlock_bh(&ptp->ptp_lock);
144 return 0;
145}
146
147static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb)
148{
149 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
150 ptp_info);
151 struct hwrm_port_mac_cfg_input *req;
152 struct bnxt *bp = ptp->bp;
153 int rc;
154
155 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
156 if (rc)
157 return rc;
158
159 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
160 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
161 rc = hwrm_req_send(ptp->bp, req);
162 if (rc)
163 netdev_err(ptp->bp->dev,
164 "ptp adjfreq failed. rc = %d\n", rc);
165 return rc;
166}
167
168void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
169{
170 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
171 struct ptp_clock_event event;
172 u64 ns, pps_ts;
173
174 pps_ts = EVENT_PPS_TS(data2, data1);
175 spin_lock_bh(&ptp->ptp_lock);
176 ns = timecounter_cyc2time(&ptp->tc, pps_ts);
177 spin_unlock_bh(&ptp->ptp_lock);
178
179 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
180 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
181 event.pps_times.ts_real = ns_to_timespec64(ns);
182 event.type = PTP_CLOCK_PPSUSR;
183 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
184 break;
185 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
186 event.timestamp = ns;
187 event.type = PTP_CLOCK_EXTTS;
188 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
189 break;
190 }
191
192 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
193}
194
195static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
196{
197 struct hwrm_func_ptp_pin_cfg_input *req;
198 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
199 u8 state = usage != BNXT_PPS_PIN_NONE;
200 u8 *pin_state, *pin_usg;
201 u32 enables;
202 int rc;
203
204 if (!TSIO_PIN_VALID(pin)) {
205 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
206 return -EOPNOTSUPP;
207 }
208
209 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
210 if (rc)
211 return rc;
212
213 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
214 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
215 req->enables = cpu_to_le32(enables);
216
217 pin_state = &req->pin0_state;
218 pin_usg = &req->pin0_usage;
219
220 *(pin_state + (pin * 2)) = state;
221 *(pin_usg + (pin * 2)) = usage;
222
223 rc = hwrm_req_send(ptp->bp, req);
224 if (rc)
225 return rc;
226
227 ptp->pps_info.pins[pin].usage = usage;
228 ptp->pps_info.pins[pin].state = state;
229
230 return 0;
231}
232
233static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
234{
235 struct hwrm_func_ptp_cfg_input *req;
236 int rc;
237
238 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
239 if (rc)
240 return rc;
241
242 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
243 req->ptp_pps_event = event;
244 return hwrm_req_send(bp, req);
245}
246
247void bnxt_ptp_reapply_pps(struct bnxt *bp)
248{
249 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
250 struct bnxt_pps *pps;
251 u32 pin = 0;
252 int rc;
253
254 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
255 !(ptp->ptp_info.pin_config))
256 return;
257 pps = &ptp->pps_info;
258 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
259 if (pps->pins[pin].state) {
260 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
261 if (!rc && pps->pins[pin].event)
262 rc = bnxt_ptp_cfg_event(bp,
263 pps->pins[pin].event);
264 if (rc)
265 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
266 pin);
267 }
268 }
269}
270
271static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
272 u64 *cycles_delta)
273{
274 u64 cycles_now;
275 u64 nsec_now, nsec_delta;
276 int rc;
277
278 spin_lock_bh(&ptp->ptp_lock);
279 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
280 if (rc) {
281 spin_unlock_bh(&ptp->ptp_lock);
282 return rc;
283 }
284 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now);
285 spin_unlock_bh(&ptp->ptp_lock);
286
287 nsec_delta = target_ns - nsec_now;
288 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
289 return 0;
290}
291
292static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
293 struct ptp_clock_request *rq)
294{
295 struct hwrm_func_ptp_cfg_input *req;
296 struct bnxt *bp = ptp->bp;
297 struct timespec64 ts;
298 u64 target_ns, delta;
299 u16 enables;
300 int rc;
301
302 ts.tv_sec = rq->perout.start.sec;
303 ts.tv_nsec = rq->perout.start.nsec;
304 target_ns = timespec64_to_ns(&ts);
305
306 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
307 if (rc)
308 return rc;
309
310 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
311 if (rc)
312 return rc;
313
314 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
315 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
316 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
317 req->enables = cpu_to_le16(enables);
318 req->ptp_pps_event = 0;
319 req->ptp_freq_adj_dll_source = 0;
320 req->ptp_freq_adj_dll_phase = 0;
321 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
322 req->ptp_freq_adj_ext_up = 0;
323 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
324
325 return hwrm_req_send(bp, req);
326}
327
328static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
329 struct ptp_clock_request *rq, int on)
330{
331 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
332 ptp_info);
333 struct bnxt *bp = ptp->bp;
334 u8 pin_id;
335 int rc;
336
337 switch (rq->type) {
338 case PTP_CLK_REQ_EXTTS:
339
340 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
341 rq->extts.index);
342 if (!on)
343 break;
344 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
345 if (rc)
346 return rc;
347 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
348 if (!rc)
349 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
350 return rc;
351 case PTP_CLK_REQ_PEROUT:
352
353 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
354 rq->perout.index);
355 if (!on)
356 break;
357
358 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
359 if (!rc)
360 rc = bnxt_ptp_perout_cfg(ptp, rq);
361
362 return rc;
363 case PTP_CLK_REQ_PPS:
364
365 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
366 if (rc)
367 return rc;
368 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
369 if (!rc)
370 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
371 return rc;
372 default:
373 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
374 return -EOPNOTSUPP;
375 }
376
377 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
378}
379
380static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
381{
382 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
383 struct hwrm_port_mac_cfg_input *req;
384 u32 flags = 0;
385 int rc;
386
387 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
388 if (rc)
389 return rc;
390
391 if (ptp->rx_filter)
392 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
393 else
394 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
395 if (ptp->tx_tstamp_en)
396 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
397 else
398 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
399 req->flags = cpu_to_le32(flags);
400 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
401 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
402
403 return hwrm_req_send(bp, req);
404}
405
406int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
407{
408 struct bnxt *bp = netdev_priv(dev);
409 struct hwtstamp_config stmpconf;
410 struct bnxt_ptp_cfg *ptp;
411 u16 old_rxctl;
412 int old_rx_filter, rc;
413 u8 old_tx_tstamp_en;
414
415 ptp = bp->ptp_cfg;
416 if (!ptp)
417 return -EOPNOTSUPP;
418
419 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
420 return -EFAULT;
421
422 if (stmpconf.flags)
423 return -EINVAL;
424
425 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
426 stmpconf.tx_type != HWTSTAMP_TX_OFF)
427 return -ERANGE;
428
429 old_rx_filter = ptp->rx_filter;
430 old_rxctl = ptp->rxctl;
431 old_tx_tstamp_en = ptp->tx_tstamp_en;
432 switch (stmpconf.rx_filter) {
433 case HWTSTAMP_FILTER_NONE:
434 ptp->rxctl = 0;
435 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
436 break;
437 case HWTSTAMP_FILTER_PTP_V2_EVENT:
438 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
439 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
440 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
441 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
442 break;
443 case HWTSTAMP_FILTER_PTP_V2_SYNC:
444 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
445 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
446 ptp->rxctl = BNXT_PTP_MSG_SYNC;
447 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
448 break;
449 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
450 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
451 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
452 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
453 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
454 break;
455 default:
456 return -ERANGE;
457 }
458
459 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
460 ptp->tx_tstamp_en = 1;
461 else
462 ptp->tx_tstamp_en = 0;
463
464 rc = bnxt_hwrm_ptp_cfg(bp);
465 if (rc)
466 goto ts_set_err;
467
468 stmpconf.rx_filter = ptp->rx_filter;
469 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
470 -EFAULT : 0;
471
472ts_set_err:
473 ptp->rx_filter = old_rx_filter;
474 ptp->rxctl = old_rxctl;
475 ptp->tx_tstamp_en = old_tx_tstamp_en;
476 return rc;
477}
478
479int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
480{
481 struct bnxt *bp = netdev_priv(dev);
482 struct hwtstamp_config stmpconf;
483 struct bnxt_ptp_cfg *ptp;
484
485 ptp = bp->ptp_cfg;
486 if (!ptp)
487 return -EOPNOTSUPP;
488
489 stmpconf.flags = 0;
490 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
491
492 stmpconf.rx_filter = ptp->rx_filter;
493 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
494 -EFAULT : 0;
495}
496
497static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
498{
499 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
500 u32 win_off;
501 int i;
502
503 for (i = 0; i < count; i++) {
504 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
505 return -ERANGE;
506 }
507 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
508 writel(reg_base, bp->bar0 + win_off);
509 return 0;
510}
511
512static int bnxt_map_ptp_regs(struct bnxt *bp)
513{
514 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
515 u32 *reg_arr;
516 int rc, i;
517
518 reg_arr = ptp->refclk_regs;
519 if (bp->flags & BNXT_FLAG_CHIP_P5) {
520 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
521 if (rc)
522 return rc;
523 for (i = 0; i < 2; i++)
524 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
525 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
526 return 0;
527 }
528 return -ENODEV;
529}
530
531static void bnxt_unmap_ptp_regs(struct bnxt *bp)
532{
533 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
534 (BNXT_PTP_GRC_WIN - 1) * 4);
535}
536
537static u64 bnxt_cc_read(const struct cyclecounter *cc)
538{
539 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
540 u64 ns = 0;
541
542 bnxt_refclk_read(ptp->bp, NULL, &ns);
543 return ns;
544}
545
546static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)
547{
548 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
549 struct skb_shared_hwtstamps timestamp;
550 u64 ts = 0, ns = 0;
551 int rc;
552
553 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts);
554 if (!rc) {
555 memset(×tamp, 0, sizeof(timestamp));
556 spin_lock_bh(&ptp->ptp_lock);
557 ns = timecounter_cyc2time(&ptp->tc, ts);
558 spin_unlock_bh(&ptp->ptp_lock);
559 timestamp.hwtstamp = ns_to_ktime(ns);
560 skb_tstamp_tx(ptp->tx_skb, ×tamp);
561 } else {
562 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n",
563 rc);
564 }
565
566 dev_kfree_skb_any(ptp->tx_skb);
567 ptp->tx_skb = NULL;
568 atomic_inc(&ptp->tx_avail);
569}
570
571static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
572{
573 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
574 ptp_info);
575 unsigned long now = jiffies;
576 struct bnxt *bp = ptp->bp;
577
578 if (ptp->tx_skb)
579 bnxt_stamp_tx_skb(bp, ptp->tx_skb);
580
581 if (!time_after_eq(now, ptp->next_period))
582 return ptp->next_period - now;
583
584 bnxt_ptp_get_current_time(bp);
585 ptp->next_period = now + HZ;
586 if (time_after_eq(now, ptp->next_overflow_check)) {
587 spin_lock_bh(&ptp->ptp_lock);
588 timecounter_read(&ptp->tc);
589 spin_unlock_bh(&ptp->ptp_lock);
590 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
591 }
592 return HZ;
593}
594
595int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb)
596{
597 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
598
599 if (ptp->tx_skb) {
600 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n");
601 return -EBUSY;
602 }
603 ptp->tx_skb = skb;
604 ptp_schedule_worker(ptp->ptp_clock, 0);
605 return 0;
606}
607
608int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
609{
610 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
611 u64 time;
612
613 if (!ptp)
614 return -ENODEV;
615
616 BNXT_READ_TIME64(ptp, time, ptp->old_time);
617 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
618 if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
619 *ts += BNXT_LO_TIMER_MASK + 1;
620
621 return 0;
622}
623
624static const struct ptp_clock_info bnxt_ptp_caps = {
625 .owner = THIS_MODULE,
626 .name = "bnxt clock",
627 .max_adj = BNXT_MAX_PHC_DRIFT,
628 .n_alarm = 0,
629 .n_ext_ts = 0,
630 .n_per_out = 0,
631 .n_pins = 0,
632 .pps = 0,
633 .adjfreq = bnxt_ptp_adjfreq,
634 .adjtime = bnxt_ptp_adjtime,
635 .do_aux_work = bnxt_ptp_ts_aux_work,
636 .gettimex64 = bnxt_ptp_gettimex,
637 .settime64 = bnxt_ptp_settime,
638 .enable = bnxt_ptp_enable,
639};
640
641static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
642 enum ptp_pin_function func, unsigned int chan)
643{
644 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
645 ptp_info);
646
647 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
648 func != PTP_PF_PHYSYNC)
649 return 0;
650 else
651 return -EOPNOTSUPP;
652}
653
654static int bnxt_ptp_pps_init(struct bnxt *bp)
655{
656 struct hwrm_func_ptp_pin_qcfg_output *resp;
657 struct hwrm_func_ptp_pin_qcfg_input *req;
658 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
659 struct ptp_clock_info *ptp_info;
660 struct bnxt_pps *pps_info;
661 u8 *pin_usg;
662 u32 i, rc;
663
664
665 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
666 if (rc)
667 return rc;
668
669 resp = hwrm_req_hold(bp, req);
670 rc = hwrm_req_send(bp, req);
671 if (rc || !resp->num_pins) {
672 hwrm_req_drop(bp, req);
673 return -EOPNOTSUPP;
674 }
675
676 ptp_info = &ptp->ptp_info;
677 pps_info = &ptp->pps_info;
678 pps_info->num_pins = resp->num_pins;
679 ptp_info->n_pins = pps_info->num_pins;
680 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
681 sizeof(*ptp_info->pin_config),
682 GFP_KERNEL);
683 if (!ptp_info->pin_config) {
684 hwrm_req_drop(bp, req);
685 return -ENOMEM;
686 }
687
688
689 pin_usg = &resp->pin0_usage;
690 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
691 snprintf(ptp_info->pin_config[i].name,
692 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
693 ptp_info->pin_config[i].index = i;
694 ptp_info->pin_config[i].chan = i;
695 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
696 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
697 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
698 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
699 else
700 ptp_info->pin_config[i].func = PTP_PF_NONE;
701
702 pps_info->pins[i].usage = *pin_usg;
703 }
704 hwrm_req_drop(bp, req);
705
706
707 ptp_info->n_ext_ts = 1;
708 ptp_info->n_per_out = 1;
709 ptp_info->pps = 1;
710 ptp_info->verify = bnxt_ptp_verify;
711
712 return 0;
713}
714
715static bool bnxt_pps_config_ok(struct bnxt *bp)
716{
717 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
718
719 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
720}
721
722int bnxt_ptp_init(struct bnxt *bp)
723{
724 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
725 int rc;
726
727 if (!ptp)
728 return 0;
729
730 rc = bnxt_map_ptp_regs(bp);
731 if (rc)
732 return rc;
733
734 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
735 return 0;
736
737 if (ptp->ptp_clock) {
738 ptp_clock_unregister(ptp->ptp_clock);
739 ptp->ptp_clock = NULL;
740 kfree(ptp->ptp_info.pin_config);
741 ptp->ptp_info.pin_config = NULL;
742 }
743 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
744 spin_lock_init(&ptp->ptp_lock);
745
746 memset(&ptp->cc, 0, sizeof(ptp->cc));
747 ptp->cc.read = bnxt_cc_read;
748 ptp->cc.mask = CYCLECOUNTER_MASK(48);
749 ptp->cc.shift = 0;
750 ptp->cc.mult = 1;
751
752 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
753 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
754
755 ptp->ptp_info = bnxt_ptp_caps;
756 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
757 if (bnxt_ptp_pps_init(bp))
758 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
759 }
760 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
761 if (IS_ERR(ptp->ptp_clock)) {
762 int err = PTR_ERR(ptp->ptp_clock);
763
764 ptp->ptp_clock = NULL;
765 bnxt_unmap_ptp_regs(bp);
766 return err;
767 }
768 if (bp->flags & BNXT_FLAG_CHIP_P5) {
769 spin_lock_bh(&ptp->ptp_lock);
770 bnxt_refclk_read(bp, NULL, &ptp->current_time);
771 WRITE_ONCE(ptp->old_time, ptp->current_time);
772 spin_unlock_bh(&ptp->ptp_lock);
773 ptp_schedule_worker(ptp->ptp_clock, 0);
774 }
775 return 0;
776}
777
778void bnxt_ptp_clear(struct bnxt *bp)
779{
780 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
781
782 if (!ptp)
783 return;
784
785 if (ptp->ptp_clock)
786 ptp_clock_unregister(ptp->ptp_clock);
787
788 ptp->ptp_clock = NULL;
789 kfree(ptp->ptp_info.pin_config);
790 ptp->ptp_info.pin_config = NULL;
791
792 if (ptp->tx_skb) {
793 dev_kfree_skb_any(ptp->tx_skb);
794 ptp->tx_skb = NULL;
795 }
796 bnxt_unmap_ptp_regs(bp);
797}
798
