linux/drivers/net/ethernet/broadcom/tg3.c
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   1/*
   2 * tg3.c: Broadcom Tigon3 ethernet driver.
   3 *
   4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6 * Copyright (C) 2004 Sun Microsystems Inc.
   7 * Copyright (C) 2005-2016 Broadcom Corporation.
   8 * Copyright (C) 2016-2017 Broadcom Limited.
   9 * Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
  10 * refers to Broadcom Inc. and/or its subsidiaries.
  11 *
  12 * Firmware is:
  13 *      Derived from proprietary unpublished source code,
  14 *      Copyright (C) 2000-2016 Broadcom Corporation.
  15 *      Copyright (C) 2016-2017 Broadcom Ltd.
  16 *      Copyright (C) 2018 Broadcom. All Rights Reserved. The term "Broadcom"
  17 *      refers to Broadcom Inc. and/or its subsidiaries.
  18 *
  19 *      Permission is hereby granted for the distribution of this firmware
  20 *      data in hexadecimal or equivalent format, provided this copyright
  21 *      notice is accompanying it.
  22 */
  23
  24
  25#include <linux/module.h>
  26#include <linux/moduleparam.h>
  27#include <linux/stringify.h>
  28#include <linux/kernel.h>
  29#include <linux/sched/signal.h>
  30#include <linux/types.h>
  31#include <linux/compiler.h>
  32#include <linux/slab.h>
  33#include <linux/delay.h>
  34#include <linux/in.h>
  35#include <linux/interrupt.h>
  36#include <linux/ioport.h>
  37#include <linux/pci.h>
  38#include <linux/netdevice.h>
  39#include <linux/etherdevice.h>
  40#include <linux/skbuff.h>
  41#include <linux/ethtool.h>
  42#include <linux/mdio.h>
  43#include <linux/mii.h>
  44#include <linux/phy.h>
  45#include <linux/brcmphy.h>
  46#include <linux/if.h>
  47#include <linux/if_vlan.h>
  48#include <linux/ip.h>
  49#include <linux/tcp.h>
  50#include <linux/workqueue.h>
  51#include <linux/prefetch.h>
  52#include <linux/dma-mapping.h>
  53#include <linux/firmware.h>
  54#include <linux/ssb/ssb_driver_gige.h>
  55#include <linux/hwmon.h>
  56#include <linux/hwmon-sysfs.h>
  57#include <linux/crc32poly.h>
  58
  59#include <net/checksum.h>
  60#include <net/ip.h>
  61
  62#include <linux/io.h>
  63#include <asm/byteorder.h>
  64#include <linux/uaccess.h>
  65
  66#include <uapi/linux/net_tstamp.h>
  67#include <linux/ptp_clock_kernel.h>
  68
  69#define BAR_0   0
  70#define BAR_2   2
  71
  72#include "tg3.h"
  73
  74/* Functions & macros to verify TG3_FLAGS types */
  75
  76static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
  77{
  78        return test_bit(flag, bits);
  79}
  80
  81static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
  82{
  83        set_bit(flag, bits);
  84}
  85
  86static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
  87{
  88        clear_bit(flag, bits);
  89}
  90
  91#define tg3_flag(tp, flag)                              \
  92        _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
  93#define tg3_flag_set(tp, flag)                          \
  94        _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
  95#define tg3_flag_clear(tp, flag)                        \
  96        _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
  97
  98#define DRV_MODULE_NAME         "tg3"
  99#define TG3_MAJ_NUM                     3
 100#define TG3_MIN_NUM                     137
 101#define DRV_MODULE_VERSION      \
 102        __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
 103#define DRV_MODULE_RELDATE      "May 11, 2014"
 104
 105#define RESET_KIND_SHUTDOWN     0
 106#define RESET_KIND_INIT         1
 107#define RESET_KIND_SUSPEND      2
 108
 109#define TG3_DEF_RX_MODE         0
 110#define TG3_DEF_TX_MODE         0
 111#define TG3_DEF_MSG_ENABLE        \
 112        (NETIF_MSG_DRV          | \
 113         NETIF_MSG_PROBE        | \
 114         NETIF_MSG_LINK         | \
 115         NETIF_MSG_TIMER        | \
 116         NETIF_MSG_IFDOWN       | \
 117         NETIF_MSG_IFUP         | \
 118         NETIF_MSG_RX_ERR       | \
 119         NETIF_MSG_TX_ERR)
 120
 121#define TG3_GRC_LCLCTL_PWRSW_DELAY      100
 122
 123/* length of time before we decide the hardware is borked,
 124 * and dev->tx_timeout() should be called to fix the problem
 125 */
 126
 127#define TG3_TX_TIMEOUT                  (5 * HZ)
 128
 129/* hardware minimum and maximum for a single frame's data payload */
 130#define TG3_MIN_MTU                     ETH_ZLEN
 131#define TG3_MAX_MTU(tp) \
 132        (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
 133
 134/* These numbers seem to be hard coded in the NIC firmware somehow.
 135 * You can't change the ring sizes, but you can change where you place
 136 * them in the NIC onboard memory.
 137 */
 138#define TG3_RX_STD_RING_SIZE(tp) \
 139        (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 140         TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
 141#define TG3_DEF_RX_RING_PENDING         200
 142#define TG3_RX_JMB_RING_SIZE(tp) \
 143        (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
 144         TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
 145#define TG3_DEF_RX_JUMBO_RING_PENDING   100
 146
 147/* Do not place this n-ring entries value into the tp struct itself,
 148 * we really want to expose these constants to GCC so that modulo et
 149 * al.  operations are done with shifts and masks instead of with
 150 * hw multiply/modulo instructions.  Another solution would be to
 151 * replace things like '% foo' with '& (foo - 1)'.
 152 */
 153
 154#define TG3_TX_RING_SIZE                512
 155#define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 156
 157#define TG3_RX_STD_RING_BYTES(tp) \
 158        (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 159#define TG3_RX_JMB_RING_BYTES(tp) \
 160        (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 161#define TG3_RX_RCB_RING_BYTES(tp) \
 162        (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 163#define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 164                                 TG3_TX_RING_SIZE)
 165#define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 166
 167#define TG3_DMA_BYTE_ENAB               64
 168
 169#define TG3_RX_STD_DMA_SZ               1536
 170#define TG3_RX_JMB_DMA_SZ               9046
 171
 172#define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 173
 174#define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 175#define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 176
 177#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 178        (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 179
 180#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 181        (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 182
 183/* Due to a hardware bug, the 5701 can only DMA to memory addresses
 184 * that are at least dword aligned when used in PCIX mode.  The driver
 185 * works around this bug by double copying the packet.  This workaround
 186 * is built into the normal double copy length check for efficiency.
 187 *
 188 * However, the double copy is only necessary on those architectures
 189 * where unaligned memory accesses are inefficient.  For those architectures
 190 * where unaligned memory accesses incur little penalty, we can reintegrate
 191 * the 5701 in the normal rx path.  Doing so saves a device structure
 192 * dereference by hardcoding the double copy threshold in place.
 193 */
 194#define TG3_RX_COPY_THRESHOLD           256
 195#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 196        #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 197#else
 198        #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 199#endif
 200
 201#if (NET_IP_ALIGN != 0)
 202#define TG3_RX_OFFSET(tp)       ((tp)->rx_offset)
 203#else
 204#define TG3_RX_OFFSET(tp)       (NET_SKB_PAD)
 205#endif
 206
 207/* minimum number of free TX descriptors required to wake up TX process */
 208#define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 209#define TG3_TX_BD_DMA_MAX_2K            2048
 210#define TG3_TX_BD_DMA_MAX_4K            4096
 211
 212#define TG3_RAW_IP_ALIGN 2
 213
 214#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
 215#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
 216
 217#define TG3_FW_UPDATE_TIMEOUT_SEC       5
 218#define TG3_FW_UPDATE_FREQ_SEC          (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
 219
 220#define FIRMWARE_TG3            "tigon/tg3.bin"
 221#define FIRMWARE_TG357766       "tigon/tg357766.bin"
 222#define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 223#define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 224
 225static char version[] =
 226        DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 227
 228MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 229MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 230MODULE_LICENSE("GPL");
 231MODULE_VERSION(DRV_MODULE_VERSION);
 232MODULE_FIRMWARE(FIRMWARE_TG3);
 233MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 234MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 235
 236static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 237module_param(tg3_debug, int, 0);
 238MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 239
 240#define TG3_DRV_DATA_FLAG_10_100_ONLY   0x0001
 241#define TG3_DRV_DATA_FLAG_5705_10_100   0x0002
 242
 243static const struct pci_device_id tg3_pci_tbl[] = {
 244        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 245        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 246        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 247        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 248        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 249        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 250        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 251        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 252        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 253        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 254        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 255        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 256        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 257        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 258        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 259        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 260        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 261        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 262        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
 263         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 264                        TG3_DRV_DATA_FLAG_5705_10_100},
 265        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
 266         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 267                        TG3_DRV_DATA_FLAG_5705_10_100},
 268        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 269        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
 270         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
 271                        TG3_DRV_DATA_FLAG_5705_10_100},
 272        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 273        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 274        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 275        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 276        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 277        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
 278         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 279        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 280        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 281        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 282        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 283        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
 284         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 285        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 286        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 287        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 288        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 289        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 290        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 291        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 292        {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
 293                        PCI_VENDOR_ID_LENOVO,
 294                        TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
 295         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 296        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 297        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
 298         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 299        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 300        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 301        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 302        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 303        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 304        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 305        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 306        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 307        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 308        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 309        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 310        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 311        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 312        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 313        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 314        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 315        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 316        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 317        {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
 318                        PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
 319         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 320        {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
 321                        PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
 322         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 323        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 324        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 325        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
 326         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 327        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 328        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 329        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
 330        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 331        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 332        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 333        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 334        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 335        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
 336         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 337        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
 338         .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
 339        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 340        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
 341        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
 342        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
 343        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
 344        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
 345        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
 346        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
 347        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
 348        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
 349        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
 350        {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
 351        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 352        {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 353        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 354        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 355        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 356        {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 357        {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 358        {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
 359        {}
 360};
 361
 362MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 363
 364static const struct {
 365        const char string[ETH_GSTRING_LEN];
 366} ethtool_stats_keys[] = {
 367        { "rx_octets" },
 368        { "rx_fragments" },
 369        { "rx_ucast_packets" },
 370        { "rx_mcast_packets" },
 371        { "rx_bcast_packets" },
 372        { "rx_fcs_errors" },
 373        { "rx_align_errors" },
 374        { "rx_xon_pause_rcvd" },
 375        { "rx_xoff_pause_rcvd" },
 376        { "rx_mac_ctrl_rcvd" },
 377        { "rx_xoff_entered" },
 378        { "rx_frame_too_long_errors" },
 379        { "rx_jabbers" },
 380        { "rx_undersize_packets" },
 381        { "rx_in_length_errors" },
 382        { "rx_out_length_errors" },
 383        { "rx_64_or_less_octet_packets" },
 384        { "rx_65_to_127_octet_packets" },
 385        { "rx_128_to_255_octet_packets" },
 386        { "rx_256_to_511_octet_packets" },
 387        { "rx_512_to_1023_octet_packets" },
 388        { "rx_1024_to_1522_octet_packets" },
 389        { "rx_1523_to_2047_octet_packets" },
 390        { "rx_2048_to_4095_octet_packets" },
 391        { "rx_4096_to_8191_octet_packets" },
 392        { "rx_8192_to_9022_octet_packets" },
 393
 394        { "tx_octets" },
 395        { "tx_collisions" },
 396
 397        { "tx_xon_sent" },
 398        { "tx_xoff_sent" },
 399        { "tx_flow_control" },
 400        { "tx_mac_errors" },
 401        { "tx_single_collisions" },
 402        { "tx_mult_collisions" },
 403        { "tx_deferred" },
 404        { "tx_excessive_collisions" },
 405        { "tx_late_collisions" },
 406        { "tx_collide_2times" },
 407        { "tx_collide_3times" },
 408        { "tx_collide_4times" },
 409        { "tx_collide_5times" },
 410        { "tx_collide_6times" },
 411        { "tx_collide_7times" },
 412        { "tx_collide_8times" },
 413        { "tx_collide_9times" },
 414        { "tx_collide_10times" },
 415        { "tx_collide_11times" },
 416        { "tx_collide_12times" },
 417        { "tx_collide_13times" },
 418        { "tx_collide_14times" },
 419        { "tx_collide_15times" },
 420        { "tx_ucast_packets" },
 421        { "tx_mcast_packets" },
 422        { "tx_bcast_packets" },
 423        { "tx_carrier_sense_errors" },
 424        { "tx_discards" },
 425        { "tx_errors" },
 426
 427        { "dma_writeq_full" },
 428        { "dma_write_prioq_full" },
 429        { "rxbds_empty" },
 430        { "rx_discards" },
 431        { "rx_errors" },
 432        { "rx_threshold_hit" },
 433
 434        { "dma_readq_full" },
 435        { "dma_read_prioq_full" },
 436        { "tx_comp_queue_full" },
 437
 438        { "ring_set_send_prod_index" },
 439        { "ring_status_update" },
 440        { "nic_irqs" },
 441        { "nic_avoided_irqs" },
 442        { "nic_tx_threshold_hit" },
 443
 444        { "mbuf_lwm_thresh_hit" },
 445};
 446
 447#define TG3_NUM_STATS   ARRAY_SIZE(ethtool_stats_keys)
 448#define TG3_NVRAM_TEST          0
 449#define TG3_LINK_TEST           1
 450#define TG3_REGISTER_TEST       2
 451#define TG3_MEMORY_TEST         3
 452#define TG3_MAC_LOOPB_TEST      4
 453#define TG3_PHY_LOOPB_TEST      5
 454#define TG3_EXT_LOOPB_TEST      6
 455#define TG3_INTERRUPT_TEST      7
 456
 457
 458static const struct {
 459        const char string[ETH_GSTRING_LEN];
 460} ethtool_test_keys[] = {
 461        [TG3_NVRAM_TEST]        = { "nvram test        (online) " },
 462        [TG3_LINK_TEST]         = { "link test         (online) " },
 463        [TG3_REGISTER_TEST]     = { "register test     (offline)" },
 464        [TG3_MEMORY_TEST]       = { "memory test       (offline)" },
 465        [TG3_MAC_LOOPB_TEST]    = { "mac loopback test (offline)" },
 466        [TG3_PHY_LOOPB_TEST]    = { "phy loopback test (offline)" },
 467        [TG3_EXT_LOOPB_TEST]    = { "ext loopback test (offline)" },
 468        [TG3_INTERRUPT_TEST]    = { "interrupt test    (offline)" },
 469};
 470
 471#define TG3_NUM_TEST    ARRAY_SIZE(ethtool_test_keys)
 472
 473
 474static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 475{
 476        writel(val, tp->regs + off);
 477}
 478
 479static u32 tg3_read32(struct tg3 *tp, u32 off)
 480{
 481        return readl(tp->regs + off);
 482}
 483
 484static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 485{
 486        writel(val, tp->aperegs + off);
 487}
 488
 489static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 490{
 491        return readl(tp->aperegs + off);
 492}
 493
 494static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 495{
 496        unsigned long flags;
 497
 498        spin_lock_irqsave(&tp->indirect_lock, flags);
 499        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 500        pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 501        spin_unlock_irqrestore(&tp->indirect_lock, flags);
 502}
 503
 504static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 505{
 506        writel(val, tp->regs + off);
 507        readl(tp->regs + off);
 508}
 509
 510static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 511{
 512        unsigned long flags;
 513        u32 val;
 514
 515        spin_lock_irqsave(&tp->indirect_lock, flags);
 516        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 517        pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 518        spin_unlock_irqrestore(&tp->indirect_lock, flags);
 519        return val;
 520}
 521
 522static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 523{
 524        unsigned long flags;
 525
 526        if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 527                pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 528                                       TG3_64BIT_REG_LOW, val);
 529                return;
 530        }
 531        if (off == TG3_RX_STD_PROD_IDX_REG) {
 532                pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 533                                       TG3_64BIT_REG_LOW, val);
 534                return;
 535        }
 536
 537        spin_lock_irqsave(&tp->indirect_lock, flags);
 538        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 539        pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 540        spin_unlock_irqrestore(&tp->indirect_lock, flags);
 541
 542        /* In indirect mode when disabling interrupts, we also need
 543         * to clear the interrupt bit in the GRC local ctrl register.
 544         */
 545        if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 546            (val == 0x1)) {
 547                pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 548                                       tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 549        }
 550}
 551
 552static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 553{
 554        unsigned long flags;
 555        u32 val;
 556
 557        spin_lock_irqsave(&tp->indirect_lock, flags);
 558        pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 559        pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 560        spin_unlock_irqrestore(&tp->indirect_lock, flags);
 561        return val;
 562}
 563
 564/* usec_wait specifies the wait time in usec when writing to certain registers
 565 * where it is unsafe to read back the register without some delay.
 566 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 567 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 568 */
 569static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 570{
 571        if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
 572                /* Non-posted methods */
 573                tp->write32(tp, off, val);
 574        else {
 575                /* Posted method */
 576                tg3_write32(tp, off, val);
 577                if (usec_wait)
 578                        udelay(usec_wait);
 579                tp->read32(tp, off);
 580        }
 581        /* Wait again after the read for the posted method to guarantee that
 582         * the wait time is met.
 583         */
 584        if (usec_wait)
 585                udelay(usec_wait);
 586}
 587
 588static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 589{
 590        tp->write32_mbox(tp, off, val);
 591        if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
 592            (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
 593             !tg3_flag(tp, ICH_WORKAROUND)))
 594                tp->read32_mbox(tp, off);
 595}
 596
 597static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 598{
 599        void __iomem *mbox = tp->regs + off;
 600        writel(val, mbox);
 601        if (tg3_flag(tp, TXD_MBOX_HWBUG))
 602                writel(val, mbox);
 603        if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
 604            tg3_flag(tp, FLUSH_POSTED_WRITES))
 605                readl(mbox);
 606}
 607
 608static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 609{
 610        return readl(tp->regs + off + GRCMBOX_BASE);
 611}
 612
 613static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 614{
 615        writel(val, tp->regs + off + GRCMBOX_BASE);
 616}
 617
 618#define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 619#define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 620#define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 621#define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 622#define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 623
 624#define tw32(reg, val)                  tp->write32(tp, reg, val)
 625#define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 626#define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 627#define tr32(reg)                       tp->read32(tp, reg)
 628
 629static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 630{
 631        unsigned long flags;
 632
 633        if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
 634            (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 635                return;
 636
 637        spin_lock_irqsave(&tp->indirect_lock, flags);
 638        if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 639                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 640                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 641
 642                /* Always leave this as zero. */
 643                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 644        } else {
 645                tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 646                tw32_f(TG3PCI_MEM_WIN_DATA, val);
 647
 648                /* Always leave this as zero. */
 649                tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 650        }
 651        spin_unlock_irqrestore(&tp->indirect_lock, flags);
 652}
 653
 654static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 655{
 656        unsigned long flags;
 657
 658        if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
 659            (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 660                *val = 0;
 661                return;
 662        }
 663
 664        spin_lock_irqsave(&tp->indirect_lock, flags);
 665        if (tg3_flag(tp, SRAM_USE_CONFIG)) {
 666                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 667                pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 668
 669                /* Always leave this as zero. */
 670                pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 671        } else {
 672                tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 673                *val = tr32(TG3PCI_MEM_WIN_DATA);
 674
 675                /* Always leave this as zero. */
 676                tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 677        }
 678        spin_unlock_irqrestore(&tp->indirect_lock, flags);
 679}
 680
 681static void tg3_ape_lock_init(struct tg3 *tp)
 682{
 683        int i;
 684        u32 regbase, bit;
 685
 686        if (tg3_asic_rev(tp) == ASIC_REV_5761)
 687                regbase = TG3_APE_LOCK_GRANT;
 688        else
 689                regbase = TG3_APE_PER_LOCK_GRANT;
 690
 691        /* Make sure the driver hasn't any stale locks. */
 692        for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
 693                switch (i) {
 694                case TG3_APE_LOCK_PHY0:
 695                case TG3_APE_LOCK_PHY1:
 696                case TG3_APE_LOCK_PHY2:
 697                case TG3_APE_LOCK_PHY3:
 698                        bit = APE_LOCK_GRANT_DRIVER;
 699                        break;
 700                default:
 701                        if (!tp->pci_fn)
 702                                bit = APE_LOCK_GRANT_DRIVER;
 703                        else
 704                                bit = 1 << tp->pci_fn;
 705                }
 706                tg3_ape_write32(tp, regbase + 4 * i, bit);
 707        }
 708
 709}
 710
 711static int tg3_ape_lock(struct tg3 *tp, int locknum)
 712{
 713        int i, off;
 714        int ret = 0;
 715        u32 status, req, gnt, bit;
 716
 717        if (!tg3_flag(tp, ENABLE_APE))
 718                return 0;
 719
 720        switch (locknum) {
 721        case TG3_APE_LOCK_GPIO:
 722                if (tg3_asic_rev(tp) == ASIC_REV_5761)
 723                        return 0;
 724                /* fall through */
 725        case TG3_APE_LOCK_GRC:
 726        case TG3_APE_LOCK_MEM:
 727                if (!tp->pci_fn)
 728                        bit = APE_LOCK_REQ_DRIVER;
 729                else
 730                        bit = 1 << tp->pci_fn;
 731                break;
 732        case TG3_APE_LOCK_PHY0:
 733        case TG3_APE_LOCK_PHY1:
 734        case TG3_APE_LOCK_PHY2:
 735        case TG3_APE_LOCK_PHY3:
 736                bit = APE_LOCK_REQ_DRIVER;
 737                break;
 738        default:
 739                return -EINVAL;
 740        }
 741
 742        if (tg3_asic_rev(tp) == ASIC_REV_5761) {
 743                req = TG3_APE_LOCK_REQ;
 744                gnt = TG3_APE_LOCK_GRANT;
 745        } else {
 746                req = TG3_APE_PER_LOCK_REQ;
 747                gnt = TG3_APE_PER_LOCK_GRANT;
 748        }
 749
 750        off = 4 * locknum;
 751
 752        tg3_ape_write32(tp, req + off, bit);
 753
 754        /* Wait for up to 1 millisecond to acquire lock. */
 755        for (i = 0; i < 100; i++) {
 756                status = tg3_ape_read32(tp, gnt + off);
 757                if (status == bit)
 758                        break;
 759                if (pci_channel_offline(tp->pdev))
 760                        break;
 761
 762                udelay(10);
 763        }
 764
 765        if (status != bit) {
 766                /* Revoke the lock request. */
 767                tg3_ape_write32(tp, gnt + off, bit);
 768                ret = -EBUSY;
 769        }
 770
 771        return ret;
 772}
 773
 774static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 775{
 776        u32 gnt, bit;
 777
 778        if (!tg3_flag(tp, ENABLE_APE))
 779                return;
 780
 781        switch (locknum) {
 782        case TG3_APE_LOCK_GPIO:
 783                if (tg3_asic_rev(tp) == ASIC_REV_5761)
 784                        return;
 785                /* fall through */
 786        case TG3_APE_LOCK_GRC:
 787        case TG3_APE_LOCK_MEM:
 788                if (!tp->pci_fn)
 789                        bit = APE_LOCK_GRANT_DRIVER;
 790                else
 791                        bit = 1 << tp->pci_fn;
 792                break;
 793        case TG3_APE_LOCK_PHY0:
 794        case TG3_APE_LOCK_PHY1:
 795        case TG3_APE_LOCK_PHY2:
 796        case TG3_APE_LOCK_PHY3:
 797                bit = APE_LOCK_GRANT_DRIVER;
 798                break;
 799        default:
 800                return;
 801        }
 802
 803        if (tg3_asic_rev(tp) == ASIC_REV_5761)
 804                gnt = TG3_APE_LOCK_GRANT;
 805        else
 806                gnt = TG3_APE_PER_LOCK_GRANT;
 807
 808        tg3_ape_write32(tp, gnt + 4 * locknum, bit);
 809}
 810
 811static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
 812{
 813        u32 apedata;
 814
 815        while (timeout_us) {
 816                if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
 817                        return -EBUSY;
 818
 819                apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
 820                if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
 821                        break;
 822
 823                tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 824
 825                udelay(10);
 826                timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
 827        }
 828
 829        return timeout_us ? 0 : -EBUSY;
 830}
 831
 832#ifdef CONFIG_TIGON3_HWMON
 833static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
 834{
 835        u32 i, apedata;
 836
 837        for (i = 0; i < timeout_us / 10; i++) {
 838                apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
 839
 840                if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
 841                        break;
 842
 843                udelay(10);
 844        }
 845
 846        return i == timeout_us / 10;
 847}
 848
 849static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
 850                                   u32 len)
 851{
 852        int err;
 853        u32 i, bufoff, msgoff, maxlen, apedata;
 854
 855        if (!tg3_flag(tp, APE_HAS_NCSI))
 856                return 0;
 857
 858        apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
 859        if (apedata != APE_SEG_SIG_MAGIC)
 860                return -ENODEV;
 861
 862        apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 863        if (!(apedata & APE_FW_STATUS_READY))
 864                return -EAGAIN;
 865
 866        bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
 867                 TG3_APE_SHMEM_BASE;
 868        msgoff = bufoff + 2 * sizeof(u32);
 869        maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
 870
 871        while (len) {
 872                u32 length;
 873
 874                /* Cap xfer sizes to scratchpad limits. */
 875                length = (len > maxlen) ? maxlen : len;
 876                len -= length;
 877
 878                apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 879                if (!(apedata & APE_FW_STATUS_READY))
 880                        return -EAGAIN;
 881
 882                /* Wait for up to 1 msec for APE to service previous event. */
 883                err = tg3_ape_event_lock(tp, 1000);
 884                if (err)
 885                        return err;
 886
 887                apedata = APE_EVENT_STATUS_DRIVER_EVNT |
 888                          APE_EVENT_STATUS_SCRTCHPD_READ |
 889                          APE_EVENT_STATUS_EVENT_PENDING;
 890                tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
 891
 892                tg3_ape_write32(tp, bufoff, base_off);
 893                tg3_ape_write32(tp, bufoff + sizeof(u32), length);
 894
 895                tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 896                tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
 897
 898                base_off += length;
 899
 900                if (tg3_ape_wait_for_event(tp, 30000))
 901                        return -EAGAIN;
 902
 903                for (i = 0; length; i += 4, length -= 4) {
 904                        u32 val = tg3_ape_read32(tp, msgoff + i);
 905                        memcpy(data, &val, sizeof(u32));
 906                        data++;
 907                }
 908        }
 909
 910        return 0;
 911}
 912#endif
 913
 914static int tg3_ape_send_event(struct tg3 *tp, u32 event)
 915{
 916        int err;
 917        u32 apedata;
 918
 919        apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
 920        if (apedata != APE_SEG_SIG_MAGIC)
 921                return -EAGAIN;
 922
 923        apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
 924        if (!(apedata & APE_FW_STATUS_READY))
 925                return -EAGAIN;
 926
 927        /* Wait for up to 20 millisecond for APE to service previous event. */
 928        err = tg3_ape_event_lock(tp, 20000);
 929        if (err)
 930                return err;
 931
 932        tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
 933                        event | APE_EVENT_STATUS_EVENT_PENDING);
 934
 935        tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
 936        tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
 937
 938        return 0;
 939}
 940
 941static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
 942{
 943        u32 event;
 944        u32 apedata;
 945
 946        if (!tg3_flag(tp, ENABLE_APE))
 947                return;
 948
 949        switch (kind) {
 950        case RESET_KIND_INIT:
 951                tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
 952                tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
 953                                APE_HOST_SEG_SIG_MAGIC);
 954                tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
 955                                APE_HOST_SEG_LEN_MAGIC);
 956                apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
 957                tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
 958                tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
 959                        APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
 960                tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
 961                                APE_HOST_BEHAV_NO_PHYLOCK);
 962                tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
 963                                    TG3_APE_HOST_DRVR_STATE_START);
 964
 965                event = APE_EVENT_STATUS_STATE_START;
 966                break;
 967        case RESET_KIND_SHUTDOWN:
 968                if (device_may_wakeup(&tp->pdev->dev) &&
 969                    tg3_flag(tp, WOL_ENABLE)) {
 970                        tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
 971                                            TG3_APE_HOST_WOL_SPEED_AUTO);
 972                        apedata = TG3_APE_HOST_DRVR_STATE_WOL;
 973                } else
 974                        apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
 975
 976                tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
 977
 978                event = APE_EVENT_STATUS_STATE_UNLOAD;
 979                break;
 980        default:
 981                return;
 982        }
 983
 984        event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
 985
 986        tg3_ape_send_event(tp, event);
 987}
 988
 989static void tg3_send_ape_heartbeat(struct tg3 *tp,
 990                                   unsigned long interval)
 991{
 992        /* Check if hb interval has exceeded */
 993        if (!tg3_flag(tp, ENABLE_APE) ||
 994            time_before(jiffies, tp->ape_hb_jiffies + interval))
 995                return;
 996
 997        tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
 998        tp->ape_hb_jiffies = jiffies;
 999}
1000
1001static void tg3_disable_ints(struct tg3 *tp)
1002{
1003        int i;
1004
1005        tw32(TG3PCI_MISC_HOST_CTRL,
1006             (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
1007        for (i = 0; i < tp->irq_max; i++)
1008                tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1009}
1010
1011static void tg3_enable_ints(struct tg3 *tp)
1012{
1013        int i;
1014
1015        tp->irq_sync = 0;
1016        wmb();
1017
1018        tw32(TG3PCI_MISC_HOST_CTRL,
1019             (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1020
1021        tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1022        for (i = 0; i < tp->irq_cnt; i++) {
1023                struct tg3_napi *tnapi = &tp->napi[i];
1024
1025                tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1026                if (tg3_flag(tp, 1SHOT_MSI))
1027                        tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1028
1029                tp->coal_now |= tnapi->coal_now;
1030        }
1031
1032        /* Force an initial interrupt */
1033        if (!tg3_flag(tp, TAGGED_STATUS) &&
1034            (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1035                tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1036        else
1037                tw32(HOSTCC_MODE, tp->coal_now);
1038
1039        tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1040}
1041
1042static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1043{
1044        struct tg3 *tp = tnapi->tp;
1045        struct tg3_hw_status *sblk = tnapi->hw_status;
1046        unsigned int work_exists = 0;
1047
1048        /* check for phy events */
1049        if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1050                if (sblk->status & SD_STATUS_LINK_CHG)
1051                        work_exists = 1;
1052        }
1053
1054        /* check for TX work to do */
1055        if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1056                work_exists = 1;
1057
1058        /* check for RX work to do */
1059        if (tnapi->rx_rcb_prod_idx &&
1060            *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1061                work_exists = 1;
1062
1063        return work_exists;
1064}
1065
1066/* tg3_int_reenable
1067 *  similar to tg3_enable_ints, but it accurately determines whether there
1068 *  is new work pending and can return without flushing the PIO write
1069 *  which reenables interrupts
1070 */
1071static void tg3_int_reenable(struct tg3_napi *tnapi)
1072{
1073        struct tg3 *tp = tnapi->tp;
1074
1075        tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1076
1077        /* When doing tagged status, this work check is unnecessary.
1078         * The last_tag we write above tells the chip which piece of
1079         * work we've completed.
1080         */
1081        if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1082                tw32(HOSTCC_MODE, tp->coalesce_mode |
1083                     HOSTCC_MODE_ENABLE | tnapi->coal_now);
1084}
1085
1086static void tg3_switch_clocks(struct tg3 *tp)
1087{
1088        u32 clock_ctrl;
1089        u32 orig_clock_ctrl;
1090
1091        if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1092                return;
1093
1094        clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1095
1096        orig_clock_ctrl = clock_ctrl;
1097        clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1098                       CLOCK_CTRL_CLKRUN_OENABLE |
1099                       0x1f);
1100        tp->pci_clock_ctrl = clock_ctrl;
1101
1102        if (tg3_flag(tp, 5705_PLUS)) {
1103                if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1104                        tw32_wait_f(TG3PCI_CLOCK_CTRL,
1105                                    clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1106                }
1107        } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1108                tw32_wait_f(TG3PCI_CLOCK_CTRL,
1109                            clock_ctrl |
1110                            (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1111                            40);
1112                tw32_wait_f(TG3PCI_CLOCK_CTRL,
1113                            clock_ctrl | (CLOCK_CTRL_ALTCLK),
1114                            40);
1115        }
1116        tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1117}
1118
1119#define PHY_BUSY_LOOPS  5000
1120
1121static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1122                         u32 *val)
1123{
1124        u32 frame_val;
1125        unsigned int loops;
1126        int ret;
1127
1128        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1129                tw32_f(MAC_MI_MODE,
1130                     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1131                udelay(80);
1132        }
1133
1134        tg3_ape_lock(tp, tp->phy_ape_lock);
1135
1136        *val = 0x0;
1137
1138        frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1139                      MI_COM_PHY_ADDR_MASK);
1140        frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1141                      MI_COM_REG_ADDR_MASK);
1142        frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1143
1144        tw32_f(MAC_MI_COM, frame_val);
1145
1146        loops = PHY_BUSY_LOOPS;
1147        while (loops != 0) {
1148                udelay(10);
1149                frame_val = tr32(MAC_MI_COM);
1150
1151                if ((frame_val & MI_COM_BUSY) == 0) {
1152                        udelay(5);
1153                        frame_val = tr32(MAC_MI_COM);
1154                        break;
1155                }
1156                loops -= 1;
1157        }
1158
1159        ret = -EBUSY;
1160        if (loops != 0) {
1161                *val = frame_val & MI_COM_DATA_MASK;
1162                ret = 0;
1163        }
1164
1165        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1166                tw32_f(MAC_MI_MODE, tp->mi_mode);
1167                udelay(80);
1168        }
1169
1170        tg3_ape_unlock(tp, tp->phy_ape_lock);
1171
1172        return ret;
1173}
1174
1175static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1176{
1177        return __tg3_readphy(tp, tp->phy_addr, reg, val);
1178}
1179
1180static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1181                          u32 val)
1182{
1183        u32 frame_val;
1184        unsigned int loops;
1185        int ret;
1186
1187        if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1188            (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1189                return 0;
1190
1191        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1192                tw32_f(MAC_MI_MODE,
1193                     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1194                udelay(80);
1195        }
1196
1197        tg3_ape_lock(tp, tp->phy_ape_lock);
1198
1199        frame_val  = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1200                      MI_COM_PHY_ADDR_MASK);
1201        frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1202                      MI_COM_REG_ADDR_MASK);
1203        frame_val |= (val & MI_COM_DATA_MASK);
1204        frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1205
1206        tw32_f(MAC_MI_COM, frame_val);
1207
1208        loops = PHY_BUSY_LOOPS;
1209        while (loops != 0) {
1210                udelay(10);
1211                frame_val = tr32(MAC_MI_COM);
1212                if ((frame_val & MI_COM_BUSY) == 0) {
1213                        udelay(5);
1214                        frame_val = tr32(MAC_MI_COM);
1215                        break;
1216                }
1217                loops -= 1;
1218        }
1219
1220        ret = -EBUSY;
1221        if (loops != 0)
1222                ret = 0;
1223
1224        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1225                tw32_f(MAC_MI_MODE, tp->mi_mode);
1226                udelay(80);
1227        }
1228
1229        tg3_ape_unlock(tp, tp->phy_ape_lock);
1230
1231        return ret;
1232}
1233
1234static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1235{
1236        return __tg3_writephy(tp, tp->phy_addr, reg, val);
1237}
1238
1239static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1240{
1241        int err;
1242
1243        err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1244        if (err)
1245                goto done;
1246
1247        err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1248        if (err)
1249                goto done;
1250
1251        err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1252                           MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1253        if (err)
1254                goto done;
1255
1256        err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1257
1258done:
1259        return err;
1260}
1261
1262static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1263{
1264        int err;
1265
1266        err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1267        if (err)
1268                goto done;
1269
1270        err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1271        if (err)
1272                goto done;
1273
1274        err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1275                           MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1276        if (err)
1277                goto done;
1278
1279        err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1280
1281done:
1282        return err;
1283}
1284
1285static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1286{
1287        int err;
1288
1289        err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290        if (!err)
1291                err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1292
1293        return err;
1294}
1295
1296static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1297{
1298        int err;
1299
1300        err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1301        if (!err)
1302                err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1303
1304        return err;
1305}
1306
1307static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1308{
1309        int err;
1310
1311        err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1312                           (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1313                           MII_TG3_AUXCTL_SHDWSEL_MISC);
1314        if (!err)
1315                err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1316
1317        return err;
1318}
1319
1320static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1321{
1322        if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1323                set |= MII_TG3_AUXCTL_MISC_WREN;
1324
1325        return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1326}
1327
1328static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1329{
1330        u32 val;
1331        int err;
1332
1333        err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1334
1335        if (err)
1336                return err;
1337
1338        if (enable)
1339                val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1340        else
1341                val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1342
1343        err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1344                                   val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1345
1346        return err;
1347}
1348
1349static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1350{
1351        return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1352                            reg | val | MII_TG3_MISC_SHDW_WREN);
1353}
1354
1355static int tg3_bmcr_reset(struct tg3 *tp)
1356{
1357        u32 phy_control;
1358        int limit, err;
1359
1360        /* OK, reset it, and poll the BMCR_RESET bit until it
1361         * clears or we time out.
1362         */
1363        phy_control = BMCR_RESET;
1364        err = tg3_writephy(tp, MII_BMCR, phy_control);
1365        if (err != 0)
1366                return -EBUSY;
1367
1368        limit = 5000;
1369        while (limit--) {
1370                err = tg3_readphy(tp, MII_BMCR, &phy_control);
1371                if (err != 0)
1372                        return -EBUSY;
1373
1374                if ((phy_control & BMCR_RESET) == 0) {
1375                        udelay(40);
1376                        break;
1377                }
1378                udelay(10);
1379        }
1380        if (limit < 0)
1381                return -EBUSY;
1382
1383        return 0;
1384}
1385
1386static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1387{
1388        struct tg3 *tp = bp->priv;
1389        u32 val;
1390
1391        spin_lock_bh(&tp->lock);
1392
1393        if (__tg3_readphy(tp, mii_id, reg, &val))
1394                val = -EIO;
1395
1396        spin_unlock_bh(&tp->lock);
1397
1398        return val;
1399}
1400
1401static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1402{
1403        struct tg3 *tp = bp->priv;
1404        u32 ret = 0;
1405
1406        spin_lock_bh(&tp->lock);
1407
1408        if (__tg3_writephy(tp, mii_id, reg, val))
1409                ret = -EIO;
1410
1411        spin_unlock_bh(&tp->lock);
1412
1413        return ret;
1414}
1415
1416static void tg3_mdio_config_5785(struct tg3 *tp)
1417{
1418        u32 val;
1419        struct phy_device *phydev;
1420
1421        phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1422        switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1423        case PHY_ID_BCM50610:
1424        case PHY_ID_BCM50610M:
1425                val = MAC_PHYCFG2_50610_LED_MODES;
1426                break;
1427        case PHY_ID_BCMAC131:
1428                val = MAC_PHYCFG2_AC131_LED_MODES;
1429                break;
1430        case PHY_ID_RTL8211C:
1431                val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1432                break;
1433        case PHY_ID_RTL8201E:
1434                val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1435                break;
1436        default:
1437                return;
1438        }
1439
1440        if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1441                tw32(MAC_PHYCFG2, val);
1442
1443                val = tr32(MAC_PHYCFG1);
1444                val &= ~(MAC_PHYCFG1_RGMII_INT |
1445                         MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1446                val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1447                tw32(MAC_PHYCFG1, val);
1448
1449                return;
1450        }
1451
1452        if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1453                val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1454                       MAC_PHYCFG2_FMODE_MASK_MASK |
1455                       MAC_PHYCFG2_GMODE_MASK_MASK |
1456                       MAC_PHYCFG2_ACT_MASK_MASK   |
1457                       MAC_PHYCFG2_QUAL_MASK_MASK |
1458                       MAC_PHYCFG2_INBAND_ENABLE;
1459
1460        tw32(MAC_PHYCFG2, val);
1461
1462        val = tr32(MAC_PHYCFG1);
1463        val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1464                 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1465        if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1466                if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1467                        val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1468                if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1469                        val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1470        }
1471        val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1472               MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1473        tw32(MAC_PHYCFG1, val);
1474
1475        val = tr32(MAC_EXT_RGMII_MODE);
1476        val &= ~(MAC_RGMII_MODE_RX_INT_B |
1477                 MAC_RGMII_MODE_RX_QUALITY |
1478                 MAC_RGMII_MODE_RX_ACTIVITY |
1479                 MAC_RGMII_MODE_RX_ENG_DET |
1480                 MAC_RGMII_MODE_TX_ENABLE |
1481                 MAC_RGMII_MODE_TX_LOWPWR |
1482                 MAC_RGMII_MODE_TX_RESET);
1483        if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1484                if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1485                        val |= MAC_RGMII_MODE_RX_INT_B |
1486                               MAC_RGMII_MODE_RX_QUALITY |
1487                               MAC_RGMII_MODE_RX_ACTIVITY |
1488                               MAC_RGMII_MODE_RX_ENG_DET;
1489                if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1490                        val |= MAC_RGMII_MODE_TX_ENABLE |
1491                               MAC_RGMII_MODE_TX_LOWPWR |
1492                               MAC_RGMII_MODE_TX_RESET;
1493        }
1494        tw32(MAC_EXT_RGMII_MODE, val);
1495}
1496
1497static void tg3_mdio_start(struct tg3 *tp)
1498{
1499        tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1500        tw32_f(MAC_MI_MODE, tp->mi_mode);
1501        udelay(80);
1502
1503        if (tg3_flag(tp, MDIOBUS_INITED) &&
1504            tg3_asic_rev(tp) == ASIC_REV_5785)
1505                tg3_mdio_config_5785(tp);
1506}
1507
1508static int tg3_mdio_init(struct tg3 *tp)
1509{
1510        int i;
1511        u32 reg;
1512        struct phy_device *phydev;
1513
1514        if (tg3_flag(tp, 5717_PLUS)) {
1515                u32 is_serdes;
1516
1517                tp->phy_addr = tp->pci_fn + 1;
1518
1519                if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1520                        is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1521                else
1522                        is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1523                                    TG3_CPMU_PHY_STRAP_IS_SERDES;
1524                if (is_serdes)
1525                        tp->phy_addr += 7;
1526        } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1527                int addr;
1528
1529                addr = ssb_gige_get_phyaddr(tp->pdev);
1530                if (addr < 0)
1531                        return addr;
1532                tp->phy_addr = addr;
1533        } else
1534                tp->phy_addr = TG3_PHY_MII_ADDR;
1535
1536        tg3_mdio_start(tp);
1537
1538        if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1539                return 0;
1540
1541        tp->mdio_bus = mdiobus_alloc();
1542        if (tp->mdio_bus == NULL)
1543                return -ENOMEM;
1544
1545        tp->mdio_bus->name     = "tg3 mdio bus";
1546        snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1547                 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1548        tp->mdio_bus->priv     = tp;
1549        tp->mdio_bus->parent   = &tp->pdev->dev;
1550        tp->mdio_bus->read     = &tg3_mdio_read;
1551        tp->mdio_bus->write    = &tg3_mdio_write;
1552        tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1553
1554        /* The bus registration will look for all the PHYs on the mdio bus.
1555         * Unfortunately, it does not ensure the PHY is powered up before
1556         * accessing the PHY ID registers.  A chip reset is the
1557         * quickest way to bring the device back to an operational state..
1558         */
1559        if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1560                tg3_bmcr_reset(tp);
1561
1562        i = mdiobus_register(tp->mdio_bus);
1563        if (i) {
1564                dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1565                mdiobus_free(tp->mdio_bus);
1566                return i;
1567        }
1568
1569        phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1570
1571        if (!phydev || !phydev->drv) {
1572                dev_warn(&tp->pdev->dev, "No PHY devices\n");
1573                mdiobus_unregister(tp->mdio_bus);
1574                mdiobus_free(tp->mdio_bus);
1575                return -ENODEV;
1576        }
1577
1578        switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1579        case PHY_ID_BCM57780:
1580                phydev->interface = PHY_INTERFACE_MODE_GMII;
1581                phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1582                break;
1583        case PHY_ID_BCM50610:
1584        case PHY_ID_BCM50610M:
1585                phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1586                                     PHY_BRCM_RX_REFCLK_UNUSED |
1587                                     PHY_BRCM_DIS_TXCRXC_NOENRGY |
1588                                     PHY_BRCM_AUTO_PWRDWN_ENABLE;
1589                if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1590                        phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1591                if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1592                        phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1593                if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1594                        phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1595                /* fall through */
1596        case PHY_ID_RTL8211C:
1597                phydev->interface = PHY_INTERFACE_MODE_RGMII;
1598                break;
1599        case PHY_ID_RTL8201E:
1600        case PHY_ID_BCMAC131:
1601                phydev->interface = PHY_INTERFACE_MODE_MII;
1602                phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1603                tp->phy_flags |= TG3_PHYFLG_IS_FET;
1604                break;
1605        }
1606
1607        tg3_flag_set(tp, MDIOBUS_INITED);
1608
1609        if (tg3_asic_rev(tp) == ASIC_REV_5785)
1610                tg3_mdio_config_5785(tp);
1611
1612        return 0;
1613}
1614
1615static void tg3_mdio_fini(struct tg3 *tp)
1616{
1617        if (tg3_flag(tp, MDIOBUS_INITED)) {
1618                tg3_flag_clear(tp, MDIOBUS_INITED);
1619                mdiobus_unregister(tp->mdio_bus);
1620                mdiobus_free(tp->mdio_bus);
1621        }
1622}
1623
1624/* tp->lock is held. */
1625static inline void tg3_generate_fw_event(struct tg3 *tp)
1626{
1627        u32 val;
1628
1629        val = tr32(GRC_RX_CPU_EVENT);
1630        val |= GRC_RX_CPU_DRIVER_EVENT;
1631        tw32_f(GRC_RX_CPU_EVENT, val);
1632
1633        tp->last_event_jiffies = jiffies;
1634}
1635
1636#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1637
1638/* tp->lock is held. */
1639static void tg3_wait_for_event_ack(struct tg3 *tp)
1640{
1641        int i;
1642        unsigned int delay_cnt;
1643        long time_remain;
1644
1645        /* If enough time has passed, no wait is necessary. */
1646        time_remain = (long)(tp->last_event_jiffies + 1 +
1647                      usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1648                      (long)jiffies;
1649        if (time_remain < 0)
1650                return;
1651
1652        /* Check if we can shorten the wait time. */
1653        delay_cnt = jiffies_to_usecs(time_remain);
1654        if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1655                delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1656        delay_cnt = (delay_cnt >> 3) + 1;
1657
1658        for (i = 0; i < delay_cnt; i++) {
1659                if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1660                        break;
1661                if (pci_channel_offline(tp->pdev))
1662                        break;
1663
1664                udelay(8);
1665        }
1666}
1667
1668/* tp->lock is held. */
1669static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1670{
1671        u32 reg, val;
1672
1673        val = 0;
1674        if (!tg3_readphy(tp, MII_BMCR, &reg))
1675                val = reg << 16;
1676        if (!tg3_readphy(tp, MII_BMSR, &reg))
1677                val |= (reg & 0xffff);
1678        *data++ = val;
1679
1680        val = 0;
1681        if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1682                val = reg << 16;
1683        if (!tg3_readphy(tp, MII_LPA, &reg))
1684                val |= (reg & 0xffff);
1685        *data++ = val;
1686
1687        val = 0;
1688        if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1689                if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1690                        val = reg << 16;
1691                if (!tg3_readphy(tp, MII_STAT1000, &reg))
1692                        val |= (reg & 0xffff);
1693        }
1694        *data++ = val;
1695
1696        if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1697                val = reg << 16;
1698        else
1699                val = 0;
1700        *data++ = val;
1701}
1702
1703/* tp->lock is held. */
1704static void tg3_ump_link_report(struct tg3 *tp)
1705{
1706        u32 data[4];
1707
1708        if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1709                return;
1710
1711        tg3_phy_gather_ump_data(tp, data);
1712
1713        tg3_wait_for_event_ack(tp);
1714
1715        tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1716        tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1717        tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1718        tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1719        tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1720        tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1721
1722        tg3_generate_fw_event(tp);
1723}
1724
1725/* tp->lock is held. */
1726static void tg3_stop_fw(struct tg3 *tp)
1727{
1728        if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1729                /* Wait for RX cpu to ACK the previous event. */
1730                tg3_wait_for_event_ack(tp);
1731
1732                tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1733
1734                tg3_generate_fw_event(tp);
1735
1736                /* Wait for RX cpu to ACK this event. */
1737                tg3_wait_for_event_ack(tp);
1738        }
1739}
1740
1741/* tp->lock is held. */
1742static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1743{
1744        tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1745                      NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1746
1747        if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1748                switch (kind) {
1749                case RESET_KIND_INIT:
1750                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1751                                      DRV_STATE_START);
1752                        break;
1753
1754                case RESET_KIND_SHUTDOWN:
1755                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1756                                      DRV_STATE_UNLOAD);
1757                        break;
1758
1759                case RESET_KIND_SUSPEND:
1760                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1761                                      DRV_STATE_SUSPEND);
1762                        break;
1763
1764                default:
1765                        break;
1766                }
1767        }
1768}
1769
1770/* tp->lock is held. */
1771static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1772{
1773        if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1774                switch (kind) {
1775                case RESET_KIND_INIT:
1776                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1777                                      DRV_STATE_START_DONE);
1778                        break;
1779
1780                case RESET_KIND_SHUTDOWN:
1781                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1782                                      DRV_STATE_UNLOAD_DONE);
1783                        break;
1784
1785                default:
1786                        break;
1787                }
1788        }
1789}
1790
1791/* tp->lock is held. */
1792static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1793{
1794        if (tg3_flag(tp, ENABLE_ASF)) {
1795                switch (kind) {
1796                case RESET_KIND_INIT:
1797                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798                                      DRV_STATE_START);
1799                        break;
1800
1801                case RESET_KIND_SHUTDOWN:
1802                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1803                                      DRV_STATE_UNLOAD);
1804                        break;
1805
1806                case RESET_KIND_SUSPEND:
1807                        tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1808                                      DRV_STATE_SUSPEND);
1809                        break;
1810
1811                default:
1812                        break;
1813                }
1814        }
1815}
1816
1817static int tg3_poll_fw(struct tg3 *tp)
1818{
1819        int i;
1820        u32 val;
1821
1822        if (tg3_flag(tp, NO_FWARE_REPORTED))
1823                return 0;
1824
1825        if (tg3_flag(tp, IS_SSB_CORE)) {
1826                /* We don't use firmware. */
1827                return 0;
1828        }
1829
1830        if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1831                /* Wait up to 20ms for init done. */
1832                for (i = 0; i < 200; i++) {
1833                        if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1834                                return 0;
1835                        if (pci_channel_offline(tp->pdev))
1836                                return -ENODEV;
1837
1838                        udelay(100);
1839                }
1840                return -ENODEV;
1841        }
1842
1843        /* Wait for firmware initialization to complete. */
1844        for (i = 0; i < 100000; i++) {
1845                tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1846                if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1847                        break;
1848                if (pci_channel_offline(tp->pdev)) {
1849                        if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1850                                tg3_flag_set(tp, NO_FWARE_REPORTED);
1851                                netdev_info(tp->dev, "No firmware running\n");
1852                        }
1853
1854                        break;
1855                }
1856
1857                udelay(10);
1858        }
1859
1860        /* Chip might not be fitted with firmware.  Some Sun onboard
1861         * parts are configured like that.  So don't signal the timeout
1862         * of the above loop as an error, but do report the lack of
1863         * running firmware once.
1864         */
1865        if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1866                tg3_flag_set(tp, NO_FWARE_REPORTED);
1867
1868                netdev_info(tp->dev, "No firmware running\n");
1869        }
1870
1871        if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1872                /* The 57765 A0 needs a little more
1873                 * time to do some important work.
1874                 */
1875                mdelay(10);
1876        }
1877
1878        return 0;
1879}
1880
1881static void tg3_link_report(struct tg3 *tp)
1882{
1883        if (!netif_carrier_ok(tp->dev)) {
1884                netif_info(tp, link, tp->dev, "Link is down\n");
1885                tg3_ump_link_report(tp);
1886        } else if (netif_msg_link(tp)) {
1887                netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1888                            (tp->link_config.active_speed == SPEED_1000 ?
1889                             1000 :
1890                             (tp->link_config.active_speed == SPEED_100 ?
1891                              100 : 10)),
1892                            (tp->link_config.active_duplex == DUPLEX_FULL ?
1893                             "full" : "half"));
1894
1895                netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1896                            (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1897                            "on" : "off",
1898                            (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1899                            "on" : "off");
1900
1901                if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1902                        netdev_info(tp->dev, "EEE is %s\n",
1903                                    tp->setlpicnt ? "enabled" : "disabled");
1904
1905                tg3_ump_link_report(tp);
1906        }
1907
1908        tp->link_up = netif_carrier_ok(tp->dev);
1909}
1910
1911static u32 tg3_decode_flowctrl_1000T(u32 adv)
1912{
1913        u32 flowctrl = 0;
1914
1915        if (adv & ADVERTISE_PAUSE_CAP) {
1916                flowctrl |= FLOW_CTRL_RX;
1917                if (!(adv & ADVERTISE_PAUSE_ASYM))
1918                        flowctrl |= FLOW_CTRL_TX;
1919        } else if (adv & ADVERTISE_PAUSE_ASYM)
1920                flowctrl |= FLOW_CTRL_TX;
1921
1922        return flowctrl;
1923}
1924
1925static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1926{
1927        u16 miireg;
1928
1929        if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1930                miireg = ADVERTISE_1000XPAUSE;
1931        else if (flow_ctrl & FLOW_CTRL_TX)
1932                miireg = ADVERTISE_1000XPSE_ASYM;
1933        else if (flow_ctrl & FLOW_CTRL_RX)
1934                miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1935        else
1936                miireg = 0;
1937
1938        return miireg;
1939}
1940
1941static u32 tg3_decode_flowctrl_1000X(u32 adv)
1942{
1943        u32 flowctrl = 0;
1944
1945        if (adv & ADVERTISE_1000XPAUSE) {
1946                flowctrl |= FLOW_CTRL_RX;
1947                if (!(adv & ADVERTISE_1000XPSE_ASYM))
1948                        flowctrl |= FLOW_CTRL_TX;
1949        } else if (adv & ADVERTISE_1000XPSE_ASYM)
1950                flowctrl |= FLOW_CTRL_TX;
1951
1952        return flowctrl;
1953}
1954
1955static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1956{
1957        u8 cap = 0;
1958
1959        if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1960                cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1961        } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1962                if (lcladv & ADVERTISE_1000XPAUSE)
1963                        cap = FLOW_CTRL_RX;
1964                if (rmtadv & ADVERTISE_1000XPAUSE)
1965                        cap = FLOW_CTRL_TX;
1966        }
1967
1968        return cap;
1969}
1970
1971static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1972{
1973        u8 autoneg;
1974        u8 flowctrl = 0;
1975        u32 old_rx_mode = tp->rx_mode;
1976        u32 old_tx_mode = tp->tx_mode;
1977
1978        if (tg3_flag(tp, USE_PHYLIB))
1979                autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1980        else
1981                autoneg = tp->link_config.autoneg;
1982
1983        if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1984                if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1985                        flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1986                else
1987                        flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1988        } else
1989                flowctrl = tp->link_config.flowctrl;
1990
1991        tp->link_config.active_flowctrl = flowctrl;
1992
1993        if (flowctrl & FLOW_CTRL_RX)
1994                tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1995        else
1996                tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1997
1998        if (old_rx_mode != tp->rx_mode)
1999                tw32_f(MAC_RX_MODE, tp->rx_mode);
2000
2001        if (flowctrl & FLOW_CTRL_TX)
2002                tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
2003        else
2004                tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2005
2006        if (old_tx_mode != tp->tx_mode)
2007                tw32_f(MAC_TX_MODE, tp->tx_mode);
2008}
2009
2010static void tg3_adjust_link(struct net_device *dev)
2011{
2012        u8 oldflowctrl, linkmesg = 0;
2013        u32 mac_mode, lcl_adv, rmt_adv;
2014        struct tg3 *tp = netdev_priv(dev);
2015        struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2016
2017        spin_lock_bh(&tp->lock);
2018
2019        mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2020                                    MAC_MODE_HALF_DUPLEX);
2021
2022        oldflowctrl = tp->link_config.active_flowctrl;
2023
2024        if (phydev->link) {
2025                lcl_adv = 0;
2026                rmt_adv = 0;
2027
2028                if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2029                        mac_mode |= MAC_MODE_PORT_MODE_MII;
2030                else if (phydev->speed == SPEED_1000 ||
2031                         tg3_asic_rev(tp) != ASIC_REV_5785)
2032                        mac_mode |= MAC_MODE_PORT_MODE_GMII;
2033                else
2034                        mac_mode |= MAC_MODE_PORT_MODE_MII;
2035
2036                if (phydev->duplex == DUPLEX_HALF)
2037                        mac_mode |= MAC_MODE_HALF_DUPLEX;
2038                else {
2039                        lcl_adv = mii_advertise_flowctrl(
2040                                  tp->link_config.flowctrl);
2041
2042                        if (phydev->pause)
2043                                rmt_adv = LPA_PAUSE_CAP;
2044                        if (phydev->asym_pause)
2045                                rmt_adv |= LPA_PAUSE_ASYM;
2046                }
2047
2048                tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2049        } else
2050                mac_mode |= MAC_MODE_PORT_MODE_GMII;
2051
2052        if (mac_mode != tp->mac_mode) {
2053                tp->mac_mode = mac_mode;
2054                tw32_f(MAC_MODE, tp->mac_mode);
2055                udelay(40);
2056        }
2057
2058        if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2059                if (phydev->speed == SPEED_10)
2060                        tw32(MAC_MI_STAT,
2061                             MAC_MI_STAT_10MBPS_MODE |
2062                             MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2063                else
2064                        tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2065        }
2066
2067        if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2068                tw32(MAC_TX_LENGTHS,
2069                     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2070                      (6 << TX_LENGTHS_IPG_SHIFT) |
2071                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2072        else
2073                tw32(MAC_TX_LENGTHS,
2074                     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2075                      (6 << TX_LENGTHS_IPG_SHIFT) |
2076                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2077
2078        if (phydev->link != tp->old_link ||
2079            phydev->speed != tp->link_config.active_speed ||
2080            phydev->duplex != tp->link_config.active_duplex ||
2081            oldflowctrl != tp->link_config.active_flowctrl)
2082                linkmesg = 1;
2083
2084        tp->old_link = phydev->link;
2085        tp->link_config.active_speed = phydev->speed;
2086        tp->link_config.active_duplex = phydev->duplex;
2087
2088        spin_unlock_bh(&tp->lock);
2089
2090        if (linkmesg)
2091                tg3_link_report(tp);
2092}
2093
2094static int tg3_phy_init(struct tg3 *tp)
2095{
2096        struct phy_device *phydev;
2097
2098        if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2099                return 0;
2100
2101        /* Bring the PHY back to a known state. */
2102        tg3_bmcr_reset(tp);
2103
2104        phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2105
2106        /* Attach the MAC to the PHY. */
2107        phydev = phy_connect(tp->dev, phydev_name(phydev),
2108                             tg3_adjust_link, phydev->interface);
2109        if (IS_ERR(phydev)) {
2110                dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2111                return PTR_ERR(phydev);
2112        }
2113
2114        /* Mask with MAC supported features. */
2115        switch (phydev->interface) {
2116        case PHY_INTERFACE_MODE_GMII:
2117        case PHY_INTERFACE_MODE_RGMII:
2118                if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2119                        phy_set_max_speed(phydev, SPEED_1000);
2120                        phy_support_asym_pause(phydev);
2121                        break;
2122                }
2123                /* fall through */
2124        case PHY_INTERFACE_MODE_MII:
2125                phy_set_max_speed(phydev, SPEED_100);
2126                phy_support_asym_pause(phydev);
2127                break;
2128        default:
2129                phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2130                return -EINVAL;
2131        }
2132
2133        tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2134
2135        phy_attached_info(phydev);
2136
2137        return 0;
2138}
2139
2140static void tg3_phy_start(struct tg3 *tp)
2141{
2142        struct phy_device *phydev;
2143
2144        if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2145                return;
2146
2147        phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2148
2149        if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2150                tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2151                phydev->speed = tp->link_config.speed;
2152                phydev->duplex = tp->link_config.duplex;
2153                phydev->autoneg = tp->link_config.autoneg;
2154                ethtool_convert_legacy_u32_to_link_mode(
2155                        phydev->advertising, tp->link_config.advertising);
2156        }
2157
2158        phy_start(phydev);
2159
2160        phy_start_aneg(phydev);
2161}
2162
2163static void tg3_phy_stop(struct tg3 *tp)
2164{
2165        if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2166                return;
2167
2168        phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2169}
2170
2171static void tg3_phy_fini(struct tg3 *tp)
2172{
2173        if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2174                phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2175                tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2176        }
2177}
2178
2179static int tg3_phy_set_extloopbk(struct tg3 *tp)
2180{
2181        int err;
2182        u32 val;
2183
2184        if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2185                return 0;
2186
2187        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2188                /* Cannot do read-modify-write on 5401 */
2189                err = tg3_phy_auxctl_write(tp,
2190                                           MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2191                                           MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2192                                           0x4c20);
2193                goto done;
2194        }
2195
2196        err = tg3_phy_auxctl_read(tp,
2197                                  MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2198        if (err)
2199                return err;
2200
2201        val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2202        err = tg3_phy_auxctl_write(tp,
2203                                   MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2204
2205done:
2206        return err;
2207}
2208
2209static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2210{
2211        u32 phytest;
2212
2213        if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2214                u32 phy;
2215
2216                tg3_writephy(tp, MII_TG3_FET_TEST,
2217                             phytest | MII_TG3_FET_SHADOW_EN);
2218                if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2219                        if (enable)
2220                                phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2221                        else
2222                                phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2223                        tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2224                }
2225                tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2226        }
2227}
2228
2229static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2230{
2231        u32 reg;
2232
2233        if (!tg3_flag(tp, 5705_PLUS) ||
2234            (tg3_flag(tp, 5717_PLUS) &&
2235             (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2236                return;
2237
2238        if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2239                tg3_phy_fet_toggle_apd(tp, enable);
2240                return;
2241        }
2242
2243        reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2244              MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2245              MII_TG3_MISC_SHDW_SCR5_SDTL |
2246              MII_TG3_MISC_SHDW_SCR5_C125OE;
2247        if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2248                reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2249
2250        tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2251
2252
2253        reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2254        if (enable)
2255                reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2256
2257        tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2258}
2259
2260static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2261{
2262        u32 phy;
2263
2264        if (!tg3_flag(tp, 5705_PLUS) ||
2265            (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2266                return;
2267
2268        if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2269                u32 ephy;
2270
2271                if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2272                        u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2273
2274                        tg3_writephy(tp, MII_TG3_FET_TEST,
2275                                     ephy | MII_TG3_FET_SHADOW_EN);
2276                        if (!tg3_readphy(tp, reg, &phy)) {
2277                                if (enable)
2278                                        phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2279                                else
2280                                        phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2281                                tg3_writephy(tp, reg, phy);
2282                        }
2283                        tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2284                }
2285        } else {
2286                int ret;
2287
2288                ret = tg3_phy_auxctl_read(tp,
2289                                          MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2290                if (!ret) {
2291                        if (enable)
2292                                phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2293                        else
2294                                phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2295                        tg3_phy_auxctl_write(tp,
2296                                             MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2297                }
2298        }
2299}
2300
2301static void tg3_phy_set_wirespeed(struct tg3 *tp)
2302{
2303        int ret;
2304        u32 val;
2305
2306        if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2307                return;
2308
2309        ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2310        if (!ret)
2311                tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2312                                     val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2313}
2314
2315static void tg3_phy_apply_otp(struct tg3 *tp)
2316{
2317        u32 otp, phy;
2318
2319        if (!tp->phy_otp)
2320                return;
2321
2322        otp = tp->phy_otp;
2323
2324        if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2325                return;
2326
2327        phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2328        phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2329        tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2330
2331        phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2332              ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2333        tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2334
2335        phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2336        phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2337        tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2338
2339        phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2340        tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2341
2342        phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2343        tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2344
2345        phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2346              ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2347        tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2348
2349        tg3_phy_toggle_auxctl_smdsp(tp, false);
2350}
2351
2352static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2353{
2354        u32 val;
2355        struct ethtool_eee *dest = &tp->eee;
2356
2357        if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2358                return;
2359
2360        if (eee)
2361                dest = eee;
2362
2363        if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2364                return;
2365
2366        /* Pull eee_active */
2367        if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2368            val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2369                dest->eee_active = 1;
2370        } else
2371                dest->eee_active = 0;
2372
2373        /* Pull lp advertised settings */
2374        if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2375                return;
2376        dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377
2378        /* Pull advertised and eee_enabled settings */
2379        if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2380                return;
2381        dest->eee_enabled = !!val;
2382        dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2383
2384        /* Pull tx_lpi_enabled */
2385        val = tr32(TG3_CPMU_EEE_MODE);
2386        dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2387
2388        /* Pull lpi timer value */
2389        dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2390}
2391
2392static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2393{
2394        u32 val;
2395
2396        if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2397                return;
2398
2399        tp->setlpicnt = 0;
2400
2401        if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2402            current_link_up &&
2403            tp->link_config.active_duplex == DUPLEX_FULL &&
2404            (tp->link_config.active_speed == SPEED_100 ||
2405             tp->link_config.active_speed == SPEED_1000)) {
2406                u32 eeectl;
2407
2408                if (tp->link_config.active_speed == SPEED_1000)
2409                        eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2410                else
2411                        eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2412
2413                tw32(TG3_CPMU_EEE_CTRL, eeectl);
2414
2415                tg3_eee_pull_config(tp, NULL);
2416                if (tp->eee.eee_active)
2417                        tp->setlpicnt = 2;
2418        }
2419
2420        if (!tp->setlpicnt) {
2421                if (current_link_up &&
2422                   !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2423                        tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2424                        tg3_phy_toggle_auxctl_smdsp(tp, false);
2425                }
2426
2427                val = tr32(TG3_CPMU_EEE_MODE);
2428                tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2429        }
2430}
2431
2432static void tg3_phy_eee_enable(struct tg3 *tp)
2433{
2434        u32 val;
2435
2436        if (tp->link_config.active_speed == SPEED_1000 &&
2437            (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2438             tg3_asic_rev(tp) == ASIC_REV_5719 ||
2439             tg3_flag(tp, 57765_CLASS)) &&
2440            !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2441                val = MII_TG3_DSP_TAP26_ALNOKO |
2442                      MII_TG3_DSP_TAP26_RMRXSTO;
2443                tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2444                tg3_phy_toggle_auxctl_smdsp(tp, false);
2445        }
2446
2447        val = tr32(TG3_CPMU_EEE_MODE);
2448        tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2449}
2450
2451static int tg3_wait_macro_done(struct tg3 *tp)
2452{
2453        int limit = 100;
2454
2455        while (limit--) {
2456                u32 tmp32;
2457
2458                if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2459                        if ((tmp32 & 0x1000) == 0)
2460                                break;
2461                }
2462        }
2463        if (limit < 0)
2464                return -EBUSY;
2465
2466        return 0;
2467}
2468
2469static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2470{
2471        static const u32 test_pat[4][6] = {
2472        { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2473        { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2474        { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2475        { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2476        };
2477        int chan;
2478
2479        for (chan = 0; chan < 4; chan++) {
2480                int i;
2481
2482                tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2483                             (chan * 0x2000) | 0x0200);
2484                tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2485
2486                for (i = 0; i < 6; i++)
2487                        tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2488                                     test_pat[chan][i]);
2489
2490                tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2491                if (tg3_wait_macro_done(tp)) {
2492                        *resetp = 1;
2493                        return -EBUSY;
2494                }
2495
2496                tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2497                             (chan * 0x2000) | 0x0200);
2498                tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2499                if (tg3_wait_macro_done(tp)) {
2500                        *resetp = 1;
2501                        return -EBUSY;
2502                }
2503
2504                tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2505                if (tg3_wait_macro_done(tp)) {
2506                        *resetp = 1;
2507                        return -EBUSY;
2508                }
2509
2510                for (i = 0; i < 6; i += 2) {
2511                        u32 low, high;
2512
2513                        if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2514                            tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2515                            tg3_wait_macro_done(tp)) {
2516                                *resetp = 1;
2517                                return -EBUSY;
2518                        }
2519                        low &= 0x7fff;
2520                        high &= 0x000f;
2521                        if (low != test_pat[chan][i] ||
2522                            high != test_pat[chan][i+1]) {
2523                                tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2524                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2525                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2526
2527                                return -EBUSY;
2528                        }
2529                }
2530        }
2531
2532        return 0;
2533}
2534
2535static int tg3_phy_reset_chanpat(struct tg3 *tp)
2536{
2537        int chan;
2538
2539        for (chan = 0; chan < 4; chan++) {
2540                int i;
2541
2542                tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2543                             (chan * 0x2000) | 0x0200);
2544                tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2545                for (i = 0; i < 6; i++)
2546                        tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2547                tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2548                if (tg3_wait_macro_done(tp))
2549                        return -EBUSY;
2550        }
2551
2552        return 0;
2553}
2554
2555static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2556{
2557        u32 reg32, phy9_orig;
2558        int retries, do_phy_reset, err;
2559
2560        retries = 10;
2561        do_phy_reset = 1;
2562        do {
2563                if (do_phy_reset) {
2564                        err = tg3_bmcr_reset(tp);
2565                        if (err)
2566                                return err;
2567                        do_phy_reset = 0;
2568                }
2569
2570                /* Disable transmitter and interrupt.  */
2571                if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2572                        continue;
2573
2574                reg32 |= 0x3000;
2575                tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2576
2577                /* Set full-duplex, 1000 mbps.  */
2578                tg3_writephy(tp, MII_BMCR,
2579                             BMCR_FULLDPLX | BMCR_SPEED1000);
2580
2581                /* Set to master mode.  */
2582                if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2583                        continue;
2584
2585                tg3_writephy(tp, MII_CTRL1000,
2586                             CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2587
2588                err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2589                if (err)
2590                        return err;
2591
2592                /* Block the PHY control access.  */
2593                tg3_phydsp_write(tp, 0x8005, 0x0800);
2594
2595                err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2596                if (!err)
2597                        break;
2598        } while (--retries);
2599
2600        err = tg3_phy_reset_chanpat(tp);
2601        if (err)
2602                return err;
2603
2604        tg3_phydsp_write(tp, 0x8005, 0x0000);
2605
2606        tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2607        tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2608
2609        tg3_phy_toggle_auxctl_smdsp(tp, false);
2610
2611        tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2612
2613        err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
2614        if (err)
2615                return err;
2616
2617        reg32 &= ~0x3000;
2618        tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2619
2620        return 0;
2621}
2622
2623static void tg3_carrier_off(struct tg3 *tp)
2624{
2625        netif_carrier_off(tp->dev);
2626        tp->link_up = false;
2627}
2628
2629static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2630{
2631        if (tg3_flag(tp, ENABLE_ASF))
2632                netdev_warn(tp->dev,
2633                            "Management side-band traffic will be interrupted during phy settings change\n");
2634}
2635
2636/* This will reset the tigon3 PHY if there is no valid
2637 * link unless the FORCE argument is non-zero.
2638 */
2639static int tg3_phy_reset(struct tg3 *tp)
2640{
2641        u32 val, cpmuctrl;
2642        int err;
2643
2644        if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2645                val = tr32(GRC_MISC_CFG);
2646                tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2647                udelay(40);
2648        }
2649        err  = tg3_readphy(tp, MII_BMSR, &val);
2650        err |= tg3_readphy(tp, MII_BMSR, &val);
2651        if (err != 0)
2652                return -EBUSY;
2653
2654        if (netif_running(tp->dev) && tp->link_up) {
2655                netif_carrier_off(tp->dev);
2656                tg3_link_report(tp);
2657        }
2658
2659        if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2660            tg3_asic_rev(tp) == ASIC_REV_5704 ||
2661            tg3_asic_rev(tp) == ASIC_REV_5705) {
2662                err = tg3_phy_reset_5703_4_5(tp);
2663                if (err)
2664                        return err;
2665                goto out;
2666        }
2667
2668        cpmuctrl = 0;
2669        if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2670            tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2671                cpmuctrl = tr32(TG3_CPMU_CTRL);
2672                if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2673                        tw32(TG3_CPMU_CTRL,
2674                             cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2675        }
2676
2677        err = tg3_bmcr_reset(tp);
2678        if (err)
2679                return err;
2680
2681        if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2682                val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2683                tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2684
2685                tw32(TG3_CPMU_CTRL, cpmuctrl);
2686        }
2687
2688        if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2689            tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2690                val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2691                if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2692                    CPMU_LSPD_1000MB_MACCLK_12_5) {
2693                        val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2694                        udelay(40);
2695                        tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2696                }
2697        }
2698
2699        if (tg3_flag(tp, 5717_PLUS) &&
2700            (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2701                return 0;
2702
2703        tg3_phy_apply_otp(tp);
2704
2705        if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2706                tg3_phy_toggle_apd(tp, true);
2707        else
2708                tg3_phy_toggle_apd(tp, false);
2709
2710out:
2711        if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2712            !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2713                tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2714                tg3_phydsp_write(tp, 0x000a, 0x0323);
2715                tg3_phy_toggle_auxctl_smdsp(tp, false);
2716        }
2717
2718        if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2719                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2720                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2721        }
2722
2723        if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2724                if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2725                        tg3_phydsp_write(tp, 0x000a, 0x310b);
2726                        tg3_phydsp_write(tp, 0x201f, 0x9506);
2727                        tg3_phydsp_write(tp, 0x401f, 0x14e2);
2728                        tg3_phy_toggle_auxctl_smdsp(tp, false);
2729                }
2730        } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2731                if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2732                        tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2733                        if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2734                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2735                                tg3_writephy(tp, MII_TG3_TEST1,
2736                                             MII_TG3_TEST1_TRIM_EN | 0x4);
2737                        } else
2738                                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2739
2740                        tg3_phy_toggle_auxctl_smdsp(tp, false);
2741                }
2742        }
2743
2744        /* Set Extended packet length bit (bit 14) on all chips that */
2745        /* support jumbo frames */
2746        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2747                /* Cannot do read-modify-write on 5401 */
2748                tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2749        } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2750                /* Set bit 14 with read-modify-write to preserve other bits */
2751                err = tg3_phy_auxctl_read(tp,
2752                                          MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2753                if (!err)
2754                        tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2755                                           val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2756        }
2757
2758        /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2759         * jumbo frames transmission.
2760         */
2761        if (tg3_flag(tp, JUMBO_CAPABLE)) {
2762                if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2763                        tg3_writephy(tp, MII_TG3_EXT_CTRL,
2764                                     val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2765        }
2766
2767        if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2768                /* adjust output voltage */
2769                tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2770        }
2771
2772        if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2773                tg3_phydsp_write(tp, 0xffb, 0x4000);
2774
2775        tg3_phy_toggle_automdix(tp, true);
2776        tg3_phy_set_wirespeed(tp);
2777        return 0;
2778}
2779
2780#define TG3_GPIO_MSG_DRVR_PRES           0x00000001
2781#define TG3_GPIO_MSG_NEED_VAUX           0x00000002
2782#define TG3_GPIO_MSG_MASK                (TG3_GPIO_MSG_DRVR_PRES | \
2783                                          TG3_GPIO_MSG_NEED_VAUX)
2784#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2785        ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2786         (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2787         (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2788         (TG3_GPIO_MSG_DRVR_PRES << 12))
2789
2790#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2791        ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2792         (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2793         (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2794         (TG3_GPIO_MSG_NEED_VAUX << 12))
2795
2796static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2797{
2798        u32 status, shift;
2799
2800        if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2801            tg3_asic_rev(tp) == ASIC_REV_5719)
2802                status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2803        else
2804                status = tr32(TG3_CPMU_DRV_STATUS);
2805
2806        shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2807        status &= ~(TG3_GPIO_MSG_MASK << shift);
2808        status |= (newstat << shift);
2809
2810        if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2811            tg3_asic_rev(tp) == ASIC_REV_5719)
2812                tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2813        else
2814                tw32(TG3_CPMU_DRV_STATUS, status);
2815
2816        return status >> TG3_APE_GPIO_MSG_SHIFT;
2817}
2818
2819static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2820{
2821        if (!tg3_flag(tp, IS_NIC))
2822                return 0;
2823
2824        if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2825            tg3_asic_rev(tp) == ASIC_REV_5719 ||
2826            tg3_asic_rev(tp) == ASIC_REV_5720) {
2827                if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2828                        return -EIO;
2829
2830                tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2831
2832                tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2833                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2834
2835                tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2836        } else {
2837                tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2838                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2839        }
2840
2841        return 0;
2842}
2843
2844static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2845{
2846        u32 grc_local_ctrl;
2847
2848        if (!tg3_flag(tp, IS_NIC) ||
2849            tg3_asic_rev(tp) == ASIC_REV_5700 ||
2850            tg3_asic_rev(tp) == ASIC_REV_5701)
2851                return;
2852
2853        grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2854
2855        tw32_wait_f(GRC_LOCAL_CTRL,
2856                    grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2857                    TG3_GRC_LCLCTL_PWRSW_DELAY);
2858
2859        tw32_wait_f(GRC_LOCAL_CTRL,
2860                    grc_local_ctrl,
2861                    TG3_GRC_LCLCTL_PWRSW_DELAY);
2862
2863        tw32_wait_f(GRC_LOCAL_CTRL,
2864                    grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2865                    TG3_GRC_LCLCTL_PWRSW_DELAY);
2866}
2867
2868static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2869{
2870        if (!tg3_flag(tp, IS_NIC))
2871                return;
2872
2873        if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2874            tg3_asic_rev(tp) == ASIC_REV_5701) {
2875                tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2876                            (GRC_LCLCTRL_GPIO_OE0 |
2877                             GRC_LCLCTRL_GPIO_OE1 |
2878                             GRC_LCLCTRL_GPIO_OE2 |
2879                             GRC_LCLCTRL_GPIO_OUTPUT0 |
2880                             GRC_LCLCTRL_GPIO_OUTPUT1),
2881                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2882        } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2883                   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2884                /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2885                u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2886                                     GRC_LCLCTRL_GPIO_OE1 |
2887                                     GRC_LCLCTRL_GPIO_OE2 |
2888                                     GRC_LCLCTRL_GPIO_OUTPUT0 |
2889                                     GRC_LCLCTRL_GPIO_OUTPUT1 |
2890                                     tp->grc_local_ctrl;
2891                tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2892                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2893
2894                grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2895                tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2896                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2897
2898                grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2899                tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2900                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2901        } else {
2902                u32 no_gpio2;
2903                u32 grc_local_ctrl = 0;
2904
2905                /* Workaround to prevent overdrawing Amps. */
2906                if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2907                        grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2908                        tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2909                                    grc_local_ctrl,
2910                                    TG3_GRC_LCLCTL_PWRSW_DELAY);
2911                }
2912
2913                /* On 5753 and variants, GPIO2 cannot be used. */
2914                no_gpio2 = tp->nic_sram_data_cfg &
2915                           NIC_SRAM_DATA_CFG_NO_GPIO2;
2916
2917                grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2918                                  GRC_LCLCTRL_GPIO_OE1 |
2919                                  GRC_LCLCTRL_GPIO_OE2 |
2920                                  GRC_LCLCTRL_GPIO_OUTPUT1 |
2921                                  GRC_LCLCTRL_GPIO_OUTPUT2;
2922                if (no_gpio2) {
2923                        grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2924                                            GRC_LCLCTRL_GPIO_OUTPUT2);
2925                }
2926                tw32_wait_f(GRC_LOCAL_CTRL,
2927                            tp->grc_local_ctrl | grc_local_ctrl,
2928                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2929
2930                grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2931
2932                tw32_wait_f(GRC_LOCAL_CTRL,
2933                            tp->grc_local_ctrl | grc_local_ctrl,
2934                            TG3_GRC_LCLCTL_PWRSW_DELAY);
2935
2936                if (!no_gpio2) {
2937                        grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2938                        tw32_wait_f(GRC_LOCAL_CTRL,
2939                                    tp->grc_local_ctrl | grc_local_ctrl,
2940                                    TG3_GRC_LCLCTL_PWRSW_DELAY);
2941                }
2942        }
2943}
2944
2945static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2946{
2947        u32 msg = 0;
2948
2949        /* Serialize power state transitions */
2950        if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2951                return;
2952
2953        if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2954                msg = TG3_GPIO_MSG_NEED_VAUX;
2955
2956        msg = tg3_set_function_status(tp, msg);
2957
2958        if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2959                goto done;
2960
2961        if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2962                tg3_pwrsrc_switch_to_vaux(tp);
2963        else
2964                tg3_pwrsrc_die_with_vmain(tp);
2965
2966done:
2967        tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2968}
2969
2970static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2971{
2972        bool need_vaux = false;
2973
2974        /* The GPIOs do something completely different on 57765. */
2975        if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2976                return;
2977
2978        if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2979            tg3_asic_rev(tp) == ASIC_REV_5719 ||
2980            tg3_asic_rev(tp) == ASIC_REV_5720) {
2981                tg3_frob_aux_power_5717(tp, include_wol ?
2982                                        tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2983                return;
2984        }
2985
2986        if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2987                struct net_device *dev_peer;
2988
2989                dev_peer = pci_get_drvdata(tp->pdev_peer);
2990
2991                /* remove_one() may have been run on the peer. */
2992                if (dev_peer) {
2993                        struct tg3 *tp_peer = netdev_priv(dev_peer);
2994
2995                        if (tg3_flag(tp_peer, INIT_COMPLETE))
2996                                return;
2997
2998                        if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2999                            tg3_flag(tp_peer, ENABLE_ASF))
3000                                need_vaux = true;
3001                }
3002        }
3003
3004        if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3005            tg3_flag(tp, ENABLE_ASF))
3006                need_vaux = true;
3007
3008        if (need_vaux)
3009                tg3_pwrsrc_switch_to_vaux(tp);
3010        else
3011                tg3_pwrsrc_die_with_vmain(tp);
3012}
3013
3014static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3015{
3016        if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3017                return 1;
3018        else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3019                if (speed != SPEED_10)
3020                        return 1;
3021        } else if (speed == SPEED_10)
3022                return 1;
3023
3024        return 0;
3025}
3026
3027static bool tg3_phy_power_bug(struct tg3 *tp)
3028{
3029        switch (tg3_asic_rev(tp)) {
3030        case ASIC_REV_5700:
3031        case ASIC_REV_5704:
3032                return true;
3033        case ASIC_REV_5780:
3034                if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3035                        return true;
3036                return false;
3037        case ASIC_REV_5717:
3038                if (!tp->pci_fn)
3039                        return true;
3040                return false;
3041        case ASIC_REV_5719:
3042        case ASIC_REV_5720:
3043                if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3044                    !tp->pci_fn)
3045                        return true;
3046                return false;
3047        }
3048
3049        return false;
3050}
3051
3052static bool tg3_phy_led_bug(struct tg3 *tp)
3053{
3054        switch (tg3_asic_rev(tp)) {
3055        case ASIC_REV_5719:
3056        case ASIC_REV_5720:
3057                if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3058                    !tp->pci_fn)
3059                        return true;
3060                return false;
3061        }
3062
3063        return false;
3064}
3065
3066static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3067{
3068        u32 val;
3069
3070        if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3071                return;
3072
3073        if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3074                if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3075                        u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3076                        u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3077
3078                        sg_dig_ctrl |=
3079                                SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3080                        tw32(SG_DIG_CTRL, sg_dig_ctrl);
3081                        tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3082                }
3083                return;
3084        }
3085
3086        if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3087                tg3_bmcr_reset(tp);
3088                val = tr32(GRC_MISC_CFG);
3089                tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3090                udelay(40);
3091                return;
3092        } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3093                u32 phytest;
3094                if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3095                        u32 phy;
3096
3097                        tg3_writephy(tp, MII_ADVERTISE, 0);
3098                        tg3_writephy(tp, MII_BMCR,
3099                                     BMCR_ANENABLE | BMCR_ANRESTART);
3100
3101                        tg3_writephy(tp, MII_TG3_FET_TEST,
3102                                     phytest | MII_TG3_FET_SHADOW_EN);
3103                        if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3104                                phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3105                                tg3_writephy(tp,
3106                                             MII_TG3_FET_SHDW_AUXMODE4,
3107                                             phy);
3108                        }
3109                        tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3110                }
3111                return;
3112        } else if (do_low_power) {
3113                if (!tg3_phy_led_bug(tp))
3114                        tg3_writephy(tp, MII_TG3_EXT_CTRL,
3115                                     MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3116
3117                val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3118                      MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3119                      MII_TG3_AUXCTL_PCTL_VREG_11V;
3120                tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3121        }
3122
3123        /* The PHY should not be powered down on some chips because
3124         * of bugs.
3125         */
3126        if (tg3_phy_power_bug(tp))
3127                return;
3128
3129        if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3130            tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3131                val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3132                val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3133                val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3134                tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3135        }
3136
3137        tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3138}
3139
3140/* tp->lock is held. */
3141static int tg3_nvram_lock(struct tg3 *tp)
3142{
3143        if (tg3_flag(tp, NVRAM)) {
3144                int i;
3145
3146                if (tp->nvram_lock_cnt == 0) {
3147                        tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3148                        for (i = 0; i < 8000; i++) {
3149                                if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3150                                        break;
3151                                udelay(20);
3152                        }
3153                        if (i == 8000) {
3154                                tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3155                                return -ENODEV;
3156                        }
3157                }
3158                tp->nvram_lock_cnt++;
3159        }
3160        return 0;
3161}
3162
3163/* tp->lock is held. */
3164static void tg3_nvram_unlock(struct tg3 *tp)
3165{
3166        if (tg3_flag(tp, NVRAM)) {
3167                if (tp->nvram_lock_cnt > 0)
3168                        tp->nvram_lock_cnt--;
3169                if (tp->nvram_lock_cnt == 0)
3170                        tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3171        }
3172}
3173
3174/* tp->lock is held. */
3175static void tg3_enable_nvram_access(struct tg3 *tp)
3176{
3177        if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3178                u32 nvaccess = tr32(NVRAM_ACCESS);
3179
3180                tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3181        }
3182}
3183
3184/* tp->lock is held. */
3185static void tg3_disable_nvram_access(struct tg3 *tp)
3186{
3187        if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3188                u32 nvaccess = tr32(NVRAM_ACCESS);
3189
3190                tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3191        }
3192}
3193
3194static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3195                                        u32 offset, u32 *val)
3196{
3197        u32 tmp;
3198        int i;
3199
3200        if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3201                return -EINVAL;
3202
3203        tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3204                                        EEPROM_ADDR_DEVID_MASK |
3205                                        EEPROM_ADDR_READ);
3206        tw32(GRC_EEPROM_ADDR,
3207             tmp |
3208             (0 << EEPROM_ADDR_DEVID_SHIFT) |
3209             ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3210              EEPROM_ADDR_ADDR_MASK) |
3211             EEPROM_ADDR_READ | EEPROM_ADDR_START);
3212
3213        for (i = 0; i < 1000; i++) {
3214                tmp = tr32(GRC_EEPROM_ADDR);
3215
3216                if (tmp & EEPROM_ADDR_COMPLETE)
3217                        break;
3218                msleep(1);
3219        }
3220        if (!(tmp & EEPROM_ADDR_COMPLETE))
3221                return -EBUSY;
3222
3223        tmp = tr32(GRC_EEPROM_DATA);
3224
3225        /*
3226         * The data will always be opposite the native endian
3227         * format.  Perform a blind byteswap to compensate.
3228         */
3229        *val = swab32(tmp);
3230
3231        return 0;
3232}
3233
3234#define NVRAM_CMD_TIMEOUT 10000
3235
3236static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3237{
3238        int i;
3239
3240        tw32(NVRAM_CMD, nvram_cmd);
3241        for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3242                usleep_range(10, 40);
3243                if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3244                        udelay(10);
3245                        break;
3246                }
3247        }
3248
3249        if (i == NVRAM_CMD_TIMEOUT)
3250                return -EBUSY;
3251
3252        return 0;
3253}
3254
3255static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3256{
3257        if (tg3_flag(tp, NVRAM) &&
3258            tg3_flag(tp, NVRAM_BUFFERED) &&
3259            tg3_flag(tp, FLASH) &&
3260            !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3261            (tp->nvram_jedecnum == JEDEC_ATMEL))
3262
3263                addr = ((addr / tp->nvram_pagesize) <<
3264                        ATMEL_AT45DB0X1B_PAGE_POS) +
3265                       (addr % tp->nvram_pagesize);
3266
3267        return addr;
3268}
3269
3270static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3271{
3272        if (tg3_flag(tp, NVRAM) &&
3273            tg3_flag(tp, NVRAM_BUFFERED) &&
3274            tg3_flag(tp, FLASH) &&
3275            !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3276            (tp->nvram_jedecnum == JEDEC_ATMEL))
3277
3278                addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3279                        tp->nvram_pagesize) +
3280                       (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3281
3282        return addr;
3283}
3284
3285/* NOTE: Data read in from NVRAM is byteswapped according to
3286 * the byteswapping settings for all other register accesses.
3287 * tg3 devices are BE devices, so on a BE machine, the data
3288 * returned will be exactly as it is seen in NVRAM.  On a LE
3289 * machine, the 32-bit value will be byteswapped.
3290 */
3291static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3292{
3293        int ret;
3294
3295        if (!tg3_flag(tp, NVRAM))
3296                return tg3_nvram_read_using_eeprom(tp, offset, val);
3297
3298        offset = tg3_nvram_phys_addr(tp, offset);
3299
3300        if (offset > NVRAM_ADDR_MSK)
3301                return -EINVAL;
3302
3303        ret = tg3_nvram_lock(tp);
3304        if (ret)
3305                return ret;
3306
3307        tg3_enable_nvram_access(tp);
3308
3309        tw32(NVRAM_ADDR, offset);
3310        ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3311                NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3312
3313        if (ret == 0)
3314                *val = tr32(NVRAM_RDDATA);
3315
3316        tg3_disable_nvram_access(tp);
3317
3318        tg3_nvram_unlock(tp);
3319
3320        return ret;
3321}
3322
3323/* Ensures NVRAM data is in bytestream format. */
3324static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3325{
3326        u32 v;
3327        int res = tg3_nvram_read(tp, offset, &v);
3328        if (!res)
3329                *val = cpu_to_be32(v);
3330        return res;
3331}
3332
3333static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3334                                    u32 offset, u32 len, u8 *buf)
3335{
3336        int i, j, rc = 0;
3337        u32 val;
3338
3339        for (i = 0; i < len; i += 4) {
3340                u32 addr;
3341                __be32 data;
3342
3343                addr = offset + i;
3344
3345                memcpy(&data, buf + i, 4);
3346
3347                /*
3348                 * The SEEPROM interface expects the data to always be opposite
3349                 * the native endian format.  We accomplish this by reversing
3350                 * all the operations that would have been performed on the
3351                 * data from a call to tg3_nvram_read_be32().
3352                 */
3353                tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3354
3355                val = tr32(GRC_EEPROM_ADDR);
3356                tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3357
3358                val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3359                        EEPROM_ADDR_READ);
3360                tw32(GRC_EEPROM_ADDR, val |
3361                        (0 << EEPROM_ADDR_DEVID_SHIFT) |
3362                        (addr & EEPROM_ADDR_ADDR_MASK) |
3363                        EEPROM_ADDR_START |
3364                        EEPROM_ADDR_WRITE);
3365
3366                for (j = 0; j < 1000; j++) {
3367                        val = tr32(GRC_EEPROM_ADDR);
3368
3369                        if (val & EEPROM_ADDR_COMPLETE)
3370                                break;
3371                        msleep(1);
3372                }
3373                if (!(val & EEPROM_ADDR_COMPLETE)) {
3374                        rc = -EBUSY;
3375                        break;
3376                }
3377        }
3378
3379        return rc;
3380}
3381
3382/* offset and length are dword aligned */
3383static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3384                u8 *buf)
3385{
3386        int ret = 0;
3387        u32 pagesize = tp->nvram_pagesize;
3388        u32 pagemask = pagesize - 1;
3389        u32 nvram_cmd;
3390        u8 *tmp;
3391
3392        tmp = kmalloc(pagesize, GFP_KERNEL);
3393        if (tmp == NULL)
3394                return -ENOMEM;
3395
3396        while (len) {
3397                int j;
3398                u32 phy_addr, page_off, size;
3399
3400                phy_addr = offset & ~pagemask;
3401
3402                for (j = 0; j < pagesize; j += 4) {
3403                        ret = tg3_nvram_read_be32(tp, phy_addr + j,
3404                                                  (__be32 *) (tmp + j));
3405                        if (ret)
3406                                break;
3407                }
3408                if (ret)
3409                        break;
3410
3411                page_off = offset & pagemask;
3412                size = pagesize;
3413                if (len < size)
3414                        size = len;
3415
3416                len -= size;
3417
3418                memcpy(tmp + page_off, buf, size);
3419
3420                offset = offset + (pagesize - page_off);
3421
3422                tg3_enable_nvram_access(tp);
3423
3424                /*
3425                 * Before we can erase the flash page, we need
3426                 * to issue a special "write enable" command.
3427                 */
3428                nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3429
3430                if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3431                        break;
3432
3433                /* Erase the target page */
3434                tw32(NVRAM_ADDR, phy_addr);
3435
3436                nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3437                        NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3438
3439                if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3440                        break;
3441
3442                /* Issue another write enable to start the write. */
3443                nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3444
3445                if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3446                        break;
3447
3448                for (j = 0; j < pagesize; j += 4) {
3449                        __be32 data;
3450
3451                        data = *((__be32 *) (tmp + j));
3452
3453                        tw32(NVRAM_WRDATA, be32_to_cpu(data));
3454
3455                        tw32(NVRAM_ADDR, phy_addr + j);
3456
3457                        nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3458                                NVRAM_CMD_WR;
3459
3460                        if (j == 0)
3461                                nvram_cmd |= NVRAM_CMD_FIRST;
3462                        else if (j == (pagesize - 4))
3463                                nvram_cmd |= NVRAM_CMD_LAST;
3464
3465                        ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3466                        if (ret)
3467                                break;
3468                }
3469                if (ret)
3470                        break;
3471        }
3472
3473        nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3474        tg3_nvram_exec_cmd(tp, nvram_cmd);
3475
3476        kfree(tmp);
3477
3478        return ret;
3479}
3480
3481/* offset and length are dword aligned */
3482static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3483                u8 *buf)
3484{
3485        int i, ret = 0;
3486
3487        for (i = 0; i < len; i += 4, offset += 4) {
3488                u32 page_off, phy_addr, nvram_cmd;
3489                __be32 data;
3490
3491                memcpy(&data, buf + i, 4);
3492                tw32(NVRAM_WRDATA, be32_to_cpu(data));
3493
3494                page_off = offset % tp->nvram_pagesize;
3495
3496                phy_addr = tg3_nvram_phys_addr(tp, offset);
3497
3498                nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3499
3500                if (page_off == 0 || i == 0)
3501                        nvram_cmd |= NVRAM_CMD_FIRST;
3502                if (page_off == (tp->nvram_pagesize - 4))
3503                        nvram_cmd |= NVRAM_CMD_LAST;
3504
3505                if (i == (len - 4))
3506                        nvram_cmd |= NVRAM_CMD_LAST;
3507
3508                if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3509                    !tg3_flag(tp, FLASH) ||
3510                    !tg3_flag(tp, 57765_PLUS))
3511                        tw32(NVRAM_ADDR, phy_addr);
3512
3513                if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3514                    !tg3_flag(tp, 5755_PLUS) &&
3515                    (tp->nvram_jedecnum == JEDEC_ST) &&
3516                    (nvram_cmd & NVRAM_CMD_FIRST)) {
3517                        u32 cmd;
3518
3519                        cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3520                        ret = tg3_nvram_exec_cmd(tp, cmd);
3521                        if (ret)
3522                                break;
3523                }
3524                if (!tg3_flag(tp, FLASH)) {
3525                        /* We always do complete word writes to eeprom. */
3526                        nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3527                }
3528
3529                ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3530                if (ret)
3531                        break;
3532        }
3533        return ret;
3534}
3535
3536/* offset and length are dword aligned */
3537static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3538{
3539        int ret;
3540
3541        if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3542                tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3543                       ~GRC_LCLCTRL_GPIO_OUTPUT1);
3544                udelay(40);
3545        }
3546
3547        if (!tg3_flag(tp, NVRAM)) {
3548                ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3549        } else {
3550                u32 grc_mode;
3551
3552                ret = tg3_nvram_lock(tp);
3553                if (ret)
3554                        return ret;
3555
3556                tg3_enable_nvram_access(tp);
3557                if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3558                        tw32(NVRAM_WRITE1, 0x406);
3559
3560                grc_mode = tr32(GRC_MODE);
3561                tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3562
3563                if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3564                        ret = tg3_nvram_write_block_buffered(tp, offset, len,
3565                                buf);
3566                } else {
3567                        ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3568                                buf);
3569                }
3570
3571                grc_mode = tr32(GRC_MODE);
3572                tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3573
3574                tg3_disable_nvram_access(tp);
3575                tg3_nvram_unlock(tp);
3576        }
3577
3578        if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3579                tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3580                udelay(40);
3581        }
3582
3583        return ret;
3584}
3585
3586#define RX_CPU_SCRATCH_BASE     0x30000
3587#define RX_CPU_SCRATCH_SIZE     0x04000
3588#define TX_CPU_SCRATCH_BASE     0x34000
3589#define TX_CPU_SCRATCH_SIZE     0x04000
3590
3591/* tp->lock is held. */
3592static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3593{
3594        int i;
3595        const int iters = 10000;
3596
3597        for (i = 0; i < iters; i++) {
3598                tw32(cpu_base + CPU_STATE, 0xffffffff);
3599                tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
3600                if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3601                        break;
3602                if (pci_channel_offline(tp->pdev))
3603                        return -EBUSY;
3604        }
3605
3606        return (i == iters) ? -EBUSY : 0;
3607}
3608
3609/* tp->lock is held. */
3610static int tg3_rxcpu_pause(struct tg3 *tp)
3611{
3612        int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3613
3614        tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3615        tw32_f(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
3616        udelay(10);
3617
3618        return rc;
3619}
3620
3621/* tp->lock is held. */
3622static int tg3_txcpu_pause(struct tg3 *tp)
3623{
3624        return tg3_pause_cpu(tp, TX_CPU_BASE);
3625}
3626
3627/* tp->lock is held. */
3628static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3629{
3630        tw32(cpu_base + CPU_STATE, 0xffffffff);
3631        tw32_f(cpu_base + CPU_MODE,  0x00000000);
3632}
3633
3634/* tp->lock is held. */
3635static void tg3_rxcpu_resume(struct tg3 *tp)
3636{
3637        tg3_resume_cpu(tp, RX_CPU_BASE);
3638}
3639
3640/* tp->lock is held. */
3641static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3642{
3643        int rc;
3644
3645        BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3646
3647        if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3648                u32 val = tr32(GRC_VCPU_EXT_CTRL);
3649
3650                tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3651                return 0;
3652        }
3653        if (cpu_base == RX_CPU_BASE) {
3654                rc = tg3_rxcpu_pause(tp);
3655        } else {
3656                /*
3657                 * There is only an Rx CPU for the 5750 derivative in the
3658                 * BCM4785.
3659                 */
3660                if (tg3_flag(tp, IS_SSB_CORE))
3661                        return 0;
3662
3663                rc = tg3_txcpu_pause(tp);
3664        }
3665
3666        if (rc) {
3667                netdev_err(tp->dev, "%s timed out, %s CPU\n",
3668                           __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3669                return -ENODEV;
3670        }
3671
3672        /* Clear firmware's nvram arbitration. */
3673        if (tg3_flag(tp, NVRAM))
3674                tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3675        return 0;
3676}
3677
3678static int tg3_fw_data_len(struct tg3 *tp,
3679                           const struct tg3_firmware_hdr *fw_hdr)
3680{
3681        int fw_len;
3682
3683        /* Non fragmented firmware have one firmware header followed by a
3684         * contiguous chunk of data to be written. The length field in that
3685         * header is not the length of data to be written but the complete
3686         * length of the bss. The data length is determined based on
3687         * tp->fw->size minus headers.
3688         *
3689         * Fragmented firmware have a main header followed by multiple
3690         * fragments. Each fragment is identical to non fragmented firmware
3691         * with a firmware header followed by a contiguous chunk of data. In
3692         * the main header, the length field is unused and set to 0xffffffff.
3693         * In each fragment header the length is the entire size of that
3694         * fragment i.e. fragment data + header length. Data length is
3695         * therefore length field in the header minus TG3_FW_HDR_LEN.
3696         */
3697        if (tp->fw_len == 0xffffffff)
3698                fw_len = be32_to_cpu(fw_hdr->len);
3699        else
3700                fw_len = tp->fw->size;
3701
3702        return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3703}
3704
3705/* tp->lock is held. */
3706static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3707                                 u32 cpu_scratch_base, int cpu_scratch_size,
3708                                 const struct tg3_firmware_hdr *fw_hdr)
3709{
3710        int err, i;
3711        void (*write_op)(struct tg3 *, u32, u32);
3712        int total_len = tp->fw->size;
3713
3714        if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3715                netdev_err(tp->dev,
3716                           "%s: Trying to load TX cpu firmware which is 5705\n",
3717                           __func__);
3718                return -EINVAL;
3719        }
3720
3721        if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3722                write_op = tg3_write_mem;
3723        else
3724                write_op = tg3_write_indirect_reg32;
3725
3726        if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3727                /* It is possible that bootcode is still loading at this point.
3728                 * Get the nvram lock first before halting the cpu.
3729                 */
3730                int lock_err = tg3_nvram_lock(tp);
3731                err = tg3_halt_cpu(tp, cpu_base);
3732                if (!lock_err)
3733                        tg3_nvram_unlock(tp);
3734                if (err)
3735                        goto out;
3736
3737                for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3738                        write_op(tp, cpu_scratch_base + i, 0);
3739                tw32(cpu_base + CPU_STATE, 0xffffffff);
3740                tw32(cpu_base + CPU_MODE,
3741                     tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3742        } else {
3743                /* Subtract additional main header for fragmented firmware and
3744                 * advance to the first fragment
3745                 */
3746                total_len -= TG3_FW_HDR_LEN;
3747                fw_hdr++;
3748        }
3749
3750        do {
3751                u32 *fw_data = (u32 *)(fw_hdr + 1);
3752                for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3753                        write_op(tp, cpu_scratch_base +
3754                                     (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3755                                     (i * sizeof(u32)),
3756                                 be32_to_cpu(fw_data[i]));
3757
3758                total_len -= be32_to_cpu(fw_hdr->len);
3759
3760                /* Advance to next fragment */
3761                fw_hdr = (struct tg3_firmware_hdr *)
3762                         ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3763        } while (total_len > 0);
3764
3765        err = 0;
3766
3767out:
3768        return err;
3769}
3770
3771/* tp->lock is held. */
3772static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3773{
3774        int i;
3775        const int iters = 5;
3776
3777        tw32(cpu_base + CPU_STATE, 0xffffffff);
3778        tw32_f(cpu_base + CPU_PC, pc);
3779
3780        for (i = 0; i < iters; i++) {
3781                if (tr32(cpu_base + CPU_PC) == pc)
3782                        break;
3783                tw32(cpu_base + CPU_STATE, 0xffffffff);
3784                tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
3785                tw32_f(cpu_base + CPU_PC, pc);
3786                udelay(1000);
3787        }
3788
3789        return (i == iters) ? -EBUSY : 0;
3790}
3791
3792/* tp->lock is held. */
3793static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3794{
3795        const struct tg3_firmware_hdr *fw_hdr;
3796        int err;
3797
3798        fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3799
3800        /* Firmware blob starts with version numbers, followed by
3801           start address and length. We are setting complete length.
3802           length = end_address_of_bss - start_address_of_text.
3803           Remainder is the blob to be loaded contiguously
3804           from start address. */
3805
3806        err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3807                                    RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3808                                    fw_hdr);
3809        if (err)
3810                return err;
3811
3812        err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3813                                    TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3814                                    fw_hdr);
3815        if (err)
3816                return err;
3817
3818        /* Now startup only the RX cpu. */
3819        err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3820                                       be32_to_cpu(fw_hdr->base_addr));
3821        if (err) {
3822                netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3823                           "should be %08x\n", __func__,
3824                           tr32(RX_CPU_BASE + CPU_PC),
3825                                be32_to_cpu(fw_hdr->base_addr));
3826                return -ENODEV;
3827        }
3828
3829        tg3_rxcpu_resume(tp);
3830
3831        return 0;
3832}
3833
3834static int tg3_validate_rxcpu_state(struct tg3 *tp)
3835{
3836        const int iters = 1000;
3837        int i;
3838        u32 val;
3839
3840        /* Wait for boot code to complete initialization and enter service
3841         * loop. It is then safe to download service patches
3842         */
3843        for (i = 0; i < iters; i++) {
3844                if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3845                        break;
3846
3847                udelay(10);
3848        }
3849
3850        if (i == iters) {
3851                netdev_err(tp->dev, "Boot code not ready for service patches\n");
3852                return -EBUSY;
3853        }
3854
3855        val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3856        if (val & 0xff) {
3857                netdev_warn(tp->dev,
3858                            "Other patches exist. Not downloading EEE patch\n");
3859                return -EEXIST;
3860        }
3861
3862        return 0;
3863}
3864
3865/* tp->lock is held. */
3866static void tg3_load_57766_firmware(struct tg3 *tp)
3867{
3868        struct tg3_firmware_hdr *fw_hdr;
3869
3870        if (!tg3_flag(tp, NO_NVRAM))
3871                return;
3872
3873        if (tg3_validate_rxcpu_state(tp))
3874                return;
3875
3876        if (!tp->fw)
3877                return;
3878
3879        /* This firmware blob has a different format than older firmware
3880         * releases as given below. The main difference is we have fragmented
3881         * data to be written to non-contiguous locations.
3882         *
3883         * In the beginning we have a firmware header identical to other
3884         * firmware which consists of version, base addr and length. The length
3885         * here is unused and set to 0xffffffff.
3886         *
3887         * This is followed by a series of firmware fragments which are
3888         * individually identical to previous firmware. i.e. they have the
3889         * firmware header and followed by data for that fragment. The version
3890         * field of the individual fragment header is unused.
3891         */
3892
3893        fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3894        if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3895                return;
3896
3897        if (tg3_rxcpu_pause(tp))
3898                return;
3899
3900        /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3901        tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3902
3903        tg3_rxcpu_resume(tp);
3904}
3905
3906/* tp->lock is held. */
3907static int tg3_load_tso_firmware(struct tg3 *tp)
3908{
3909        const struct tg3_firmware_hdr *fw_hdr;
3910        unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3911        int err;
3912
3913        if (!tg3_flag(tp, FW_TSO))
3914                return 0;
3915
3916        fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3917
3918        /* Firmware blob starts with version numbers, followed by
3919           start address and length. We are setting complete length.
3920           length = end_address_of_bss - start_address_of_text.
3921           Remainder is the blob to be loaded contiguously
3922           from start address. */
3923
3924        cpu_scratch_size = tp->fw_len;
3925
3926        if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3927                cpu_base = RX_CPU_BASE;
3928                cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3929        } else {
3930                cpu_base = TX_CPU_BASE;
3931                cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3932                cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3933        }
3934
3935        err = tg3_load_firmware_cpu(tp, cpu_base,
3936                                    cpu_scratch_base, cpu_scratch_size,
3937                                    fw_hdr);
3938        if (err)
3939                return err;
3940
3941        /* Now startup the cpu. */
3942        err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3943                                       be32_to_cpu(fw_hdr->base_addr));
3944        if (err) {
3945                netdev_err(tp->dev,
3946                           "%s fails to set CPU PC, is %08x should be %08x\n",
3947                           __func__, tr32(cpu_base + CPU_PC),
3948                           be32_to_cpu(fw_hdr->base_addr));
3949                return -ENODEV;
3950        }
3951
3952        tg3_resume_cpu(tp, cpu_base);
3953        return 0;
3954}
3955
3956/* tp->lock is held. */
3957static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3958{
3959        u32 addr_high, addr_low;
3960
3961        addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3962        addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3963                    (mac_addr[4] <<  8) | mac_addr[5]);
3964
3965        if (index < 4) {
3966                tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3967                tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3968        } else {
3969                index -= 4;
3970                tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3971                tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3972        }
3973}
3974
3975/* tp->lock is held. */
3976static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3977{
3978        u32 addr_high;
3979        int i;
3980
3981        for (i = 0; i < 4; i++) {
3982                if (i == 1 && skip_mac_1)
3983                        continue;
3984                __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3985        }
3986
3987        if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3988            tg3_asic_rev(tp) == ASIC_REV_5704) {
3989                for (i = 4; i < 16; i++)
3990                        __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3991        }
3992
3993        addr_high = (tp->dev->dev_addr[0] +
3994                     tp->dev->dev_addr[1] +
3995                     tp->dev->dev_addr[2] +
3996                     tp->dev->dev_addr[3] +
3997                     tp->dev->dev_addr[4] +
3998                     tp->dev->dev_addr[5]) &
3999                TX_BACKOFF_SEED_MASK;
4000        tw32(MAC_TX_BACKOFF_SEED, addr_high);
4001}
4002
4003static void tg3_enable_register_access(struct tg3 *tp)
4004{
4005        /*
4006         * Make sure register accesses (indirect or otherwise) will function
4007         * correctly.
4008         */
4009        pci_write_config_dword(tp->pdev,
4010                               TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4011}
4012
4013static int tg3_power_up(struct tg3 *tp)
4014{
4015        int err;
4016
4017        tg3_enable_register_access(tp);
4018
4019        err = pci_set_power_state(tp->pdev, PCI_D0);
4020        if (!err) {
4021                /* Switch out of Vaux if it is a NIC */
4022                tg3_pwrsrc_switch_to_vmain(tp);
4023        } else {
4024                netdev_err(tp->dev, "Transition to D0 failed\n");
4025        }
4026
4027        return err;
4028}
4029
4030static int tg3_setup_phy(struct tg3 *, bool);
4031
4032static int tg3_power_down_prepare(struct tg3 *tp)
4033{
4034        u32 misc_host_ctrl;
4035        bool device_should_wake, do_low_power;
4036
4037        tg3_enable_register_access(tp);
4038
4039        /* Restore the CLKREQ setting. */
4040        if (tg3_flag(tp, CLKREQ_BUG))
4041                pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4042                                         PCI_EXP_LNKCTL_CLKREQ_EN);
4043
4044        misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4045        tw32(TG3PCI_MISC_HOST_CTRL,
4046             misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4047
4048        device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4049                             tg3_flag(tp, WOL_ENABLE);
4050
4051        if (tg3_flag(tp, USE_PHYLIB)) {
4052                do_low_power = false;
4053                if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4054                    !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4055                        __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, };
4056                        struct phy_device *phydev;
4057                        u32 phyid;
4058
4059                        phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4060
4061                        tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4062
4063                        tp->link_config.speed = phydev->speed;
4064                        tp->link_config.duplex = phydev->duplex;
4065                        tp->link_config.autoneg = phydev->autoneg;
4066                        ethtool_convert_link_mode_to_legacy_u32(
4067                                &tp->link_config.advertising,
4068                                phydev->advertising);
4069
4070                        linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, advertising);
4071                        linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
4072                                         advertising);
4073                        linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
4074                                         advertising);
4075                        linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
4076                                         advertising);
4077
4078                        if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4079                                if (tg3_flag(tp, WOL_SPEED_100MB)) {
4080                                        linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
4081                                                         advertising);
4082                                        linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
4083                                                         advertising);
4084                                        linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4085                                                         advertising);
4086                                } else {
4087                                        linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4088                                                         advertising);
4089                                }
4090                        }
4091
4092                        linkmode_copy(phydev->advertising, advertising);
4093                        phy_start_aneg(phydev);
4094
4095                        phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4096                        if (phyid != PHY_ID_BCMAC131) {
4097                                phyid &= PHY_BCM_OUI_MASK;
4098                                if (phyid == PHY_BCM_OUI_1 ||
4099                                    phyid == PHY_BCM_OUI_2 ||
4100                                    phyid == PHY_BCM_OUI_3)
4101                                        do_low_power = true;
4102                        }
4103                }
4104        } else {
4105                do_low_power = true;
4106
4107                if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4108                        tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4109
4110                if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4111                        tg3_setup_phy(tp, false);
4112        }
4113
4114        if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4115                u32 val;
4116
4117                val = tr32(GRC_VCPU_EXT_CTRL);
4118                tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4119        } else if (!tg3_flag(tp, ENABLE_ASF)) {
4120                int i;
4121                u32 val;
4122
4123                for (i = 0; i < 200; i++) {
4124                        tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4125                        if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4126                                break;
4127                        msleep(1);
4128                }
4129        }
4130        if (tg3_flag(tp, WOL_CAP))
4131                tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4132                                                     WOL_DRV_STATE_SHUTDOWN |
4133                                                     WOL_DRV_WOL |
4134                                                     WOL_SET_MAGIC_PKT);
4135
4136        if (device_should_wake) {
4137                u32 mac_mode;
4138
4139                if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4140                        if (do_low_power &&
4141                            !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4142                                tg3_phy_auxctl_write(tp,
4143                                               MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4144                                               MII_TG3_AUXCTL_PCTL_WOL_EN |
4145                                               MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4146                                               MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4147                                udelay(40);
4148                        }
4149
4150                        if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4151                                mac_mode = MAC_MODE_PORT_MODE_GMII;
4152                        else if (tp->phy_flags &
4153                                 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4154                                if (tp->link_config.active_speed == SPEED_1000)
4155                                        mac_mode = MAC_MODE_PORT_MODE_GMII;
4156                                else
4157                                        mac_mode = MAC_MODE_PORT_MODE_MII;
4158                        } else
4159                                mac_mode = MAC_MODE_PORT_MODE_MII;
4160
4161                        mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4162                        if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4163                                u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4164                                             SPEED_100 : SPEED_10;
4165                                if (tg3_5700_link_polarity(tp, speed))
4166                                        mac_mode |= MAC_MODE_LINK_POLARITY;
4167                                else
4168                                        mac_mode &= ~MAC_MODE_LINK_POLARITY;
4169                        }
4170                } else {
4171                        mac_mode = MAC_MODE_PORT_MODE_TBI;
4172                }
4173
4174                if (!tg3_flag(tp, 5750_PLUS))
4175                        tw32(MAC_LED_CTRL, tp->led_ctrl);
4176
4177                mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4178                if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4179                    (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4180                        mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4181
4182                if (tg3_flag(tp, ENABLE_APE))
4183                        mac_mode |= MAC_MODE_APE_TX_EN |
4184                                    MAC_MODE_APE_RX_EN |
4185                                    MAC_MODE_TDE_ENABLE;
4186
4187                tw32_f(MAC_MODE, mac_mode);
4188                udelay(100);
4189
4190                tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4191                udelay(10);
4192        }
4193
4194        if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4195            (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4196             tg3_asic_rev(tp) == ASIC_REV_5701)) {
4197                u32 base_val;
4198
4199                base_val = tp->pci_clock_ctrl;
4200                base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4201                             CLOCK_CTRL_TXCLK_DISABLE);
4202
4203                tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4204                            CLOCK_CTRL_PWRDOWN_PLL133, 40);
4205        } else if (tg3_flag(tp, 5780_CLASS) ||
4206                   tg3_flag(tp, CPMU_PRESENT) ||
4207                   tg3_asic_rev(tp) == ASIC_REV_5906) {
4208                /* do nothing */
4209        } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4210                u32 newbits1, newbits2;
4211
4212                if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4213                    tg3_asic_rev(tp) == ASIC_REV_5701) {
4214                        newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4215                                    CLOCK_CTRL_TXCLK_DISABLE |
4216                                    CLOCK_CTRL_ALTCLK);
4217                        newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4218                } else if (tg3_flag(tp, 5705_PLUS)) {
4219                        newbits1 = CLOCK_CTRL_625_CORE;
4220                        newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4221                } else {
4222                        newbits1 = CLOCK_CTRL_ALTCLK;
4223                        newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4224                }
4225
4226                tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4227                            40);
4228
4229                tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4230                            40);
4231
4232                if (!tg3_flag(tp, 5705_PLUS)) {
4233                        u32 newbits3;
4234
4235                        if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4236                            tg3_asic_rev(tp) == ASIC_REV_5701) {
4237                                newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4238                                            CLOCK_CTRL_TXCLK_DISABLE |
4239                                            CLOCK_CTRL_44MHZ_CORE);
4240                        } else {
4241                                newbits3 = CLOCK_CTRL_44MHZ_CORE;
4242                        }
4243
4244                        tw32_wait_f(TG3PCI_CLOCK_CTRL,
4245                                    tp->pci_clock_ctrl | newbits3, 40);
4246                }
4247        }
4248
4249        if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4250                tg3_power_down_phy(tp, do_low_power);
4251
4252        tg3_frob_aux_power(tp, true);
4253
4254        /* Workaround for unstable PLL clock */
4255        if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4256            ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4257             (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4258                u32 val = tr32(0x7d00);
4259
4260                val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4261                tw32(0x7d00, val);
4262                if (!tg3_flag(tp, ENABLE_ASF)) {
4263                        int err;
4264
4265                        err = tg3_nvram_lock(tp);
4266                        tg3_halt_cpu(tp, RX_CPU_BASE);
4267                        if (!err)
4268                                tg3_nvram_unlock(tp);
4269                }
4270        }
4271
4272        tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4273
4274        tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4275
4276        return 0;
4277}
4278
4279static void tg3_power_down(struct tg3 *tp)
4280{
4281        pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4282        pci_set_power_state(tp->pdev, PCI_D3hot);
4283}
4284
4285static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
4286{
4287        switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4288        case MII_TG3_AUX_STAT_10HALF:
4289                *speed = SPEED_10;
4290                *duplex = DUPLEX_HALF;
4291                break;
4292
4293        case MII_TG3_AUX_STAT_10FULL:
4294                *speed = SPEED_10;
4295                *duplex = DUPLEX_FULL;
4296                break;
4297
4298        case MII_TG3_AUX_STAT_100HALF:
4299                *speed = SPEED_100;
4300                *duplex = DUPLEX_HALF;
4301                break;
4302
4303        case MII_TG3_AUX_STAT_100FULL:
4304                *speed = SPEED_100;
4305                *duplex = DUPLEX_FULL;
4306                break;
4307
4308        case MII_TG3_AUX_STAT_1000HALF:
4309                *speed = SPEED_1000;
4310                *duplex = DUPLEX_HALF;
4311                break;
4312
4313        case MII_TG3_AUX_STAT_1000FULL:
4314                *speed = SPEED_1000;
4315                *duplex = DUPLEX_FULL;
4316                break;
4317
4318        default:
4319                if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4320                        *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4321                                 SPEED_10;
4322                        *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4323                                  DUPLEX_HALF;
4324                        break;
4325                }
4326                *speed = SPEED_UNKNOWN;
4327                *duplex = DUPLEX_UNKNOWN;
4328                break;
4329        }
4330}
4331
4332static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4333{
4334        int err = 0;
4335        u32 val, new_adv;
4336
4337        new_adv = ADVERTISE_CSMA;
4338        new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4339        new_adv |= mii_advertise_flowctrl(flowctrl);
4340
4341        err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4342        if (err)
4343                goto done;
4344
4345        if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4346                new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4347
4348                if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4349                    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4350                        new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4351
4352                err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4353                if (err)
4354                        goto done;
4355        }
4356
4357        if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4358                goto done;
4359
4360        tw32(TG3_CPMU_EEE_MODE,
4361             tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4362
4363        err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4364        if (!err) {
4365                u32 err2;
4366
4367                val = 0;
4368                /* Advertise 100-BaseTX EEE ability */
4369                if (advertise & ADVERTISED_100baseT_Full)
4370                        val |= MDIO_AN_EEE_ADV_100TX;
4371                /* Advertise 1000-BaseT EEE ability */
4372                if (advertise & ADVERTISED_1000baseT_Full)
4373                        val |= MDIO_AN_EEE_ADV_1000T;
4374
4375                if (!tp->eee.eee_enabled) {
4376                        val = 0;
4377                        tp->eee.advertised = 0;
4378                } else {
4379                        tp->eee.advertised = advertise &
4380                                             (ADVERTISED_100baseT_Full |
4381                                              ADVERTISED_1000baseT_Full);
4382                }
4383
4384                err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4385                if (err)
4386                        val = 0;
4387
4388                switch (tg3_asic_rev(tp)) {
4389                case ASIC_REV_5717:
4390                case ASIC_REV_57765:
4391                case ASIC_REV_57766:
4392                case ASIC_REV_5719:
4393                        /* If we advertised any eee advertisements above... */
4394                        if (val)
4395                                val = MII_TG3_DSP_TAP26_ALNOKO |
4396                                      MII_TG3_DSP_TAP26_RMRXSTO |
4397                                      MII_TG3_DSP_TAP26_OPCSINPT;
4398                        tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4399                        /* Fall through */
4400                case ASIC_REV_5720:
4401                case ASIC_REV_5762:
4402                        if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4403                                tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4404                                                 MII_TG3_DSP_CH34TP2_HIBW01);
4405                }
4406
4407                err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4408                if (!err)
4409                        err = err2;
4410        }
4411
4412done:
4413        return err;
4414}
4415
4416static void tg3_phy_copper_begin(struct tg3 *tp)
4417{
4418        if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4419            (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4420                u32 adv, fc;
4421
4422                if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4423                    !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4424                        adv = ADVERTISED_10baseT_Half |
4425                              ADVERTISED_10baseT_Full;
4426                        if (tg3_flag(tp, WOL_SPEED_100MB))
4427                                adv |= ADVERTISED_100baseT_Half |
4428                                       ADVERTISED_100baseT_Full;
4429                        if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4430                                if (!(tp->phy_flags &
4431                                      TG3_PHYFLG_DISABLE_1G_HD_ADV))
4432                                        adv |= ADVERTISED_1000baseT_Half;
4433                                adv |= ADVERTISED_1000baseT_Full;
4434                        }
4435
4436                        fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4437                } else {
4438                        adv = tp->link_config.advertising;
4439                        if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4440                                adv &= ~(ADVERTISED_1000baseT_Half |
4441                                         ADVERTISED_1000baseT_Full);
4442
4443                        fc = tp->link_config.flowctrl;
4444                }
4445
4446                tg3_phy_autoneg_cfg(tp, adv, fc);
4447
4448                if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4449                    (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4450                        /* Normally during power down we want to autonegotiate
4451                         * the lowest possible speed for WOL. However, to avoid
4452                         * link flap, we leave it untouched.
4453                         */
4454                        return;
4455                }
4456
4457                tg3_writephy(tp, MII_BMCR,
4458                             BMCR_ANENABLE | BMCR_ANRESTART);
4459        } else {
4460                int i;
4461                u32 bmcr, orig_bmcr;
4462
4463                tp->link_config.active_speed = tp->link_config.speed;
4464                tp->link_config.active_duplex = tp->link_config.duplex;
4465
4466                if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4467                        /* With autoneg disabled, 5715 only links up when the
4468                         * advertisement register has the configured speed
4469                         * enabled.
4470                         */
4471                        tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4472                }
4473
4474                bmcr = 0;
4475                switch (tp->link_config.speed) {
4476                default:
4477                case SPEED_10:
4478                        break;
4479
4480                case SPEED_100:
4481                        bmcr |= BMCR_SPEED100;
4482                        break;
4483
4484                case SPEED_1000:
4485                        bmcr |= BMCR_SPEED1000;
4486                        break;
4487                }
4488
4489                if (tp->link_config.duplex == DUPLEX_FULL)
4490                        bmcr |= BMCR_FULLDPLX;
4491
4492                if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4493                    (bmcr != orig_bmcr)) {
4494                        tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4495                        for (i = 0; i < 1500; i++) {
4496                                u32 tmp;
4497
4498                                udelay(10);
4499                                if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4500                                    tg3_readphy(tp, MII_BMSR, &tmp))
4501                                        continue;
4502                                if (!(tmp & BMSR_LSTATUS)) {
4503                                        udelay(40);
4504                                        break;
4505                                }
4506                        }
4507                        tg3_writephy(tp, MII_BMCR, bmcr);
4508                        udelay(40);
4509                }
4510        }
4511}
4512
4513static int tg3_phy_pull_config(struct tg3 *tp)
4514{
4515        int err;
4516        u32 val;
4517
4518        err = tg3_readphy(tp, MII_BMCR, &val);
4519        if (err)
4520                goto done;
4521
4522        if (!(val & BMCR_ANENABLE)) {
4523                tp->link_config.autoneg = AUTONEG_DISABLE;
4524                tp->link_config.advertising = 0;
4525                tg3_flag_clear(tp, PAUSE_AUTONEG);
4526
4527                err = -EIO;
4528
4529                switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4530                case 0:
4531                        if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4532                                goto done;
4533
4534                        tp->link_config.speed = SPEED_10;
4535                        break;
4536                case BMCR_SPEED100:
4537                        if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4538                                goto done;
4539
4540                        tp->link_config.speed = SPEED_100;
4541                        break;
4542                case BMCR_SPEED1000:
4543                        if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4544                                tp->link_config.speed = SPEED_1000;
4545                                break;
4546                        }
4547                        /* Fall through */
4548                default:
4549                        goto done;
4550                }
4551
4552                if (val & BMCR_FULLDPLX)
4553                        tp->link_config.duplex = DUPLEX_FULL;
4554                else
4555                        tp->link_config.duplex = DUPLEX_HALF;
4556
4557                tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4558
4559                err = 0;
4560                goto done;
4561        }
4562
4563        tp->link_config.autoneg = AUTONEG_ENABLE;
4564        tp->link_config.advertising = ADVERTISED_Autoneg;
4565        tg3_flag_set(tp, PAUSE_AUTONEG);
4566
4567        if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4568                u32 adv;
4569
4570                err = tg3_readphy(tp, MII_ADVERTISE, &val);
4571                if (err)
4572                        goto done;
4573
4574                adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4575                tp->link_config.advertising |= adv | ADVERTISED_TP;
4576
4577                tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4578        } else {
4579                tp->link_config.advertising |= ADVERTISED_FIBRE;
4580        }
4581
4582        if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4583                u32 adv;
4584
4585                if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4586                        err = tg3_readphy(tp, MII_CTRL1000, &val);
4587                        if (err)
4588                                goto done;
4589
4590                        adv = mii_ctrl1000_to_ethtool_adv_t(val);
4591                } else {
4592                        err = tg3_readphy(tp, MII_ADVERTISE, &val);
4593                        if (err)
4594                                goto done;
4595
4596                        adv = tg3_decode_flowctrl_1000X(val);
4597                        tp->link_config.flowctrl = adv;
4598
4599                        val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4600                        adv = mii_adv_to_ethtool_adv_x(val);
4601                }
4602
4603                tp->link_config.advertising |= adv;
4604        }
4605
4606done:
4607        return err;
4608}
4609
4610static int tg3_init_5401phy_dsp(struct tg3 *tp)
4611{
4612        int err;
4613
4614        /* Turn off tap power management. */
4615        /* Set Extended packet length bit */
4616        err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4617
4618        err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4619        err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4620        err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4621        err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4622        err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4623
4624        udelay(40);
4625
4626        return err;
4627}
4628
4629static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4630{
4631        struct ethtool_eee eee;
4632
4633        if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4634                return true;
4635
4636        tg3_eee_pull_config(tp, &eee);
4637
4638        if (tp->eee.eee_enabled) {
4639                if (tp->eee.advertised != eee.advertised ||
4640                    tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4641                    tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4642                        return false;
4643        } else {
4644                /* EEE is disabled but we're advertising */
4645                if (eee.advertised)
4646                        return false;
4647        }
4648
4649        return true;
4650}
4651
4652static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4653{
4654        u32 advmsk, tgtadv, advertising;
4655
4656        advertising = tp->link_config.advertising;
4657        tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4658
4659        advmsk = ADVERTISE_ALL;
4660        if (tp->link_config.active_duplex == DUPLEX_FULL) {
4661                tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4662                advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4663        }
4664
4665        if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4666                return false;
4667
4668        if ((*lcladv & advmsk) != tgtadv)
4669                return false;
4670
4671        if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4672                u32 tg3_ctrl;
4673
4674                tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4675
4676                if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4677                        return false;
4678
4679                if (tgtadv &&
4680                    (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4681                     tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4682                        tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4683                        tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4684                                     CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4685                } else {
4686                        tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4687                }
4688
4689                if (tg3_ctrl != tgtadv)
4690                        return false;
4691        }
4692
4693        return true;
4694}
4695
4696static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4697{
4698        u32 lpeth = 0;
4699
4700        if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4701                u32 val;
4702
4703                if (tg3_readphy(tp, MII_STAT1000, &val))
4704                        return false;
4705
4706                lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4707        }
4708
4709        if (tg3_readphy(tp, MII_LPA, rmtadv))
4710                return false;
4711
4712        lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4713        tp->link_config.rmt_adv = lpeth;
4714
4715        return true;
4716}
4717
4718static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4719{
4720        if (curr_link_up != tp->link_up) {
4721                if (curr_link_up) {
4722                        netif_carrier_on(tp->dev);
4723                } else {
4724                        netif_carrier_off(tp->dev);
4725                        if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4726                                tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4727                }
4728
4729                tg3_link_report(tp);
4730                return true;
4731        }
4732
4733        return false;
4734}
4735
4736static void tg3_clear_mac_status(struct tg3 *tp)
4737{
4738        tw32(MAC_EVENT, 0);
4739
4740        tw32_f(MAC_STATUS,
4741               MAC_STATUS_SYNC_CHANGED |
4742               MAC_STATUS_CFG_CHANGED |
4743               MAC_STATUS_MI_COMPLETION |
4744               MAC_STATUS_LNKSTATE_CHANGED);
4745        udelay(40);
4746}
4747
4748static void tg3_setup_eee(struct tg3 *tp)
4749{
4750        u32 val;
4751
4752        val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4753              TG3_CPMU_EEE_LNKIDL_UART_IDL;
4754        if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4755                val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4756
4757        tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4758
4759        tw32_f(TG3_CPMU_EEE_CTRL,
4760               TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4761
4762        val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4763              (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4764              TG3_CPMU_EEEMD_LPI_IN_RX |
4765              TG3_CPMU_EEEMD_EEE_ENABLE;
4766
4767        if (tg3_asic_rev(tp) != ASIC_REV_5717)
4768                val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4769
4770        if (tg3_flag(tp, ENABLE_APE))
4771                val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4772
4773        tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4774
4775        tw32_f(TG3_CPMU_EEE_DBTMR1,
4776               TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4777               (tp->eee.tx_lpi_timer & 0xffff));
4778
4779        tw32_f(TG3_CPMU_EEE_DBTMR2,
4780               TG3_CPMU_DBTMR2_APE_TX_2047US |
4781               TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4782}
4783
4784static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4785{
4786        bool current_link_up;
4787        u32 bmsr, val;
4788        u32 lcl_adv, rmt_adv;
4789        u32 current_speed;
4790        u8 current_duplex;
4791        int i, err;
4792
4793        tg3_clear_mac_status(tp);
4794
4795        if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4796                tw32_f(MAC_MI_MODE,
4797                     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4798                udelay(80);
4799        }
4800
4801        tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4802
4803        /* Some third-party PHYs need to be reset on link going
4804         * down.
4805         */
4806        if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4807             tg3_asic_rev(tp) == ASIC_REV_5704 ||
4808             tg3_asic_rev(tp) == ASIC_REV_5705) &&
4809            tp->link_up) {
4810                tg3_readphy(tp, MII_BMSR, &bmsr);
4811                if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4812                    !(bmsr & BMSR_LSTATUS))
4813                        force_reset = true;
4814        }
4815        if (force_reset)
4816                tg3_phy_reset(tp);
4817
4818        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4819                tg3_readphy(tp, MII_BMSR, &bmsr);
4820                if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4821                    !tg3_flag(tp, INIT_COMPLETE))
4822                        bmsr = 0;
4823
4824                if (!(bmsr & BMSR_LSTATUS)) {
4825                        err = tg3_init_5401phy_dsp(tp);
4826                        if (err)
4827                                return err;
4828
4829                        tg3_readphy(tp, MII_BMSR, &bmsr);
4830                        for (i = 0; i < 1000; i++) {
4831                                udelay(10);
4832                                if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4833                                    (bmsr & BMSR_LSTATUS)) {
4834                                        udelay(40);
4835                                        break;
4836                                }
4837                        }
4838
4839                        if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4840                            TG3_PHY_REV_BCM5401_B0 &&
4841                            !(bmsr & BMSR_LSTATUS) &&
4842                            tp->link_config.active_speed == SPEED_1000) {
4843                                err = tg3_phy_reset(tp);
4844                                if (!err)
4845                                        err = tg3_init_5401phy_dsp(tp);
4846                                if (err)
4847                                        return err;
4848                        }
4849                }
4850        } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4851                   tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4852                /* 5701 {A0,B0} CRC bug workaround */
4853                tg3_writephy(tp, 0x15, 0x0a75);
4854                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4855                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4856                tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4857        }
4858
4859        /* Clear pending interrupts... */
4860        tg3_readphy(tp, MII_TG3_ISTAT, &val);
4861        tg3_readphy(tp, MII_TG3_ISTAT, &val);
4862
4863        if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4864                tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4865        else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4866                tg3_writephy(tp, MII_TG3_IMASK, ~0);
4867
4868        if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4869            tg3_asic_rev(tp) == ASIC_REV_5701) {
4870                if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4871                        tg3_writephy(tp, MII_TG3_EXT_CTRL,
4872                                     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4873                else
4874                        tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4875        }
4876
4877        current_link_up = false;
4878        current_speed = SPEED_UNKNOWN;
4879        current_duplex = DUPLEX_UNKNOWN;
4880        tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4881        tp->link_config.rmt_adv = 0;
4882
4883        if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4884                err = tg3_phy_auxctl_read(tp,
4885                                          MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4886                                          &val);
4887                if (!err && !(val & (1 << 10))) {
4888                        tg3_phy_auxctl_write(tp,
4889                                             MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4890                                             val | (1 << 10));
4891                        goto relink;
4892                }
4893        }
4894
4895        bmsr = 0;
4896        for (i = 0; i < 100; i++) {
4897                tg3_readphy(tp, MII_BMSR, &bmsr);
4898                if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4899                    (bmsr & BMSR_LSTATUS))
4900                        break;
4901                udelay(40);
4902        }
4903
4904        if (bmsr & BMSR_LSTATUS) {
4905                u32 aux_stat, bmcr;
4906
4907                tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4908                for (i = 0; i < 2000; i++) {
4909                        udelay(10);
4910                        if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4911                            aux_stat)
4912                                break;
4913                }
4914
4915                tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4916                                             &current_speed,
4917                                             &current_duplex);
4918
4919                bmcr = 0;
4920                for (i = 0; i < 200; i++) {
4921                        tg3_readphy(tp, MII_BMCR, &bmcr);
4922                        if (tg3_readphy(tp, MII_BMCR, &bmcr))
4923                                continue;
4924                        if (bmcr && bmcr != 0x7fff)
4925                                break;
4926                        udelay(10);
4927                }
4928
4929                lcl_adv = 0;
4930                rmt_adv = 0;
4931
4932                tp->link_config.active_speed = current_speed;
4933                tp->link_config.active_duplex = current_duplex;
4934
4935                if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4936                        bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4937
4938                        if ((bmcr & BMCR_ANENABLE) &&
4939                            eee_config_ok &&
4940                            tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4941                            tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4942                                current_link_up = true;
4943
4944                        /* EEE settings changes take effect only after a phy
4945                         * reset.  If we have skipped a reset due to Link Flap
4946                         * Avoidance being enabled, do it now.
4947                         */
4948                        if (!eee_config_ok &&
4949                            (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4950                            !force_reset) {
4951                                tg3_setup_eee(tp);
4952                                tg3_phy_reset(tp);
4953                        }
4954                } else {
4955                        if (!(bmcr & BMCR_ANENABLE) &&
4956                            tp->link_config.speed == current_speed &&
4957                            tp->link_config.duplex == current_duplex) {
4958                                current_link_up = true;
4959                        }
4960                }
4961
4962                if (current_link_up &&
4963                    tp->link_config.active_duplex == DUPLEX_FULL) {
4964                        u32 reg, bit;
4965
4966                        if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4967                                reg = MII_TG3_FET_GEN_STAT;
4968                                bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4969                        } else {
4970                                reg = MII_TG3_EXT_STAT;
4971                                bit = MII_TG3_EXT_STAT_MDIX;
4972                        }
4973
4974                        if (!tg3_readphy(tp, reg, &val) && (val & bit))
4975                                tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4976
4977                        tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4978                }
4979        }
4980
4981relink:
4982        if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4983                tg3_phy_copper_begin(tp);
4984
4985                if (tg3_flag(tp, ROBOSWITCH)) {
4986                        current_link_up = true;
4987                        /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4988                        current_speed = SPEED_1000;
4989                        current_duplex = DUPLEX_FULL;
4990                        tp->link_config.active_speed = current_speed;
4991                        tp->link_config.active_duplex = current_duplex;
4992                }
4993
4994                tg3_readphy(tp, MII_BMSR, &bmsr);
4995                if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4996                    (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4997                        current_link_up = true;
4998        }
4999
5000        tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5001        if (current_link_up) {
5002                if (tp->link_config.active_speed == SPEED_100 ||
5003                    tp->link_config.active_speed == SPEED_10)
5004                        tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5005                else
5006                        tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5007        } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
5008                tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5009        else
5010                tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5011
5012        /* In order for the 5750 core in BCM4785 chip to work properly
5013         * in RGMII mode, the Led Control Register must be set up.
5014         */
5015        if (tg3_flag(tp, RGMII_MODE)) {
5016                u32 led_ctrl = tr32(MAC_LED_CTRL);
5017                led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5018
5019                if (tp->link_config.active_speed == SPEED_10)
5020                        led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5021                else if (tp->link_config.active_speed == SPEED_100)
5022                        led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5023                                     LED_CTRL_100MBPS_ON);
5024                else if (tp->link_config.active_speed == SPEED_1000)
5025                        led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5026                                     LED_CTRL_1000MBPS_ON);
5027
5028                tw32(MAC_LED_CTRL, led_ctrl);
5029                udelay(40);
5030        }
5031
5032        tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5033        if (tp->link_config.active_duplex == DUPLEX_HALF)
5034                tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5035
5036        if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5037                if (current_link_up &&
5038                    tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5039                        tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5040                else
5041                        tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5042        }
5043
5044        /* ??? Without this setting Netgear GA302T PHY does not
5045         * ??? send/receive packets...
5046         */
5047        if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5048            tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5049                tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5050                tw32_f(MAC_MI_MODE, tp->mi_mode);
5051                udelay(80);
5052        }
5053
5054        tw32_f(MAC_MODE, tp->mac_mode);
5055        udelay(40);
5056
5057        tg3_phy_eee_adjust(tp, current_link_up);
5058
5059        if (tg3_flag(tp, USE_LINKCHG_REG)) {
5060                /* Polled via timer. */
5061                tw32_f(MAC_EVENT, 0);
5062        } else {
5063                tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5064        }
5065        udelay(40);
5066
5067        if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5068            current_link_up &&
5069            tp->link_config.active_speed == SPEED_1000 &&
5070            (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5071                udelay(120);
5072                tw32_f(MAC_STATUS,
5073                     (MAC_STATUS_SYNC_CHANGED |
5074                      MAC_STATUS_CFG_CHANGED));
5075                udelay(40);
5076                tg3_write_mem(tp,
5077                              NIC_SRAM_FIRMWARE_MBOX,
5078                              NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5079        }
5080
5081        /* Prevent send BD corruption. */
5082        if (tg3_flag(tp, CLKREQ_BUG)) {
5083                if (tp->link_config.active_speed == SPEED_100 ||
5084                    tp->link_config.active_speed == SPEED_10)
5085                        pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5086                                                   PCI_EXP_LNKCTL_CLKREQ_EN);
5087                else
5088                        pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5089                                                 PCI_EXP_LNKCTL_CLKREQ_EN);
5090        }
5091
5092        tg3_test_and_report_link_chg(tp, current_link_up);
5093
5094        return 0;
5095}
5096
5097struct tg3_fiber_aneginfo {
5098        int state;
5099#define ANEG_STATE_UNKNOWN              0
5100#define ANEG_STATE_AN_ENABLE            1
5101#define ANEG_STATE_RESTART_INIT         2
5102#define ANEG_STATE_RESTART              3
5103#define ANEG_STATE_DISABLE_LINK_OK      4
5104#define ANEG_STATE_ABILITY_DETECT_INIT  5
5105#define ANEG_STATE_ABILITY_DETECT       6
5106#define ANEG_STATE_ACK_DETECT_INIT      7
5107#define ANEG_STATE_ACK_DETECT           8
5108#define ANEG_STATE_COMPLETE_ACK_INIT    9
5109#define ANEG_STATE_COMPLETE_ACK         10
5110#define ANEG_STATE_IDLE_DETECT_INIT     11
5111#define ANEG_STATE_IDLE_DETECT          12
5112#define ANEG_STATE_LINK_OK              13
5113#define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
5114#define ANEG_STATE_NEXT_PAGE_WAIT       15
5115
5116        u32 flags;
5117#define MR_AN_ENABLE            0x00000001
5118#define MR_RESTART_AN           0x00000002
5119#define MR_AN_COMPLETE          0x00000004
5120#define MR_PAGE_RX              0x00000008
5121#define MR_NP_LOADED            0x00000010
5122#define MR_TOGGLE_TX            0x00000020
5123#define MR_LP_ADV_FULL_DUPLEX   0x00000040
5124#define MR_LP_ADV_HALF_DUPLEX   0x00000080
5125#define MR_LP_ADV_SYM_PAUSE     0x00000100
5126#define MR_LP_ADV_ASYM_PAUSE    0x00000200
5127#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5128#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5129#define MR_LP_ADV_NEXT_PAGE     0x00001000
5130#define MR_TOGGLE_RX            0x00002000
5131#define MR_NP_RX                0x00004000
5132
5133#define MR_LINK_OK              0x80000000
5134
5135        unsigned long link_time, cur_time;
5136
5137        u32 ability_match_cfg;
5138        int ability_match_count;
5139
5140        char ability_match, idle_match, ack_match;
5141
5142        u32 txconfig, rxconfig;
5143#define ANEG_CFG_NP             0x00000080
5144#define ANEG_CFG_ACK            0x00000040
5145#define ANEG_CFG_RF2            0x00000020
5146#define ANEG_CFG_RF1            0x00000010
5147#define ANEG_CFG_PS2            0x00000001
5148#define ANEG_CFG_PS1            0x00008000
5149#define ANEG_CFG_HD             0x00004000
5150#define ANEG_CFG_FD             0x00002000
5151#define ANEG_CFG_INVAL          0x00001f06
5152
5153};
5154#define ANEG_OK         0
5155#define ANEG_DONE       1
5156#define ANEG_TIMER_ENAB 2
5157#define ANEG_FAILED     -1
5158
5159#define ANEG_STATE_SETTLE_TIME  10000
5160
5161static int