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6
7#ifndef _MACB_H
8#define _MACB_H
9
10#include <linux/clk.h>
11#include <linux/phylink.h>
12#include <linux/ptp_clock_kernel.h>
13#include <linux/net_tstamp.h>
14#include <linux/interrupt.h>
15
16#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
17#define MACB_EXT_DESC
18#endif
19
20#define MACB_GREGS_NBR 16
21#define MACB_GREGS_VERSION 2
22#define MACB_MAX_QUEUES 8
23
24
25#define MACB_NCR 0x0000
26#define MACB_NCFGR 0x0004
27#define MACB_NSR 0x0008
28#define MACB_TAR 0x000c
29#define MACB_TCR 0x0010
30#define MACB_TSR 0x0014
31#define MACB_RBQP 0x0018
32#define MACB_TBQP 0x001c
33#define MACB_RSR 0x0020
34#define MACB_ISR 0x0024
35#define MACB_IER 0x0028
36#define MACB_IDR 0x002c
37#define MACB_IMR 0x0030
38#define MACB_MAN 0x0034
39#define MACB_PTR 0x0038
40#define MACB_PFR 0x003c
41#define MACB_FTO 0x0040
42#define MACB_SCF 0x0044
43#define MACB_MCF 0x0048
44#define MACB_FRO 0x004c
45#define MACB_FCSE 0x0050
46#define MACB_ALE 0x0054
47#define MACB_DTF 0x0058
48#define MACB_LCOL 0x005c
49#define MACB_EXCOL 0x0060
50#define MACB_TUND 0x0064
51#define MACB_CSE 0x0068
52#define MACB_RRE 0x006c
53#define MACB_ROVR 0x0070
54#define MACB_RSE 0x0074
55#define MACB_ELE 0x0078
56#define MACB_RJA 0x007c
57#define MACB_USF 0x0080
58#define MACB_STE 0x0084
59#define MACB_RLE 0x0088
60#define MACB_TPF 0x008c
61#define MACB_HRB 0x0090
62#define MACB_HRT 0x0094
63#define MACB_SA1B 0x0098
64#define MACB_SA1T 0x009c
65#define MACB_SA2B 0x00a0
66#define MACB_SA2T 0x00a4
67#define MACB_SA3B 0x00a8
68#define MACB_SA3T 0x00ac
69#define MACB_SA4B 0x00b0
70#define MACB_SA4T 0x00b4
71#define MACB_TID 0x00b8
72#define MACB_TPQ 0x00bc
73#define MACB_USRIO 0x00c0
74#define MACB_WOL 0x00c4
75#define MACB_MID 0x00fc
76#define MACB_TBQPH 0x04C8
77#define MACB_RBQPH 0x04D4
78
79
80#define GEM_NCR 0x0000
81#define GEM_NCFGR 0x0004
82#define GEM_USRIO 0x000c
83#define GEM_DMACFG 0x0010
84#define GEM_JML 0x0048
85#define GEM_HS_MAC_CONFIG 0x0050
86#define GEM_HRB 0x0080
87#define GEM_HRT 0x0084
88#define GEM_SA1B 0x0088
89#define GEM_SA1T 0x008C
90#define GEM_SA2B 0x0090
91#define GEM_SA2T 0x0094
92#define GEM_SA3B 0x0098
93#define GEM_SA3T 0x009C
94#define GEM_SA4B 0x00A0
95#define GEM_SA4T 0x00A4
96#define GEM_WOL 0x00b8
97#define GEM_EFTSH 0x00e8
98#define GEM_EFRSH 0x00ec
99#define GEM_PEFTSH 0x00f0
100#define GEM_PEFRSH 0x00f4
101#define GEM_OTX 0x0100
102#define GEM_OCTTXL 0x0100
103#define GEM_OCTTXH 0x0104
104#define GEM_TXCNT 0x0108
105#define GEM_TXBCCNT 0x010c
106#define GEM_TXMCCNT 0x0110
107#define GEM_TXPAUSECNT 0x0114
108#define GEM_TX64CNT 0x0118
109#define GEM_TX65CNT 0x011c
110#define GEM_TX128CNT 0x0120
111#define GEM_TX256CNT 0x0124
112#define GEM_TX512CNT 0x0128
113#define GEM_TX1024CNT 0x012c
114#define GEM_TX1519CNT 0x0130
115#define GEM_TXURUNCNT 0x0134
116#define GEM_SNGLCOLLCNT 0x0138
117#define GEM_MULTICOLLCNT 0x013c
118#define GEM_EXCESSCOLLCNT 0x0140
119#define GEM_LATECOLLCNT 0x0144
120#define GEM_TXDEFERCNT 0x0148
121#define GEM_TXCSENSECNT 0x014c
122#define GEM_ORX 0x0150
123#define GEM_OCTRXL 0x0150
124#define GEM_OCTRXH 0x0154
125#define GEM_RXCNT 0x0158
126#define GEM_RXBROADCNT 0x015c
127#define GEM_RXMULTICNT 0x0160
128#define GEM_RXPAUSECNT 0x0164
129#define GEM_RX64CNT 0x0168
130#define GEM_RX65CNT 0x016c
131#define GEM_RX128CNT 0x0170
132#define GEM_RX256CNT 0x0174
133#define GEM_RX512CNT 0x0178
134#define GEM_RX1024CNT 0x017c
135#define GEM_RX1519CNT 0x0180
136#define GEM_RXUNDRCNT 0x0184
137#define GEM_RXOVRCNT 0x0188
138#define GEM_RXJABCNT 0x018c
139#define GEM_RXFCSCNT 0x0190
140#define GEM_RXLENGTHCNT 0x0194
141#define GEM_RXSYMBCNT 0x0198
142#define GEM_RXALIGNCNT 0x019c
143#define GEM_RXRESERRCNT 0x01a0
144#define GEM_RXORCNT 0x01a4
145#define GEM_RXIPCCNT 0x01a8
146#define GEM_RXTCPCCNT 0x01ac
147#define GEM_RXUDPCCNT 0x01b0
148#define GEM_TISUBN 0x01bc
149#define GEM_TSH 0x01c0
150#define GEM_TSL 0x01d0
151#define GEM_TN 0x01d4
152#define GEM_TA 0x01d8
153#define GEM_TI 0x01dc
154#define GEM_EFTSL 0x01e0
155#define GEM_EFTN 0x01e4
156#define GEM_EFRSL 0x01e8
157#define GEM_EFRN 0x01ec
158#define GEM_PEFTSL 0x01f0
159#define GEM_PEFTN 0x01f4
160#define GEM_PEFRSL 0x01f8
161#define GEM_PEFRN 0x01fc
162#define GEM_PCSCNTRL 0x0200
163#define GEM_PCSSTS 0x0204
164#define GEM_PCSPHYTOPID 0x0208
165#define GEM_PCSPHYBOTID 0x020c
166#define GEM_PCSANADV 0x0210
167#define GEM_PCSANLPBASE 0x0214
168#define GEM_PCSANEXP 0x0218
169#define GEM_PCSANNPTX 0x021c
170#define GEM_PCSANNPLP 0x0220
171#define GEM_PCSANEXTSTS 0x023c
172#define GEM_DCFG1 0x0280
173#define GEM_DCFG2 0x0284
174#define GEM_DCFG3 0x0288
175#define GEM_DCFG4 0x028c
176#define GEM_DCFG5 0x0290
177#define GEM_DCFG6 0x0294
178#define GEM_DCFG7 0x0298
179#define GEM_DCFG8 0x029C
180#define GEM_DCFG10 0x02A4
181#define GEM_DCFG12 0x02AC
182#define GEM_USX_CONTROL 0x0A80
183#define GEM_USX_STATUS 0x0A88
184
185#define GEM_TXBDCTRL 0x04cc
186#define GEM_RXBDCTRL 0x04d0
187
188
189#define GEM_SCRT2 0x540
190
191
192#define GEM_ETHT 0x06E0
193
194
195#define GEM_T2CMPW0 0x0700
196#define GEM_T2CMPW1 0x0704
197#define T2CMP_OFST(t2idx) (t2idx * 2)
198
199
200
201
202#define GEM_IP4SRC_CMP(idx) (idx * 3)
203#define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
204#define GEM_PORT_CMP(idx) (idx * 3 + 2)
205
206
207#define SCRT2_ETHT 0
208
209#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
210#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
211#define GEM_TBQPH(hw_q) (0x04C8)
212#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
213#define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
214#define GEM_RBQPH(hw_q) (0x04D4)
215#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
216#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
217#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
218
219
220#define MACB_LB_OFFSET 0
221#define MACB_LB_SIZE 1
222#define MACB_LLB_OFFSET 1
223#define MACB_LLB_SIZE 1
224#define MACB_RE_OFFSET 2
225#define MACB_RE_SIZE 1
226#define MACB_TE_OFFSET 3
227#define MACB_TE_SIZE 1
228#define MACB_MPE_OFFSET 4
229#define MACB_MPE_SIZE 1
230#define MACB_CLRSTAT_OFFSET 5
231#define MACB_CLRSTAT_SIZE 1
232#define MACB_INCSTAT_OFFSET 6
233#define MACB_INCSTAT_SIZE 1
234#define MACB_WESTAT_OFFSET 7
235#define MACB_WESTAT_SIZE 1
236#define MACB_BP_OFFSET 8
237#define MACB_BP_SIZE 1
238#define MACB_TSTART_OFFSET 9
239#define MACB_TSTART_SIZE 1
240#define MACB_THALT_OFFSET 10
241#define MACB_THALT_SIZE 1
242#define MACB_NCR_TPF_OFFSET 11
243#define MACB_NCR_TPF_SIZE 1
244#define MACB_TZQ_OFFSET 12
245#define MACB_TZQ_SIZE 1
246#define MACB_SRTSM_OFFSET 15
247#define MACB_OSSMODE_OFFSET 24
248#define MACB_OSSMODE_SIZE 1
249
250
251#define MACB_SPD_OFFSET 0
252#define MACB_SPD_SIZE 1
253#define MACB_FD_OFFSET 1
254#define MACB_FD_SIZE 1
255#define MACB_BIT_RATE_OFFSET 2
256#define MACB_BIT_RATE_SIZE 1
257#define MACB_JFRAME_OFFSET 3
258#define MACB_JFRAME_SIZE 1
259#define MACB_CAF_OFFSET 4
260#define MACB_CAF_SIZE 1
261#define MACB_NBC_OFFSET 5
262#define MACB_NBC_SIZE 1
263#define MACB_NCFGR_MTI_OFFSET 6
264#define MACB_NCFGR_MTI_SIZE 1
265#define MACB_UNI_OFFSET 7
266#define MACB_UNI_SIZE 1
267#define MACB_BIG_OFFSET 8
268#define MACB_BIG_SIZE 1
269#define MACB_EAE_OFFSET 9
270#define MACB_EAE_SIZE 1
271#define MACB_CLK_OFFSET 10
272#define MACB_CLK_SIZE 2
273#define MACB_RTY_OFFSET 12
274#define MACB_RTY_SIZE 1
275#define MACB_PAE_OFFSET 13
276#define MACB_PAE_SIZE 1
277#define MACB_RM9200_RMII_OFFSET 13
278#define MACB_RM9200_RMII_SIZE 1
279#define MACB_RBOF_OFFSET 14
280#define MACB_RBOF_SIZE 2
281#define MACB_RLCE_OFFSET 16
282#define MACB_RLCE_SIZE 1
283#define MACB_DRFCS_OFFSET 17
284#define MACB_DRFCS_SIZE 1
285#define MACB_EFRHD_OFFSET 18
286#define MACB_EFRHD_SIZE 1
287#define MACB_IRXFCS_OFFSET 19
288#define MACB_IRXFCS_SIZE 1
289
290
291#define GEM_ENABLE_HS_MAC_OFFSET 31
292#define GEM_ENABLE_HS_MAC_SIZE 1
293
294
295#define GEM_FD_OFFSET 1
296#define GEM_FD_SIZE 1
297#define GEM_GBE_OFFSET 10
298#define GEM_GBE_SIZE 1
299#define GEM_PCSSEL_OFFSET 11
300#define GEM_PCSSEL_SIZE 1
301#define GEM_PAE_OFFSET 13
302#define GEM_PAE_SIZE 1
303#define GEM_CLK_OFFSET 18
304#define GEM_CLK_SIZE 3
305#define GEM_DBW_OFFSET 21
306#define GEM_DBW_SIZE 2
307#define GEM_RXCOEN_OFFSET 24
308#define GEM_RXCOEN_SIZE 1
309#define GEM_SGMIIEN_OFFSET 27
310#define GEM_SGMIIEN_SIZE 1
311
312
313
314#define GEM_DBW32 0
315#define GEM_DBW64 1
316#define GEM_DBW128 2
317
318
319#define GEM_FBLDO_OFFSET 0
320#define GEM_FBLDO_SIZE 5
321#define GEM_ENDIA_DESC_OFFSET 6
322#define GEM_ENDIA_DESC_SIZE 1
323#define GEM_ENDIA_PKT_OFFSET 7
324#define GEM_ENDIA_PKT_SIZE 1
325#define GEM_RXBMS_OFFSET 8
326#define GEM_RXBMS_SIZE 2
327#define GEM_TXPBMS_OFFSET 10
328#define GEM_TXPBMS_SIZE 1
329#define GEM_TXCOEN_OFFSET 11
330#define GEM_TXCOEN_SIZE 1
331#define GEM_RXBS_OFFSET 16
332#define GEM_RXBS_SIZE 8
333#define GEM_DDRP_OFFSET 24
334#define GEM_DDRP_SIZE 1
335#define GEM_RXEXT_OFFSET 28
336#define GEM_RXEXT_SIZE 1
337#define GEM_TXEXT_OFFSET 29
338#define GEM_TXEXT_SIZE 1
339#define GEM_ADDR64_OFFSET 30
340#define GEM_ADDR64_SIZE 1
341
342
343
344#define MACB_NSR_LINK_OFFSET 0
345#define MACB_NSR_LINK_SIZE 1
346#define MACB_MDIO_OFFSET 1
347#define MACB_MDIO_SIZE 1
348#define MACB_IDLE_OFFSET 2
349#define MACB_IDLE_SIZE 1
350
351
352#define MACB_UBR_OFFSET 0
353#define MACB_UBR_SIZE 1
354#define MACB_COL_OFFSET 1
355#define MACB_COL_SIZE 1
356#define MACB_TSR_RLE_OFFSET 2
357#define MACB_TSR_RLE_SIZE 1
358#define MACB_TGO_OFFSET 3
359#define MACB_TGO_SIZE 1
360#define MACB_BEX_OFFSET 4
361#define MACB_BEX_SIZE 1
362#define MACB_RM9200_BNQ_OFFSET 4
363#define MACB_RM9200_BNQ_SIZE 1
364#define MACB_COMP_OFFSET 5
365#define MACB_COMP_SIZE 1
366#define MACB_UND_OFFSET 6
367#define MACB_UND_SIZE 1
368
369
370#define MACB_BNA_OFFSET 0
371#define MACB_BNA_SIZE 1
372#define MACB_REC_OFFSET 1
373#define MACB_REC_SIZE 1
374#define MACB_OVR_OFFSET 2
375#define MACB_OVR_SIZE 1
376
377
378#define MACB_MFD_OFFSET 0
379#define MACB_MFD_SIZE 1
380#define MACB_RCOMP_OFFSET 1
381#define MACB_RCOMP_SIZE 1
382#define MACB_RXUBR_OFFSET 2
383#define MACB_RXUBR_SIZE 1
384#define MACB_TXUBR_OFFSET 3
385#define MACB_TXUBR_SIZE 1
386#define MACB_ISR_TUND_OFFSET 4
387#define MACB_ISR_TUND_SIZE 1
388#define MACB_ISR_RLE_OFFSET 5
389#define MACB_ISR_RLE_SIZE 1
390#define MACB_TXERR_OFFSET 6
391#define MACB_TXERR_SIZE 1
392#define MACB_RM9200_TBRE_OFFSET 6
393#define MACB_RM9200_TBRE_SIZE 1
394#define MACB_TCOMP_OFFSET 7
395#define MACB_TCOMP_SIZE 1
396#define MACB_ISR_LINK_OFFSET 9
397#define MACB_ISR_LINK_SIZE 1
398#define MACB_ISR_ROVR_OFFSET 10
399#define MACB_ISR_ROVR_SIZE 1
400#define MACB_HRESP_OFFSET 11
401#define MACB_HRESP_SIZE 1
402#define MACB_PFR_OFFSET 12
403#define MACB_PFR_SIZE 1
404#define MACB_PTZ_OFFSET 13
405#define MACB_PTZ_SIZE 1
406#define MACB_WOL_OFFSET 14
407#define MACB_WOL_SIZE 1
408#define MACB_DRQFR_OFFSET 18
409#define MACB_DRQFR_SIZE 1
410#define MACB_SFR_OFFSET 19
411#define MACB_SFR_SIZE 1
412#define MACB_DRQFT_OFFSET 20
413#define MACB_DRQFT_SIZE 1
414#define MACB_SFT_OFFSET 21
415#define MACB_SFT_SIZE 1
416#define MACB_PDRQFR_OFFSET 22
417#define MACB_PDRQFR_SIZE 1
418#define MACB_PDRSFR_OFFSET 23
419#define MACB_PDRSFR_SIZE 1
420#define MACB_PDRQFT_OFFSET 24
421#define MACB_PDRQFT_SIZE 1
422#define MACB_PDRSFT_OFFSET 25
423#define MACB_PDRSFT_SIZE 1
424#define MACB_SRI_OFFSET 26
425#define MACB_SRI_SIZE 1
426#define GEM_WOL_OFFSET 28
427#define GEM_WOL_SIZE 1
428
429
430#define MACB_TI_CNS_OFFSET 0
431#define MACB_TI_CNS_SIZE 8
432#define MACB_TI_ACNS_OFFSET 8
433#define MACB_TI_ACNS_SIZE 8
434#define MACB_TI_NIT_OFFSET 16
435#define MACB_TI_NIT_SIZE 8
436
437
438#define MACB_DATA_OFFSET 0
439#define MACB_DATA_SIZE 16
440#define MACB_CODE_OFFSET 16
441#define MACB_CODE_SIZE 2
442#define MACB_REGA_OFFSET 18
443#define MACB_REGA_SIZE 5
444#define MACB_PHYA_OFFSET 23
445#define MACB_PHYA_SIZE 5
446#define MACB_RW_OFFSET 28
447#define MACB_RW_SIZE 2
448#define MACB_SOF_OFFSET 30
449#define MACB_SOF_SIZE 2
450
451
452#define MACB_MII_OFFSET 0
453#define MACB_MII_SIZE 1
454#define MACB_EAM_OFFSET 1
455#define MACB_EAM_SIZE 1
456#define MACB_TX_PAUSE_OFFSET 2
457#define MACB_TX_PAUSE_SIZE 1
458#define MACB_TX_PAUSE_ZERO_OFFSET 3
459#define MACB_TX_PAUSE_ZERO_SIZE 1
460
461
462#define MACB_RMII_OFFSET 0
463#define MACB_RMII_SIZE 1
464#define GEM_RGMII_OFFSET 0
465#define GEM_RGMII_SIZE 1
466#define MACB_CLKEN_OFFSET 1
467#define MACB_CLKEN_SIZE 1
468
469
470#define MACB_IP_OFFSET 0
471#define MACB_IP_SIZE 16
472#define MACB_MAG_OFFSET 16
473#define MACB_MAG_SIZE 1
474#define MACB_ARP_OFFSET 17
475#define MACB_ARP_SIZE 1
476#define MACB_SA1_OFFSET 18
477#define MACB_SA1_SIZE 1
478#define MACB_WOL_MTI_OFFSET 19
479#define MACB_WOL_MTI_SIZE 1
480
481
482#define MACB_IDNUM_OFFSET 16
483#define MACB_IDNUM_SIZE 12
484#define MACB_REV_OFFSET 0
485#define MACB_REV_SIZE 16
486
487
488#define GEM_HS_MAC_SPEED_OFFSET 0
489#define GEM_HS_MAC_SPEED_SIZE 3
490
491
492#define GEM_PCSAUTONEG_OFFSET 12
493#define GEM_PCSAUTONEG_SIZE 1
494
495
496#define GEM_IRQCOR_OFFSET 23
497#define GEM_IRQCOR_SIZE 1
498#define GEM_DBWDEF_OFFSET 25
499#define GEM_DBWDEF_SIZE 3
500#define GEM_NO_PCS_OFFSET 0
501#define GEM_NO_PCS_SIZE 1
502
503
504#define GEM_RX_PKT_BUFF_OFFSET 20
505#define GEM_RX_PKT_BUFF_SIZE 1
506#define GEM_TX_PKT_BUFF_OFFSET 21
507#define GEM_TX_PKT_BUFF_SIZE 1
508
509
510
511#define GEM_TSU_OFFSET 8
512#define GEM_TSU_SIZE 1
513
514
515#define GEM_PBUF_LSO_OFFSET 27
516#define GEM_PBUF_LSO_SIZE 1
517#define GEM_DAW64_OFFSET 23
518#define GEM_DAW64_SIZE 1
519
520
521#define GEM_T1SCR_OFFSET 24
522#define GEM_T1SCR_SIZE 8
523#define GEM_T2SCR_OFFSET 16
524#define GEM_T2SCR_SIZE 8
525#define GEM_SCR2ETH_OFFSET 8
526#define GEM_SCR2ETH_SIZE 8
527#define GEM_SCR2CMP_OFFSET 0
528#define GEM_SCR2CMP_SIZE 8
529
530
531#define GEM_TXBD_RDBUFF_OFFSET 12
532#define GEM_TXBD_RDBUFF_SIZE 4
533#define GEM_RXBD_RDBUFF_OFFSET 8
534#define GEM_RXBD_RDBUFF_SIZE 4
535
536
537#define GEM_HIGH_SPEED_OFFSET 26
538#define GEM_HIGH_SPEED_SIZE 1
539
540
541#define GEM_USX_CTRL_SPEED_OFFSET 14
542#define GEM_USX_CTRL_SPEED_SIZE 3
543#define GEM_SERDES_RATE_OFFSET 12
544#define GEM_SERDES_RATE_SIZE 2
545#define GEM_RX_SCR_BYPASS_OFFSET 9
546#define GEM_RX_SCR_BYPASS_SIZE 1
547#define GEM_TX_SCR_BYPASS_OFFSET 8
548#define GEM_TX_SCR_BYPASS_SIZE 1
549#define GEM_TX_EN_OFFSET 1
550#define GEM_TX_EN_SIZE 1
551#define GEM_SIGNAL_OK_OFFSET 0
552#define GEM_SIGNAL_OK_SIZE 1
553
554
555#define GEM_USX_BLOCK_LOCK_OFFSET 0
556#define GEM_USX_BLOCK_LOCK_SIZE 1
557
558
559#define GEM_SUBNSINCR_OFFSET 0
560#define GEM_SUBNSINCRL_OFFSET 24
561#define GEM_SUBNSINCRL_SIZE 8
562#define GEM_SUBNSINCRH_OFFSET 0
563#define GEM_SUBNSINCRH_SIZE 16
564#define GEM_SUBNSINCR_SIZE 24
565
566
567#define GEM_NSINCR_OFFSET 0
568#define GEM_NSINCR_SIZE 8
569
570
571#define GEM_TSH_OFFSET 0
572#define GEM_TSH_SIZE 16
573
574
575#define GEM_TSL_OFFSET 0
576#define GEM_TSL_SIZE 32
577
578
579#define GEM_TN_OFFSET 0
580#define GEM_TN_SIZE 30
581
582
583#define GEM_TXTSMODE_OFFSET 4
584#define GEM_TXTSMODE_SIZE 2
585
586
587#define GEM_RXTSMODE_OFFSET 4
588#define GEM_RXTSMODE_SIZE 2
589
590
591#define GEM_QUEUE_OFFSET 0
592#define GEM_QUEUE_SIZE 4
593#define GEM_VLANPR_OFFSET 4
594#define GEM_VLANPR_SIZE 3
595#define GEM_VLANEN_OFFSET 8
596#define GEM_VLANEN_SIZE 1
597#define GEM_ETHT2IDX_OFFSET 9
598#define GEM_ETHT2IDX_SIZE 3
599#define GEM_ETHTEN_OFFSET 12
600#define GEM_ETHTEN_SIZE 1
601#define GEM_CMPA_OFFSET 13
602#define GEM_CMPA_SIZE 5
603#define GEM_CMPAEN_OFFSET 18
604#define GEM_CMPAEN_SIZE 1
605#define GEM_CMPB_OFFSET 19
606#define GEM_CMPB_SIZE 5
607#define GEM_CMPBEN_OFFSET 24
608#define GEM_CMPBEN_SIZE 1
609#define GEM_CMPC_OFFSET 25
610#define GEM_CMPC_SIZE 5
611#define GEM_CMPCEN_OFFSET 30
612#define GEM_CMPCEN_SIZE 1
613
614
615#define GEM_ETHTCMP_OFFSET 0
616#define GEM_ETHTCMP_SIZE 16
617
618
619#define GEM_T2CMP_OFFSET 16
620#define GEM_T2CMP_SIZE 16
621#define GEM_T2MASK_OFFSET 0
622#define GEM_T2MASK_SIZE 16
623
624
625#define GEM_T2DISMSK_OFFSET 9
626#define GEM_T2DISMSK_SIZE 1
627#define GEM_T2CMPOFST_OFFSET 7
628#define GEM_T2CMPOFST_SIZE 2
629#define GEM_T2OFST_OFFSET 0
630#define GEM_T2OFST_SIZE 7
631
632
633
634
635
636
637#define GEM_T2COMPOFST_SOF 0
638#define GEM_T2COMPOFST_ETYPE 1
639#define GEM_T2COMPOFST_IPHDR 2
640#define GEM_T2COMPOFST_TCPUDP 3
641
642
643#define ETYPE_SRCIP_OFFSET 12
644#define ETYPE_DSTIP_OFFSET 16
645
646
647#define IPHDR_SRCPORT_OFFSET 0
648#define IPHDR_DSTPORT_OFFSET 2
649
650
651#define GEM_DMA_TXVALID_OFFSET 23
652#define GEM_DMA_TXVALID_SIZE 1
653
654
655#define GEM_DMA_RXVALID_OFFSET 2
656#define GEM_DMA_RXVALID_SIZE 1
657
658
659#define GEM_DMA_SECL_OFFSET 30
660#define GEM_DMA_SECL_SIZE 2
661#define GEM_DMA_NSEC_OFFSET 0
662#define GEM_DMA_NSEC_SIZE 30
663
664
665
666
667
668
669
670#define GEM_DMA_SECH_OFFSET 0
671#define GEM_DMA_SECH_SIZE 4
672#define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
673#define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
674#define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
675
676
677#define GEM_ADDSUB_OFFSET 31
678#define GEM_ADDSUB_SIZE 1
679
680#define MACB_CLK_DIV8 0
681#define MACB_CLK_DIV16 1
682#define MACB_CLK_DIV32 2
683#define MACB_CLK_DIV64 3
684
685
686#define GEM_CLK_DIV8 0
687#define GEM_CLK_DIV16 1
688#define GEM_CLK_DIV32 2
689#define GEM_CLK_DIV48 3
690#define GEM_CLK_DIV64 4
691#define GEM_CLK_DIV96 5
692
693
694#define MACB_MAN_C22_SOF 1
695#define MACB_MAN_C22_WRITE 1
696#define MACB_MAN_C22_READ 2
697#define MACB_MAN_C22_CODE 2
698
699#define MACB_MAN_C45_SOF 0
700#define MACB_MAN_C45_ADDR 0
701#define MACB_MAN_C45_WRITE 1
702#define MACB_MAN_C45_POST_READ_INCR 2
703#define MACB_MAN_C45_READ 3
704#define MACB_MAN_C45_CODE 2
705
706
707#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
708#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
709#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
710#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
711#define MACB_CAPS_USRIO_DISABLED 0x00000010
712#define MACB_CAPS_JUMBO 0x00000020
713#define MACB_CAPS_GEM_HAS_PTP 0x00000040
714#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
715#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
716#define MACB_CAPS_CLK_HW_CHG 0x04000000
717#define MACB_CAPS_MACB_IS_EMAC 0x08000000
718#define MACB_CAPS_FIFO_MODE 0x10000000
719#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
720#define MACB_CAPS_SG_DISABLED 0x40000000
721#define MACB_CAPS_MACB_IS_GEM 0x80000000
722#define MACB_CAPS_PCS 0x01000000
723#define MACB_CAPS_HIGH_SPEED 0x02000000
724
725
726#define MACB_LSO_UFO_ENABLE 0x01
727#define MACB_LSO_TSO_ENABLE 0x02
728
729
730#define MACB_BIT(name) \
731 (1 << MACB_##name##_OFFSET)
732#define MACB_BF(name,value) \
733 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
734 << MACB_##name##_OFFSET)
735#define MACB_BFEXT(name,value)\
736 (((value) >> MACB_##name##_OFFSET) \
737 & ((1 << MACB_##name##_SIZE) - 1))
738#define MACB_BFINS(name,value,old) \
739 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
740 << MACB_##name##_OFFSET)) \
741 | MACB_BF(name,value))
742
743#define GEM_BIT(name) \
744 (1 << GEM_##name##_OFFSET)
745#define GEM_BF(name, value) \
746 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
747 << GEM_##name##_OFFSET)
748#define GEM_BFEXT(name, value)\
749 (((value) >> GEM_##name##_OFFSET) \
750 & ((1 << GEM_##name##_SIZE) - 1))
751#define GEM_BFINS(name, value, old) \
752 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
753 << GEM_##name##_OFFSET)) \
754 | GEM_BF(name, value))
755
756
757#define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
758#define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
759#define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
760#define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
761#define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
762#define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
763#define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
764#define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
765
766#define PTP_TS_BUFFER_SIZE 128
767
768
769
770
771
772
773#define macb_or_gem_writel(__bp, __reg, __value) \
774 ({ \
775 if (macb_is_gem((__bp))) \
776 gem_writel((__bp), __reg, __value); \
777 else \
778 macb_writel((__bp), __reg, __value); \
779 })
780
781#define macb_or_gem_readl(__bp, __reg) \
782 ({ \
783 u32 __v; \
784 if (macb_is_gem((__bp))) \
785 __v = gem_readl((__bp), __reg); \
786 else \
787 __v = macb_readl((__bp), __reg); \
788 __v; \
789 })
790
791#define MACB_READ_NSR(bp) macb_readl(bp, NSR)
792
793
794
795
796
797struct macb_dma_desc {
798 u32 addr;
799 u32 ctrl;
800};
801
802#ifdef MACB_EXT_DESC
803#define HW_DMA_CAP_32B 0
804#define HW_DMA_CAP_64B (1 << 0)
805#define HW_DMA_CAP_PTP (1 << 1)
806#define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
807
808struct macb_dma_desc_64 {
809 u32 addrh;
810 u32 resvd;
811};
812
813struct macb_dma_desc_ptp {
814 u32 ts_1;
815 u32 ts_2;
816};
817
818struct gem_tx_ts {
819 struct sk_buff *skb;
820 struct macb_dma_desc_ptp desc_ptp;
821};
822#endif
823
824
825#define MACB_RX_USED_OFFSET 0
826#define MACB_RX_USED_SIZE 1
827#define MACB_RX_WRAP_OFFSET 1
828#define MACB_RX_WRAP_SIZE 1
829#define MACB_RX_WADDR_OFFSET 2
830#define MACB_RX_WADDR_SIZE 30
831
832#define MACB_RX_FRMLEN_OFFSET 0
833#define MACB_RX_FRMLEN_SIZE 12
834#define MACB_RX_OFFSET_OFFSET 12
835#define MACB_RX_OFFSET_SIZE 2
836#define MACB_RX_SOF_OFFSET 14
837#define MACB_RX_SOF_SIZE 1
838#define MACB_RX_EOF_OFFSET 15
839#define MACB_RX_EOF_SIZE 1
840#define MACB_RX_CFI_OFFSET 16
841#define MACB_RX_CFI_SIZE 1
842#define MACB_RX_VLAN_PRI_OFFSET 17
843#define MACB_RX_VLAN_PRI_SIZE 3
844#define MACB_RX_PRI_TAG_OFFSET 20
845#define MACB_RX_PRI_TAG_SIZE 1
846#define MACB_RX_VLAN_TAG_OFFSET 21
847#define MACB_RX_VLAN_TAG_SIZE 1
848#define MACB_RX_TYPEID_MATCH_OFFSET 22
849#define MACB_RX_TYPEID_MATCH_SIZE 1
850#define MACB_RX_SA4_MATCH_OFFSET 23
851#define MACB_RX_SA4_MATCH_SIZE 1
852#define MACB_RX_SA3_MATCH_OFFSET 24
853#define MACB_RX_SA3_MATCH_SIZE 1
854#define MACB_RX_SA2_MATCH_OFFSET 25
855#define MACB_RX_SA2_MATCH_SIZE 1
856#define MACB_RX_SA1_MATCH_OFFSET 26
857#define MACB_RX_SA1_MATCH_SIZE 1
858#define MACB_RX_EXT_MATCH_OFFSET 28
859#define MACB_RX_EXT_MATCH_SIZE 1
860#define MACB_RX_UHASH_MATCH_OFFSET 29
861#define MACB_RX_UHASH_MATCH_SIZE 1
862#define MACB_RX_MHASH_MATCH_OFFSET 30
863#define MACB_RX_MHASH_MATCH_SIZE 1
864#define MACB_RX_BROADCAST_OFFSET 31
865#define MACB_RX_BROADCAST_SIZE 1
866
867#define MACB_RX_FRMLEN_MASK 0xFFF
868#define MACB_RX_JFRMLEN_MASK 0x3FFF
869
870
871#define GEM_RX_TYPEID_MATCH_OFFSET 22
872#define GEM_RX_TYPEID_MATCH_SIZE 2
873
874
875#define GEM_RX_CSUM_OFFSET 22
876#define GEM_RX_CSUM_SIZE 2
877
878#define MACB_TX_FRMLEN_OFFSET 0
879#define MACB_TX_FRMLEN_SIZE 11
880#define MACB_TX_LAST_OFFSET 15
881#define MACB_TX_LAST_SIZE 1
882#define MACB_TX_NOCRC_OFFSET 16
883#define MACB_TX_NOCRC_SIZE 1
884#define MACB_MSS_MFS_OFFSET 16
885#define MACB_MSS_MFS_SIZE 14
886#define MACB_TX_LSO_OFFSET 17
887#define MACB_TX_LSO_SIZE 2
888#define MACB_TX_TCP_SEQ_SRC_OFFSET 19
889#define MACB_TX_TCP_SEQ_SRC_SIZE 1
890#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
891#define MACB_TX_BUF_EXHAUSTED_SIZE 1
892#define MACB_TX_UNDERRUN_OFFSET 28
893#define MACB_TX_UNDERRUN_SIZE 1
894#define MACB_TX_ERROR_OFFSET 29
895#define MACB_TX_ERROR_SIZE 1
896#define MACB_TX_WRAP_OFFSET 30
897#define MACB_TX_WRAP_SIZE 1
898#define MACB_TX_USED_OFFSET 31
899#define MACB_TX_USED_SIZE 1
900
901#define GEM_TX_FRMLEN_OFFSET 0
902#define GEM_TX_FRMLEN_SIZE 14
903
904
905#define GEM_RX_CSUM_NONE 0
906#define GEM_RX_CSUM_IP_ONLY 1
907#define GEM_RX_CSUM_IP_TCP 2
908#define GEM_RX_CSUM_IP_UDP 3
909
910
911#define GEM_RX_CSUM_CHECKED_MASK 2
912
913
914#define PPM_FRACTION 16
915
916
917
918
919
920
921
922
923
924struct macb_tx_skb {
925 struct sk_buff *skb;
926 dma_addr_t mapping;
927 size_t size;
928 bool mapped_as_page;
929};
930
931
932
933
934struct macb_stats {
935 u32 rx_pause_frames;
936 u32 tx_ok;
937 u32 tx_single_cols;
938 u32 tx_multiple_cols;
939 u32 rx_ok;
940 u32 rx_fcs_errors;
941 u32 rx_align_errors;
942 u32 tx_deferred;
943 u32 tx_late_cols;
944 u32 tx_excessive_cols;
945 u32 tx_underruns;
946 u32 tx_carrier_errors;
947 u32 rx_resource_errors;
948 u32 rx_overruns;
949 u32 rx_symbol_errors;
950 u32 rx_oversize_pkts;
951 u32 rx_jabbers;
952 u32 rx_undersize_pkts;
953 u32 sqe_test_errors;
954 u32 rx_length_mismatch;
955 u32 tx_pause_frames;
956};
957
958struct gem_stats {
959 u32 tx_octets_31_0;
960 u32 tx_octets_47_32;
961 u32 tx_frames;
962 u32 tx_broadcast_frames;
963 u32 tx_multicast_frames;
964 u32 tx_pause_frames;
965 u32 tx_64_byte_frames;
966 u32 tx_65_127_byte_frames;
967 u32 tx_128_255_byte_frames;
968 u32 tx_256_511_byte_frames;
969 u32 tx_512_1023_byte_frames;
970 u32 tx_1024_1518_byte_frames;
971 u32 tx_greater_than_1518_byte_frames;
972 u32 tx_underrun;
973 u32 tx_single_collision_frames;
974 u32 tx_multiple_collision_frames;
975 u32 tx_excessive_collisions;
976 u32 tx_late_collisions;
977 u32 tx_deferred_frames;
978 u32 tx_carrier_sense_errors;
979 u32 rx_octets_31_0;
980 u32 rx_octets_47_32;
981 u32 rx_frames;
982 u32 rx_broadcast_frames;
983 u32 rx_multicast_frames;
984 u32 rx_pause_frames;
985 u32 rx_64_byte_frames;
986 u32 rx_65_127_byte_frames;
987 u32 rx_128_255_byte_frames;
988 u32 rx_256_511_byte_frames;
989 u32 rx_512_1023_byte_frames;
990 u32 rx_1024_1518_byte_frames;
991 u32 rx_greater_than_1518_byte_frames;
992 u32 rx_undersized_frames;
993 u32 rx_oversize_frames;
994 u32 rx_jabbers;
995 u32 rx_frame_check_sequence_errors;
996 u32 rx_length_field_frame_errors;
997 u32 rx_symbol_errors;
998 u32 rx_alignment_errors;
999 u32 rx_resource_errors;
1000 u32 rx_overruns;
1001 u32 rx_ip_header_checksum_errors;
1002 u32 rx_tcp_checksum_errors;
1003 u32 rx_udp_checksum_errors;
1004};
1005
1006
1007
1008
1009
1010struct gem_statistic {
1011 char stat_string[ETH_GSTRING_LEN];
1012 int offset;
1013 u32 stat_bits;
1014};
1015
1016
1017#define GEM_NDS_RXERR_OFFSET 0
1018#define GEM_NDS_RXLENERR_OFFSET 1
1019#define GEM_NDS_RXOVERERR_OFFSET 2
1020#define GEM_NDS_RXCRCERR_OFFSET 3
1021#define GEM_NDS_RXFRAMEERR_OFFSET 4
1022#define GEM_NDS_RXFIFOERR_OFFSET 5
1023#define GEM_NDS_TXERR_OFFSET 6
1024#define GEM_NDS_TXABORTEDERR_OFFSET 7
1025#define GEM_NDS_TXCARRIERERR_OFFSET 8
1026#define GEM_NDS_TXFIFOERR_OFFSET 9
1027#define GEM_NDS_COLLISIONS_OFFSET 10
1028
1029#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
1030#define GEM_STAT_TITLE_BITS(name, title, bits) { \
1031 .stat_string = title, \
1032 .offset = GEM_##name, \
1033 .stat_bits = bits \
1034}
1035
1036
1037
1038
1039static const struct gem_statistic gem_statistics[] = {
1040 GEM_STAT_TITLE(OCTTXL, "tx_octets"),
1041 GEM_STAT_TITLE(TXCNT, "tx_frames"),
1042 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
1043 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
1044 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
1045 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
1046 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
1047 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
1048 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
1049 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
1050 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
1051 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
1052 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
1053 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
1054 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
1055 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1056 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
1057 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1058 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
1059 GEM_BIT(NDS_TXERR)|
1060 GEM_BIT(NDS_TXABORTEDERR)|
1061 GEM_BIT(NDS_COLLISIONS)),
1062 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
1063 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1064 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
1065 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
1066 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1067 GEM_STAT_TITLE(OCTRXL, "rx_octets"),
1068 GEM_STAT_TITLE(RXCNT, "rx_frames"),
1069 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
1070 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
1071 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1072 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1073 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1074 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1075 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1076 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1077 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1078 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1079 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1080 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1081 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1082 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1083 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1084 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1085 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1086 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1087 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1088 GEM_BIT(NDS_RXERR)),
1089 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1090 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1091 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1092 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1093 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1094 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1095 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1096 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1097 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1098 GEM_BIT(NDS_RXERR)),
1099 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1100 GEM_BIT(NDS_RXERR)),
1101 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1102 GEM_BIT(NDS_RXERR)),
1103};
1104
1105#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1106
1107#define QUEUE_STAT_TITLE(title) { \
1108 .stat_string = title, \
1109}
1110
1111
1112struct queue_stats {
1113 union {
1114 unsigned long first;
1115 unsigned long rx_packets;
1116 };
1117 unsigned long rx_bytes;
1118 unsigned long rx_dropped;
1119 unsigned long tx_packets;
1120 unsigned long tx_bytes;
1121 unsigned long tx_dropped;
1122};
1123
1124static const struct gem_statistic queue_statistics[] = {
1125 QUEUE_STAT_TITLE("rx_packets"),
1126 QUEUE_STAT_TITLE("rx_bytes"),
1127 QUEUE_STAT_TITLE("rx_dropped"),
1128 QUEUE_STAT_TITLE("tx_packets"),
1129 QUEUE_STAT_TITLE("tx_bytes"),
1130 QUEUE_STAT_TITLE("tx_dropped"),
1131};
1132
1133#define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1134
1135struct macb;
1136struct macb_queue;
1137
1138struct macb_or_gem_ops {
1139 int (*mog_alloc_rx_buffers)(struct macb *bp);
1140 void (*mog_free_rx_buffers)(struct macb *bp);
1141 void (*mog_init_rings)(struct macb *bp);
1142 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1143 int budget);
1144};
1145
1146
1147struct macb_ptp_info {
1148 void (*ptp_init)(struct net_device *ndev);
1149 void (*ptp_remove)(struct net_device *ndev);
1150 s32 (*get_ptp_max_adj)(void);
1151 unsigned int (*get_tsu_rate)(struct macb *bp);
1152 int (*get_ts_info)(struct net_device *dev,
1153 struct ethtool_ts_info *info);
1154 int (*get_hwtst)(struct net_device *netdev,
1155 struct ifreq *ifr);
1156 int (*set_hwtst)(struct net_device *netdev,
1157 struct ifreq *ifr, int cmd);
1158};
1159
1160struct macb_pm_data {
1161 u32 scrt2;
1162 u32 usrio;
1163};
1164
1165struct macb_usrio_config {
1166 u32 mii;
1167 u32 rmii;
1168 u32 rgmii;
1169 u32 refclk;
1170 u32 hdfctlen;
1171};
1172
1173struct macb_config {
1174 u32 caps;
1175 unsigned int dma_burst_length;
1176 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1177 struct clk **hclk, struct clk **tx_clk,
1178 struct clk **rx_clk, struct clk **tsu_clk);
1179 int (*init)(struct platform_device *pdev);
1180 int jumbo_max_len;
1181 const struct macb_usrio_config *usrio;
1182};
1183
1184struct tsu_incr {
1185 u32 sub_ns;
1186 u32 ns;
1187};
1188
1189struct macb_queue {
1190 struct macb *bp;
1191 int irq;
1192
1193 unsigned int ISR;
1194 unsigned int IER;
1195 unsigned int IDR;
1196 unsigned int IMR;
1197 unsigned int TBQP;
1198 unsigned int TBQPH;
1199 unsigned int RBQS;
1200 unsigned int RBQP;
1201 unsigned int RBQPH;
1202
1203 unsigned int tx_head, tx_tail;
1204 struct macb_dma_desc *tx_ring;
1205 struct macb_tx_skb *tx_skb;
1206 dma_addr_t tx_ring_dma;
1207 struct work_struct tx_error_task;
1208
1209 dma_addr_t rx_ring_dma;
1210 dma_addr_t rx_buffers_dma;
1211 unsigned int rx_tail;
1212 unsigned int rx_prepared_head;
1213 struct macb_dma_desc *rx_ring;
1214 struct sk_buff **rx_skbuff;
1215 void *rx_buffers;
1216 struct napi_struct napi;
1217 struct queue_stats stats;
1218
1219#ifdef CONFIG_MACB_USE_HWSTAMP
1220 struct work_struct tx_ts_task;
1221 unsigned int tx_ts_head, tx_ts_tail;
1222 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
1223#endif
1224};
1225
1226struct ethtool_rx_fs_item {
1227 struct ethtool_rx_flow_spec fs;
1228 struct list_head list;
1229};
1230
1231struct ethtool_rx_fs_list {
1232 struct list_head list;
1233 unsigned int count;
1234};
1235
1236struct macb {
1237 void __iomem *regs;
1238 bool native_io;
1239
1240
1241 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1242 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1243
1244 size_t rx_buffer_size;
1245
1246 unsigned int rx_ring_size;
1247 unsigned int tx_ring_size;
1248
1249 unsigned int num_queues;
1250 unsigned int queue_mask;
1251 struct macb_queue queues[MACB_MAX_QUEUES];
1252
1253 spinlock_t lock;
1254 struct platform_device *pdev;
1255 struct clk *pclk;
1256 struct clk *hclk;
1257 struct clk *tx_clk;
1258 struct clk *rx_clk;
1259 struct clk *tsu_clk;
1260 struct net_device *dev;
1261 union {
1262 struct macb_stats macb;
1263 struct gem_stats gem;
1264 } hw_stats;
1265
1266 struct macb_or_gem_ops macbgem_ops;
1267
1268 struct mii_bus *mii_bus;
1269 struct phylink *phylink;
1270 struct phylink_config phylink_config;
1271 struct phylink_pcs phylink_pcs;
1272
1273 u32 caps;
1274 unsigned int dma_burst_length;
1275
1276 phy_interface_t phy_interface;
1277
1278
1279 struct macb_tx_skb rm9200_txq[2];
1280 unsigned int max_tx_length;
1281
1282 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1283
1284 unsigned int rx_frm_len_mask;
1285 unsigned int jumbo_max_len;
1286
1287 u32 wol;
1288
1289 struct macb_ptp_info *ptp_info;
1290#ifdef MACB_EXT_DESC
1291 uint8_t hw_dma_cap;
1292#endif
1293 spinlock_t tsu_clk_lock;
1294 unsigned int tsu_rate;
1295 struct ptp_clock *ptp_clock;
1296 struct ptp_clock_info ptp_clock_info;
1297 struct tsu_incr tsu_incr;
1298 struct hwtstamp_config tstamp_config;
1299
1300
1301 struct ethtool_rx_fs_list rx_fs_list;
1302 spinlock_t rx_fs_lock;
1303 unsigned int max_tuples;
1304
1305 struct tasklet_struct hresp_err_tasklet;
1306
1307 int rx_bd_rd_prefetch;
1308 int tx_bd_rd_prefetch;
1309
1310 u32 rx_intr_mask;
1311
1312 struct macb_pm_data pm_data;
1313 const struct macb_usrio_config *usrio;
1314};
1315
1316#ifdef CONFIG_MACB_USE_HWSTAMP
1317#define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1318#define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1319#define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1320
1321enum macb_bd_control {
1322 TSTAMP_DISABLED,
1323 TSTAMP_FRAME_PTP_EVENT_ONLY,
1324 TSTAMP_ALL_PTP_FRAMES,
1325 TSTAMP_ALL_FRAMES,
1326};
1327
1328void gem_ptp_init(struct net_device *ndev);
1329void gem_ptp_remove(struct net_device *ndev);
1330int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1331void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1332static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1333{
1334 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1335 return -ENOTSUPP;
1336
1337 return gem_ptp_txstamp(queue, skb, desc);
1338}
1339
1340static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1341{
1342 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1343 return;
1344
1345 gem_ptp_rxstamp(bp, skb, desc);
1346}
1347int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1348int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1349#else
1350static inline void gem_ptp_init(struct net_device *ndev) { }
1351static inline void gem_ptp_remove(struct net_device *ndev) { }
1352
1353static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1354{
1355 return -1;
1356}
1357
1358static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1359#endif
1360
1361static inline bool macb_is_gem(struct macb *bp)
1362{
1363 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1364}
1365
1366static inline bool gem_has_ptp(struct macb *bp)
1367{
1368 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1369}
1370
1371
1372
1373
1374
1375
1376struct macb_platform_data {
1377 struct clk *pclk;
1378 struct clk *hclk;
1379};
1380
1381#endif
1382