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10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/clk.h>
13#include <linux/device.h>
14#include <linux/etherdevice.h>
15#include <linux/platform_device.h>
16#include <linux/time64.h>
17#include <linux/ptp_classify.h>
18#include <linux/if_ether.h>
19#include <linux/if_vlan.h>
20#include <linux/net_tstamp.h>
21#include <linux/circ_buf.h>
22#include <linux/spinlock.h>
23
24#include "macb.h"
25
26#define GEM_PTP_TIMER_NAME "gem-ptp-timer"
27
28static struct macb_dma_desc_ptp *macb_ptp_desc(struct macb *bp,
29 struct macb_dma_desc *desc)
30{
31 if (bp->hw_dma_cap == HW_DMA_CAP_PTP)
32 return (struct macb_dma_desc_ptp *)
33 ((u8 *)desc + sizeof(struct macb_dma_desc));
34 if (bp->hw_dma_cap == HW_DMA_CAP_64B_PTP)
35 return (struct macb_dma_desc_ptp *)
36 ((u8 *)desc + sizeof(struct macb_dma_desc)
37 + sizeof(struct macb_dma_desc_64));
38 return NULL;
39}
40
41static int gem_tsu_get_time(struct ptp_clock_info *ptp, struct timespec64 *ts)
42{
43 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
44 unsigned long flags;
45 long first, second;
46 u32 secl, sech;
47
48 spin_lock_irqsave(&bp->tsu_clk_lock, flags);
49 first = gem_readl(bp, TN);
50 secl = gem_readl(bp, TSL);
51 sech = gem_readl(bp, TSH);
52 second = gem_readl(bp, TN);
53
54
55 if (first > second) {
56
57
58
59 ts->tv_nsec = gem_readl(bp, TN);
60 secl = gem_readl(bp, TSL);
61 sech = gem_readl(bp, TSH);
62 } else {
63 ts->tv_nsec = first;
64 }
65
66 spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
67 ts->tv_sec = (((u64)sech << GEM_TSL_SIZE) | secl)
68 & TSU_SEC_MAX_VAL;
69 return 0;
70}
71
72static int gem_tsu_set_time(struct ptp_clock_info *ptp,
73 const struct timespec64 *ts)
74{
75 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
76 unsigned long flags;
77 u32 ns, sech, secl;
78
79 secl = (u32)ts->tv_sec;
80 sech = (ts->tv_sec >> GEM_TSL_SIZE) & ((1 << GEM_TSH_SIZE) - 1);
81 ns = ts->tv_nsec;
82
83 spin_lock_irqsave(&bp->tsu_clk_lock, flags);
84
85
86 gem_writel(bp, TN, 0);
87 gem_writel(bp, TSH, sech);
88
89 gem_writel(bp, TSL, secl);
90 gem_writel(bp, TN, ns);
91
92 spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
93
94 return 0;
95}
96
97static int gem_tsu_incr_set(struct macb *bp, struct tsu_incr *incr_spec)
98{
99 unsigned long flags;
100
101
102
103
104
105
106 spin_lock_irqsave(&bp->tsu_clk_lock, flags);
107
108 gem_writel(bp, TISUBN, GEM_BF(SUBNSINCRL, incr_spec->sub_ns) |
109 GEM_BF(SUBNSINCRH, (incr_spec->sub_ns >>
110 GEM_SUBNSINCRL_SIZE)));
111 gem_writel(bp, TI, GEM_BF(NSINCR, incr_spec->ns));
112 spin_unlock_irqrestore(&bp->tsu_clk_lock, flags);
113
114 return 0;
115}
116
117static int gem_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
118{
119 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
120 struct tsu_incr incr_spec;
121 bool neg_adj = false;
122 u32 word;
123 u64 adj;
124
125 if (scaled_ppm < 0) {
126 neg_adj = true;
127 scaled_ppm = -scaled_ppm;
128 }
129
130
131 incr_spec.sub_ns = bp->tsu_incr.sub_ns;
132 incr_spec.ns = bp->tsu_incr.ns;
133
134
135 word = ((u64)incr_spec.ns << GEM_SUBNSINCR_SIZE) + incr_spec.sub_ns;
136 adj = (u64)scaled_ppm * word;
137
138
139
140 adj += (USEC_PER_SEC >> 1);
141 adj >>= PPM_FRACTION;
142 adj = div_u64(adj, USEC_PER_SEC);
143 adj = neg_adj ? (word - adj) : (word + adj);
144
145 incr_spec.ns = (adj >> GEM_SUBNSINCR_SIZE)
146 & ((1 << GEM_NSINCR_SIZE) - 1);
147 incr_spec.sub_ns = adj & ((1 << GEM_SUBNSINCR_SIZE) - 1);
148 gem_tsu_incr_set(bp, &incr_spec);
149 return 0;
150}
151
152static int gem_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
153{
154 struct macb *bp = container_of(ptp, struct macb, ptp_clock_info);
155 struct timespec64 now, then = ns_to_timespec64(delta);
156 u32 adj, sign = 0;
157
158 if (delta < 0) {
159 sign = 1;
160 delta = -delta;
161 }
162
163 if (delta > TSU_NSEC_MAX_VAL) {
164 gem_tsu_get_time(&bp->ptp_clock_info, &now);
165 now = timespec64_add(now, then);
166
167 gem_tsu_set_time(&bp->ptp_clock_info,
168 (const struct timespec64 *)&now);
169 } else {
170 adj = (sign << GEM_ADDSUB_OFFSET) | delta;
171
172 gem_writel(bp, TA, adj);
173 }
174
175 return 0;
176}
177
178static int gem_ptp_enable(struct ptp_clock_info *ptp,
179 struct ptp_clock_request *rq, int on)
180{
181 return -EOPNOTSUPP;
182}
183
184static const struct ptp_clock_info gem_ptp_caps_template = {
185 .owner = THIS_MODULE,
186 .name = GEM_PTP_TIMER_NAME,
187 .max_adj = 0,
188 .n_alarm = 0,
189 .n_ext_ts = 0,
190 .n_per_out = 0,
191 .n_pins = 0,
192 .pps = 1,
193 .adjfine = gem_ptp_adjfine,
194 .adjtime = gem_ptp_adjtime,
195 .gettime64 = gem_tsu_get_time,
196 .settime64 = gem_tsu_set_time,
197 .enable = gem_ptp_enable,
198};
199
200static void gem_ptp_init_timer(struct macb *bp)
201{
202 u32 rem = 0;
203 u64 adj;
204
205 bp->tsu_incr.ns = div_u64_rem(NSEC_PER_SEC, bp->tsu_rate, &rem);
206 if (rem) {
207 adj = rem;
208 adj <<= GEM_SUBNSINCR_SIZE;
209 bp->tsu_incr.sub_ns = div_u64(adj, bp->tsu_rate);
210 } else {
211 bp->tsu_incr.sub_ns = 0;
212 }
213}
214
215static void gem_ptp_init_tsu(struct macb *bp)
216{
217 struct timespec64 ts;
218
219
220 ts = ns_to_timespec64(ktime_to_ns(ktime_get_real()));
221
222
223 gem_tsu_set_time(&bp->ptp_clock_info, &ts);
224
225
226 gem_tsu_incr_set(bp, &bp->tsu_incr);
227
228 gem_writel(bp, TA, 0);
229}
230
231static void gem_ptp_clear_timer(struct macb *bp)
232{
233 bp->tsu_incr.sub_ns = 0;
234 bp->tsu_incr.ns = 0;
235
236 gem_writel(bp, TISUBN, GEM_BF(SUBNSINCR, 0));
237 gem_writel(bp, TI, GEM_BF(NSINCR, 0));
238 gem_writel(bp, TA, 0);
239}
240
241static int gem_hw_timestamp(struct macb *bp, u32 dma_desc_ts_1,
242 u32 dma_desc_ts_2, struct timespec64 *ts)
243{
244 struct timespec64 tsu;
245
246 ts->tv_sec = (GEM_BFEXT(DMA_SECH, dma_desc_ts_2) << GEM_DMA_SECL_SIZE) |
247 GEM_BFEXT(DMA_SECL, dma_desc_ts_1);
248 ts->tv_nsec = GEM_BFEXT(DMA_NSEC, dma_desc_ts_1);
249
250
251
252
253
254 gem_tsu_get_time(&bp->ptp_clock_info, &tsu);
255
256
257
258
259
260 if ((ts->tv_sec & (GEM_DMA_SEC_TOP >> 1)) &&
261 !(tsu.tv_sec & (GEM_DMA_SEC_TOP >> 1)))
262 ts->tv_sec -= GEM_DMA_SEC_TOP;
263
264 ts->tv_sec += ((~GEM_DMA_SEC_MASK) & tsu.tv_sec);
265
266 return 0;
267}
268
269void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb,
270 struct macb_dma_desc *desc)
271{
272 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
273 struct macb_dma_desc_ptp *desc_ptp;
274 struct timespec64 ts;
275
276 if (GEM_BFEXT(DMA_RXVALID, desc->addr)) {
277 desc_ptp = macb_ptp_desc(bp, desc);
278
279 if (!desc_ptp) {
280 dev_warn_ratelimited(&bp->pdev->dev,
281 "Timestamp not supported in BD\n");
282 return;
283 }
284 gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
285 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
286 shhwtstamps->hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
287 }
288}
289
290static void gem_tstamp_tx(struct macb *bp, struct sk_buff *skb,
291 struct macb_dma_desc_ptp *desc_ptp)
292{
293 struct skb_shared_hwtstamps shhwtstamps;
294 struct timespec64 ts;
295
296 gem_hw_timestamp(bp, desc_ptp->ts_1, desc_ptp->ts_2, &ts);
297 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
298 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
299 skb_tstamp_tx(skb, &shhwtstamps);
300}
301
302int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb,
303 struct macb_dma_desc *desc)
304{
305 unsigned long tail = READ_ONCE(queue->tx_ts_tail);
306 unsigned long head = queue->tx_ts_head;
307 struct macb_dma_desc_ptp *desc_ptp;
308 struct gem_tx_ts *tx_timestamp;
309
310 if (!GEM_BFEXT(DMA_TXVALID, desc->ctrl))
311 return -EINVAL;
312
313 if (CIRC_SPACE(head, tail, PTP_TS_BUFFER_SIZE) == 0)
314 return -ENOMEM;
315
316 desc_ptp = macb_ptp_desc(queue->bp, desc);
317
318 if (!desc_ptp)
319 return -EINVAL;
320 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
321 tx_timestamp = &queue->tx_timestamps[head];
322 tx_timestamp->skb = skb;
323
324 dma_rmb();
325 tx_timestamp->desc_ptp.ts_1 = desc_ptp->ts_1;
326 tx_timestamp->desc_ptp.ts_2 = desc_ptp->ts_2;
327
328 smp_store_release(&queue->tx_ts_head,
329 (head + 1) & (PTP_TS_BUFFER_SIZE - 1));
330
331 schedule_work(&queue->tx_ts_task);
332 return 0;
333}
334
335static void gem_tx_timestamp_flush(struct work_struct *work)
336{
337 struct macb_queue *queue =
338 container_of(work, struct macb_queue, tx_ts_task);
339 unsigned long head, tail;
340 struct gem_tx_ts *tx_ts;
341
342
343 head = smp_load_acquire(&queue->tx_ts_head);
344 tail = queue->tx_ts_tail;
345
346 while (CIRC_CNT(head, tail, PTP_TS_BUFFER_SIZE)) {
347 tx_ts = &queue->tx_timestamps[tail];
348 gem_tstamp_tx(queue->bp, tx_ts->skb, &tx_ts->desc_ptp);
349
350 dev_kfree_skb_any(tx_ts->skb);
351
352 smp_store_release(&queue->tx_ts_tail,
353 (tail + 1) & (PTP_TS_BUFFER_SIZE - 1));
354 tail = queue->tx_ts_tail;
355 }
356}
357
358void gem_ptp_init(struct net_device *dev)
359{
360 struct macb *bp = netdev_priv(dev);
361 struct macb_queue *queue;
362 unsigned int q;
363
364 bp->ptp_clock_info = gem_ptp_caps_template;
365
366
367 bp->tsu_rate = bp->ptp_info->get_tsu_rate(bp);
368 bp->ptp_clock_info.max_adj = bp->ptp_info->get_ptp_max_adj();
369 gem_ptp_init_timer(bp);
370 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &dev->dev);
371 if (IS_ERR(bp->ptp_clock)) {
372 pr_err("ptp clock register failed: %ld\n",
373 PTR_ERR(bp->ptp_clock));
374 bp->ptp_clock = NULL;
375 return;
376 } else if (bp->ptp_clock == NULL) {
377 pr_err("ptp clock register failed\n");
378 return;
379 }
380
381 spin_lock_init(&bp->tsu_clk_lock);
382 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
383 queue->tx_ts_head = 0;
384 queue->tx_ts_tail = 0;
385 INIT_WORK(&queue->tx_ts_task, gem_tx_timestamp_flush);
386 }
387
388 gem_ptp_init_tsu(bp);
389
390 dev_info(&bp->pdev->dev, "%s ptp clock registered.\n",
391 GEM_PTP_TIMER_NAME);
392}
393
394void gem_ptp_remove(struct net_device *ndev)
395{
396 struct macb *bp = netdev_priv(ndev);
397
398 if (bp->ptp_clock)
399 ptp_clock_unregister(bp->ptp_clock);
400
401 gem_ptp_clear_timer(bp);
402
403 dev_info(&bp->pdev->dev, "%s ptp clock unregistered.\n",
404 GEM_PTP_TIMER_NAME);
405}
406
407static int gem_ptp_set_ts_mode(struct macb *bp,
408 enum macb_bd_control tx_bd_control,
409 enum macb_bd_control rx_bd_control)
410{
411 gem_writel(bp, TXBDCTRL, GEM_BF(TXTSMODE, tx_bd_control));
412 gem_writel(bp, RXBDCTRL, GEM_BF(RXTSMODE, rx_bd_control));
413
414 return 0;
415}
416
417int gem_get_hwtst(struct net_device *dev, struct ifreq *rq)
418{
419 struct hwtstamp_config *tstamp_config;
420 struct macb *bp = netdev_priv(dev);
421
422 tstamp_config = &bp->tstamp_config;
423 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
424 return -EOPNOTSUPP;
425
426 if (copy_to_user(rq->ifr_data, tstamp_config, sizeof(*tstamp_config)))
427 return -EFAULT;
428 else
429 return 0;
430}
431
432static int gem_ptp_set_one_step_sync(struct macb *bp, u8 enable)
433{
434 u32 reg_val;
435
436 reg_val = macb_readl(bp, NCR);
437
438 if (enable)
439 macb_writel(bp, NCR, reg_val | MACB_BIT(OSSMODE));
440 else
441 macb_writel(bp, NCR, reg_val & ~MACB_BIT(OSSMODE));
442
443 return 0;
444}
445
446int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd)
447{
448 enum macb_bd_control tx_bd_control = TSTAMP_DISABLED;
449 enum macb_bd_control rx_bd_control = TSTAMP_DISABLED;
450 struct hwtstamp_config *tstamp_config;
451 struct macb *bp = netdev_priv(dev);
452 u32 regval;
453
454 tstamp_config = &bp->tstamp_config;
455 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0)
456 return -EOPNOTSUPP;
457
458 if (copy_from_user(tstamp_config, ifr->ifr_data,
459 sizeof(*tstamp_config)))
460 return -EFAULT;
461
462
463 if (tstamp_config->flags)
464 return -EINVAL;
465
466 switch (tstamp_config->tx_type) {
467 case HWTSTAMP_TX_OFF:
468 break;
469 case HWTSTAMP_TX_ONESTEP_SYNC:
470 if (gem_ptp_set_one_step_sync(bp, 1) != 0)
471 return -ERANGE;
472 fallthrough;
473 case HWTSTAMP_TX_ON:
474 tx_bd_control = TSTAMP_ALL_FRAMES;
475 break;
476 default:
477 return -ERANGE;
478 }
479
480 switch (tstamp_config->rx_filter) {
481 case HWTSTAMP_FILTER_NONE:
482 break;
483 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
484 break;
485 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
486 break;
487 case HWTSTAMP_FILTER_PTP_V2_EVENT:
488 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
489 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
490 case HWTSTAMP_FILTER_PTP_V2_SYNC:
491 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
492 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
493 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
494 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
495 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
496 rx_bd_control = TSTAMP_ALL_PTP_FRAMES;
497 tstamp_config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
498 regval = macb_readl(bp, NCR);
499 macb_writel(bp, NCR, (regval | MACB_BIT(SRTSM)));
500 break;
501 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
502 case HWTSTAMP_FILTER_ALL:
503 rx_bd_control = TSTAMP_ALL_FRAMES;
504 tstamp_config->rx_filter = HWTSTAMP_FILTER_ALL;
505 break;
506 default:
507 tstamp_config->rx_filter = HWTSTAMP_FILTER_NONE;
508 return -ERANGE;
509 }
510
511 if (gem_ptp_set_ts_mode(bp, tx_bd_control, rx_bd_control) != 0)
512 return -ERANGE;
513
514 if (copy_to_user(ifr->ifr_data, tstamp_config, sizeof(*tstamp_config)))
515 return -EFAULT;
516 else
517 return 0;
518}
519
520
