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39#include "common.h"
40#include "elmer0.h"
41#include "regs.h"
42#include "gmac.h"
43#include "cphy.h"
44#include "sge.h"
45#include "tp.h"
46#include "espi.h"
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61static int t1_wait_op_done(adapter_t *adapter, int reg, u32 mask, int polarity,
62 int attempts, int delay)
63{
64 while (1) {
65 u32 val = readl(adapter->regs + reg) & mask;
66
67 if (!!val == polarity)
68 return 0;
69 if (--attempts == 0)
70 return 1;
71 if (delay)
72 udelay(delay);
73 }
74}
75
76#define TPI_ATTEMPTS 50
77
78
79
80
81int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
82{
83 int tpi_busy;
84
85 writel(addr, adapter->regs + A_TPI_ADDR);
86 writel(value, adapter->regs + A_TPI_WR_DATA);
87 writel(F_TPIWR, adapter->regs + A_TPI_CSR);
88
89 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
90 TPI_ATTEMPTS, 3);
91 if (tpi_busy)
92 pr_alert("%s: TPI write to 0x%x failed\n",
93 adapter->name, addr);
94 return tpi_busy;
95}
96
97int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value)
98{
99 int ret;
100
101 spin_lock(&adapter->tpi_lock);
102 ret = __t1_tpi_write(adapter, addr, value);
103 spin_unlock(&adapter->tpi_lock);
104 return ret;
105}
106
107
108
109
110int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
111{
112 int tpi_busy;
113
114 writel(addr, adapter->regs + A_TPI_ADDR);
115 writel(0, adapter->regs + A_TPI_CSR);
116
117 tpi_busy = t1_wait_op_done(adapter, A_TPI_CSR, F_TPIRDY, 1,
118 TPI_ATTEMPTS, 3);
119 if (tpi_busy)
120 pr_alert("%s: TPI read from 0x%x failed\n",
121 adapter->name, addr);
122 else
123 *valp = readl(adapter->regs + A_TPI_RD_DATA);
124 return tpi_busy;
125}
126
127int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp)
128{
129 int ret;
130
131 spin_lock(&adapter->tpi_lock);
132 ret = __t1_tpi_read(adapter, addr, valp);
133 spin_unlock(&adapter->tpi_lock);
134 return ret;
135}
136
137
138
139
140static void t1_tpi_par(adapter_t *adapter, u32 value)
141{
142 writel(V_TPIPAR(value), adapter->regs + A_TPI_PAR);
143}
144
145
146
147
148
149
150void t1_link_changed(adapter_t *adapter, int port_id)
151{
152 int link_ok, speed, duplex, fc;
153 struct cphy *phy = adapter->port[port_id].phy;
154 struct link_config *lc = &adapter->port[port_id].link_config;
155
156 phy->ops->get_link_status(phy, &link_ok, &speed, &duplex, &fc);
157
158 lc->speed = speed < 0 ? SPEED_INVALID : speed;
159 lc->duplex = duplex < 0 ? DUPLEX_INVALID : duplex;
160 if (!(lc->requested_fc & PAUSE_AUTONEG))
161 fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
162
163 if (link_ok && speed >= 0 && lc->autoneg == AUTONEG_ENABLE) {
164
165 struct cmac *mac = adapter->port[port_id].mac;
166
167 mac->ops->set_speed_duplex_fc(mac, speed, duplex, fc);
168 lc->fc = (unsigned char)fc;
169 }
170 t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
171}
172
173static bool t1_pci_intr_handler(adapter_t *adapter)
174{
175 u32 pcix_cause;
176
177 pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
178
179 if (pcix_cause) {
180 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
181 pcix_cause);
182
183 t1_interrupts_disable(adapter);
184 adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR;
185 pr_alert("%s: PCI error encountered.\n", adapter->name);
186 return true;
187 }
188 return false;
189}
190
191#ifdef CONFIG_CHELSIO_T1_1G
192#include "fpga_defs.h"
193
194
195
196
197static int fpga_phy_intr_handler(adapter_t *adapter)
198{
199 int p;
200 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
201
202 for_each_port(adapter, p)
203 if (cause & (1 << p)) {
204 struct cphy *phy = adapter->port[p].phy;
205 int phy_cause = phy->ops->interrupt_handler(phy);
206
207 if (phy_cause & cphy_cause_link_change)
208 t1_link_changed(adapter, p);
209 }
210 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE);
211 return 0;
212}
213
214
215
216
217static irqreturn_t fpga_slow_intr(adapter_t *adapter)
218{
219 u32 cause = readl(adapter->regs + A_PL_CAUSE);
220 irqreturn_t ret = IRQ_NONE;
221
222 cause &= ~F_PL_INTR_SGE_DATA;
223 if (cause & F_PL_INTR_SGE_ERR) {
224 if (t1_sge_intr_error_handler(adapter->sge))
225 ret = IRQ_WAKE_THREAD;
226 }
227
228 if (cause & FPGA_PCIX_INTERRUPT_GMAC)
229 fpga_phy_intr_handler(adapter);
230
231 if (cause & FPGA_PCIX_INTERRUPT_TP) {
232
233
234
235
236 u32 tp_cause = readl(adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
237
238
239 writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
240 }
241 if (cause & FPGA_PCIX_INTERRUPT_PCIX) {
242 if (t1_pci_intr_handler(adapter))
243 ret = IRQ_WAKE_THREAD;
244 }
245
246
247 if (cause)
248 writel(cause, adapter->regs + A_PL_CAUSE);
249
250 if (ret != IRQ_NONE)
251 return ret;
252
253 return cause == 0 ? IRQ_NONE : IRQ_HANDLED;
254}
255#endif
256
257
258
259
260static int mi1_wait_until_ready(adapter_t *adapter, int mi1_reg)
261{
262 int attempts = 100, busy;
263
264 do {
265 u32 val;
266
267 __t1_tpi_read(adapter, mi1_reg, &val);
268 busy = val & F_MI1_OP_BUSY;
269 if (busy)
270 udelay(10);
271 } while (busy && --attempts);
272 if (busy)
273 pr_alert("%s: MDIO operation timed out\n", adapter->name);
274 return busy;
275}
276
277
278
279
280static void mi1_mdio_init(adapter_t *adapter, const struct board_info *bi)
281{
282 u32 clkdiv = bi->clock_elmer0 / (2 * bi->mdio_mdc) - 1;
283 u32 val = F_MI1_PREAMBLE_ENABLE | V_MI1_MDI_INVERT(bi->mdio_mdiinv) |
284 V_MI1_MDI_ENABLE(bi->mdio_mdien) | V_MI1_CLK_DIV(clkdiv);
285
286 if (!(bi->caps & SUPPORTED_10000baseT_Full))
287 val |= V_MI1_SOF(1);
288 t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_CFG, val);
289}
290
291#if defined(CONFIG_CHELSIO_T1_1G)
292
293
294
295static int mi1_mdio_read(struct net_device *dev, int phy_addr, int mmd_addr,
296 u16 reg_addr)
297{
298 struct adapter *adapter = dev->ml_priv;
299 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
300 unsigned int val;
301
302 spin_lock(&adapter->tpi_lock);
303 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
304 __t1_tpi_write(adapter,
305 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_READ);
306 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
307 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
308 spin_unlock(&adapter->tpi_lock);
309 return val;
310}
311
312static int mi1_mdio_write(struct net_device *dev, int phy_addr, int mmd_addr,
313 u16 reg_addr, u16 val)
314{
315 struct adapter *adapter = dev->ml_priv;
316 u32 addr = V_MI1_REG_ADDR(reg_addr) | V_MI1_PHY_ADDR(phy_addr);
317
318 spin_lock(&adapter->tpi_lock);
319 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
320 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
321 __t1_tpi_write(adapter,
322 A_ELMER0_PORT0_MI1_OP, MI1_OP_DIRECT_WRITE);
323 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
324 spin_unlock(&adapter->tpi_lock);
325 return 0;
326}
327
328static const struct mdio_ops mi1_mdio_ops = {
329 .init = mi1_mdio_init,
330 .read = mi1_mdio_read,
331 .write = mi1_mdio_write,
332 .mode_support = MDIO_SUPPORTS_C22
333};
334
335#endif
336
337static int mi1_mdio_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
338 u16 reg_addr)
339{
340 struct adapter *adapter = dev->ml_priv;
341 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
342 unsigned int val;
343
344 spin_lock(&adapter->tpi_lock);
345
346
347 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
348 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
349 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
350 MI1_OP_INDIRECT_ADDRESS);
351 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
352
353
354 __t1_tpi_write(adapter,
355 A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_READ);
356 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
357
358
359 __t1_tpi_read(adapter, A_ELMER0_PORT0_MI1_DATA, &val);
360 spin_unlock(&adapter->tpi_lock);
361 return val;
362}
363
364static int mi1_mdio_ext_write(struct net_device *dev, int phy_addr,
365 int mmd_addr, u16 reg_addr, u16 val)
366{
367 struct adapter *adapter = dev->ml_priv;
368 u32 addr = V_MI1_REG_ADDR(mmd_addr) | V_MI1_PHY_ADDR(phy_addr);
369
370 spin_lock(&adapter->tpi_lock);
371
372
373 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_ADDR, addr);
374 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, reg_addr);
375 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP,
376 MI1_OP_INDIRECT_ADDRESS);
377 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
378
379
380 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_DATA, val);
381 __t1_tpi_write(adapter, A_ELMER0_PORT0_MI1_OP, MI1_OP_INDIRECT_WRITE);
382 mi1_wait_until_ready(adapter, A_ELMER0_PORT0_MI1_OP);
383 spin_unlock(&adapter->tpi_lock);
384 return 0;
385}
386
387static const struct mdio_ops mi1_mdio_ext_ops = {
388 .init = mi1_mdio_init,
389 .read = mi1_mdio_ext_read,
390 .write = mi1_mdio_ext_write,
391 .mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
392};
393
394enum {
395 CH_BRD_T110_1CU,
396 CH_BRD_N110_1F,
397 CH_BRD_N210_1F,
398 CH_BRD_T210_1F,
399 CH_BRD_T210_1CU,
400 CH_BRD_N204_4CU,
401};
402
403static const struct board_info t1_board[] = {
404 {
405 .board = CHBT_BOARD_CHT110,
406 .port_number = 1,
407 .caps = SUPPORTED_10000baseT_Full,
408 .chip_term = CHBT_TERM_T1,
409 .chip_mac = CHBT_MAC_PM3393,
410 .chip_phy = CHBT_PHY_MY3126,
411 .clock_core = 125000000,
412 .clock_mc3 = 150000000,
413 .clock_mc4 = 125000000,
414 .espi_nports = 1,
415 .clock_elmer0 = 44,
416 .mdio_mdien = 1,
417 .mdio_mdiinv = 1,
418 .mdio_mdc = 1,
419 .mdio_phybaseaddr = 1,
420 .gmac = &t1_pm3393_ops,
421 .gphy = &t1_my3126_ops,
422 .mdio_ops = &mi1_mdio_ext_ops,
423 .desc = "Chelsio T110 1x10GBase-CX4 TOE",
424 },
425
426 {
427 .board = CHBT_BOARD_N110,
428 .port_number = 1,
429 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
430 .chip_term = CHBT_TERM_T1,
431 .chip_mac = CHBT_MAC_PM3393,
432 .chip_phy = CHBT_PHY_88X2010,
433 .clock_core = 125000000,
434 .espi_nports = 1,
435 .clock_elmer0 = 44,
436 .mdio_mdien = 0,
437 .mdio_mdiinv = 0,
438 .mdio_mdc = 1,
439 .mdio_phybaseaddr = 0,
440 .gmac = &t1_pm3393_ops,
441 .gphy = &t1_mv88x201x_ops,
442 .mdio_ops = &mi1_mdio_ext_ops,
443 .desc = "Chelsio N110 1x10GBaseX NIC",
444 },
445
446 {
447 .board = CHBT_BOARD_N210,
448 .port_number = 1,
449 .caps = SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE,
450 .chip_term = CHBT_TERM_T2,
451 .chip_mac = CHBT_MAC_PM3393,
452 .chip_phy = CHBT_PHY_88X2010,
453 .clock_core = 125000000,
454 .espi_nports = 1,
455 .clock_elmer0 = 44,
456 .mdio_mdien = 0,
457 .mdio_mdiinv = 0,
458 .mdio_mdc = 1,
459 .mdio_phybaseaddr = 0,
460 .gmac = &t1_pm3393_ops,
461 .gphy = &t1_mv88x201x_ops,
462 .mdio_ops = &mi1_mdio_ext_ops,
463 .desc = "Chelsio N210 1x10GBaseX NIC",
464 },
465
466 {
467 .board = CHBT_BOARD_CHT210,
468 .port_number = 1,
469 .caps = SUPPORTED_10000baseT_Full,
470 .chip_term = CHBT_TERM_T2,
471 .chip_mac = CHBT_MAC_PM3393,
472 .chip_phy = CHBT_PHY_88X2010,
473 .clock_core = 125000000,
474 .clock_mc3 = 133000000,
475 .clock_mc4 = 125000000,
476 .espi_nports = 1,
477 .clock_elmer0 = 44,
478 .mdio_mdien = 0,
479 .mdio_mdiinv = 0,
480 .mdio_mdc = 1,
481 .mdio_phybaseaddr = 0,
482 .gmac = &t1_pm3393_ops,
483 .gphy = &t1_mv88x201x_ops,
484 .mdio_ops = &mi1_mdio_ext_ops,
485 .desc = "Chelsio T210 1x10GBaseX TOE",
486 },
487
488 {
489 .board = CHBT_BOARD_CHT210,
490 .port_number = 1,
491 .caps = SUPPORTED_10000baseT_Full,
492 .chip_term = CHBT_TERM_T2,
493 .chip_mac = CHBT_MAC_PM3393,
494 .chip_phy = CHBT_PHY_MY3126,
495 .clock_core = 125000000,
496 .clock_mc3 = 133000000,
497 .clock_mc4 = 125000000,
498 .espi_nports = 1,
499 .clock_elmer0 = 44,
500 .mdio_mdien = 1,
501 .mdio_mdiinv = 1,
502 .mdio_mdc = 1,
503 .mdio_phybaseaddr = 1,
504 .gmac = &t1_pm3393_ops,
505 .gphy = &t1_my3126_ops,
506 .mdio_ops = &mi1_mdio_ext_ops,
507 .desc = "Chelsio T210 1x10GBase-CX4 TOE",
508 },
509
510#ifdef CONFIG_CHELSIO_T1_1G
511 {
512 .board = CHBT_BOARD_CHN204,
513 .port_number = 4,
514 .caps = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
515 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
516 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
517 SUPPORTED_PAUSE | SUPPORTED_TP,
518 .chip_term = CHBT_TERM_T2,
519 .chip_mac = CHBT_MAC_VSC7321,
520 .chip_phy = CHBT_PHY_88E1111,
521 .clock_core = 100000000,
522 .espi_nports = 4,
523 .clock_elmer0 = 44,
524 .mdio_mdien = 0,
525 .mdio_mdiinv = 0,
526 .mdio_mdc = 0,
527 .mdio_phybaseaddr = 4,
528 .gmac = &t1_vsc7326_ops,
529 .gphy = &t1_mv88e1xxx_ops,
530 .mdio_ops = &mi1_mdio_ops,
531 .desc = "Chelsio N204 4x100/1000BaseT NIC",
532 },
533#endif
534
535};
536
537const struct pci_device_id t1_pci_tbl[] = {
538 CH_DEVICE(8, 0, CH_BRD_T110_1CU),
539 CH_DEVICE(8, 1, CH_BRD_T110_1CU),
540 CH_DEVICE(7, 0, CH_BRD_N110_1F),
541 CH_DEVICE(10, 1, CH_BRD_N210_1F),
542 CH_DEVICE(11, 1, CH_BRD_T210_1F),
543 CH_DEVICE(14, 1, CH_BRD_T210_1CU),
544 CH_DEVICE(16, 1, CH_BRD_N204_4CU),
545 { 0 }
546};
547
548MODULE_DEVICE_TABLE(pci, t1_pci_tbl);
549
550
551
552
553
554const struct board_info *t1_get_board_info(unsigned int board_id)
555{
556 return board_id < ARRAY_SIZE(t1_board) ? &t1_board[board_id] : NULL;
557}
558
559struct chelsio_vpd_t {
560 u32 format_version;
561 u8 serial_number[16];
562 u8 mac_base_address[6];
563 u8 pad[2];
564};
565
566#define EEPROMSIZE (8 * 1024)
567#define EEPROM_MAX_POLL 4
568
569
570
571
572
573
574int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data)
575{
576 int i = EEPROM_MAX_POLL;
577 u16 val;
578 u32 v;
579
580 if (addr >= EEPROMSIZE || (addr & 3))
581 return -EINVAL;
582
583 pci_write_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, (u16)addr);
584 do {
585 udelay(50);
586 pci_read_config_word(adapter->pdev, A_PCICFG_VPD_ADDR, &val);
587 } while (!(val & F_VPD_OP_FLAG) && --i);
588
589 if (!(val & F_VPD_OP_FLAG)) {
590 pr_err("%s: reading EEPROM address 0x%x failed\n",
591 adapter->name, addr);
592 return -EIO;
593 }
594 pci_read_config_dword(adapter->pdev, A_PCICFG_VPD_DATA, &v);
595 *data = cpu_to_le32(v);
596 return 0;
597}
598
599static int t1_eeprom_vpd_get(adapter_t *adapter, struct chelsio_vpd_t *vpd)
600{
601 int addr, ret = 0;
602
603 for (addr = 0; !ret && addr < sizeof(*vpd); addr += sizeof(u32))
604 ret = t1_seeprom_read(adapter, addr,
605 (__le32 *)((u8 *)vpd + addr));
606
607 return ret;
608}
609
610
611
612
613static int vpd_macaddress_get(adapter_t *adapter, int index, u8 mac_addr[])
614{
615 struct chelsio_vpd_t vpd;
616
617 if (t1_eeprom_vpd_get(adapter, &vpd))
618 return 1;
619 memcpy(mac_addr, vpd.mac_base_address, 5);
620 mac_addr[5] = vpd.mac_base_address[5] + index;
621 return 0;
622}
623
624
625
626
627
628
629
630
631
632
633
634
635int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc)
636{
637 unsigned int fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
638
639 if (lc->supported & SUPPORTED_Autoneg) {
640 lc->advertising &= ~(ADVERTISED_ASYM_PAUSE | ADVERTISED_PAUSE);
641 if (fc) {
642 if (fc == ((PAUSE_RX | PAUSE_TX) &
643 (mac->adapter->params.nports < 2)))
644 lc->advertising |= ADVERTISED_PAUSE;
645 else {
646 lc->advertising |= ADVERTISED_ASYM_PAUSE;
647 if (fc == PAUSE_RX)
648 lc->advertising |= ADVERTISED_PAUSE;
649 }
650 }
651 phy->ops->advertise(phy, lc->advertising);
652
653 if (lc->autoneg == AUTONEG_DISABLE) {
654 lc->speed = lc->requested_speed;
655 lc->duplex = lc->requested_duplex;
656 lc->fc = (unsigned char)fc;
657 mac->ops->set_speed_duplex_fc(mac, lc->speed,
658 lc->duplex, fc);
659
660 phy->state = PHY_AUTONEG_RDY;
661 phy->ops->set_speed_duplex(phy, lc->speed, lc->duplex);
662 phy->ops->reset(phy, 0);
663 } else {
664 phy->state = PHY_AUTONEG_EN;
665 phy->ops->autoneg_enable(phy);
666 }
667 } else {
668 phy->state = PHY_AUTONEG_RDY;
669 mac->ops->set_speed_duplex_fc(mac, -1, -1, fc);
670 lc->fc = (unsigned char)fc;
671 phy->ops->reset(phy, 0);
672 }
673 return 0;
674}
675
676
677
678
679int t1_elmer0_ext_intr_handler(adapter_t *adapter)
680{
681 struct cphy *phy;
682 int phy_cause;
683 u32 cause;
684
685 t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
686
687 switch (board_info(adapter)->board) {
688#ifdef CONFIG_CHELSIO_T1_1G
689 case CHBT_BOARD_CHT204:
690 case CHBT_BOARD_CHT204E:
691 case CHBT_BOARD_CHN204:
692 case CHBT_BOARD_CHT204V: {
693 int i, port_bit;
694 for_each_port(adapter, i) {
695 port_bit = i + 1;
696 if (!(cause & (1 << port_bit)))
697 continue;
698
699 phy = adapter->port[i].phy;
700 phy_cause = phy->ops->interrupt_handler(phy);
701 if (phy_cause & cphy_cause_link_change)
702 t1_link_changed(adapter, i);
703 }
704 break;
705 }
706 case CHBT_BOARD_CHT101:
707 if (cause & ELMER0_GP_BIT1) {
708 phy = adapter->port[0].phy;
709 phy_cause = phy->ops->interrupt_handler(phy);
710 if (phy_cause & cphy_cause_link_change)
711 t1_link_changed(adapter, 0);
712 }
713 break;
714 case CHBT_BOARD_7500: {
715 int p;
716
717
718
719
720
721
722 for_each_port(adapter, p) {
723 phy = adapter->port[p].phy;
724 phy_cause = phy->ops->interrupt_handler(phy);
725 if (phy_cause & cphy_cause_link_change)
726 t1_link_changed(adapter, p);
727 }
728 break;
729 }
730#endif
731 case CHBT_BOARD_CHT210:
732 case CHBT_BOARD_N210:
733 case CHBT_BOARD_N110:
734 if (cause & ELMER0_GP_BIT6) {
735 phy = adapter->port[0].phy;
736 phy_cause = phy->ops->interrupt_handler(phy);
737 if (phy_cause & cphy_cause_link_change)
738 t1_link_changed(adapter, 0);
739 }
740 break;
741 case CHBT_BOARD_8000:
742 case CHBT_BOARD_CHT110:
743 if (netif_msg_intr(adapter))
744 dev_dbg(&adapter->pdev->dev,
745 "External interrupt cause 0x%x\n", cause);
746 if (cause & ELMER0_GP_BIT1) {
747 struct cmac *mac = adapter->port[0].mac;
748
749 mac->ops->interrupt_handler(mac);
750 }
751 if (cause & ELMER0_GP_BIT5) {
752 u32 mod_detect;
753
754 t1_tpi_read(adapter,
755 A_ELMER0_GPI_STAT, &mod_detect);
756 if (netif_msg_link(adapter))
757 dev_info(&adapter->pdev->dev, "XPAK %s\n",
758 mod_detect ? "removed" : "inserted");
759 }
760 break;
761 }
762 t1_tpi_write(adapter, A_ELMER0_INT_CAUSE, cause);
763 return 0;
764}
765
766
767void t1_interrupts_enable(adapter_t *adapter)
768{
769 unsigned int i;
770
771 adapter->slow_intr_mask = F_PL_INTR_SGE_ERR | F_PL_INTR_TP;
772
773 t1_sge_intr_enable(adapter->sge);
774 t1_tp_intr_enable(adapter->tp);
775 if (adapter->espi) {
776 adapter->slow_intr_mask |= F_PL_INTR_ESPI;
777 t1_espi_intr_enable(adapter->espi);
778 }
779
780
781 for_each_port(adapter, i) {
782 adapter->port[i].mac->ops->interrupt_enable(adapter->port[i].mac);
783 adapter->port[i].phy->ops->interrupt_enable(adapter->port[i].phy);
784 }
785
786
787 if (t1_is_asic(adapter)) {
788 u32 pl_intr = readl(adapter->regs + A_PL_ENABLE);
789
790
791 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE,
792 0xffffffff);
793
794 adapter->slow_intr_mask |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
795 pl_intr |= F_PL_INTR_EXT | F_PL_INTR_PCIX;
796 writel(pl_intr, adapter->regs + A_PL_ENABLE);
797 }
798}
799
800
801void t1_interrupts_disable(adapter_t* adapter)
802{
803 unsigned int i;
804
805 t1_sge_intr_disable(adapter->sge);
806 t1_tp_intr_disable(adapter->tp);
807 if (adapter->espi)
808 t1_espi_intr_disable(adapter->espi);
809
810
811 for_each_port(adapter, i) {
812 adapter->port[i].mac->ops->interrupt_disable(adapter->port[i].mac);
813 adapter->port[i].phy->ops->interrupt_disable(adapter->port[i].phy);
814 }
815
816
817 if (t1_is_asic(adapter))
818 writel(0, adapter->regs + A_PL_ENABLE);
819
820
821 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_ENABLE, 0);
822
823 adapter->slow_intr_mask = 0;
824}
825
826
827void t1_interrupts_clear(adapter_t* adapter)
828{
829 unsigned int i;
830
831 t1_sge_intr_clear(adapter->sge);
832 t1_tp_intr_clear(adapter->tp);
833 if (adapter->espi)
834 t1_espi_intr_clear(adapter->espi);
835
836
837 for_each_port(adapter, i) {
838 adapter->port[i].mac->ops->interrupt_clear(adapter->port[i].mac);
839 adapter->port[i].phy->ops->interrupt_clear(adapter->port[i].phy);
840 }
841
842
843 if (t1_is_asic(adapter)) {
844 u32 pl_intr = readl(adapter->regs + A_PL_CAUSE);
845
846 writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
847 adapter->regs + A_PL_CAUSE);
848 }
849
850
851 pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, 0xffffffff);
852}
853
854
855
856
857static irqreturn_t asic_slow_intr(adapter_t *adapter)
858{
859 u32 cause = readl(adapter->regs + A_PL_CAUSE);
860 irqreturn_t ret = IRQ_HANDLED;
861
862 cause &= adapter->slow_intr_mask;
863 if (!cause)
864 return IRQ_NONE;
865 if (cause & F_PL_INTR_SGE_ERR) {
866 if (t1_sge_intr_error_handler(adapter->sge))
867 ret = IRQ_WAKE_THREAD;
868 }
869 if (cause & F_PL_INTR_TP)
870 t1_tp_intr_handler(adapter->tp);
871 if (cause & F_PL_INTR_ESPI)
872 t1_espi_intr_handler(adapter->espi);
873 if (cause & F_PL_INTR_PCIX) {
874 if (t1_pci_intr_handler(adapter))
875 ret = IRQ_WAKE_THREAD;
876 }
877 if (cause & F_PL_INTR_EXT) {
878
879
880
881
882 adapter->pending_thread_intr |= F_PL_INTR_EXT;
883 adapter->slow_intr_mask &= ~F_PL_INTR_EXT;
884 writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
885 adapter->regs + A_PL_ENABLE);
886 ret = IRQ_WAKE_THREAD;
887 }
888
889
890 writel(cause, adapter->regs + A_PL_CAUSE);
891 readl(adapter->regs + A_PL_CAUSE);
892 return ret;
893}
894
895irqreturn_t t1_slow_intr_handler(adapter_t *adapter)
896{
897#ifdef CONFIG_CHELSIO_T1_1G
898 if (!t1_is_asic(adapter))
899 return fpga_slow_intr(adapter);
900#endif
901 return asic_slow_intr(adapter);
902}
903
904
905static void power_sequence_xpak(adapter_t* adapter)
906{
907 u32 mod_detect;
908 u32 gpo;
909
910
911 t1_tpi_read(adapter, A_ELMER0_GPI_STAT, &mod_detect);
912 if (!(ELMER0_GP_BIT5 & mod_detect)) {
913
914 t1_tpi_read(adapter, A_ELMER0_GPO, &gpo);
915 gpo |= ELMER0_GP_BIT18;
916 t1_tpi_write(adapter, A_ELMER0_GPO, gpo);
917 }
918}
919
920int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
921 struct adapter_params *p)
922{
923 p->chip_version = bi->chip_term;
924 p->is_asic = (p->chip_version != CHBT_TERM_FPGA);
925 if (p->chip_version == CHBT_TERM_T1 ||
926 p->chip_version == CHBT_TERM_T2 ||
927 p->chip_version == CHBT_TERM_FPGA) {
928 u32 val = readl(adapter->regs + A_TP_PC_CONFIG);
929
930 val = G_TP_PC_REV(val);
931 if (val == 2)
932 p->chip_revision = TERM_T1B;
933 else if (val == 3)
934 p->chip_revision = TERM_T2;
935 else
936 return -1;
937 } else
938 return -1;
939 return 0;
940}
941
942
943
944
945
946static int board_init(adapter_t *adapter, const struct board_info *bi)
947{
948 switch (bi->board) {
949 case CHBT_BOARD_8000:
950 case CHBT_BOARD_N110:
951 case CHBT_BOARD_N210:
952 case CHBT_BOARD_CHT210:
953 t1_tpi_par(adapter, 0xf);
954 t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
955 break;
956 case CHBT_BOARD_CHT110:
957 t1_tpi_par(adapter, 0xf);
958 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1800);
959
960
961
962
963 power_sequence_xpak(adapter);
964 break;
965#ifdef CONFIG_CHELSIO_T1_1G
966 case CHBT_BOARD_CHT204E:
967
968 case CHBT_BOARD_CHT204:
969 case CHBT_BOARD_CHT204V:
970 case CHBT_BOARD_CHN204:
971 t1_tpi_par(adapter, 0xf);
972 t1_tpi_write(adapter, A_ELMER0_GPO, 0x804);
973 break;
974 case CHBT_BOARD_CHT101:
975 case CHBT_BOARD_7500:
976 t1_tpi_par(adapter, 0xf);
977 t1_tpi_write(adapter, A_ELMER0_GPO, 0x1804);
978 break;
979#endif
980 }
981 return 0;
982}
983
984
985
986
987
988int t1_init_hw_modules(adapter_t *adapter)
989{
990 int err = -EIO;
991 const struct board_info *bi = board_info(adapter);
992
993 if (!bi->clock_mc4) {
994 u32 val = readl(adapter->regs + A_MC4_CFG);
995
996 writel(val | F_READY | F_MC4_SLOW, adapter->regs + A_MC4_CFG);
997 writel(F_M_BUS_ENABLE | F_TCAM_RESET,
998 adapter->regs + A_MC5_CONFIG);
999 }
1000
1001 if (adapter->espi && t1_espi_init(adapter->espi, bi->chip_mac,
1002 bi->espi_nports))
1003 goto out_err;
1004
1005 if (t1_tp_reset(adapter->tp, &adapter->params.tp, bi->clock_core))
1006 goto out_err;
1007
1008 err = t1_sge_configure(adapter->sge, &adapter->params.sge);
1009 if (err)
1010 goto out_err;
1011
1012 err = 0;
1013out_err:
1014 return err;
1015}
1016
1017
1018
1019
1020static void get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
1021{
1022 static const unsigned short speed_map[] = { 33, 66, 100, 133 };
1023 u32 pci_mode;
1024
1025 pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
1026 p->speed = speed_map[G_PCI_MODE_CLK(pci_mode)];
1027 p->width = (pci_mode & F_PCI_MODE_64BIT) ? 64 : 32;
1028 p->is_pcix = (pci_mode & F_PCI_MODE_PCIX) != 0;
1029}
1030
1031
1032
1033
1034void t1_free_sw_modules(adapter_t *adapter)
1035{
1036 unsigned int i;
1037
1038 for_each_port(adapter, i) {
1039 struct cmac *mac = adapter->port[i].mac;
1040 struct cphy *phy = adapter->port[i].phy;
1041
1042 if (mac)
1043 mac->ops->destroy(mac);
1044 if (phy)
1045 phy->ops->destroy(phy);
1046 }
1047
1048 if (adapter->sge)
1049 t1_sge_destroy(adapter->sge);
1050 if (adapter->tp)
1051 t1_tp_destroy(adapter->tp);
1052 if (adapter->espi)
1053 t1_espi_destroy(adapter->espi);
1054}
1055
1056static void init_link_config(struct link_config *lc,
1057 const struct board_info *bi)
1058{
1059 lc->supported = bi->caps;
1060 lc->requested_speed = lc->speed = SPEED_INVALID;
1061 lc->requested_duplex = lc->duplex = DUPLEX_INVALID;
1062 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
1063 if (lc->supported & SUPPORTED_Autoneg) {
1064 lc->advertising = lc->supported;
1065 lc->autoneg = AUTONEG_ENABLE;
1066 lc->requested_fc |= PAUSE_AUTONEG;
1067 } else {
1068 lc->advertising = 0;
1069 lc->autoneg = AUTONEG_DISABLE;
1070 }
1071}
1072
1073
1074
1075
1076
1077int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi)
1078{
1079 unsigned int i;
1080
1081 adapter->params.brd_info = bi;
1082 adapter->params.nports = bi->port_number;
1083 adapter->params.stats_update_period = bi->gmac->stats_update_period;
1084
1085 adapter->sge = t1_sge_create(adapter, &adapter->params.sge);
1086 if (!adapter->sge) {
1087 pr_err("%s: SGE initialization failed\n",
1088 adapter->name);
1089 goto error;
1090 }
1091
1092 if (bi->espi_nports && !(adapter->espi = t1_espi_create(adapter))) {
1093 pr_err("%s: ESPI initialization failed\n",
1094 adapter->name);
1095 goto error;
1096 }
1097
1098 adapter->tp = t1_tp_create(adapter, &adapter->params.tp);
1099 if (!adapter->tp) {
1100 pr_err("%s: TP initialization failed\n",
1101 adapter->name);
1102 goto error;
1103 }
1104
1105 board_init(adapter, bi);
1106 bi->mdio_ops->init(adapter, bi);
1107 if (bi->gphy->reset)
1108 bi->gphy->reset(adapter);
1109 if (bi->gmac->reset)
1110 bi->gmac->reset(adapter);
1111
1112 for_each_port(adapter, i) {
1113 u8 hw_addr[6];
1114 struct cmac *mac;
1115 int phy_addr = bi->mdio_phybaseaddr + i;
1116
1117 adapter->port[i].phy = bi->gphy->create(adapter->port[i].dev,
1118 phy_addr, bi->mdio_ops);
1119 if (!adapter->port[i].phy) {
1120 pr_err("%s: PHY %d initialization failed\n",
1121 adapter->name, i);
1122 goto error;
1123 }
1124
1125 adapter->port[i].mac = mac = bi->gmac->create(adapter, i);
1126 if (!mac) {
1127 pr_err("%s: MAC %d initialization failed\n",
1128 adapter->name, i);
1129 goto error;
1130 }
1131
1132
1133
1134
1135
1136 if (!t1_is_asic(adapter) || bi->chip_mac == CHBT_MAC_DUMMY)
1137 mac->ops->macaddress_get(mac, hw_addr);
1138 else if (vpd_macaddress_get(adapter, i, hw_addr)) {
1139 pr_err("%s: could not read MAC address from VPD ROM\n",
1140 adapter->port[i].dev->name);
1141 goto error;
1142 }
1143 memcpy(adapter->port[i].dev->dev_addr, hw_addr, ETH_ALEN);
1144 init_link_config(&adapter->port[i].link_config, bi);
1145 }
1146
1147 get_pci_mode(adapter, &adapter->params.pci);
1148 t1_interrupts_clear(adapter);
1149 return 0;
1150
1151error:
1152 t1_free_sw_modules(adapter);
1153 return -1;
1154}
1155
