1
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4
5
6#include <linux/firmware.h>
7#include <linux/mdio.h>
8
9#include "cxgb4.h"
10#include "t4_regs.h"
11#include "t4fw_api.h"
12#include "cxgb4_cudbg.h"
13#include "cxgb4_filter.h"
14#include "cxgb4_tc_flower.h"
15
16#define EEPROM_MAGIC 0x38E2F10C
17
18static u32 get_msglevel(struct net_device *dev)
19{
20 return netdev2adap(dev)->msg_enable;
21}
22
23static void set_msglevel(struct net_device *dev, u32 val)
24{
25 netdev2adap(dev)->msg_enable = val;
26}
27
28enum cxgb4_ethtool_tests {
29 CXGB4_ETHTOOL_LB_TEST,
30 CXGB4_ETHTOOL_MAX_TEST,
31};
32
33static const char cxgb4_selftest_strings[CXGB4_ETHTOOL_MAX_TEST][ETH_GSTRING_LEN] = {
34 "Loop back test (offline)",
35};
36
37static const char * const flash_region_strings[] = {
38 "All",
39 "Firmware",
40 "PHY Firmware",
41 "Boot",
42 "Boot CFG",
43};
44
45static const char stats_strings[][ETH_GSTRING_LEN] = {
46 "tx_octets_ok ",
47 "tx_frames_ok ",
48 "tx_broadcast_frames ",
49 "tx_multicast_frames ",
50 "tx_unicast_frames ",
51 "tx_error_frames ",
52
53 "tx_frames_64 ",
54 "tx_frames_65_to_127 ",
55 "tx_frames_128_to_255 ",
56 "tx_frames_256_to_511 ",
57 "tx_frames_512_to_1023 ",
58 "tx_frames_1024_to_1518 ",
59 "tx_frames_1519_to_max ",
60
61 "tx_frames_dropped ",
62 "tx_pause_frames ",
63 "tx_ppp0_frames ",
64 "tx_ppp1_frames ",
65 "tx_ppp2_frames ",
66 "tx_ppp3_frames ",
67 "tx_ppp4_frames ",
68 "tx_ppp5_frames ",
69 "tx_ppp6_frames ",
70 "tx_ppp7_frames ",
71
72 "rx_octets_ok ",
73 "rx_frames_ok ",
74 "rx_broadcast_frames ",
75 "rx_multicast_frames ",
76 "rx_unicast_frames ",
77
78 "rx_frames_too_long ",
79 "rx_jabber_errors ",
80 "rx_fcs_errors ",
81 "rx_length_errors ",
82 "rx_symbol_errors ",
83 "rx_runt_frames ",
84
85 "rx_frames_64 ",
86 "rx_frames_65_to_127 ",
87 "rx_frames_128_to_255 ",
88 "rx_frames_256_to_511 ",
89 "rx_frames_512_to_1023 ",
90 "rx_frames_1024_to_1518 ",
91 "rx_frames_1519_to_max ",
92
93 "rx_pause_frames ",
94 "rx_ppp0_frames ",
95 "rx_ppp1_frames ",
96 "rx_ppp2_frames ",
97 "rx_ppp3_frames ",
98 "rx_ppp4_frames ",
99 "rx_ppp5_frames ",
100 "rx_ppp6_frames ",
101 "rx_ppp7_frames ",
102
103 "rx_bg0_frames_dropped ",
104 "rx_bg1_frames_dropped ",
105 "rx_bg2_frames_dropped ",
106 "rx_bg3_frames_dropped ",
107 "rx_bg0_frames_trunc ",
108 "rx_bg1_frames_trunc ",
109 "rx_bg2_frames_trunc ",
110 "rx_bg3_frames_trunc ",
111
112 "tso ",
113 "uso ",
114 "tx_csum_offload ",
115 "rx_csum_good ",
116 "vlan_extractions ",
117 "vlan_insertions ",
118 "gro_packets ",
119 "gro_merged ",
120#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
121 "tx_tls_encrypted_packets",
122 "tx_tls_encrypted_bytes ",
123 "tx_tls_ctx ",
124 "tx_tls_ooo ",
125 "tx_tls_skip_no_sync_data",
126 "tx_tls_drop_no_sync_data",
127 "tx_tls_drop_bypass_req ",
128#endif
129};
130
131static char adapter_stats_strings[][ETH_GSTRING_LEN] = {
132 "db_drop ",
133 "db_full ",
134 "db_empty ",
135 "write_coal_success ",
136 "write_coal_fail ",
137};
138
139static char loopback_stats_strings[][ETH_GSTRING_LEN] = {
140 "-------Loopback----------- ",
141 "octets_ok ",
142 "frames_ok ",
143 "bcast_frames ",
144 "mcast_frames ",
145 "ucast_frames ",
146 "error_frames ",
147 "frames_64 ",
148 "frames_65_to_127 ",
149 "frames_128_to_255 ",
150 "frames_256_to_511 ",
151 "frames_512_to_1023 ",
152 "frames_1024_to_1518 ",
153 "frames_1519_to_max ",
154 "frames_dropped ",
155 "bg0_frames_dropped ",
156 "bg1_frames_dropped ",
157 "bg2_frames_dropped ",
158 "bg3_frames_dropped ",
159 "bg0_frames_trunc ",
160 "bg1_frames_trunc ",
161 "bg2_frames_trunc ",
162 "bg3_frames_trunc ",
163};
164
165static const char cxgb4_priv_flags_strings[][ETH_GSTRING_LEN] = {
166 [PRIV_FLAG_PORT_TX_VM_BIT] = "port_tx_vm_wr",
167};
168
169static int get_sset_count(struct net_device *dev, int sset)
170{
171 switch (sset) {
172 case ETH_SS_STATS:
173 return ARRAY_SIZE(stats_strings) +
174 ARRAY_SIZE(adapter_stats_strings) +
175 ARRAY_SIZE(loopback_stats_strings);
176 case ETH_SS_PRIV_FLAGS:
177 return ARRAY_SIZE(cxgb4_priv_flags_strings);
178 case ETH_SS_TEST:
179 return ARRAY_SIZE(cxgb4_selftest_strings);
180 default:
181 return -EOPNOTSUPP;
182 }
183}
184
185static int get_regs_len(struct net_device *dev)
186{
187 struct adapter *adap = netdev2adap(dev);
188
189 return t4_get_regs_len(adap);
190}
191
192static int get_eeprom_len(struct net_device *dev)
193{
194 return EEPROMSIZE;
195}
196
197static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
198{
199 struct adapter *adapter = netdev2adap(dev);
200 u32 exprom_vers;
201
202 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver));
203 strlcpy(info->bus_info, pci_name(adapter->pdev),
204 sizeof(info->bus_info));
205 info->regdump_len = get_regs_len(dev);
206
207 if (adapter->params.fw_vers)
208 snprintf(info->fw_version, sizeof(info->fw_version),
209 "%u.%u.%u.%u, TP %u.%u.%u.%u",
210 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
211 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
212 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
213 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers),
214 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
215 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
216 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
217 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
218
219 if (!t4_get_exprom_version(adapter, &exprom_vers))
220 snprintf(info->erom_version, sizeof(info->erom_version),
221 "%u.%u.%u.%u",
222 FW_HDR_FW_VER_MAJOR_G(exprom_vers),
223 FW_HDR_FW_VER_MINOR_G(exprom_vers),
224 FW_HDR_FW_VER_MICRO_G(exprom_vers),
225 FW_HDR_FW_VER_BUILD_G(exprom_vers));
226 info->n_priv_flags = ARRAY_SIZE(cxgb4_priv_flags_strings);
227}
228
229static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
230{
231 if (stringset == ETH_SS_STATS) {
232 memcpy(data, stats_strings, sizeof(stats_strings));
233 data += sizeof(stats_strings);
234 memcpy(data, adapter_stats_strings,
235 sizeof(adapter_stats_strings));
236 data += sizeof(adapter_stats_strings);
237 memcpy(data, loopback_stats_strings,
238 sizeof(loopback_stats_strings));
239 } else if (stringset == ETH_SS_PRIV_FLAGS) {
240 memcpy(data, cxgb4_priv_flags_strings,
241 sizeof(cxgb4_priv_flags_strings));
242 } else if (stringset == ETH_SS_TEST) {
243 memcpy(data, cxgb4_selftest_strings,
244 sizeof(cxgb4_selftest_strings));
245 }
246}
247
248
249
250
251struct queue_port_stats {
252 u64 tso;
253 u64 uso;
254 u64 tx_csum;
255 u64 rx_csum;
256 u64 vlan_ex;
257 u64 vlan_ins;
258 u64 gro_pkts;
259 u64 gro_merged;
260#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
261 u64 tx_tls_encrypted_packets;
262 u64 tx_tls_encrypted_bytes;
263 u64 tx_tls_ctx;
264 u64 tx_tls_ooo;
265 u64 tx_tls_skip_no_sync_data;
266 u64 tx_tls_drop_no_sync_data;
267 u64 tx_tls_drop_bypass_req;
268#endif
269};
270
271struct adapter_stats {
272 u64 db_drop;
273 u64 db_full;
274 u64 db_empty;
275 u64 wc_success;
276 u64 wc_fail;
277};
278
279static void collect_sge_port_stats(const struct adapter *adap,
280 const struct port_info *p,
281 struct queue_port_stats *s)
282{
283 const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
284 const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
285#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
286 const struct ch_ktls_port_stats_debug *ktls_stats;
287#endif
288 struct sge_eohw_txq *eohw_tx;
289 unsigned int i;
290
291 memset(s, 0, sizeof(*s));
292 for (i = 0; i < p->nqsets; i++, rx++, tx++) {
293 s->tso += tx->tso;
294 s->uso += tx->uso;
295 s->tx_csum += tx->tx_cso;
296 s->rx_csum += rx->stats.rx_cso;
297 s->vlan_ex += rx->stats.vlan_ex;
298 s->vlan_ins += tx->vlan_ins;
299 s->gro_pkts += rx->stats.lro_pkts;
300 s->gro_merged += rx->stats.lro_merged;
301 }
302
303 if (adap->sge.eohw_txq) {
304 eohw_tx = &adap->sge.eohw_txq[p->first_qset];
305 for (i = 0; i < p->nqsets; i++, eohw_tx++) {
306 s->tso += eohw_tx->tso;
307 s->uso += eohw_tx->uso;
308 s->tx_csum += eohw_tx->tx_cso;
309 s->vlan_ins += eohw_tx->vlan_ins;
310 }
311 }
312#if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
313 ktls_stats = &adap->ch_ktls_stats.ktls_port[p->port_id];
314 s->tx_tls_encrypted_packets =
315 atomic64_read(&ktls_stats->ktls_tx_encrypted_packets);
316 s->tx_tls_encrypted_bytes =
317 atomic64_read(&ktls_stats->ktls_tx_encrypted_bytes);
318 s->tx_tls_ctx = atomic64_read(&ktls_stats->ktls_tx_ctx);
319 s->tx_tls_ooo = atomic64_read(&ktls_stats->ktls_tx_ooo);
320 s->tx_tls_skip_no_sync_data =
321 atomic64_read(&ktls_stats->ktls_tx_skip_no_sync_data);
322 s->tx_tls_drop_no_sync_data =
323 atomic64_read(&ktls_stats->ktls_tx_drop_no_sync_data);
324 s->tx_tls_drop_bypass_req =
325 atomic64_read(&ktls_stats->ktls_tx_drop_bypass_req);
326#endif
327}
328
329static void collect_adapter_stats(struct adapter *adap, struct adapter_stats *s)
330{
331 u64 val1, val2;
332
333 memset(s, 0, sizeof(*s));
334
335 s->db_drop = adap->db_stats.db_drop;
336 s->db_full = adap->db_stats.db_full;
337 s->db_empty = adap->db_stats.db_empty;
338
339 if (!is_t4(adap->params.chip)) {
340 int v;
341
342 v = t4_read_reg(adap, SGE_STAT_CFG_A);
343 if (STATSOURCE_T5_G(v) == 7) {
344 val2 = t4_read_reg(adap, SGE_STAT_MATCH_A);
345 val1 = t4_read_reg(adap, SGE_STAT_TOTAL_A);
346 s->wc_success = val1 - val2;
347 s->wc_fail = val2;
348 }
349 }
350}
351
352static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
353 u64 *data)
354{
355 struct port_info *pi = netdev_priv(dev);
356 struct adapter *adapter = pi->adapter;
357 struct lb_port_stats s;
358 int i;
359 u64 *p0;
360
361 t4_get_port_stats_offset(adapter, pi->tx_chan,
362 (struct port_stats *)data,
363 &pi->stats_base);
364
365 data += sizeof(struct port_stats) / sizeof(u64);
366 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
367 data += sizeof(struct queue_port_stats) / sizeof(u64);
368 collect_adapter_stats(adapter, (struct adapter_stats *)data);
369 data += sizeof(struct adapter_stats) / sizeof(u64);
370
371 *data++ = (u64)pi->port_id;
372 memset(&s, 0, sizeof(s));
373 t4_get_lb_stats(adapter, pi->port_id, &s);
374
375 p0 = &s.octets;
376 for (i = 0; i < ARRAY_SIZE(loopback_stats_strings) - 1; i++)
377 *data++ = (unsigned long long)*p0++;
378}
379
380static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
381 void *buf)
382{
383 struct adapter *adap = netdev2adap(dev);
384 size_t buf_size;
385
386 buf_size = t4_get_regs_len(adap);
387 regs->version = mk_adap_vers(adap);
388 t4_get_regs(adap, buf, buf_size);
389}
390
391static int restart_autoneg(struct net_device *dev)
392{
393 struct port_info *p = netdev_priv(dev);
394
395 if (!netif_running(dev))
396 return -EAGAIN;
397 if (p->link_cfg.autoneg != AUTONEG_ENABLE)
398 return -EINVAL;
399 t4_restart_aneg(p->adapter, p->adapter->pf, p->tx_chan);
400 return 0;
401}
402
403static int identify_port(struct net_device *dev,
404 enum ethtool_phys_id_state state)
405{
406 unsigned int val;
407 struct adapter *adap = netdev2adap(dev);
408
409 if (state == ETHTOOL_ID_ACTIVE)
410 val = 0xffff;
411 else if (state == ETHTOOL_ID_INACTIVE)
412 val = 0;
413 else
414 return -EINVAL;
415
416 return t4_identify_port(adap, adap->pf, netdev2pinfo(dev)->viid, val);
417}
418
419
420
421
422
423
424
425
426static int from_fw_port_mod_type(enum fw_port_type port_type,
427 enum fw_port_module_type mod_type)
428{
429 if (port_type == FW_PORT_TYPE_BT_SGMII ||
430 port_type == FW_PORT_TYPE_BT_XFI ||
431 port_type == FW_PORT_TYPE_BT_XAUI) {
432 return PORT_TP;
433 } else if (port_type == FW_PORT_TYPE_FIBER_XFI ||
434 port_type == FW_PORT_TYPE_FIBER_XAUI) {
435 return PORT_FIBRE;
436 } else if (port_type == FW_PORT_TYPE_SFP ||
437 port_type == FW_PORT_TYPE_QSFP_10G ||
438 port_type == FW_PORT_TYPE_QSA ||
439 port_type == FW_PORT_TYPE_QSFP ||
440 port_type == FW_PORT_TYPE_CR4_QSFP ||
441 port_type == FW_PORT_TYPE_CR_QSFP ||
442 port_type == FW_PORT_TYPE_CR2_QSFP ||
443 port_type == FW_PORT_TYPE_SFP28) {
444 if (mod_type == FW_PORT_MOD_TYPE_LR ||
445 mod_type == FW_PORT_MOD_TYPE_SR ||
446 mod_type == FW_PORT_MOD_TYPE_ER ||
447 mod_type == FW_PORT_MOD_TYPE_LRM)
448 return PORT_FIBRE;
449 else if (mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
450 mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
451 return PORT_DA;
452 else
453 return PORT_OTHER;
454 } else if (port_type == FW_PORT_TYPE_KR4_100G ||
455 port_type == FW_PORT_TYPE_KR_SFP28 ||
456 port_type == FW_PORT_TYPE_KR_XLAUI) {
457 return PORT_NONE;
458 }
459
460 return PORT_OTHER;
461}
462
463
464
465
466
467
468
469
470static unsigned int speed_to_fw_caps(int speed)
471{
472 if (speed == 100)
473 return FW_PORT_CAP32_SPEED_100M;
474 if (speed == 1000)
475 return FW_PORT_CAP32_SPEED_1G;
476 if (speed == 10000)
477 return FW_PORT_CAP32_SPEED_10G;
478 if (speed == 25000)
479 return FW_PORT_CAP32_SPEED_25G;
480 if (speed == 40000)
481 return FW_PORT_CAP32_SPEED_40G;
482 if (speed == 50000)
483 return FW_PORT_CAP32_SPEED_50G;
484 if (speed == 100000)
485 return FW_PORT_CAP32_SPEED_100G;
486 if (speed == 200000)
487 return FW_PORT_CAP32_SPEED_200G;
488 if (speed == 400000)
489 return FW_PORT_CAP32_SPEED_400G;
490 return 0;
491}
492
493
494
495
496
497
498
499
500
501
502static void fw_caps_to_lmm(enum fw_port_type port_type,
503 fw_port_cap32_t fw_caps,
504 unsigned long *link_mode_mask)
505{
506 #define SET_LMM(__lmm_name) \
507 do { \
508 __set_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \
509 link_mode_mask); \
510 } while (0)
511
512 #define FW_CAPS_TO_LMM(__fw_name, __lmm_name) \
513 do { \
514 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
515 SET_LMM(__lmm_name); \
516 } while (0)
517
518 switch (port_type) {
519 case FW_PORT_TYPE_BT_SGMII:
520 case FW_PORT_TYPE_BT_XFI:
521 case FW_PORT_TYPE_BT_XAUI:
522 SET_LMM(TP);
523 FW_CAPS_TO_LMM(SPEED_100M, 100baseT_Full);
524 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
525 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
526 break;
527
528 case FW_PORT_TYPE_KX4:
529 case FW_PORT_TYPE_KX:
530 SET_LMM(Backplane);
531 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
532 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
533 break;
534
535 case FW_PORT_TYPE_KR:
536 SET_LMM(Backplane);
537 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
538 break;
539
540 case FW_PORT_TYPE_BP_AP:
541 SET_LMM(Backplane);
542 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
543 FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
544 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
545 break;
546
547 case FW_PORT_TYPE_BP4_AP:
548 SET_LMM(Backplane);
549 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
550 FW_CAPS_TO_LMM(SPEED_10G, 10000baseR_FEC);
551 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
552 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKX4_Full);
553 break;
554
555 case FW_PORT_TYPE_FIBER_XFI:
556 case FW_PORT_TYPE_FIBER_XAUI:
557 case FW_PORT_TYPE_SFP:
558 case FW_PORT_TYPE_QSFP_10G:
559 case FW_PORT_TYPE_QSA:
560 SET_LMM(FIBRE);
561 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
562 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
563 break;
564
565 case FW_PORT_TYPE_BP40_BA:
566 case FW_PORT_TYPE_QSFP:
567 SET_LMM(FIBRE);
568 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
569 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
570 FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
571 break;
572
573 case FW_PORT_TYPE_CR_QSFP:
574 case FW_PORT_TYPE_SFP28:
575 SET_LMM(FIBRE);
576 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
577 FW_CAPS_TO_LMM(SPEED_10G, 10000baseT_Full);
578 FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
579 break;
580
581 case FW_PORT_TYPE_KR_SFP28:
582 SET_LMM(Backplane);
583 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
584 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
585 FW_CAPS_TO_LMM(SPEED_25G, 25000baseKR_Full);
586 break;
587
588 case FW_PORT_TYPE_KR_XLAUI:
589 SET_LMM(Backplane);
590 FW_CAPS_TO_LMM(SPEED_1G, 1000baseKX_Full);
591 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
592 FW_CAPS_TO_LMM(SPEED_40G, 40000baseKR4_Full);
593 break;
594
595 case FW_PORT_TYPE_CR2_QSFP:
596 SET_LMM(FIBRE);
597 FW_CAPS_TO_LMM(SPEED_50G, 50000baseSR2_Full);
598 break;
599
600 case FW_PORT_TYPE_KR4_100G:
601 case FW_PORT_TYPE_CR4_QSFP:
602 SET_LMM(FIBRE);
603 FW_CAPS_TO_LMM(SPEED_1G, 1000baseT_Full);
604 FW_CAPS_TO_LMM(SPEED_10G, 10000baseKR_Full);
605 FW_CAPS_TO_LMM(SPEED_40G, 40000baseSR4_Full);
606 FW_CAPS_TO_LMM(SPEED_25G, 25000baseCR_Full);
607 FW_CAPS_TO_LMM(SPEED_50G, 50000baseCR2_Full);
608 FW_CAPS_TO_LMM(SPEED_100G, 100000baseCR4_Full);
609 break;
610
611 default:
612 break;
613 }
614
615 if (fw_caps & FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M)) {
616 FW_CAPS_TO_LMM(FEC_RS, FEC_RS);
617 FW_CAPS_TO_LMM(FEC_BASER_RS, FEC_BASER);
618 } else {
619 SET_LMM(FEC_NONE);
620 }
621
622 FW_CAPS_TO_LMM(ANEG, Autoneg);
623 FW_CAPS_TO_LMM(802_3_PAUSE, Pause);
624 FW_CAPS_TO_LMM(802_3_ASM_DIR, Asym_Pause);
625
626 #undef FW_CAPS_TO_LMM
627 #undef SET_LMM
628}
629
630
631
632
633
634
635
636
637
638static unsigned int lmm_to_fw_caps(const unsigned long *link_mode_mask)
639{
640 unsigned int fw_caps = 0;
641
642 #define LMM_TO_FW_CAPS(__lmm_name, __fw_name) \
643 do { \
644 if (test_bit(ETHTOOL_LINK_MODE_ ## __lmm_name ## _BIT, \
645 link_mode_mask)) \
646 fw_caps |= FW_PORT_CAP32_ ## __fw_name; \
647 } while (0)
648
649 LMM_TO_FW_CAPS(100baseT_Full, SPEED_100M);
650 LMM_TO_FW_CAPS(1000baseT_Full, SPEED_1G);
651 LMM_TO_FW_CAPS(10000baseT_Full, SPEED_10G);
652 LMM_TO_FW_CAPS(40000baseSR4_Full, SPEED_40G);
653 LMM_TO_FW_CAPS(25000baseCR_Full, SPEED_25G);
654 LMM_TO_FW_CAPS(50000baseCR2_Full, SPEED_50G);
655 LMM_TO_FW_CAPS(100000baseCR4_Full, SPEED_100G);
656
657 #undef LMM_TO_FW_CAPS
658
659 return fw_caps;
660}
661
662static int get_link_ksettings(struct net_device *dev,
663 struct ethtool_link_ksettings *link_ksettings)
664{
665 struct port_info *pi = netdev_priv(dev);
666 struct ethtool_link_settings *base = &link_ksettings->base;
667
668
669
670
671
672 if (!netif_running(dev))
673 (void)t4_update_port_info(pi);
674
675 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
676 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
677 ethtool_link_ksettings_zero_link_mode(link_ksettings, lp_advertising);
678
679 base->port = from_fw_port_mod_type(pi->port_type, pi->mod_type);
680
681 if (pi->mdio_addr >= 0) {
682 base->phy_address = pi->mdio_addr;
683 base->mdio_support = (pi->port_type == FW_PORT_TYPE_BT_SGMII
684 ? ETH_MDIO_SUPPORTS_C22
685 : ETH_MDIO_SUPPORTS_C45);
686 } else {
687 base->phy_address = 255;
688 base->mdio_support = 0;
689 }
690
691 fw_caps_to_lmm(pi->port_type, pi->link_cfg.pcaps,
692 link_ksettings->link_modes.supported);
693 fw_caps_to_lmm(pi->port_type,
694 t4_link_acaps(pi->adapter,
695 pi->lport,
696 &pi->link_cfg),
697 link_ksettings->link_modes.advertising);
698 fw_caps_to_lmm(pi->port_type, pi->link_cfg.lpacaps,
699 link_ksettings->link_modes.lp_advertising);
700
701 base->speed = (netif_carrier_ok(dev)
702 ? pi->link_cfg.speed
703 : SPEED_UNKNOWN);
704 base->duplex = DUPLEX_FULL;
705
706 base->autoneg = pi->link_cfg.autoneg;
707 if (pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG)
708 ethtool_link_ksettings_add_link_mode(link_ksettings,
709 supported, Autoneg);
710 if (pi->link_cfg.autoneg)
711 ethtool_link_ksettings_add_link_mode(link_ksettings,
712 advertising, Autoneg);
713
714 return 0;
715}
716
717static int set_link_ksettings(struct net_device *dev,
718 const struct ethtool_link_ksettings *link_ksettings)
719{
720 struct port_info *pi = netdev_priv(dev);
721 struct link_config *lc = &pi->link_cfg;
722 const struct ethtool_link_settings *base = &link_ksettings->base;
723 struct link_config old_lc;
724 unsigned int fw_caps;
725 int ret = 0;
726
727
728 if (base->duplex != DUPLEX_FULL)
729 return -EINVAL;
730
731 old_lc = *lc;
732 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) ||
733 base->autoneg == AUTONEG_DISABLE) {
734 fw_caps = speed_to_fw_caps(base->speed);
735
736
737 if (!(lc->pcaps & fw_caps))
738 return -EINVAL;
739
740 lc->speed_caps = fw_caps;
741 lc->acaps = fw_caps;
742 } else {
743 fw_caps =
744 lmm_to_fw_caps(link_ksettings->link_modes.advertising);
745 if (!(lc->pcaps & fw_caps))
746 return -EINVAL;
747 lc->speed_caps = 0;
748 lc->acaps = fw_caps | FW_PORT_CAP32_ANEG;
749 }
750 lc->autoneg = base->autoneg;
751
752
753
754
755 ret = t4_link_l1cfg(pi->adapter, pi->adapter->mbox, pi->tx_chan, lc);
756 if (ret)
757 *lc = old_lc;
758
759 return ret;
760}
761
762
763static inline unsigned int fwcap_to_eth_fec(unsigned int fw_fec)
764{
765 unsigned int eth_fec = 0;
766
767 if (fw_fec & FW_PORT_CAP32_FEC_RS)
768 eth_fec |= ETHTOOL_FEC_RS;
769 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
770 eth_fec |= ETHTOOL_FEC_BASER;
771
772
773 if (!eth_fec)
774 eth_fec = ETHTOOL_FEC_OFF;
775
776 return eth_fec;
777}
778
779
780static inline unsigned int cc_to_eth_fec(unsigned int cc_fec)
781{
782 unsigned int eth_fec = 0;
783
784 if (cc_fec & FEC_AUTO)
785 eth_fec |= ETHTOOL_FEC_AUTO;
786 if (cc_fec & FEC_RS)
787 eth_fec |= ETHTOOL_FEC_RS;
788 if (cc_fec & FEC_BASER_RS)
789 eth_fec |= ETHTOOL_FEC_BASER;
790
791
792 if (!eth_fec)
793 eth_fec = ETHTOOL_FEC_OFF;
794
795 return eth_fec;
796}
797
798
799static inline unsigned int eth_to_cc_fec(unsigned int eth_fec)
800{
801 unsigned int cc_fec = 0;
802
803 if (eth_fec & ETHTOOL_FEC_OFF)
804 return cc_fec;
805
806 if (eth_fec & ETHTOOL_FEC_AUTO)
807 cc_fec |= FEC_AUTO;
808 if (eth_fec & ETHTOOL_FEC_RS)
809 cc_fec |= FEC_RS;
810 if (eth_fec & ETHTOOL_FEC_BASER)
811 cc_fec |= FEC_BASER_RS;
812
813 return cc_fec;
814}
815
816static int get_fecparam(struct net_device *dev, struct ethtool_fecparam *fec)
817{
818 const struct port_info *pi = netdev_priv(dev);
819 const struct link_config *lc = &pi->link_cfg;
820
821
822
823
824
825 fec->fec = fwcap_to_eth_fec(lc->pcaps);
826 if (fec->fec != ETHTOOL_FEC_OFF)
827 fec->fec |= ETHTOOL_FEC_AUTO;
828
829
830
831
832 fec->active_fec = cc_to_eth_fec(lc->fec);
833
834 return 0;
835}
836
837static int set_fecparam(struct net_device *dev, struct ethtool_fecparam *fec)
838{
839 struct port_info *pi = netdev_priv(dev);
840 struct link_config *lc = &pi->link_cfg;
841 struct link_config old_lc;
842 int ret;
843
844
845
846
847 old_lc = *lc;
848
849
850
851
852 lc->requested_fec = eth_to_cc_fec(fec->fec);
853 ret = t4_link_l1cfg(pi->adapter, pi->adapter->mbox,
854 pi->tx_chan, lc);
855 if (ret)
856 *lc = old_lc;
857 return ret;
858}
859
860static void get_pauseparam(struct net_device *dev,
861 struct ethtool_pauseparam *epause)
862{
863 struct port_info *p = netdev_priv(dev);
864
865 epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
866 epause->rx_pause = (p->link_cfg.advertised_fc & PAUSE_RX) != 0;
867 epause->tx_pause = (p->link_cfg.advertised_fc & PAUSE_TX) != 0;
868}
869
870static int set_pauseparam(struct net_device *dev,
871 struct ethtool_pauseparam *epause)
872{
873 struct port_info *p = netdev_priv(dev);
874 struct link_config *lc = &p->link_cfg;
875
876 if (epause->autoneg == AUTONEG_DISABLE)
877 lc->requested_fc = 0;
878 else if (lc->pcaps & FW_PORT_CAP32_ANEG)
879 lc->requested_fc = PAUSE_AUTONEG;
880 else
881 return -EINVAL;
882
883 if (epause->rx_pause)
884 lc->requested_fc |= PAUSE_RX;
885 if (epause->tx_pause)
886 lc->requested_fc |= PAUSE_TX;
887 if (netif_running(dev))
888 return t4_link_l1cfg(p->adapter, p->adapter->mbox, p->tx_chan,
889 lc);
890 return 0;
891}
892
893static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
894{
895 const struct port_info *pi = netdev_priv(dev);
896 const struct sge *s = &pi->adapter->sge;
897
898 e->rx_max_pending = MAX_RX_BUFFERS;
899 e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
900 e->rx_jumbo_max_pending = 0;
901 e->tx_max_pending = MAX_TXQ_ENTRIES;
902
903 e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
904 e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
905 e->rx_jumbo_pending = 0;
906 e->tx_pending = s->ethtxq[pi->first_qset].q.size;
907}
908
909static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
910{
911 int i;
912 const struct port_info *pi = netdev_priv(dev);
913 struct adapter *adapter = pi->adapter;
914 struct sge *s = &adapter->sge;
915
916 if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
917 e->tx_pending > MAX_TXQ_ENTRIES ||
918 e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
919 e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
920 e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
921 return -EINVAL;
922
923 if (adapter->flags & CXGB4_FULL_INIT_DONE)
924 return -EBUSY;
925
926 for (i = 0; i < pi->nqsets; ++i) {
927 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
928 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
929 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
930 }
931 return 0;
932}
933
934
935
936
937
938
939
940
941
942static int set_rx_intr_params(struct net_device *dev,
943 unsigned int us, unsigned int cnt)
944{
945 int i, err;
946 struct port_info *pi = netdev_priv(dev);
947 struct adapter *adap = pi->adapter;
948 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
949
950 for (i = 0; i < pi->nqsets; i++, q++) {
951 err = cxgb4_set_rspq_intr_params(&q->rspq, us, cnt);
952 if (err)
953 return err;
954 }
955 return 0;
956}
957
958static int set_adaptive_rx_setting(struct net_device *dev, int adaptive_rx)
959{
960 int i;
961 struct port_info *pi = netdev_priv(dev);
962 struct adapter *adap = pi->adapter;
963 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
964
965 for (i = 0; i < pi->nqsets; i++, q++)
966 q->rspq.adaptive_rx = adaptive_rx;
967
968 return 0;
969}
970
971static int get_adaptive_rx_setting(struct net_device *dev)
972{
973 struct port_info *pi = netdev_priv(dev);
974 struct adapter *adap = pi->adapter;
975 struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
976
977 return q->rspq.adaptive_rx;
978}
979
980
981
982
983static int get_dbqtimer_tick(struct net_device *dev)
984{
985 struct port_info *pi = netdev_priv(dev);
986 struct adapter *adap = pi->adapter;
987
988 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
989 return 0;
990
991 return adap->sge.dbqtimer_tick;
992}
993
994
995
996
997static int get_dbqtimer(struct net_device *dev)
998{
999 struct port_info *pi = netdev_priv(dev);
1000 struct adapter *adap = pi->adapter;
1001 struct sge_eth_txq *txq;
1002
1003 txq = &adap->sge.ethtxq[pi->first_qset];
1004
1005 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
1006 return 0;
1007
1008
1009 return adap->sge.dbqtimer_val[txq->dbqtimerix];
1010}
1011
1012
1013
1014
1015
1016
1017
1018
1019static int set_dbqtimer_tick(struct net_device *dev, int usecs)
1020{
1021 struct port_info *pi = netdev_priv(dev);
1022 struct adapter *adap = pi->adapter;
1023 struct sge *s = &adap->sge;
1024 u32 param, val;
1025 int ret;
1026
1027 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
1028 return 0;
1029
1030
1031 if (s->dbqtimer_tick == usecs)
1032 return 0;
1033
1034
1035 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
1036 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK));
1037 val = usecs;
1038 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val);
1039 if (ret)
1040 return ret;
1041 s->dbqtimer_tick = usecs;
1042
1043
1044 ret = t4_read_sge_dbqtimers(adap, ARRAY_SIZE(s->dbqtimer_val),
1045 s->dbqtimer_val);
1046 return ret;
1047}
1048
1049
1050
1051
1052
1053static int set_dbqtimer(struct net_device *dev, int usecs)
1054{
1055 int qix, timerix, min_timerix, delta, min_delta;
1056 struct port_info *pi = netdev_priv(dev);
1057 struct adapter *adap = pi->adapter;
1058 struct sge *s = &adap->sge;
1059 struct sge_eth_txq *txq;
1060 u32 param, val;
1061 int ret;
1062
1063 if (!(adap->flags & CXGB4_SGE_DBQ_TIMER))
1064 return 0;
1065
1066
1067
1068
1069 min_delta = INT_MAX;
1070 min_timerix = 0;
1071 for (timerix = 0; timerix < ARRAY_SIZE(s->dbqtimer_val); timerix++) {
1072 delta = s->dbqtimer_val[timerix] - usecs;
1073 if (delta < 0)
1074 delta = -delta;
1075 if (delta < min_delta) {
1076 min_delta = delta;
1077 min_timerix = timerix;
1078 }
1079 }
1080
1081
1082
1083
1084
1085 txq = &s->ethtxq[pi->first_qset];
1086 if (txq->dbqtimerix == min_timerix)
1087 return 0;
1088
1089 for (qix = 0; qix < pi->nqsets; qix++, txq++) {
1090 if (adap->flags & CXGB4_FULL_INIT_DONE) {
1091 param =
1092 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1093 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX) |
1094 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
1095 val = min_timerix;
1096 ret = t4_set_params(adap, adap->mbox, adap->pf, 0,
1097 1, ¶m, &val);
1098 if (ret)
1099 return ret;
1100 }
1101 txq->dbqtimerix = min_timerix;
1102 }
1103 return 0;
1104}
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116static int set_dbqtimer_tickval(struct net_device *dev,
1117 int tick_usecs, int timer_usecs)
1118{
1119 struct port_info *pi = netdev_priv(dev);
1120 struct adapter *adap = pi->adapter;
1121 int timer[MAX_NPORTS];
1122 unsigned int port;
1123 int ret;
1124
1125
1126
1127
1128 for_each_port(adap, port)
1129 if (port == pi->port_id)
1130 timer[port] = timer_usecs;
1131 else
1132 timer[port] = get_dbqtimer(adap->port[port]);
1133
1134
1135 ret = set_dbqtimer_tick(dev, tick_usecs);
1136 if (ret)
1137 return ret;
1138
1139
1140 for_each_port(adap, port) {
1141 ret = set_dbqtimer(adap->port[port], timer[port]);
1142 if (ret)
1143 return ret;
1144 }
1145
1146 return 0;
1147}
1148
1149static int set_coalesce(struct net_device *dev,
1150 struct ethtool_coalesce *coalesce,
1151 struct kernel_ethtool_coalesce *kernel_coal,
1152 struct netlink_ext_ack *extack)
1153{
1154 int ret;
1155
1156 set_adaptive_rx_setting(dev, coalesce->use_adaptive_rx_coalesce);
1157
1158 ret = set_rx_intr_params(dev, coalesce->rx_coalesce_usecs,
1159 coalesce->rx_max_coalesced_frames);
1160 if (ret)
1161 return ret;
1162
1163 return set_dbqtimer_tickval(dev,
1164 coalesce->tx_coalesce_usecs_irq,
1165 coalesce->tx_coalesce_usecs);
1166}
1167
1168static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c,
1169 struct kernel_ethtool_coalesce *kernel_coal,
1170 struct netlink_ext_ack *extack)
1171{
1172 const struct port_info *pi = netdev_priv(dev);
1173 const struct adapter *adap = pi->adapter;
1174 const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
1175
1176 c->rx_coalesce_usecs = qtimer_val(adap, rq);
1177 c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN_F) ?
1178 adap->sge.counter_val[rq->pktcnt_idx] : 0;
1179 c->use_adaptive_rx_coalesce = get_adaptive_rx_setting(dev);
1180 c->tx_coalesce_usecs_irq = get_dbqtimer_tick(dev);
1181 c->tx_coalesce_usecs = get_dbqtimer(dev);
1182 return 0;
1183}
1184
1185
1186
1187static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
1188{
1189 int vaddr = t4_eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1190
1191 if (vaddr >= 0)
1192 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
1193 return vaddr < 0 ? vaddr : 0;
1194}
1195
1196static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
1197{
1198 int vaddr = t4_eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
1199
1200 if (vaddr >= 0)
1201 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
1202 return vaddr < 0 ? vaddr : 0;
1203}
1204
1205#define EEPROM_MAGIC 0x38E2F10C
1206
1207static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
1208 u8 *data)
1209{
1210 int i, err = 0;
1211 struct adapter *adapter = netdev2adap(dev);
1212 u8 *buf = kvzalloc(EEPROMSIZE, GFP_KERNEL);
1213
1214 if (!buf)
1215 return -ENOMEM;
1216
1217 e->magic = EEPROM_MAGIC;
1218 for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
1219 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1220
1221 if (!err)
1222 memcpy(data, buf + e->offset, e->len);
1223 kvfree(buf);
1224 return err;
1225}
1226
1227static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
1228 u8 *data)
1229{
1230 u8 *buf;
1231 int err = 0;
1232 u32 aligned_offset, aligned_len, *p;
1233 struct adapter *adapter = netdev2adap(dev);
1234
1235 if (eeprom->magic != EEPROM_MAGIC)
1236 return -EINVAL;
1237
1238 aligned_offset = eeprom->offset & ~3;
1239 aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
1240
1241 if (adapter->pf > 0) {
1242 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1243
1244 if (aligned_offset < start ||
1245 aligned_offset + aligned_len > start + EEPROMPFSIZE)
1246 return -EPERM;
1247 }
1248
1249 if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
1250
1251
1252 buf = kvzalloc(aligned_len, GFP_KERNEL);
1253 if (!buf)
1254 return -ENOMEM;
1255 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1256 if (!err && aligned_len > 4)
1257 err = eeprom_rd_phys(adapter,
1258 aligned_offset + aligned_len - 4,
1259 (u32 *)&buf[aligned_len - 4]);
1260 if (err)
1261 goto out;
1262 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
1263 } else {
1264 buf = data;
1265 }
1266
1267 err = t4_seeprom_wp(adapter, false);
1268 if (err)
1269 goto out;
1270
1271 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1272 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1273 aligned_offset += 4;
1274 }
1275
1276 if (!err)
1277 err = t4_seeprom_wp(adapter, true);
1278out:
1279 if (buf != data)
1280 kvfree(buf);
1281 return err;
1282}
1283
1284static int cxgb4_ethtool_flash_bootcfg(struct net_device *netdev,
1285 const u8 *data, u32 size)
1286{
1287 struct adapter *adap = netdev2adap(netdev);
1288 int ret;
1289
1290 ret = t4_load_bootcfg(adap, data, size);
1291 if (ret)
1292 dev_err(adap->pdev_dev, "Failed to load boot cfg image\n");
1293
1294 return ret;
1295}
1296
1297static int cxgb4_ethtool_flash_boot(struct net_device *netdev,
1298 const u8 *bdata, u32 size)
1299{
1300 struct adapter *adap = netdev2adap(netdev);
1301 unsigned int offset;
1302 u8 *data;
1303 int ret;
1304
1305 data = kmemdup(bdata, size, GFP_KERNEL);
1306 if (!data)
1307 return -ENOMEM;
1308
1309 offset = OFFSET_G(t4_read_reg(adap, PF_REG(0, PCIE_PF_EXPROM_OFST_A)));
1310
1311 ret = t4_load_boot(adap, data, offset, size);
1312 if (ret)
1313 dev_err(adap->pdev_dev, "Failed to load boot image\n");
1314
1315 kfree(data);
1316 return ret;
1317}
1318
1319#define CXGB4_PHY_SIG 0x130000ea
1320
1321static int cxgb4_validate_phy_image(const u8 *data, u32 *size)
1322{
1323 struct cxgb4_fw_data *header;
1324
1325 header = (struct cxgb4_fw_data *)data;
1326 if (be32_to_cpu(header->signature) != CXGB4_PHY_SIG)
1327 return -EINVAL;
1328
1329 return 0;
1330}
1331
1332static int cxgb4_ethtool_flash_phy(struct net_device *netdev,
1333 const u8 *data, u32 size)
1334{
1335 struct adapter *adap = netdev2adap(netdev);
1336 int ret;
1337
1338 ret = cxgb4_validate_phy_image(data, NULL);
1339 if (ret) {
1340 dev_err(adap->pdev_dev, "PHY signature mismatch\n");
1341 return ret;
1342 }
1343
1344
1345
1346
1347
1348
1349 ret = t4_fw_reset(adap, adap->mbox, PIORSTMODE_F | PIORST_F);
1350 if (ret < 0) {
1351 dev_err(adap->pdev_dev,
1352 "Set FW to RESET for flashing PHY FW failed. ret: %d\n",
1353 ret);
1354 return ret;
1355 }
1356
1357 ret = t4_load_phy_fw(adap, MEMWIN_NIC, NULL, data, size);
1358 if (ret < 0) {
1359 dev_err(adap->pdev_dev, "Failed to load PHY FW. ret: %d\n",
1360 ret);
1361 return ret;
1362 }
1363
1364 return 0;
1365}
1366
1367static int cxgb4_ethtool_flash_fw(struct net_device *netdev,
1368 const u8 *data, u32 size)
1369{
1370 struct adapter *adap = netdev2adap(netdev);
1371 unsigned int mbox = PCIE_FW_MASTER_M + 1;
1372 int ret;
1373
1374
1375
1376
1377
1378
1379 if (adap->flags & CXGB4_FULL_INIT_DONE)
1380 mbox = adap->mbox;
1381
1382 ret = t4_fw_upgrade(adap, mbox, data, size, 1);
1383 if (ret)
1384 dev_err(adap->pdev_dev,
1385 "Failed to flash firmware\n");
1386
1387 return ret;
1388}
1389
1390static int cxgb4_ethtool_flash_region(struct net_device *netdev,
1391 const u8 *data, u32 size, u32 region)
1392{
1393 struct adapter *adap = netdev2adap(netdev);
1394 int ret;
1395
1396 switch (region) {
1397 case CXGB4_ETHTOOL_FLASH_FW:
1398 ret = cxgb4_ethtool_flash_fw(netdev, data, size);
1399 break;
1400 case CXGB4_ETHTOOL_FLASH_PHY:
1401 ret = cxgb4_ethtool_flash_phy(netdev, data, size);
1402 break;
1403 case CXGB4_ETHTOOL_FLASH_BOOT:
1404 ret = cxgb4_ethtool_flash_boot(netdev, data, size);
1405 break;
1406 case CXGB4_ETHTOOL_FLASH_BOOTCFG:
1407 ret = cxgb4_ethtool_flash_bootcfg(netdev, data, size);
1408 break;
1409 default:
1410 ret = -EOPNOTSUPP;
1411 break;
1412 }
1413
1414 if (!ret)
1415 dev_info(adap->pdev_dev,
1416 "loading %s successful, reload cxgb4 driver\n",
1417 flash_region_strings[region]);
1418 return ret;
1419}
1420
1421#define CXGB4_FW_SIG 0x4368656c
1422#define CXGB4_FW_SIG_OFFSET 0x160
1423
1424static int cxgb4_validate_fw_image(const u8 *data, u32 *size)
1425{
1426 struct cxgb4_fw_data *header;
1427
1428 header = (struct cxgb4_fw_data *)&data[CXGB4_FW_SIG_OFFSET];
1429 if (be32_to_cpu(header->signature) != CXGB4_FW_SIG)
1430 return -EINVAL;
1431
1432 if (size)
1433 *size = be16_to_cpu(((struct fw_hdr *)data)->len512) * 512;
1434
1435 return 0;
1436}
1437
1438static int cxgb4_validate_bootcfg_image(const u8 *data, u32 *size)
1439{
1440 struct cxgb4_bootcfg_data *header;
1441
1442 header = (struct cxgb4_bootcfg_data *)data;
1443 if (le16_to_cpu(header->signature) != BOOT_CFG_SIG)
1444 return -EINVAL;
1445
1446 return 0;
1447}
1448
1449static int cxgb4_validate_boot_image(const u8 *data, u32 *size)
1450{
1451 struct cxgb4_pci_exp_rom_header *exp_header;
1452 struct cxgb4_pcir_data *pcir_header;
1453 struct legacy_pci_rom_hdr *header;
1454 const u8 *cur_header = data;
1455 u16 pcir_offset;
1456
1457 exp_header = (struct cxgb4_pci_exp_rom_header *)data;
1458
1459 if (le16_to_cpu(exp_header->signature) != BOOT_SIGNATURE)
1460 return -EINVAL;
1461
1462 if (size) {
1463 do {
1464 header = (struct legacy_pci_rom_hdr *)cur_header;
1465 pcir_offset = le16_to_cpu(header->pcir_offset);
1466 pcir_header = (struct cxgb4_pcir_data *)(cur_header +
1467 pcir_offset);
1468
1469 *size += header->size512 * 512;
1470 cur_header += header->size512 * 512;
1471 } while (!(pcir_header->indicator & CXGB4_HDR_INDI));
1472 }
1473
1474 return 0;
1475}
1476
1477static int cxgb4_ethtool_get_flash_region(const u8 *data, u32 *size)
1478{
1479 if (!cxgb4_validate_fw_image(data, size))
1480 return CXGB4_ETHTOOL_FLASH_FW;
1481 if (!cxgb4_validate_boot_image(data, size))
1482 return CXGB4_ETHTOOL_FLASH_BOOT;
1483 if (!cxgb4_validate_phy_image(data, size))
1484 return CXGB4_ETHTOOL_FLASH_PHY;
1485 if (!cxgb4_validate_bootcfg_image(data, size))
1486 return CXGB4_ETHTOOL_FLASH_BOOTCFG;
1487
1488 return -EOPNOTSUPP;
1489}
1490
1491static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
1492{
1493 struct adapter *adap = netdev2adap(netdev);
1494 const struct firmware *fw;
1495 unsigned int master;
1496 u8 master_vld = 0;
1497 const u8 *fw_data;
1498 size_t fw_size;
1499 u32 size = 0;
1500 u32 pcie_fw;
1501 int region;
1502 int ret;
1503
1504 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
1505 master = PCIE_FW_MASTER_G(pcie_fw);
1506 if (pcie_fw & PCIE_FW_MASTER_VLD_F)
1507 master_vld = 1;
1508
1509 if (master_vld && (master != adap->pf)) {
1510 dev_warn(adap->pdev_dev,
1511 "cxgb4 driver needs to be loaded as MASTER to support FW flash\n");
1512 return -EOPNOTSUPP;
1513 }
1514
1515 ef->data[sizeof(ef->data) - 1] = '\0';
1516 ret = request_firmware(&fw, ef->data, adap->pdev_dev);
1517 if (ret < 0)
1518 return ret;
1519
1520 fw_data = fw->data;
1521 fw_size = fw->size;
1522 if (ef->region == ETHTOOL_FLASH_ALL_REGIONS) {
1523 while (fw_size > 0) {
1524 size = 0;
1525 region = cxgb4_ethtool_get_flash_region(fw_data, &size);
1526 if (region < 0 || !size) {
1527 ret = region;
1528 goto out_free_fw;
1529 }
1530
1531 ret = cxgb4_ethtool_flash_region(netdev, fw_data, size,
1532 region);
1533 if (ret)
1534 goto out_free_fw;
1535
1536 fw_data += size;
1537 fw_size -= size;
1538 }
1539 } else {
1540 ret = cxgb4_ethtool_flash_region(netdev, fw_data, fw_size,
1541 ef->region);
1542 }
1543
1544out_free_fw:
1545 release_firmware(fw);
1546 return ret;
1547}
1548
1549static int get_ts_info(struct net_device *dev, struct ethtool_ts_info *ts_info)
1550{
1551 struct port_info *pi = netdev_priv(dev);
1552 struct adapter *adapter = pi->adapter;
1553
1554 ts_info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1555 SOF_TIMESTAMPING_RX_SOFTWARE |
1556 SOF_TIMESTAMPING_SOFTWARE;
1557
1558 ts_info->so_timestamping |= SOF_TIMESTAMPING_RX_HARDWARE |
1559 SOF_TIMESTAMPING_TX_HARDWARE |
1560 SOF_TIMESTAMPING_RAW_HARDWARE;
1561
1562 ts_info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1563 (1 << HWTSTAMP_TX_ON);
1564
1565 ts_info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1566 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1567 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1568 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1569 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1570 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
1571
1572 if (adapter->ptp_clock)
1573 ts_info->phc_index = ptp_clock_index(adapter->ptp_clock);
1574 else
1575 ts_info->phc_index = -1;
1576
1577 return 0;
1578}
1579
1580static u32 get_rss_table_size(struct net_device *dev)
1581{
1582 const struct port_info *pi = netdev_priv(dev);
1583
1584 return pi->rss_size;
1585}
1586
1587static int get_rss_table(struct net_device *dev, u32 *p, u8 *key, u8 *hfunc)
1588{
1589 const struct port_info *pi = netdev_priv(dev);
1590 unsigned int n = pi->rss_size;
1591
1592 if (hfunc)
1593 *hfunc = ETH_RSS_HASH_TOP;
1594 if (!p)
1595 return 0;
1596 while (n--)
1597 p[n] = pi->rss[n];
1598 return 0;
1599}
1600
1601static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key,
1602 const u8 hfunc)
1603{
1604 unsigned int i;
1605 struct port_info *pi = netdev_priv(dev);
1606
1607
1608
1609
1610 if (key ||
1611 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
1612 return -EOPNOTSUPP;
1613 if (!p)
1614 return 0;
1615
1616
1617 if (pi->adapter->flags & CXGB4_FULL_INIT_DONE) {
1618 for (i = 0; i < pi->rss_size; i++)
1619 pi->rss[i] = p[i];
1620
1621 return cxgb4_write_rss(pi, pi->rss);
1622 }
1623
1624 return -EPERM;
1625}
1626
1627static struct filter_entry *cxgb4_get_filter_entry(struct adapter *adap,
1628 u32 ftid)
1629{
1630 struct tid_info *t = &adap->tids;
1631
1632 if (ftid >= t->hpftid_base && ftid < t->hpftid_base + t->nhpftids)
1633 return &t->hpftid_tab[ftid - t->hpftid_base];
1634
1635 if (ftid >= t->ftid_base && ftid < t->ftid_base + t->nftids)
1636 return &t->ftid_tab[ftid - t->ftid_base];
1637
1638 return lookup_tid(t, ftid);
1639}
1640
1641static void cxgb4_fill_filter_rule(struct ethtool_rx_flow_spec *fs,
1642 struct ch_filter_specification *dfs)
1643{
1644 switch (dfs->val.proto) {
1645 case IPPROTO_TCP:
1646 if (dfs->type)
1647 fs->flow_type = TCP_V6_FLOW;
1648 else
1649 fs->flow_type = TCP_V4_FLOW;
1650 break;
1651 case IPPROTO_UDP:
1652 if (dfs->type)
1653 fs->flow_type = UDP_V6_FLOW;
1654 else
1655 fs->flow_type = UDP_V4_FLOW;
1656 break;
1657 }
1658
1659 if (dfs->type) {
1660 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(dfs->val.fport);
1661 fs->m_u.tcp_ip6_spec.psrc = cpu_to_be16(dfs->mask.fport);
1662 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(dfs->val.lport);
1663 fs->m_u.tcp_ip6_spec.pdst = cpu_to_be16(dfs->mask.lport);
1664 memcpy(&fs->h_u.tcp_ip6_spec.ip6src, &dfs->val.fip[0],
1665 sizeof(fs->h_u.tcp_ip6_spec.ip6src));
1666 memcpy(&fs->m_u.tcp_ip6_spec.ip6src, &dfs->mask.fip[0],
1667 sizeof(fs->m_u.tcp_ip6_spec.ip6src));
1668 memcpy(&fs->h_u.tcp_ip6_spec.ip6dst, &dfs->val.lip[0],
1669 sizeof(fs->h_u.tcp_ip6_spec.ip6dst));
1670 memcpy(&fs->m_u.tcp_ip6_spec.ip6dst, &dfs->mask.lip[0],
1671 sizeof(fs->m_u.tcp_ip6_spec.ip6dst));
1672 fs->h_u.tcp_ip6_spec.tclass = dfs->val.tos;
1673 fs->m_u.tcp_ip6_spec.tclass = dfs->mask.tos;
1674 } else {
1675 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(dfs->val.fport);
1676 fs->m_u.tcp_ip4_spec.psrc = cpu_to_be16(dfs->mask.fport);
1677 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(dfs->val.lport);
1678 fs->m_u.tcp_ip4_spec.pdst = cpu_to_be16(dfs->mask.lport);
1679 memcpy(&fs->h_u.tcp_ip4_spec.ip4src, &dfs->val.fip[0],
1680 sizeof(fs->h_u.tcp_ip4_spec.ip4src));
1681 memcpy(&fs->m_u.tcp_ip4_spec.ip4src, &dfs->mask.fip[0],
1682 sizeof(fs->m_u.tcp_ip4_spec.ip4src));
1683 memcpy(&fs->h_u.tcp_ip4_spec.ip4dst, &dfs->val.lip[0],
1684 sizeof(fs->h_u.tcp_ip4_spec.ip4dst));
1685 memcpy(&fs->m_u.tcp_ip4_spec.ip4dst, &dfs->mask.lip[0],
1686 sizeof(fs->m_u.tcp_ip4_spec.ip4dst));
1687 fs->h_u.tcp_ip4_spec.tos = dfs->val.tos;
1688 fs->m_u.tcp_ip4_spec.tos = dfs->mask.tos;
1689 }
1690 fs->h_ext.vlan_tci = cpu_to_be16(dfs->val.ivlan);
1691 fs->m_ext.vlan_tci = cpu_to_be16(dfs->mask.ivlan);
1692 fs->flow_type |= FLOW_EXT;
1693
1694 if (dfs->action == FILTER_DROP)
1695 fs->ring_cookie = RX_CLS_FLOW_DISC;
1696 else
1697 fs->ring_cookie = dfs->iq;
1698}
1699
1700static int cxgb4_ntuple_get_filter(struct net_device *dev,
1701 struct ethtool_rxnfc *cmd,
1702 unsigned int loc)
1703{
1704 const struct port_info *pi = netdev_priv(dev);
1705 struct adapter *adap = netdev2adap(dev);
1706 struct filter_entry *f;
1707 int ftid;
1708
1709 if (!(adap->flags & CXGB4_FULL_INIT_DONE))
1710 return -EAGAIN;
1711
1712
1713 if (!adap->ethtool_filters)
1714 return -EOPNOTSUPP;
1715
1716 if (loc >= adap->ethtool_filters->nentries)
1717 return -ERANGE;
1718
1719 if (!test_bit(loc, adap->ethtool_filters->port[pi->port_id].bmap))
1720 return -ENOENT;
1721
1722 ftid = adap->ethtool_filters->port[pi->port_id].loc_array[loc];
1723
1724
1725 f = cxgb4_get_filter_entry(adap, ftid);
1726
1727 cxgb4_fill_filter_rule(&cmd->fs, &f->fs);
1728
1729 return 0;
1730}
1731
1732static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
1733 u32 *rules)
1734{
1735 const struct port_info *pi = netdev_priv(dev);
1736 struct adapter *adap = netdev2adap(dev);
1737 unsigned int count = 0, index = 0;
1738 int ret = 0;
1739
1740 switch (info->cmd) {
1741 case ETHTOOL_GRXFH: {
1742 unsigned int v = pi->rss_mode;
1743
1744 info->data = 0;
1745 switch (info->flow_type) {
1746 case TCP_V4_FLOW:
1747 if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F)
1748 info->data = RXH_IP_SRC | RXH_IP_DST |
1749 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1750 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
1751 info->data = RXH_IP_SRC | RXH_IP_DST;
1752 break;
1753 case UDP_V4_FLOW:
1754 if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) &&
1755 (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
1756 info->data = RXH_IP_SRC | RXH_IP_DST |
1757 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1758 else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
1759 info->data = RXH_IP_SRC | RXH_IP_DST;
1760 break;
1761 case SCTP_V4_FLOW:
1762 case AH_ESP_V4_FLOW:
1763 case IPV4_FLOW:
1764 if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F)
1765 info->data = RXH_IP_SRC | RXH_IP_DST;
1766 break;
1767 case TCP_V6_FLOW:
1768 if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F)
1769 info->data = RXH_IP_SRC | RXH_IP_DST |
1770 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1771 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
1772 info->data = RXH_IP_SRC | RXH_IP_DST;
1773 break;
1774 case UDP_V6_FLOW:
1775 if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) &&
1776 (v & FW_RSS_VI_CONFIG_CMD_UDPEN_F))
1777 info->data = RXH_IP_SRC | RXH_IP_DST |
1778 RXH_L4_B_0_1 | RXH_L4_B_2_3;
1779 else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
1780 info->data = RXH_IP_SRC | RXH_IP_DST;
1781 break;
1782 case SCTP_V6_FLOW:
1783 case AH_ESP_V6_FLOW:
1784 case IPV6_FLOW:
1785 if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F)
1786 info->data = RXH_IP_SRC | RXH_IP_DST;
1787 break;
1788 }
1789 return 0;
1790 }
1791 case ETHTOOL_GRXRINGS:
1792 info->data = pi->nqsets;
1793 return 0;
1794 case ETHTOOL_GRXCLSRLCNT:
1795 info->rule_cnt =
1796 adap->ethtool_filters->port[pi->port_id].in_use;
1797 return 0;
1798 case ETHTOOL_GRXCLSRULE:
1799 return cxgb4_ntuple_get_filter(dev, info, info->fs.location);
1800 case ETHTOOL_GRXCLSRLALL:
1801 info->data = adap->ethtool_filters->nentries;
1802 while (count < info->rule_cnt) {
1803 ret = cxgb4_ntuple_get_filter(dev, info, index);
1804 if (!ret)
1805 rules[count++] = index;
1806 index++;
1807 }
1808 return 0;
1809 }
1810
1811 return -EOPNOTSUPP;
1812}
1813
1814static int cxgb4_ntuple_del_filter(struct net_device *dev,
1815 struct ethtool_rxnfc *cmd)
1816{
1817 struct cxgb4_ethtool_filter_info *filter_info;
1818 struct adapter *adapter = netdev2adap(dev);
1819 struct port_info *pi = netdev_priv(dev);
1820 struct filter_entry *f;
1821 u32 filter_id;
1822 int ret;
1823
1824 if (!(adapter->flags & CXGB4_FULL_INIT_DONE))
1825 return -EAGAIN;
1826
1827 if (!adapter->ethtool_filters)
1828 return -EOPNOTSUPP;
1829
1830 if (cmd->fs.location >= adapter->ethtool_filters->nentries) {
1831 dev_err(adapter->pdev_dev,
1832 "Location must be < %u",
1833 adapter->ethtool_filters->nentries);
1834 return -ERANGE;
1835 }
1836
1837 filter_info = &adapter->ethtool_filters->port[pi->port_id];
1838
1839 if (!test_bit(cmd->fs.location, filter_info->bmap))
1840 return -ENOENT;
1841
1842 filter_id = filter_info->loc_array[cmd->fs.location];
1843 f = cxgb4_get_filter_entry(adapter, filter_id);
1844
1845 if (f->fs.prio)
1846 filter_id -= adapter->tids.hpftid_base;
1847 else if (!f->fs.hash)
1848 filter_id -= (adapter->tids.ftid_base - adapter->tids.nhpftids);
1849
1850 ret = cxgb4_flow_rule_destroy(dev, f->fs.tc_prio, &f->fs, filter_id);
1851 if (ret)
1852 goto err;
1853
1854 clear_bit(cmd->fs.location, filter_info->bmap);
1855 filter_info->in_use--;
1856
1857err:
1858 return ret;
1859}
1860
1861
1862static int cxgb4_ntuple_set_filter(struct net_device *netdev,
1863 struct ethtool_rxnfc *cmd)
1864{
1865 struct ethtool_rx_flow_spec_input input = {};
1866 struct cxgb4_ethtool_filter_info *filter_info;
1867 struct adapter *adapter = netdev2adap(netdev);
1868 struct port_info *pi = netdev_priv(netdev);
1869 struct ch_filter_specification fs;
1870 struct ethtool_rx_flow_rule *flow;
1871 u32 tid;
1872 int ret;
1873
1874 if (!(adapter->flags & CXGB4_FULL_INIT_DONE))
1875 return -EAGAIN;
1876
1877 if (!adapter->ethtool_filters)
1878 return -EOPNOTSUPP;
1879
1880 if (cmd->fs.location >= adapter->ethtool_filters->nentries) {
1881 dev_err(adapter->pdev_dev,
1882 "Location must be < %u",
1883 adapter->ethtool_filters->nentries);
1884 return -ERANGE;
1885 }
1886
1887 if (test_bit(cmd->fs.location,
1888 adapter->ethtool_filters->port[pi->port_id].bmap))
1889 return -EEXIST;
1890
1891 memset(&fs, 0, sizeof(fs));
1892
1893 input.fs = &cmd->fs;
1894 flow = ethtool_rx_flow_rule_create(&input);
1895 if (IS_ERR(flow)) {
1896 ret = PTR_ERR(flow);
1897 goto exit;
1898 }
1899
1900 fs.hitcnts = 1;
1901
1902 ret = cxgb4_flow_rule_replace(netdev, flow->rule, cmd->fs.location,
1903 NULL, &fs, &tid);
1904 if (ret)
1905 goto free;
1906
1907 filter_info = &adapter->ethtool_filters->port[pi->port_id];
1908
1909 if (fs.prio)
1910 tid += adapter->tids.hpftid_base;
1911 else if (!fs.hash)
1912 tid += (adapter->tids.ftid_base - adapter->tids.nhpftids);
1913
1914 filter_info->loc_array[cmd->fs.location] = tid;
1915 set_bit(cmd->fs.location, filter_info->bmap);
1916 filter_info->in_use++;
1917
1918free:
1919 ethtool_rx_flow_rule_destroy(flow);
1920exit:
1921 return ret;
1922}
1923
1924static int set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1925{
1926 int ret = -EOPNOTSUPP;
1927
1928 switch (cmd->cmd) {
1929 case ETHTOOL_SRXCLSRLINS:
1930 ret = cxgb4_ntuple_set_filter(dev, cmd);
1931 break;
1932 case ETHTOOL_SRXCLSRLDEL:
1933 ret = cxgb4_ntuple_del_filter(dev, cmd);
1934 break;
1935 default:
1936 break;
1937 }
1938
1939 return ret;
1940}
1941
1942static int set_dump(struct net_device *dev, struct ethtool_dump *eth_dump)
1943{
1944 struct adapter *adapter = netdev2adap(dev);
1945 u32 len = 0;
1946
1947 len = sizeof(struct cudbg_hdr) +
1948 sizeof(struct cudbg_entity_hdr) * CUDBG_MAX_ENTITY;
1949 len += cxgb4_get_dump_length(adapter, eth_dump->flag);
1950
1951 adapter->eth_dump.flag = eth_dump->flag;
1952 adapter->eth_dump.len = len;
1953 return 0;
1954}
1955
1956static int get_dump_flag(struct net_device *dev, struct ethtool_dump *eth_dump)
1957{
1958 struct adapter *adapter = netdev2adap(dev);
1959
1960 eth_dump->flag = adapter->eth_dump.flag;
1961 eth_dump->len = adapter->eth_dump.len;
1962 eth_dump->version = adapter->eth_dump.version;
1963 return 0;
1964}
1965
1966static int get_dump_data(struct net_device *dev, struct ethtool_dump *eth_dump,
1967 void *buf)
1968{
1969 struct adapter *adapter = netdev2adap(dev);
1970 u32 len = 0;
1971 int ret = 0;
1972
1973 if (adapter->eth_dump.flag == CXGB4_ETH_DUMP_NONE)
1974 return -ENOENT;
1975
1976 len = sizeof(struct cudbg_hdr) +
1977 sizeof(struct cudbg_entity_hdr) * CUDBG_MAX_ENTITY;
1978 len += cxgb4_get_dump_length(adapter, adapter->eth_dump.flag);
1979 if (eth_dump->len < len)
1980 return -ENOMEM;
1981
1982 ret = cxgb4_cudbg_collect(adapter, buf, &len, adapter->eth_dump.flag);
1983 if (ret)
1984 return ret;
1985
1986 eth_dump->flag = adapter->eth_dump.flag;
1987 eth_dump->len = len;
1988 eth_dump->version = adapter->eth_dump.version;
1989 return 0;
1990}
1991
1992static int cxgb4_get_module_info(struct net_device *dev,
1993 struct ethtool_modinfo *modinfo)
1994{
1995 struct port_info *pi = netdev_priv(dev);
1996 u8 sff8472_comp, sff_diag_type, sff_rev;
1997 struct adapter *adapter = pi->adapter;
1998 int ret;
1999
2000 if (!t4_is_inserted_mod_type(pi->mod_type))
2001 return -EINVAL;
2002
2003 switch (pi->port_type) {
2004 case FW_PORT_TYPE_SFP:
2005 case FW_PORT_TYPE_QSA:
2006 case FW_PORT_TYPE_SFP28:
2007 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
2008 I2C_DEV_ADDR_A0, SFF_8472_COMP_ADDR,
2009 SFF_8472_COMP_LEN, &sff8472_comp);
2010 if (ret)
2011 return ret;
2012 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
2013 I2C_DEV_ADDR_A0, SFP_DIAG_TYPE_ADDR,
2014 SFP_DIAG_TYPE_LEN, &sff_diag_type);
2015 if (ret)
2016 return ret;
2017
2018 if (!sff8472_comp || (sff_diag_type & 4)) {
2019 modinfo->type = ETH_MODULE_SFF_8079;
2020 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2021 } else {
2022 modinfo->type = ETH_MODULE_SFF_8472;
2023 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2024 }
2025 break;
2026
2027 case FW_PORT_TYPE_QSFP:
2028 case FW_PORT_TYPE_QSFP_10G:
2029 case FW_PORT_TYPE_CR_QSFP:
2030 case FW_PORT_TYPE_CR2_QSFP:
2031 case FW_PORT_TYPE_CR4_QSFP:
2032 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
2033 I2C_DEV_ADDR_A0, SFF_REV_ADDR,
2034 SFF_REV_LEN, &sff_rev);
2035
2036
2037
2038 if (ret)
2039 return ret;
2040 if (sff_rev >= 0x3) {
2041 modinfo->type = ETH_MODULE_SFF_8636;
2042 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2043 } else {
2044 modinfo->type = ETH_MODULE_SFF_8436;
2045 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2046 }
2047 break;
2048
2049 default:
2050 return -EINVAL;
2051 }
2052
2053 return 0;
2054}
2055
2056static int cxgb4_get_module_eeprom(struct net_device *dev,
2057 struct ethtool_eeprom *eprom, u8 *data)
2058{
2059 int ret = 0, offset = eprom->offset, len = eprom->len;
2060 struct port_info *pi = netdev_priv(dev);
2061 struct adapter *adapter = pi->adapter;
2062
2063 memset(data, 0, eprom->len);
2064 if (offset + len <= I2C_PAGE_SIZE)
2065 return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
2066 I2C_DEV_ADDR_A0, offset, len, data);
2067
2068
2069 if (offset <= I2C_PAGE_SIZE) {
2070
2071 len = I2C_PAGE_SIZE - offset;
2072 ret = t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan,
2073 I2C_DEV_ADDR_A0, offset, len, data);
2074 if (ret)
2075 return ret;
2076 offset = I2C_PAGE_SIZE;
2077
2078
2079
2080 len = eprom->len - len;
2081 }
2082
2083 return t4_i2c_rd(adapter, adapter->mbox, pi->tx_chan, I2C_DEV_ADDR_A2,
2084 offset, len, &data[eprom->len - len]);
2085}
2086
2087static u32 cxgb4_get_priv_flags(struct net_device *netdev)
2088{
2089 struct port_info *pi = netdev_priv(netdev);
2090 struct adapter *adapter = pi->adapter;
2091
2092 return (adapter->eth_flags | pi->eth_flags);
2093}
2094
2095
2096
2097
2098
2099
2100
2101static inline void set_flags(u32 *cur_flags, u32 new_flags, u32 flags)
2102{
2103 *cur_flags = (*cur_flags & ~flags) | (new_flags & flags);
2104}
2105
2106static int cxgb4_set_priv_flags(struct net_device *netdev, u32 flags)
2107{
2108 struct port_info *pi = netdev_priv(netdev);
2109 struct adapter *adapter = pi->adapter;
2110
2111 set_flags(&adapter->eth_flags, flags, PRIV_FLAGS_ADAP);
2112 set_flags(&pi->eth_flags, flags, PRIV_FLAGS_PORT);
2113
2114 return 0;
2115}
2116
2117static void cxgb4_lb_test(struct net_device *netdev, u64 *lb_status)
2118{
2119 int dev_state = netif_running(netdev);
2120
2121 if (dev_state) {
2122 netif_tx_stop_all_queues(netdev);
2123 netif_carrier_off(netdev);
2124 }
2125
2126 *lb_status = cxgb4_selftest_lb_pkt(netdev);
2127
2128 if (dev_state) {
2129 netif_tx_start_all_queues(netdev);
2130 netif_carrier_on(netdev);
2131 }
2132}
2133
2134static void cxgb4_self_test(struct net_device *netdev,
2135 struct ethtool_test *eth_test, u64 *data)
2136{
2137 struct port_info *pi = netdev_priv(netdev);
2138 struct adapter *adap = pi->adapter;
2139
2140 memset(data, 0, sizeof(u64) * CXGB4_ETHTOOL_MAX_TEST);
2141
2142 if (!(adap->flags & CXGB4_FULL_INIT_DONE) ||
2143 !(adap->flags & CXGB4_FW_OK)) {
2144 eth_test->flags |= ETH_TEST_FL_FAILED;
2145 return;
2146 }
2147
2148 if (eth_test->flags & ETH_TEST_FL_OFFLINE)
2149 cxgb4_lb_test(netdev, &data[CXGB4_ETHTOOL_LB_TEST]);
2150
2151 if (data[CXGB4_ETHTOOL_LB_TEST])
2152 eth_test->flags |= ETH_TEST_FL_FAILED;
2153}
2154
2155static const struct ethtool_ops cxgb_ethtool_ops = {
2156 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2157 ETHTOOL_COALESCE_RX_MAX_FRAMES |
2158 ETHTOOL_COALESCE_TX_USECS_IRQ |
2159 ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
2160 .get_link_ksettings = get_link_ksettings,
2161 .set_link_ksettings = set_link_ksettings,
2162 .get_fecparam = get_fecparam,
2163 .set_fecparam = set_fecparam,
2164 .get_drvinfo = get_drvinfo,
2165 .get_msglevel = get_msglevel,
2166 .set_msglevel = set_msglevel,
2167 .get_ringparam = get_sge_param,
2168 .set_ringparam = set_sge_param,
2169 .get_coalesce = get_coalesce,
2170 .set_coalesce = set_coalesce,
2171 .get_eeprom_len = get_eeprom_len,
2172 .get_eeprom = get_eeprom,
2173 .set_eeprom = set_eeprom,
2174 .get_pauseparam = get_pauseparam,
2175 .set_pauseparam = set_pauseparam,
2176 .get_link = ethtool_op_get_link,
2177 .get_strings = get_strings,
2178 .set_phys_id = identify_port,
2179 .nway_reset = restart_autoneg,
2180 .get_sset_count = get_sset_count,
2181 .get_ethtool_stats = get_stats,
2182 .get_regs_len = get_regs_len,
2183 .get_regs = get_regs,
2184 .get_rxnfc = get_rxnfc,
2185 .set_rxnfc = set_rxnfc,
2186 .get_rxfh_indir_size = get_rss_table_size,
2187 .get_rxfh = get_rss_table,
2188 .set_rxfh = set_rss_table,
2189 .self_test = cxgb4_self_test,
2190 .flash_device = set_flash,
2191 .get_ts_info = get_ts_info,
2192 .set_dump = set_dump,
2193 .get_dump_flag = get_dump_flag,
2194 .get_dump_data = get_dump_data,
2195 .get_module_info = cxgb4_get_module_info,
2196 .get_module_eeprom = cxgb4_get_module_eeprom,
2197 .get_priv_flags = cxgb4_get_priv_flags,
2198 .set_priv_flags = cxgb4_set_priv_flags,
2199};
2200
2201void cxgb4_cleanup_ethtool_filters(struct adapter *adap)
2202{
2203 struct cxgb4_ethtool_filter_info *eth_filter_info;
2204 u8 i;
2205
2206 if (!adap->ethtool_filters)
2207 return;
2208
2209 eth_filter_info = adap->ethtool_filters->port;
2210
2211 if (eth_filter_info) {
2212 for (i = 0; i < adap->params.nports; i++) {
2213 kvfree(eth_filter_info[i].loc_array);
2214 kfree(eth_filter_info[i].bmap);
2215 }
2216 kfree(eth_filter_info);
2217 }
2218
2219 kfree(adap->ethtool_filters);
2220}
2221
2222int cxgb4_init_ethtool_filters(struct adapter *adap)
2223{
2224 struct cxgb4_ethtool_filter_info *eth_filter_info;
2225 struct cxgb4_ethtool_filter *eth_filter;
2226 struct tid_info *tids = &adap->tids;
2227 u32 nentries, i;
2228 int ret;
2229
2230 eth_filter = kzalloc(sizeof(*eth_filter), GFP_KERNEL);
2231 if (!eth_filter)
2232 return -ENOMEM;
2233
2234 eth_filter_info = kcalloc(adap->params.nports,
2235 sizeof(*eth_filter_info),
2236 GFP_KERNEL);
2237 if (!eth_filter_info) {
2238 ret = -ENOMEM;
2239 goto free_eth_filter;
2240 }
2241
2242 eth_filter->port = eth_filter_info;
2243
2244 nentries = tids->nhpftids + tids->nftids;
2245 if (is_hashfilter(adap))
2246 nentries += tids->nhash +
2247 (adap->tids.stid_base - adap->tids.tid_base);
2248 eth_filter->nentries = nentries;
2249
2250 for (i = 0; i < adap->params.nports; i++) {
2251 eth_filter->port[i].loc_array = kvzalloc(nentries, GFP_KERNEL);
2252 if (!eth_filter->port[i].loc_array) {
2253 ret = -ENOMEM;
2254 goto free_eth_finfo;
2255 }
2256
2257 eth_filter->port[i].bmap = kcalloc(BITS_TO_LONGS(nentries),
2258 sizeof(unsigned long),
2259 GFP_KERNEL);
2260 if (!eth_filter->port[i].bmap) {
2261 ret = -ENOMEM;
2262 goto free_eth_finfo;
2263 }
2264 }
2265
2266 adap->ethtool_filters = eth_filter;
2267 return 0;
2268
2269free_eth_finfo:
2270 while (i-- > 0) {
2271 kfree(eth_filter->port[i].bmap);
2272 kvfree(eth_filter->port[i].loc_array);
2273 }
2274 kfree(eth_filter_info);
2275
2276free_eth_filter:
2277 kfree(eth_filter);
2278
2279 return ret;
2280}
2281
2282void cxgb4_set_ethtool_ops(struct net_device *netdev)
2283{
2284 netdev->ethtool_ops = &cxgb_ethtool_ops;
2285}
2286
