1
2
3
4#include <asm/unaligned.h>
5#include <linux/mdio.h>
6#include <linux/module.h>
7#include <linux/fsl/enetc_mdio.h>
8#include <linux/of_platform.h>
9#include <linux/of_mdio.h>
10#include <linux/of_net.h>
11#include "enetc_ierb.h"
12#include "enetc_pf.h"
13
14#define ENETC_DRV_NAME_STR "ENETC PF driver"
15
16static void enetc_pf_get_primary_mac_addr(struct enetc_hw *hw, int si, u8 *addr)
17{
18 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si));
19 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si));
20
21 put_unaligned_le32(upper, addr);
22 put_unaligned_le16(lower, addr + 4);
23}
24
25static void enetc_pf_set_primary_mac_addr(struct enetc_hw *hw, int si,
26 const u8 *addr)
27{
28 u32 upper = get_unaligned_le32(addr);
29 u16 lower = get_unaligned_le16(addr + 4);
30
31 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si));
32 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si));
33}
34
35static int enetc_pf_set_mac_addr(struct net_device *ndev, void *addr)
36{
37 struct enetc_ndev_priv *priv = netdev_priv(ndev);
38 struct sockaddr *saddr = addr;
39
40 if (!is_valid_ether_addr(saddr->sa_data))
41 return -EADDRNOTAVAIL;
42
43 memcpy(ndev->dev_addr, saddr->sa_data, ndev->addr_len);
44 enetc_pf_set_primary_mac_addr(&priv->si->hw, 0, saddr->sa_data);
45
46 return 0;
47}
48
49static void enetc_set_vlan_promisc(struct enetc_hw *hw, char si_map)
50{
51 u32 val = enetc_port_rd(hw, ENETC_PSIPVMR);
52
53 val &= ~ENETC_PSIPVMR_SET_VP(ENETC_VLAN_PROMISC_MAP_ALL);
54 enetc_port_wr(hw, ENETC_PSIPVMR, ENETC_PSIPVMR_SET_VP(si_map) | val);
55}
56
57static void enetc_enable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
58{
59 pf->vlan_promisc_simap |= BIT(si_idx);
60 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
61}
62
63static void enetc_disable_si_vlan_promisc(struct enetc_pf *pf, int si_idx)
64{
65 pf->vlan_promisc_simap &= ~BIT(si_idx);
66 enetc_set_vlan_promisc(&pf->si->hw, pf->vlan_promisc_simap);
67}
68
69static void enetc_set_isol_vlan(struct enetc_hw *hw, int si, u16 vlan, u8 qos)
70{
71 u32 val = 0;
72
73 if (vlan)
74 val = ENETC_PSIVLAN_EN | ENETC_PSIVLAN_SET_QOS(qos) | vlan;
75
76 enetc_port_wr(hw, ENETC_PSIVLANR(si), val);
77}
78
79static int enetc_mac_addr_hash_idx(const u8 *addr)
80{
81 u64 fold = __swab64(ether_addr_to_u64(addr)) >> 16;
82 u64 mask = 0;
83 int res = 0;
84 int i;
85
86 for (i = 0; i < 8; i++)
87 mask |= BIT_ULL(i * 6);
88
89 for (i = 0; i < 6; i++)
90 res |= (hweight64(fold & (mask << i)) & 0x1) << i;
91
92 return res;
93}
94
95static void enetc_reset_mac_addr_filter(struct enetc_mac_filter *filter)
96{
97 filter->mac_addr_cnt = 0;
98
99 bitmap_zero(filter->mac_hash_table,
100 ENETC_MADDR_HASH_TBL_SZ);
101}
102
103static void enetc_add_mac_addr_em_filter(struct enetc_mac_filter *filter,
104 const unsigned char *addr)
105{
106
107 ether_addr_copy(filter->mac_addr, addr);
108 filter->mac_addr_cnt++;
109}
110
111static void enetc_add_mac_addr_ht_filter(struct enetc_mac_filter *filter,
112 const unsigned char *addr)
113{
114 int idx = enetc_mac_addr_hash_idx(addr);
115
116
117 __set_bit(idx, filter->mac_hash_table);
118 filter->mac_addr_cnt++;
119}
120
121static void enetc_clear_mac_ht_flt(struct enetc_si *si, int si_idx, int type)
122{
123 bool err = si->errata & ENETC_ERR_UCMCSWP;
124
125 if (type == UC) {
126 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err), 0);
127 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx), 0);
128 } else {
129 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err), 0);
130 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx), 0);
131 }
132}
133
134static void enetc_set_mac_ht_flt(struct enetc_si *si, int si_idx, int type,
135 unsigned long hash)
136{
137 bool err = si->errata & ENETC_ERR_UCMCSWP;
138
139 if (type == UC) {
140 enetc_port_wr(&si->hw, ENETC_PSIUMHFR0(si_idx, err),
141 lower_32_bits(hash));
142 enetc_port_wr(&si->hw, ENETC_PSIUMHFR1(si_idx),
143 upper_32_bits(hash));
144 } else {
145 enetc_port_wr(&si->hw, ENETC_PSIMMHFR0(si_idx, err),
146 lower_32_bits(hash));
147 enetc_port_wr(&si->hw, ENETC_PSIMMHFR1(si_idx),
148 upper_32_bits(hash));
149 }
150}
151
152static void enetc_sync_mac_filters(struct enetc_pf *pf)
153{
154 struct enetc_mac_filter *f = pf->mac_filter;
155 struct enetc_si *si = pf->si;
156 int i, pos;
157
158 pos = EMETC_MAC_ADDR_FILT_RES;
159
160 for (i = 0; i < MADDR_TYPE; i++, f++) {
161 bool em = (f->mac_addr_cnt == 1) && (i == UC);
162 bool clear = !f->mac_addr_cnt;
163
164 if (clear) {
165 if (i == UC)
166 enetc_clear_mac_flt_entry(si, pos);
167
168 enetc_clear_mac_ht_flt(si, 0, i);
169 continue;
170 }
171
172
173 if (em) {
174 int err;
175
176 enetc_clear_mac_ht_flt(si, 0, UC);
177
178 err = enetc_set_mac_flt_entry(si, pos, f->mac_addr,
179 BIT(0));
180 if (!err)
181 continue;
182
183
184 dev_warn(&si->pdev->dev, "fallback to HT filt (%d)\n",
185 err);
186 }
187
188
189 if (i == UC)
190 enetc_clear_mac_flt_entry(si, pos);
191
192 enetc_set_mac_ht_flt(si, 0, i, *f->mac_hash_table);
193 }
194}
195
196static void enetc_pf_set_rx_mode(struct net_device *ndev)
197{
198 struct enetc_ndev_priv *priv = netdev_priv(ndev);
199 struct enetc_pf *pf = enetc_si_priv(priv->si);
200 struct enetc_hw *hw = &priv->si->hw;
201 bool uprom = false, mprom = false;
202 struct enetc_mac_filter *filter;
203 struct netdev_hw_addr *ha;
204 u32 psipmr = 0;
205 bool em;
206
207 if (ndev->flags & IFF_PROMISC) {
208
209 psipmr = ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0);
210 uprom = true;
211 mprom = true;
212 } else if (ndev->flags & IFF_ALLMULTI) {
213
214 psipmr = ENETC_PSIPMR_SET_MP(0);
215 mprom = true;
216 }
217
218
219 if (!uprom) {
220
221 filter = &pf->mac_filter[UC];
222 enetc_reset_mac_addr_filter(filter);
223
224 em = (netdev_uc_count(ndev) == 1);
225 netdev_for_each_uc_addr(ha, ndev) {
226 if (em) {
227 enetc_add_mac_addr_em_filter(filter, ha->addr);
228 break;
229 }
230
231 enetc_add_mac_addr_ht_filter(filter, ha->addr);
232 }
233 }
234
235 if (!mprom) {
236
237 filter = &pf->mac_filter[MC];
238 enetc_reset_mac_addr_filter(filter);
239
240 netdev_for_each_mc_addr(ha, ndev) {
241 if (!is_multicast_ether_addr(ha->addr))
242 continue;
243
244 enetc_add_mac_addr_ht_filter(filter, ha->addr);
245 }
246 }
247
248 if (!uprom || !mprom)
249
250 enetc_sync_mac_filters(pf);
251
252 psipmr |= enetc_port_rd(hw, ENETC_PSIPMR) &
253 ~(ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0));
254 enetc_port_wr(hw, ENETC_PSIPMR, psipmr);
255}
256
257static void enetc_set_vlan_ht_filter(struct enetc_hw *hw, int si_idx,
258 unsigned long hash)
259{
260 enetc_port_wr(hw, ENETC_PSIVHFR0(si_idx), lower_32_bits(hash));
261 enetc_port_wr(hw, ENETC_PSIVHFR1(si_idx), upper_32_bits(hash));
262}
263
264static int enetc_vid_hash_idx(unsigned int vid)
265{
266 int res = 0;
267 int i;
268
269 for (i = 0; i < 6; i++)
270 res |= (hweight8(vid & (BIT(i) | BIT(i + 6))) & 0x1) << i;
271
272 return res;
273}
274
275static void enetc_sync_vlan_ht_filter(struct enetc_pf *pf, bool rehash)
276{
277 int i;
278
279 if (rehash) {
280 bitmap_zero(pf->vlan_ht_filter, ENETC_VLAN_HT_SIZE);
281
282 for_each_set_bit(i, pf->active_vlans, VLAN_N_VID) {
283 int hidx = enetc_vid_hash_idx(i);
284
285 __set_bit(hidx, pf->vlan_ht_filter);
286 }
287 }
288
289 enetc_set_vlan_ht_filter(&pf->si->hw, 0, *pf->vlan_ht_filter);
290}
291
292static int enetc_vlan_rx_add_vid(struct net_device *ndev, __be16 prot, u16 vid)
293{
294 struct enetc_ndev_priv *priv = netdev_priv(ndev);
295 struct enetc_pf *pf = enetc_si_priv(priv->si);
296 int idx;
297
298 __set_bit(vid, pf->active_vlans);
299
300 idx = enetc_vid_hash_idx(vid);
301 if (!__test_and_set_bit(idx, pf->vlan_ht_filter))
302 enetc_sync_vlan_ht_filter(pf, false);
303
304 return 0;
305}
306
307static int enetc_vlan_rx_del_vid(struct net_device *ndev, __be16 prot, u16 vid)
308{
309 struct enetc_ndev_priv *priv = netdev_priv(ndev);
310 struct enetc_pf *pf = enetc_si_priv(priv->si);
311
312 __clear_bit(vid, pf->active_vlans);
313 enetc_sync_vlan_ht_filter(pf, true);
314
315 return 0;
316}
317
318static void enetc_set_loopback(struct net_device *ndev, bool en)
319{
320 struct enetc_ndev_priv *priv = netdev_priv(ndev);
321 struct enetc_hw *hw = &priv->si->hw;
322 u32 reg;
323
324 reg = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
325 if (reg & ENETC_PM0_IFM_RG) {
326
327 reg = (reg & ~ENETC_PM0_IFM_RLP) |
328 (en ? ENETC_PM0_IFM_RLP : 0);
329 enetc_port_wr(hw, ENETC_PM0_IF_MODE, reg);
330 } else {
331
332 reg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
333 reg = (reg & ~ENETC_PM0_CMD_XGLP) |
334 (en ? ENETC_PM0_CMD_XGLP : 0);
335 reg = (reg & ~ENETC_PM0_CMD_PHY_TX_EN) |
336 (en ? ENETC_PM0_CMD_PHY_TX_EN : 0);
337 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, reg);
338 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, reg);
339 }
340}
341
342static int enetc_pf_set_vf_mac(struct net_device *ndev, int vf, u8 *mac)
343{
344 struct enetc_ndev_priv *priv = netdev_priv(ndev);
345 struct enetc_pf *pf = enetc_si_priv(priv->si);
346 struct enetc_vf_state *vf_state;
347
348 if (vf >= pf->total_vfs)
349 return -EINVAL;
350
351 if (!is_valid_ether_addr(mac))
352 return -EADDRNOTAVAIL;
353
354 vf_state = &pf->vf_state[vf];
355 vf_state->flags |= ENETC_VF_FLAG_PF_SET_MAC;
356 enetc_pf_set_primary_mac_addr(&priv->si->hw, vf + 1, mac);
357 return 0;
358}
359
360static int enetc_pf_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan,
361 u8 qos, __be16 proto)
362{
363 struct enetc_ndev_priv *priv = netdev_priv(ndev);
364 struct enetc_pf *pf = enetc_si_priv(priv->si);
365
366 if (priv->si->errata & ENETC_ERR_VLAN_ISOL)
367 return -EOPNOTSUPP;
368
369 if (vf >= pf->total_vfs)
370 return -EINVAL;
371
372 if (proto != htons(ETH_P_8021Q))
373
374 return -EPROTONOSUPPORT;
375
376 enetc_set_isol_vlan(&priv->si->hw, vf + 1, vlan, qos);
377 return 0;
378}
379
380static int enetc_pf_set_vf_spoofchk(struct net_device *ndev, int vf, bool en)
381{
382 struct enetc_ndev_priv *priv = netdev_priv(ndev);
383 struct enetc_pf *pf = enetc_si_priv(priv->si);
384 u32 cfgr;
385
386 if (vf >= pf->total_vfs)
387 return -EINVAL;
388
389 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1));
390 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0);
391 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr);
392
393 return 0;
394}
395
396static int enetc_setup_mac_address(struct device_node *np, struct enetc_pf *pf,
397 int si)
398{
399 struct device *dev = &pf->si->pdev->dev;
400 struct enetc_hw *hw = &pf->si->hw;
401 u8 mac_addr[ETH_ALEN] = { 0 };
402 int err;
403
404
405 if (np) {
406 err = of_get_mac_address(np, mac_addr);
407 if (err == -EPROBE_DEFER)
408 return err;
409 }
410
411
412 if (is_zero_ether_addr(mac_addr))
413 enetc_pf_get_primary_mac_addr(hw, si, mac_addr);
414
415
416 if (is_zero_ether_addr(mac_addr)) {
417 eth_random_addr(mac_addr);
418 dev_info(dev, "no MAC address specified for SI%d, using %pM\n",
419 si, mac_addr);
420 }
421
422 enetc_pf_set_primary_mac_addr(hw, si, mac_addr);
423
424 return 0;
425}
426
427static int enetc_setup_mac_addresses(struct device_node *np,
428 struct enetc_pf *pf)
429{
430 int err, i;
431
432
433 err = enetc_setup_mac_address(np, pf, 0);
434 if (err)
435 return err;
436
437 for (i = 0; i < pf->total_vfs; i++) {
438 err = enetc_setup_mac_address(NULL, pf, i + 1);
439 if (err)
440 return err;
441 }
442
443 return 0;
444}
445
446static void enetc_port_assign_rfs_entries(struct enetc_si *si)
447{
448 struct enetc_pf *pf = enetc_si_priv(si);
449 struct enetc_hw *hw = &si->hw;
450 int num_entries, vf_entries, i;
451 u32 val;
452
453
454 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
455 num_entries = ENETC_PRFSCAPR_GET_NUM_RFS(val);
456 vf_entries = num_entries / (pf->total_vfs + 1);
457
458 for (i = 0; i < pf->total_vfs; i++)
459 enetc_port_wr(hw, ENETC_PSIRFSCFGR(i + 1), vf_entries);
460 enetc_port_wr(hw, ENETC_PSIRFSCFGR(0),
461 num_entries - vf_entries * pf->total_vfs);
462
463
464 enetc_port_wr(hw, ENETC_PRFSMR, ENETC_PRFSMR_RFSE);
465}
466
467static void enetc_port_si_configure(struct enetc_si *si)
468{
469 struct enetc_pf *pf = enetc_si_priv(si);
470 struct enetc_hw *hw = &si->hw;
471 int num_rings, i;
472 u32 val;
473
474 val = enetc_port_rd(hw, ENETC_PCAPR0);
475 num_rings = min(ENETC_PCAPR0_RXBDR(val), ENETC_PCAPR0_TXBDR(val));
476
477 val = ENETC_PSICFGR0_SET_TXBDR(ENETC_PF_NUM_RINGS);
478 val |= ENETC_PSICFGR0_SET_RXBDR(ENETC_PF_NUM_RINGS);
479
480 if (unlikely(num_rings < ENETC_PF_NUM_RINGS)) {
481 val = ENETC_PSICFGR0_SET_TXBDR(num_rings);
482 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
483
484 dev_warn(&si->pdev->dev, "Found %d rings, expected %d!\n",
485 num_rings, ENETC_PF_NUM_RINGS);
486
487 num_rings = 0;
488 }
489
490
491 val |= ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
492
493 enetc_port_wr(hw, ENETC_PSICFGR0(0), val);
494
495 if (num_rings)
496 num_rings -= ENETC_PF_NUM_RINGS;
497
498
499 val = ENETC_PSICFGR0_SIVC(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
500 val |= ENETC_PSICFGR0_VTE | ENETC_PSICFGR0_SIVIE;
501
502 if (num_rings) {
503 num_rings /= pf->total_vfs;
504 val |= ENETC_PSICFGR0_SET_TXBDR(num_rings);
505 val |= ENETC_PSICFGR0_SET_RXBDR(num_rings);
506 }
507
508 for (i = 0; i < pf->total_vfs; i++)
509 enetc_port_wr(hw, ENETC_PSICFGR0(i + 1), val);
510
511
512 val = ENETC_PVCLCTR_OVTPIDL(ENETC_VLAN_TYPE_C | ENETC_VLAN_TYPE_S);
513 enetc_port_wr(hw, ENETC_PVCLCTR, val);
514
515 enetc_port_wr(hw, ENETC_PSIVLANFMR, ENETC_PSIVLANFMR_VS);
516}
517
518static void enetc_configure_port_mac(struct enetc_hw *hw)
519{
520 int tc;
521
522 enetc_port_wr(hw, ENETC_PM0_MAXFRM,
523 ENETC_SET_MAXFRM(ENETC_RX_MAXFRM_SIZE));
524
525 for (tc = 0; tc < 8; tc++)
526 enetc_port_wr(hw, ENETC_PTCMSDUR(tc), ENETC_MAC_MAXFRM_SIZE);
527
528 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
529 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
530
531 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, ENETC_PM0_CMD_PHY_TX_EN |
532 ENETC_PM0_CMD_TXP | ENETC_PM0_PROMISC);
533
534
535
536
537
538 enetc_port_wr(hw, ENETC_PM0_RX_FIFO, ENETC_PM0_RX_FIFO_VAL);
539}
540
541static void enetc_mac_config(struct enetc_hw *hw, phy_interface_t phy_mode)
542{
543 u32 val;
544
545 if (phy_interface_mode_is_rgmii(phy_mode)) {
546 val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
547 val &= ~(ENETC_PM0_IFM_EN_AUTO | ENETC_PM0_IFM_IFMODE_MASK);
548 val |= ENETC_PM0_IFM_IFMODE_GMII | ENETC_PM0_IFM_RG;
549 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
550 }
551
552 if (phy_mode == PHY_INTERFACE_MODE_USXGMII) {
553 val = ENETC_PM0_IFM_FULL_DPX | ENETC_PM0_IFM_IFMODE_XGMII;
554 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
555 }
556}
557
558static void enetc_mac_enable(struct enetc_hw *hw, bool en)
559{
560 u32 val = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
561
562 val &= ~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN);
563 val |= en ? (ENETC_PM0_TX_EN | ENETC_PM0_RX_EN) : 0;
564
565 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, val);
566 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, val);
567}
568
569static void enetc_configure_port_pmac(struct enetc_hw *hw)
570{
571 u32 temp;
572
573
574 temp = enetc_port_rd(hw, ENETC_PFPMR);
575 enetc_port_wr(hw, ENETC_PFPMR,
576 temp | ENETC_PFPMR_PMACE | ENETC_PFPMR_MWLM);
577
578 temp = enetc_port_rd(hw, ENETC_MMCSR);
579 enetc_port_wr(hw, ENETC_MMCSR, temp | ENETC_MMCSR_ME);
580}
581
582static void enetc_configure_port(struct enetc_pf *pf)
583{
584 u8 hash_key[ENETC_RSSHASH_KEY_SIZE];
585 struct enetc_hw *hw = &pf->si->hw;
586
587 enetc_configure_port_pmac(hw);
588
589 enetc_configure_port_mac(hw);
590
591 enetc_port_si_configure(pf->si);
592
593
594 get_random_bytes(hash_key, ENETC_RSSHASH_KEY_SIZE);
595 enetc_set_rss_key(hw, hash_key);
596
597
598 enetc_port_assign_rfs_entries(pf->si);
599
600
601 pf->vlan_promisc_simap = ENETC_VLAN_PROMISC_MAP_ALL;
602 enetc_set_vlan_promisc(hw, pf->vlan_promisc_simap);
603
604 enetc_port_wr(hw, ENETC_PSIPMR, 0);
605
606
607 enetc_port_wr(hw, ENETC_PMR, ENETC_PMR_EN);
608}
609
610
611static u16 enetc_msg_pf_set_vf_primary_mac_addr(struct enetc_pf *pf,
612 int vf_id)
613{
614 struct enetc_vf_state *vf_state = &pf->vf_state[vf_id];
615 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
616 struct enetc_msg_cmd_set_primary_mac *cmd;
617 struct device *dev = &pf->si->pdev->dev;
618 u16 cmd_id;
619 char *addr;
620
621 cmd = (struct enetc_msg_cmd_set_primary_mac *)msg->vaddr;
622 cmd_id = cmd->header.id;
623 if (cmd_id != ENETC_MSG_CMD_MNG_ADD)
624 return ENETC_MSG_CMD_STATUS_FAIL;
625
626 addr = cmd->mac.sa_data;
627 if (vf_state->flags & ENETC_VF_FLAG_PF_SET_MAC)
628 dev_warn(dev, "Attempt to override PF set mac addr for VF%d\n",
629 vf_id);
630 else
631 enetc_pf_set_primary_mac_addr(&pf->si->hw, vf_id + 1, addr);
632
633 return ENETC_MSG_CMD_STATUS_OK;
634}
635
636void enetc_msg_handle_rxmsg(struct enetc_pf *pf, int vf_id, u16 *status)
637{
638 struct enetc_msg_swbd *msg = &pf->rxmsg[vf_id];
639 struct device *dev = &pf->si->pdev->dev;
640 struct enetc_msg_cmd_header *cmd_hdr;
641 u16 cmd_type;
642
643 *status = ENETC_MSG_CMD_STATUS_OK;
644 cmd_hdr = (struct enetc_msg_cmd_header *)msg->vaddr;
645 cmd_type = cmd_hdr->type;
646
647 switch (cmd_type) {
648 case ENETC_MSG_CMD_MNG_MAC:
649 *status = enetc_msg_pf_set_vf_primary_mac_addr(pf, vf_id);
650 break;
651 default:
652 dev_err(dev, "command not supported (cmd_type: 0x%x)\n",
653 cmd_type);
654 }
655}
656
657#ifdef CONFIG_PCI_IOV
658static int enetc_sriov_configure(struct pci_dev *pdev, int num_vfs)
659{
660 struct enetc_si *si = pci_get_drvdata(pdev);
661 struct enetc_pf *pf = enetc_si_priv(si);
662 int err;
663
664 if (!num_vfs) {
665 enetc_msg_psi_free(pf);
666 kfree(pf->vf_state);
667 pf->num_vfs = 0;
668 pci_disable_sriov(pdev);
669 } else {
670 pf->num_vfs = num_vfs;
671
672 pf->vf_state = kcalloc(num_vfs, sizeof(struct enetc_vf_state),
673 GFP_KERNEL);
674 if (!pf->vf_state) {
675 pf->num_vfs = 0;
676 return -ENOMEM;
677 }
678
679 err = enetc_msg_psi_init(pf);
680 if (err) {
681 dev_err(&pdev->dev, "enetc_msg_psi_init (%d)\n", err);
682 goto err_msg_psi;
683 }
684
685 err = pci_enable_sriov(pdev, num_vfs);
686 if (err) {
687 dev_err(&pdev->dev, "pci_enable_sriov err %d\n", err);
688 goto err_en_sriov;
689 }
690 }
691
692 return num_vfs;
693
694err_en_sriov:
695 enetc_msg_psi_free(pf);
696err_msg_psi:
697 kfree(pf->vf_state);
698 pf->num_vfs = 0;
699
700 return err;
701}
702#else
703#define enetc_sriov_configure(pdev, num_vfs) (void)0
704#endif
705
706static int enetc_pf_set_features(struct net_device *ndev,
707 netdev_features_t features)
708{
709 netdev_features_t changed = ndev->features ^ features;
710 struct enetc_ndev_priv *priv = netdev_priv(ndev);
711
712 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
713 struct enetc_pf *pf = enetc_si_priv(priv->si);
714
715 if (!!(features & NETIF_F_HW_VLAN_CTAG_FILTER))
716 enetc_disable_si_vlan_promisc(pf, 0);
717 else
718 enetc_enable_si_vlan_promisc(pf, 0);
719 }
720
721 if (changed & NETIF_F_LOOPBACK)
722 enetc_set_loopback(ndev, !!(features & NETIF_F_LOOPBACK));
723
724 return enetc_set_features(ndev, features);
725}
726
727static const struct net_device_ops enetc_ndev_ops = {
728 .ndo_open = enetc_open,
729 .ndo_stop = enetc_close,
730 .ndo_start_xmit = enetc_xmit,
731 .ndo_get_stats = enetc_get_stats,
732 .ndo_set_mac_address = enetc_pf_set_mac_addr,
733 .ndo_set_rx_mode = enetc_pf_set_rx_mode,
734 .ndo_vlan_rx_add_vid = enetc_vlan_rx_add_vid,
735 .ndo_vlan_rx_kill_vid = enetc_vlan_rx_del_vid,
736 .ndo_set_vf_mac = enetc_pf_set_vf_mac,
737 .ndo_set_vf_vlan = enetc_pf_set_vf_vlan,
738 .ndo_set_vf_spoofchk = enetc_pf_set_vf_spoofchk,
739 .ndo_set_features = enetc_pf_set_features,
740 .ndo_eth_ioctl = enetc_ioctl,
741 .ndo_setup_tc = enetc_setup_tc,
742 .ndo_bpf = enetc_setup_bpf,
743 .ndo_xdp_xmit = enetc_xdp_xmit,
744};
745
746static void enetc_pf_netdev_setup(struct enetc_si *si, struct net_device *ndev,
747 const struct net_device_ops *ndev_ops)
748{
749 struct enetc_ndev_priv *priv = netdev_priv(ndev);
750
751 SET_NETDEV_DEV(ndev, &si->pdev->dev);
752 priv->ndev = ndev;
753 priv->si = si;
754 priv->dev = &si->pdev->dev;
755 si->ndev = ndev;
756
757 priv->msg_enable = (NETIF_MSG_WOL << 1) - 1;
758 ndev->netdev_ops = ndev_ops;
759 enetc_set_ethtool_ops(ndev);
760 ndev->watchdog_timeo = 5 * HZ;
761 ndev->max_mtu = ENETC_MAX_MTU;
762
763 ndev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
764 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
765 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_LOOPBACK;
766 ndev->features = NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_RXCSUM |
767 NETIF_F_HW_VLAN_CTAG_TX |
768 NETIF_F_HW_VLAN_CTAG_RX;
769
770 if (si->num_rss)
771 ndev->hw_features |= NETIF_F_RXHASH;
772
773 ndev->priv_flags |= IFF_UNICAST_FLT;
774
775 if (si->hw_features & ENETC_SI_F_QBV)
776 priv->active_offloads |= ENETC_F_QBV;
777
778 if (si->hw_features & ENETC_SI_F_PSFP && !enetc_psfp_enable(priv)) {
779 priv->active_offloads |= ENETC_F_QCI;
780 ndev->features |= NETIF_F_HW_TC;
781 ndev->hw_features |= NETIF_F_HW_TC;
782 }
783
784
785 enetc_get_primary_mac_addr(&si->hw, ndev->dev_addr);
786}
787
788static int enetc_mdio_probe(struct enetc_pf *pf, struct device_node *np)
789{
790 struct device *dev = &pf->si->pdev->dev;
791 struct enetc_mdio_priv *mdio_priv;
792 struct mii_bus *bus;
793 int err;
794
795 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv));
796 if (!bus)
797 return -ENOMEM;
798
799 bus->name = "Freescale ENETC MDIO Bus";
800 bus->read = enetc_mdio_read;
801 bus->write = enetc_mdio_write;
802 bus->parent = dev;
803 mdio_priv = bus->priv;
804 mdio_priv->hw = &pf->si->hw;
805 mdio_priv->mdio_base = ENETC_EMDIO_BASE;
806 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
807
808 err = of_mdiobus_register(bus, np);
809 if (err) {
810 dev_err(dev, "cannot register MDIO bus\n");
811 return err;
812 }
813
814 pf->mdio = bus;
815
816 return 0;
817}
818
819static void enetc_mdio_remove(struct enetc_pf *pf)
820{
821 if (pf->mdio)
822 mdiobus_unregister(pf->mdio);
823}
824
825static int enetc_imdio_create(struct enetc_pf *pf)
826{
827 struct device *dev = &pf->si->pdev->dev;
828 struct enetc_mdio_priv *mdio_priv;
829 struct lynx_pcs *pcs_lynx;
830 struct mdio_device *pcs;
831 struct mii_bus *bus;
832 int err;
833
834 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
835 if (!bus)
836 return -ENOMEM;
837
838 bus->name = "Freescale ENETC internal MDIO Bus";
839 bus->read = enetc_mdio_read;
840 bus->write = enetc_mdio_write;
841 bus->parent = dev;
842 bus->phy_mask = ~0;
843 mdio_priv = bus->priv;
844 mdio_priv->hw = &pf->si->hw;
845 mdio_priv->mdio_base = ENETC_PM_IMDIO_BASE;
846 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
847
848 err = mdiobus_register(bus);
849 if (err) {
850 dev_err(dev, "cannot register internal MDIO bus (%d)\n", err);
851 goto free_mdio_bus;
852 }
853
854 pcs = mdio_device_create(bus, 0);
855 if (IS_ERR(pcs)) {
856 err = PTR_ERR(pcs);
857 dev_err(dev, "cannot create pcs (%d)\n", err);
858 goto unregister_mdiobus;
859 }
860
861 pcs_lynx = lynx_pcs_create(pcs);
862 if (!pcs_lynx) {
863 mdio_device_free(pcs);
864 err = -ENOMEM;
865 dev_err(dev, "cannot create lynx pcs (%d)\n", err);
866 goto unregister_mdiobus;
867 }
868
869 pf->imdio = bus;
870 pf->pcs = pcs_lynx;
871
872 return 0;
873
874unregister_mdiobus:
875 mdiobus_unregister(bus);
876free_mdio_bus:
877 mdiobus_free(bus);
878 return err;
879}
880
881static void enetc_imdio_remove(struct enetc_pf *pf)
882{
883 if (pf->pcs) {
884 mdio_device_free(pf->pcs->mdio);
885 lynx_pcs_destroy(pf->pcs);
886 }
887 if (pf->imdio) {
888 mdiobus_unregister(pf->imdio);
889 mdiobus_free(pf->imdio);
890 }
891}
892
893static bool enetc_port_has_pcs(struct enetc_pf *pf)
894{
895 return (pf->if_mode == PHY_INTERFACE_MODE_SGMII ||
896 pf->if_mode == PHY_INTERFACE_MODE_2500BASEX ||
897 pf->if_mode == PHY_INTERFACE_MODE_USXGMII);
898}
899
900static int enetc_mdiobus_create(struct enetc_pf *pf, struct device_node *node)
901{
902 struct device_node *mdio_np;
903 int err;
904
905 mdio_np = of_get_child_by_name(node, "mdio");
906 if (mdio_np) {
907 err = enetc_mdio_probe(pf, mdio_np);
908
909 of_node_put(mdio_np);
910 if (err)
911 return err;
912 }
913
914 if (enetc_port_has_pcs(pf)) {
915 err = enetc_imdio_create(pf);
916 if (err) {
917 enetc_mdio_remove(pf);
918 return err;
919 }
920 }
921
922 return 0;
923}
924
925static void enetc_mdiobus_destroy(struct enetc_pf *pf)
926{
927 enetc_mdio_remove(pf);
928 enetc_imdio_remove(pf);
929}
930
931static void enetc_pl_mac_validate(struct phylink_config *config,
932 unsigned long *supported,
933 struct phylink_link_state *state)
934{
935 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
936
937 if (state->interface != PHY_INTERFACE_MODE_NA &&
938 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
939 state->interface != PHY_INTERFACE_MODE_SGMII &&
940 state->interface != PHY_INTERFACE_MODE_2500BASEX &&
941 state->interface != PHY_INTERFACE_MODE_USXGMII &&
942 !phy_interface_mode_is_rgmii(state->interface)) {
943 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
944 return;
945 }
946
947 phylink_set_port_modes(mask);
948 phylink_set(mask, Autoneg);
949 phylink_set(mask, Pause);
950 phylink_set(mask, Asym_Pause);
951 phylink_set(mask, 10baseT_Half);
952 phylink_set(mask, 10baseT_Full);
953 phylink_set(mask, 100baseT_Half);
954 phylink_set(mask, 100baseT_Full);
955 phylink_set(mask, 100baseT_Half);
956 phylink_set(mask, 1000baseT_Half);
957 phylink_set(mask, 1000baseT_Full);
958
959 if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
960 state->interface == PHY_INTERFACE_MODE_2500BASEX ||
961 state->interface == PHY_INTERFACE_MODE_USXGMII) {
962 phylink_set(mask, 2500baseT_Full);
963 phylink_set(mask, 2500baseX_Full);
964 }
965
966 bitmap_and(supported, supported, mask,
967 __ETHTOOL_LINK_MODE_MASK_NBITS);
968 bitmap_and(state->advertising, state->advertising, mask,
969 __ETHTOOL_LINK_MODE_MASK_NBITS);
970}
971
972static void enetc_pl_mac_config(struct phylink_config *config,
973 unsigned int mode,
974 const struct phylink_link_state *state)
975{
976 struct enetc_pf *pf = phylink_to_enetc_pf(config);
977 struct enetc_ndev_priv *priv;
978
979 enetc_mac_config(&pf->si->hw, state->interface);
980
981 priv = netdev_priv(pf->si->ndev);
982 if (pf->pcs)
983 phylink_set_pcs(priv->phylink, &pf->pcs->pcs);
984}
985
986static void enetc_force_rgmii_mac(struct enetc_hw *hw, int speed, int duplex)
987{
988 u32 old_val, val;
989
990 old_val = val = enetc_port_rd(hw, ENETC_PM0_IF_MODE);
991
992 if (speed == SPEED_1000) {
993 val &= ~ENETC_PM0_IFM_SSP_MASK;
994 val |= ENETC_PM0_IFM_SSP_1000;
995 } else if (speed == SPEED_100) {
996 val &= ~ENETC_PM0_IFM_SSP_MASK;
997 val |= ENETC_PM0_IFM_SSP_100;
998 } else if (speed == SPEED_10) {
999 val &= ~ENETC_PM0_IFM_SSP_MASK;
1000 val |= ENETC_PM0_IFM_SSP_10;
1001 }
1002
1003 if (duplex == DUPLEX_FULL)
1004 val |= ENETC_PM0_IFM_FULL_DPX;
1005 else
1006 val &= ~ENETC_PM0_IFM_FULL_DPX;
1007
1008 if (val == old_val)
1009 return;
1010
1011 enetc_port_wr(hw, ENETC_PM0_IF_MODE, val);
1012}
1013
1014static void enetc_pl_mac_link_up(struct phylink_config *config,
1015 struct phy_device *phy, unsigned int mode,
1016 phy_interface_t interface, int speed,
1017 int duplex, bool tx_pause, bool rx_pause)
1018{
1019 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1020 u32 pause_off_thresh = 0, pause_on_thresh = 0;
1021 u32 init_quanta = 0, refresh_quanta = 0;
1022 struct enetc_hw *hw = &pf->si->hw;
1023 struct enetc_ndev_priv *priv;
1024 u32 rbmr, cmd_cfg;
1025 int idx;
1026
1027 priv = netdev_priv(pf->si->ndev);
1028 if (priv->active_offloads & ENETC_F_QBV)
1029 enetc_sched_speed_set(priv, speed);
1030
1031 if (!phylink_autoneg_inband(mode) &&
1032 phy_interface_mode_is_rgmii(interface))
1033 enetc_force_rgmii_mac(hw, speed, duplex);
1034
1035
1036 for (idx = 0; idx < priv->num_rx_rings; idx++) {
1037 rbmr = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
1038
1039 if (tx_pause)
1040 rbmr |= ENETC_RBMR_CM;
1041 else
1042 rbmr &= ~ENETC_RBMR_CM;
1043
1044 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, rbmr);
1045 }
1046
1047 if (tx_pause) {
1048
1049
1050
1051
1052
1053 init_quanta = 0xffff;
1054
1055
1056
1057
1058
1059 refresh_quanta = 0xffff / 2;
1060
1061
1062
1063
1064
1065 pause_on_thresh = 3 * ENETC_MAC_MAXFRM_SIZE;
1066 pause_off_thresh = 1 * ENETC_MAC_MAXFRM_SIZE;
1067 }
1068
1069 enetc_port_wr(hw, ENETC_PM0_PAUSE_QUANTA, init_quanta);
1070 enetc_port_wr(hw, ENETC_PM1_PAUSE_QUANTA, init_quanta);
1071 enetc_port_wr(hw, ENETC_PM0_PAUSE_THRESH, refresh_quanta);
1072 enetc_port_wr(hw, ENETC_PM1_PAUSE_THRESH, refresh_quanta);
1073 enetc_port_wr(hw, ENETC_PPAUONTR, pause_on_thresh);
1074 enetc_port_wr(hw, ENETC_PPAUOFFTR, pause_off_thresh);
1075
1076 cmd_cfg = enetc_port_rd(hw, ENETC_PM0_CMD_CFG);
1077
1078 if (rx_pause)
1079 cmd_cfg &= ~ENETC_PM0_PAUSE_IGN;
1080 else
1081 cmd_cfg |= ENETC_PM0_PAUSE_IGN;
1082
1083 enetc_port_wr(hw, ENETC_PM0_CMD_CFG, cmd_cfg);
1084 enetc_port_wr(hw, ENETC_PM1_CMD_CFG, cmd_cfg);
1085
1086 enetc_mac_enable(hw, true);
1087}
1088
1089static void enetc_pl_mac_link_down(struct phylink_config *config,
1090 unsigned int mode,
1091 phy_interface_t interface)
1092{
1093 struct enetc_pf *pf = phylink_to_enetc_pf(config);
1094
1095 enetc_mac_enable(&pf->si->hw, false);
1096}
1097
1098static const struct phylink_mac_ops enetc_mac_phylink_ops = {
1099 .validate = enetc_pl_mac_validate,
1100 .mac_config = enetc_pl_mac_config,
1101 .mac_link_up = enetc_pl_mac_link_up,
1102 .mac_link_down = enetc_pl_mac_link_down,
1103};
1104
1105static int enetc_phylink_create(struct enetc_ndev_priv *priv,
1106 struct device_node *node)
1107{
1108 struct enetc_pf *pf = enetc_si_priv(priv->si);
1109 struct phylink *phylink;
1110 int err;
1111
1112 pf->phylink_config.dev = &priv->ndev->dev;
1113 pf->phylink_config.type = PHYLINK_NETDEV;
1114
1115 phylink = phylink_create(&pf->phylink_config, of_fwnode_handle(node),
1116 pf->if_mode, &enetc_mac_phylink_ops);
1117 if (IS_ERR(phylink)) {
1118 err = PTR_ERR(phylink);
1119 return err;
1120 }
1121
1122 priv->phylink = phylink;
1123
1124 return 0;
1125}
1126
1127static void enetc_phylink_destroy(struct enetc_ndev_priv *priv)
1128{
1129 if (priv->phylink)
1130 phylink_destroy(priv->phylink);
1131}
1132
1133
1134
1135
1136static int enetc_init_port_rfs_memory(struct enetc_si *si)
1137{
1138 struct enetc_cmd_rfse rfse = {0};
1139 struct enetc_hw *hw = &si->hw;
1140 int num_rfs, i, err = 0;
1141 u32 val;
1142
1143 val = enetc_port_rd(hw, ENETC_PRFSCAPR);
1144 num_rfs = ENETC_PRFSCAPR_GET_NUM_RFS(val);
1145
1146 for (i = 0; i < num_rfs; i++) {
1147 err = enetc_set_fs_entry(si, &rfse, i);
1148 if (err)
1149 break;
1150 }
1151
1152 return err;
1153}
1154
1155static int enetc_init_port_rss_memory(struct enetc_si *si)
1156{
1157 struct enetc_hw *hw = &si->hw;
1158 int num_rss, err;
1159 int *rss_table;
1160 u32 val;
1161
1162 val = enetc_port_rd(hw, ENETC_PRSSCAPR);
1163 num_rss = ENETC_PRSSCAPR_GET_NUM_RSS(val);
1164 if (!num_rss)
1165 return 0;
1166
1167 rss_table = kcalloc(num_rss, sizeof(*rss_table), GFP_KERNEL);
1168 if (!rss_table)
1169 return -ENOMEM;
1170
1171 err = enetc_set_rss_table(si, rss_table, num_rss);
1172
1173 kfree(rss_table);
1174
1175 return err;
1176}
1177
1178static int enetc_pf_register_with_ierb(struct pci_dev *pdev)
1179{
1180 struct device_node *node = pdev->dev.of_node;
1181 struct platform_device *ierb_pdev;
1182 struct device_node *ierb_node;
1183
1184
1185 if (!node || !of_device_is_available(node))
1186 return 0;
1187
1188 ierb_node = of_find_compatible_node(NULL, NULL,
1189 "fsl,ls1028a-enetc-ierb");
1190 if (!ierb_node || !of_device_is_available(ierb_node))
1191 return -ENODEV;
1192
1193 ierb_pdev = of_find_device_by_node(ierb_node);
1194 of_node_put(ierb_node);
1195
1196 if (!ierb_pdev)
1197 return -EPROBE_DEFER;
1198
1199 return enetc_ierb_register_pf(ierb_pdev, pdev);
1200}
1201
1202static int enetc_pf_probe(struct pci_dev *pdev,
1203 const struct pci_device_id *ent)
1204{
1205 struct device_node *node = pdev->dev.of_node;
1206 struct enetc_ndev_priv *priv;
1207 struct net_device *ndev;
1208 struct enetc_si *si;
1209 struct enetc_pf *pf;
1210 int err;
1211
1212 err = enetc_pf_register_with_ierb(pdev);
1213 if (err == -EPROBE_DEFER)
1214 return err;
1215 if (err)
1216 dev_warn(&pdev->dev,
1217 "Could not register with IERB driver: %pe, please update the device tree\n",
1218 ERR_PTR(err));
1219
1220 err = enetc_pci_probe(pdev, KBUILD_MODNAME, sizeof(*pf));
1221 if (err) {
1222 dev_err(&pdev->dev, "PCI probing failed\n");
1223 return err;
1224 }
1225
1226 si = pci_get_drvdata(pdev);
1227 if (!si->hw.port || !si->hw.global) {
1228 err = -ENODEV;
1229 dev_err(&pdev->dev, "could not map PF space, probing a VF?\n");
1230 goto err_map_pf_space;
1231 }
1232
1233 err = enetc_setup_cbdr(&pdev->dev, &si->hw, ENETC_CBDR_DEFAULT_SIZE,
1234 &si->cbd_ring);
1235 if (err)
1236 goto err_setup_cbdr;
1237
1238 err = enetc_init_port_rfs_memory(si);
1239 if (err) {
1240 dev_err(&pdev->dev, "Failed to initialize RFS memory\n");
1241 goto err_init_port_rfs;
1242 }
1243
1244 err = enetc_init_port_rss_memory(si);
1245 if (err) {
1246 dev_err(&pdev->dev, "Failed to initialize RSS memory\n");
1247 goto err_init_port_rss;
1248 }
1249
1250 if (node && !of_device_is_available(node)) {
1251 dev_info(&pdev->dev, "device is disabled, skipping\n");
1252 err = -ENODEV;
1253 goto err_device_disabled;
1254 }
1255
1256 pf = enetc_si_priv(si);
1257 pf->si = si;
1258 pf->total_vfs = pci_sriov_get_totalvfs(pdev);
1259
1260 err = enetc_setup_mac_addresses(node, pf);
1261 if (err)
1262 goto err_setup_mac_addresses;
1263
1264 enetc_configure_port(pf);
1265
1266 enetc_get_si_caps(si);
1267
1268 ndev = alloc_etherdev_mq(sizeof(*priv), ENETC_MAX_NUM_TXQS);
1269 if (!ndev) {
1270 err = -ENOMEM;
1271 dev_err(&pdev->dev, "netdev creation failed\n");
1272 goto err_alloc_netdev;
1273 }
1274
1275 enetc_pf_netdev_setup(si, ndev, &enetc_ndev_ops);
1276
1277 priv = netdev_priv(ndev);
1278
1279 enetc_init_si_rings_params(priv);
1280
1281 err = enetc_alloc_si_resources(priv);
1282 if (err) {
1283 dev_err(&pdev->dev, "SI resource alloc failed\n");
1284 goto err_alloc_si_res;
1285 }
1286
1287 err = enetc_configure_si(priv);
1288 if (err) {
1289 dev_err(&pdev->dev, "Failed to configure SI\n");
1290 goto err_config_si;
1291 }
1292
1293 err = enetc_alloc_msix(priv);
1294 if (err) {
1295 dev_err(&pdev->dev, "MSIX alloc failed\n");
1296 goto err_alloc_msix;
1297 }
1298
1299 if (!of_get_phy_mode(node, &pf->if_mode)) {
1300 err = enetc_mdiobus_create(pf, node);
1301 if (err)
1302 goto err_mdiobus_create;
1303
1304 err = enetc_phylink_create(priv, node);
1305 if (err)
1306 goto err_phylink_create;
1307 }
1308
1309 err = register_netdev(ndev);
1310 if (err)
1311 goto err_reg_netdev;
1312
1313 return 0;
1314
1315err_reg_netdev:
1316 enetc_phylink_destroy(priv);
1317err_phylink_create:
1318 enetc_mdiobus_destroy(pf);
1319err_mdiobus_create:
1320 enetc_free_msix(priv);
1321err_config_si:
1322err_alloc_msix:
1323 enetc_free_si_resources(priv);
1324err_alloc_si_res:
1325 si->ndev = NULL;
1326 free_netdev(ndev);
1327err_alloc_netdev:
1328err_init_port_rss:
1329err_init_port_rfs:
1330err_device_disabled:
1331err_setup_mac_addresses:
1332 enetc_teardown_cbdr(&si->cbd_ring);
1333err_setup_cbdr:
1334err_map_pf_space:
1335 enetc_pci_remove(pdev);
1336
1337 return err;
1338}
1339
1340static void enetc_pf_remove(struct pci_dev *pdev)
1341{
1342 struct enetc_si *si = pci_get_drvdata(pdev);
1343 struct enetc_pf *pf = enetc_si_priv(si);
1344 struct enetc_ndev_priv *priv;
1345
1346 priv = netdev_priv(si->ndev);
1347
1348 if (pf->num_vfs)
1349 enetc_sriov_configure(pdev, 0);
1350
1351 unregister_netdev(si->ndev);
1352
1353 enetc_phylink_destroy(priv);
1354 enetc_mdiobus_destroy(pf);
1355
1356 enetc_free_msix(priv);
1357
1358 enetc_free_si_resources(priv);
1359 enetc_teardown_cbdr(&si->cbd_ring);
1360
1361 free_netdev(si->ndev);
1362
1363 enetc_pci_remove(pdev);
1364}
1365
1366static const struct pci_device_id enetc_pf_id_table[] = {
1367 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_PF) },
1368 { 0, }
1369};
1370MODULE_DEVICE_TABLE(pci, enetc_pf_id_table);
1371
1372static struct pci_driver enetc_pf_driver = {
1373 .name = KBUILD_MODNAME,
1374 .id_table = enetc_pf_id_table,
1375 .probe = enetc_pf_probe,
1376 .remove = enetc_pf_remove,
1377#ifdef CONFIG_PCI_IOV
1378 .sriov_configure = enetc_sriov_configure,
1379#endif
1380};
1381module_pci_driver(enetc_pf_driver);
1382
1383MODULE_DESCRIPTION(ENETC_DRV_NAME_STR);
1384MODULE_LICENSE("Dual BSD/GPL");
1385
