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13#ifndef FEC_H
14#define FEC_H
15
16
17#include <linux/clocksource.h>
18#include <linux/net_tstamp.h>
19#include <linux/ptp_clock_kernel.h>
20#include <linux/timecounter.h>
21
22#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
23 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
24 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
25
26
27
28
29
30#define FEC_IEVENT 0x004
31#define FEC_IMASK 0x008
32#define FEC_R_DES_ACTIVE_0 0x010
33#define FEC_X_DES_ACTIVE_0 0x014
34#define FEC_ECNTRL 0x024
35#define FEC_MII_DATA 0x040
36#define FEC_MII_SPEED 0x044
37#define FEC_MIB_CTRLSTAT 0x064
38#define FEC_R_CNTRL 0x084
39#define FEC_X_CNTRL 0x0c4
40#define FEC_ADDR_LOW 0x0e4
41#define FEC_ADDR_HIGH 0x0e8
42#define FEC_OPD 0x0ec
43#define FEC_TXIC0 0x0f0
44#define FEC_TXIC1 0x0f4
45#define FEC_TXIC2 0x0f8
46#define FEC_RXIC0 0x100
47#define FEC_RXIC1 0x104
48#define FEC_RXIC2 0x108
49#define FEC_HASH_TABLE_HIGH 0x118
50#define FEC_HASH_TABLE_LOW 0x11c
51#define FEC_GRP_HASH_TABLE_HIGH 0x120
52#define FEC_GRP_HASH_TABLE_LOW 0x124
53#define FEC_X_WMRK 0x144
54#define FEC_R_BOUND 0x14c
55#define FEC_R_FSTART 0x150
56#define FEC_R_DES_START_1 0x160
57#define FEC_X_DES_START_1 0x164
58#define FEC_R_BUFF_SIZE_1 0x168
59#define FEC_R_DES_START_2 0x16c
60#define FEC_X_DES_START_2 0x170
61#define FEC_R_BUFF_SIZE_2 0x174
62#define FEC_R_DES_START_0 0x180
63#define FEC_X_DES_START_0 0x184
64#define FEC_R_BUFF_SIZE_0 0x188
65#define FEC_R_FIFO_RSFL 0x190
66#define FEC_R_FIFO_RSEM 0x194
67#define FEC_R_FIFO_RAEM 0x198
68#define FEC_R_FIFO_RAFL 0x19c
69#define FEC_FTRL 0x1b0
70#define FEC_RACC 0x1c4
71#define FEC_RCMR_1 0x1c8
72#define FEC_RCMR_2 0x1cc
73#define FEC_DMA_CFG_1 0x1d8
74#define FEC_DMA_CFG_2 0x1dc
75#define FEC_R_DES_ACTIVE_1 0x1e0
76#define FEC_X_DES_ACTIVE_1 0x1e4
77#define FEC_R_DES_ACTIVE_2 0x1e8
78#define FEC_X_DES_ACTIVE_2 0x1ec
79#define FEC_QOS_SCHEME 0x1f0
80#define FEC_LPI_SLEEP 0x1f4
81#define FEC_LPI_WAKE 0x1f8
82#define FEC_MIIGSK_CFGR 0x300
83#define FEC_MIIGSK_ENR 0x308
84
85#define BM_MIIGSK_CFGR_MII 0x00
86#define BM_MIIGSK_CFGR_RMII 0x01
87#define BM_MIIGSK_CFGR_FRCONT_10M 0x40
88
89#define RMON_T_DROP 0x200
90#define RMON_T_PACKETS 0x204
91#define RMON_T_BC_PKT 0x208
92#define RMON_T_MC_PKT 0x20c
93#define RMON_T_CRC_ALIGN 0x210
94#define RMON_T_UNDERSIZE 0x214
95#define RMON_T_OVERSIZE 0x218
96#define RMON_T_FRAG 0x21c
97#define RMON_T_JAB 0x220
98#define RMON_T_COL 0x224
99#define RMON_T_P64 0x228
100#define RMON_T_P65TO127 0x22c
101#define RMON_T_P128TO255 0x230
102#define RMON_T_P256TO511 0x234
103#define RMON_T_P512TO1023 0x238
104#define RMON_T_P1024TO2047 0x23c
105#define RMON_T_P_GTE2048 0x240
106#define RMON_T_OCTETS 0x244
107#define IEEE_T_DROP 0x248
108#define IEEE_T_FRAME_OK 0x24c
109#define IEEE_T_1COL 0x250
110#define IEEE_T_MCOL 0x254
111#define IEEE_T_DEF 0x258
112#define IEEE_T_LCOL 0x25c
113#define IEEE_T_EXCOL 0x260
114#define IEEE_T_MACERR 0x264
115#define IEEE_T_CSERR 0x268
116#define IEEE_T_SQE 0x26c
117#define IEEE_T_FDXFC 0x270
118#define IEEE_T_OCTETS_OK 0x274
119#define RMON_R_PACKETS 0x284
120#define RMON_R_BC_PKT 0x288
121#define RMON_R_MC_PKT 0x28c
122#define RMON_R_CRC_ALIGN 0x290
123#define RMON_R_UNDERSIZE 0x294
124#define RMON_R_OVERSIZE 0x298
125#define RMON_R_FRAG 0x29c
126#define RMON_R_JAB 0x2a0
127#define RMON_R_RESVD_O 0x2a4
128#define RMON_R_P64 0x2a8
129#define RMON_R_P65TO127 0x2ac
130#define RMON_R_P128TO255 0x2b0
131#define RMON_R_P256TO511 0x2b4
132#define RMON_R_P512TO1023 0x2b8
133#define RMON_R_P1024TO2047 0x2bc
134#define RMON_R_P_GTE2048 0x2c0
135#define RMON_R_OCTETS 0x2c4
136#define IEEE_R_DROP 0x2c8
137#define IEEE_R_FRAME_OK 0x2cc
138#define IEEE_R_CRC 0x2d0
139#define IEEE_R_ALIGN 0x2d4
140#define IEEE_R_MACERR 0x2d8
141#define IEEE_R_FDXFC 0x2dc
142#define IEEE_R_OCTETS_OK 0x2e0
143
144#else
145
146#define FEC_ECNTRL 0x000
147#define FEC_IEVENT 0x004
148#define FEC_IMASK 0x008
149#define FEC_IVEC 0x00c
150#define FEC_R_DES_ACTIVE_0 0x010
151#define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0
152#define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0
153#define FEC_X_DES_ACTIVE_0 0x014
154#define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0
155#define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0
156#define FEC_MII_DATA 0x040
157#define FEC_MII_SPEED 0x044
158#define FEC_R_BOUND 0x08c
159#define FEC_R_FSTART 0x090
160#define FEC_X_WMRK 0x0a4
161#define FEC_X_FSTART 0x0ac
162#define FEC_R_CNTRL 0x104
163#define FEC_MAX_FRM_LEN 0x108
164#define FEC_X_CNTRL 0x144
165#define FEC_ADDR_LOW 0x3c0
166#define FEC_ADDR_HIGH 0x3c4
167#define FEC_GRP_HASH_TABLE_HIGH 0x3c8
168#define FEC_GRP_HASH_TABLE_LOW 0x3cc
169#define FEC_R_DES_START_0 0x3d0
170#define FEC_R_DES_START_1 FEC_R_DES_START_0
171#define FEC_R_DES_START_2 FEC_R_DES_START_0
172#define FEC_X_DES_START_0 0x3d4
173#define FEC_X_DES_START_1 FEC_X_DES_START_0
174#define FEC_X_DES_START_2 FEC_X_DES_START_0
175#define FEC_R_BUFF_SIZE_0 0x3d8
176#define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0
177#define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0
178#define FEC_FIFO_RAM 0x400
179
180
181
182#define FEC_RCMR_1 0xfff
183#define FEC_RCMR_2 0xfff
184#define FEC_DMA_CFG_1 0xfff
185#define FEC_DMA_CFG_2 0xfff
186#define FEC_TXIC0 0xfff
187#define FEC_TXIC1 0xfff
188#define FEC_TXIC2 0xfff
189#define FEC_RXIC0 0xfff
190#define FEC_RXIC1 0xfff
191#define FEC_RXIC2 0xfff
192#define FEC_LPI_SLEEP 0xfff
193#define FEC_LPI_WAKE 0xfff
194#endif
195
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201
202
203#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
204#define fec32_to_cpu le32_to_cpu
205#define fec16_to_cpu le16_to_cpu
206#define cpu_to_fec32 cpu_to_le32
207#define cpu_to_fec16 cpu_to_le16
208#define __fec32 __le32
209#define __fec16 __le16
210
211struct bufdesc {
212 __fec16 cbd_datlen;
213 __fec16 cbd_sc;
214 __fec32 cbd_bufaddr;
215};
216#else
217#define fec32_to_cpu be32_to_cpu
218#define fec16_to_cpu be16_to_cpu
219#define cpu_to_fec32 cpu_to_be32
220#define cpu_to_fec16 cpu_to_be16
221#define __fec32 __be32
222#define __fec16 __be16
223
224struct bufdesc {
225 __fec16 cbd_sc;
226 __fec16 cbd_datlen;
227 __fec32 cbd_bufaddr;
228};
229#endif
230
231struct bufdesc_ex {
232 struct bufdesc desc;
233 __fec32 cbd_esc;
234 __fec32 cbd_prot;
235 __fec32 cbd_bdu;
236 __fec32 ts;
237 __fec16 res0[4];
238};
239
240
241
242
243
244#define BD_SC_EMPTY ((ushort)0x8000)
245#define BD_SC_READY ((ushort)0x8000)
246#define BD_SC_WRAP ((ushort)0x2000)
247#define BD_SC_INTRPT ((ushort)0x1000)
248#define BD_SC_CM ((ushort)0x0200)
249#define BD_SC_ID ((ushort)0x0100)
250#define BD_SC_P ((ushort)0x0100)
251#define BD_SC_BR ((ushort)0x0020)
252#define BD_SC_FR ((ushort)0x0010)
253#define BD_SC_PR ((ushort)0x0008)
254#define BD_SC_OV ((ushort)0x0002)
255#define BD_SC_CD ((ushort)0x0001)
256
257
258
259#define BD_ENET_RX_EMPTY ((ushort)0x8000)
260#define BD_ENET_RX_WRAP ((ushort)0x2000)
261#define BD_ENET_RX_INTR ((ushort)0x1000)
262#define BD_ENET_RX_LAST ((ushort)0x0800)
263#define BD_ENET_RX_FIRST ((ushort)0x0400)
264#define BD_ENET_RX_MISS ((ushort)0x0100)
265#define BD_ENET_RX_LG ((ushort)0x0020)
266#define BD_ENET_RX_NO ((ushort)0x0010)
267#define BD_ENET_RX_SH ((ushort)0x0008)
268#define BD_ENET_RX_CR ((ushort)0x0004)
269#define BD_ENET_RX_OV ((ushort)0x0002)
270#define BD_ENET_RX_CL ((ushort)0x0001)
271#define BD_ENET_RX_STATS ((ushort)0x013f)
272
273
274#define BD_ENET_RX_VLAN 0x00000004
275
276
277
278#define BD_ENET_TX_READY ((ushort)0x8000)
279#define BD_ENET_TX_PAD ((ushort)0x4000)
280#define BD_ENET_TX_WRAP ((ushort)0x2000)
281#define BD_ENET_TX_INTR ((ushort)0x1000)
282#define BD_ENET_TX_LAST ((ushort)0x0800)
283#define BD_ENET_TX_TC ((ushort)0x0400)
284#define BD_ENET_TX_DEF ((ushort)0x0200)
285#define BD_ENET_TX_HB ((ushort)0x0100)
286#define BD_ENET_TX_LC ((ushort)0x0080)
287#define BD_ENET_TX_RL ((ushort)0x0040)
288#define BD_ENET_TX_RCMASK ((ushort)0x003c)
289#define BD_ENET_TX_UN ((ushort)0x0002)
290#define BD_ENET_TX_CSL ((ushort)0x0001)
291#define BD_ENET_TX_STATS ((ushort)0x0fff)
292
293
294#define BD_ENET_TX_INT 0x40000000
295#define BD_ENET_TX_TS 0x20000000
296#define BD_ENET_TX_PINS 0x10000000
297#define BD_ENET_TX_IINS 0x08000000
298
299
300
301#define FEC_IRQ_NUM 3
302
303
304
305
306
307#define FEC_ENET_MAX_TX_QS 3
308#define FEC_ENET_MAX_RX_QS 3
309
310#define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \
311 (((X) == 2) ? \
312 FEC_R_DES_START_2 : FEC_R_DES_START_0))
313#define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \
314 (((X) == 2) ? \
315 FEC_X_DES_START_2 : FEC_X_DES_START_0))
316#define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
317 (((X) == 2) ? \
318 FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
319
320#define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
321
322#define DMA_CLASS_EN (1 << 16)
323#define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
324#define IDLE_SLOPE_MASK 0xffff
325#define IDLE_SLOPE_1 0x200
326#define IDLE_SLOPE_2 0x200
327#define IDLE_SLOPE(X) (((X) == 1) ? \
328 (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
329 (IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
330#define RCMR_MATCHEN (0x1 << 16)
331#define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2))
332#define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
333 RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
334#define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
335 RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
336#define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
337#define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20)
338
339
340
341
342
343
344
345
346#define FEC_ENET_RX_PAGES 256
347#define FEC_ENET_RX_FRSIZE 2048
348#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
349#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
350#define FEC_ENET_TX_FRSIZE 2048
351#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
352#define TX_RING_SIZE 512
353#define TX_RING_MOD_MASK 511
354
355#define BD_ENET_RX_INT 0x00800000
356#define BD_ENET_RX_PTP ((ushort)0x0400)
357#define BD_ENET_RX_ICE 0x00000020
358#define BD_ENET_RX_PCR 0x00000010
359#define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
360#define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
361
362
363#define FEC_ENET_HBERR ((uint)0x80000000)
364#define FEC_ENET_BABR ((uint)0x40000000)
365#define FEC_ENET_BABT ((uint)0x20000000)
366#define FEC_ENET_GRA ((uint)0x10000000)
367#define FEC_ENET_TXF_0 ((uint)0x08000000)
368#define FEC_ENET_TXF_1 ((uint)0x00000008)
369#define FEC_ENET_TXF_2 ((uint)0x00000080)
370#define FEC_ENET_TXB ((uint)0x04000000)
371#define FEC_ENET_RXF_0 ((uint)0x02000000)
372#define FEC_ENET_RXF_1 ((uint)0x00000002)
373#define FEC_ENET_RXF_2 ((uint)0x00000020)
374#define FEC_ENET_RXB ((uint)0x01000000)
375#define FEC_ENET_MII ((uint)0x00800000)
376#define FEC_ENET_EBERR ((uint)0x00400000)
377#define FEC_ENET_WAKEUP ((uint)0x00020000)
378#define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
379#define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
380#define FEC_ENET_TS_AVAIL ((uint)0x00010000)
381#define FEC_ENET_TS_TIMER ((uint)0x00008000)
382
383#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF)
384#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
385
386#define FEC_ENET_TXC_DLY ((uint)0x00010000)
387#define FEC_ENET_RXC_DLY ((uint)0x00020000)
388
389
390#define FEC_ITR_CLK_SEL (0x1 << 30)
391#define FEC_ITR_EN (0x1 << 31)
392#define FEC_ITR_ICFT(X) (((X) & 0xff) << 20)
393#define FEC_ITR_ICTT(X) ((X) & 0xffff)
394#define FEC_ITR_ICFT_DEFAULT 200
395#define FEC_ITR_ICTT_DEFAULT 1000
396
397#define FEC_VLAN_TAG_LEN 0x04
398#define FEC_ETHTYPE_LEN 0x02
399
400
401#define FEC_QUIRK_ENET_MAC (1 << 0)
402
403#define FEC_QUIRK_SWAP_FRAME (1 << 1)
404
405#define FEC_QUIRK_USE_GASKET (1 << 2)
406
407#define FEC_QUIRK_HAS_GBIT (1 << 3)
408
409#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
410
411#define FEC_QUIRK_HAS_CSUM (1 << 5)
412
413#define FEC_QUIRK_HAS_VLAN (1 << 6)
414
415
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417
418
419
420
421
422
423#define FEC_QUIRK_ERR006358 (1 << 7)
424
425
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427
428
429
430
431
432
433#define FEC_QUIRK_HAS_AVB (1 << 8)
434
435
436
437
438
439#define FEC_QUIRK_ERR007885 (1 << 9)
440
441
442
443
444
445
446
447
448#define FEC_QUIRK_BUG_CAPTURE (1 << 10)
449
450#define FEC_QUIRK_SINGLE_MDIO (1 << 11)
451
452#define FEC_QUIRK_HAS_RACC (1 << 12)
453
454#define FEC_QUIRK_HAS_COALESCE (1 << 13)
455
456#define FEC_QUIRK_ERR006687 (1 << 14)
457
458
459
460#define FEC_QUIRK_MIB_CLEAR (1 << 15)
461
462
463
464#define FEC_QUIRK_HAS_FRREG (1 << 16)
465
466
467
468
469
470#define FEC_QUIRK_CLEAR_SETUP_MII (1 << 17)
471
472
473
474
475#define FEC_QUIRK_NO_HARD_RESET (1 << 18)
476
477
478
479
480#define FEC_QUIRK_HAS_MULTI_QUEUES (1 << 19)
481
482
483
484
485
486#define FEC_QUIRK_HAS_EEE (1 << 20)
487
488
489
490
491
492
493#define FEC_QUIRK_DELAYED_CLKS_SUPPORT (1 << 21)
494
495
496#define FEC_QUIRK_WAKEUP_FROM_INT2 (1 << 22)
497
498struct bufdesc_prop {
499 int qid;
500
501 struct bufdesc *base;
502 struct bufdesc *last;
503 struct bufdesc *cur;
504 void __iomem *reg_desc_active;
505 dma_addr_t dma;
506 unsigned short ring_size;
507 unsigned char dsize;
508 unsigned char dsize_log2;
509};
510
511struct fec_enet_priv_tx_q {
512 struct bufdesc_prop bd;
513 unsigned char *tx_bounce[TX_RING_SIZE];
514 struct sk_buff *tx_skbuff[TX_RING_SIZE];
515
516 unsigned short tx_stop_threshold;
517 unsigned short tx_wake_threshold;
518
519 struct bufdesc *dirty_tx;
520 char *tso_hdrs;
521 dma_addr_t tso_hdrs_dma;
522};
523
524struct fec_enet_priv_rx_q {
525 struct bufdesc_prop bd;
526 struct sk_buff *rx_skbuff[RX_RING_SIZE];
527};
528
529struct fec_stop_mode_gpr {
530 struct regmap *gpr;
531 u8 reg;
532 u8 bit;
533};
534
535
536
537
538
539
540
541
542
543struct fec_enet_private {
544
545 void __iomem *hwp;
546
547 struct net_device *netdev;
548
549 struct clk *clk_ipg;
550 struct clk *clk_ahb;
551 struct clk *clk_ref;
552 struct clk *clk_enet_out;
553 struct clk *clk_ptp;
554 struct clk *clk_2x_txclk;
555
556 bool ptp_clk_on;
557 struct mutex ptp_clk_mutex;
558 unsigned int num_tx_queues;
559 unsigned int num_rx_queues;
560
561
562 struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
563 struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
564
565 unsigned int total_tx_ring_size;
566 unsigned int total_rx_ring_size;
567
568 struct platform_device *pdev;
569
570 int dev_id;
571
572
573 struct mii_bus *mii_bus;
574 uint phy_speed;
575 phy_interface_t phy_interface;
576 struct device_node *phy_node;
577 bool rgmii_txc_dly;
578 bool rgmii_rxc_dly;
579 int link;
580 int full_duplex;
581 int speed;
582 int irq[FEC_IRQ_NUM];
583 bool bufdesc_ex;
584 int pause_flag;
585 int wol_flag;
586 int wake_irq;
587 u32 quirks;
588
589 struct napi_struct napi;
590 int csum_flags;
591
592 struct work_struct tx_timeout_work;
593
594 struct ptp_clock *ptp_clock;
595 struct ptp_clock_info ptp_caps;
596 unsigned long last_overflow_check;
597 spinlock_t tmreg_lock;
598 struct cyclecounter cc;
599 struct timecounter tc;
600 int rx_hwtstamp_filter;
601 u32 base_incval;
602 u32 cycle_speed;
603 int hwts_rx_en;
604 int hwts_tx_en;
605 struct delayed_work time_keep;
606 struct regulator *reg_phy;
607 struct fec_stop_mode_gpr stop_gpr;
608
609 unsigned int tx_align;
610 unsigned int rx_align;
611
612
613 unsigned int rx_pkts_itr;
614 unsigned int rx_time_itr;
615 unsigned int tx_pkts_itr;
616 unsigned int tx_time_itr;
617 unsigned int itr_clk_rate;
618
619
620 struct ethtool_eee eee;
621 unsigned int clk_ref_rate;
622
623 u32 rx_copybreak;
624
625
626 unsigned int ptp_inc;
627
628
629 int pps_channel;
630 unsigned int reload_period;
631 int pps_enable;
632 unsigned int next_counter;
633
634 u64 ethtool_stats[];
635};
636
637void fec_ptp_init(struct platform_device *pdev, int irq_idx);
638void fec_ptp_stop(struct platform_device *pdev);
639void fec_ptp_start_cyclecounter(struct net_device *ndev);
640void fec_ptp_disable_hwts(struct net_device *ndev);
641int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
642int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
643
644
645#endif
646