1
2
3
4#ifndef __HNS3_ENET_H
5#define __HNS3_ENET_H
6
7#include <linux/dim.h>
8#include <linux/if_vlan.h>
9#include <net/page_pool.h>
10
11#include "hnae3.h"
12
13enum hns3_nic_state {
14 HNS3_NIC_STATE_TESTING,
15 HNS3_NIC_STATE_RESETTING,
16 HNS3_NIC_STATE_INITED,
17 HNS3_NIC_STATE_DOWN,
18 HNS3_NIC_STATE_DISABLED,
19 HNS3_NIC_STATE_REMOVING,
20 HNS3_NIC_STATE_SERVICE_INITED,
21 HNS3_NIC_STATE_SERVICE_SCHED,
22 HNS3_NIC_STATE2_RESET_REQUESTED,
23 HNS3_NIC_STATE_HW_TX_CSUM_ENABLE,
24 HNS3_NIC_STATE_RXD_ADV_LAYOUT_ENABLE,
25 HNS3_NIC_STATE_MAX
26};
27
28#define HNS3_RING_RX_RING_BASEADDR_L_REG 0x00000
29#define HNS3_RING_RX_RING_BASEADDR_H_REG 0x00004
30#define HNS3_RING_RX_RING_BD_NUM_REG 0x00008
31#define HNS3_RING_RX_RING_BD_LEN_REG 0x0000C
32#define HNS3_RING_RX_RING_TAIL_REG 0x00018
33#define HNS3_RING_RX_RING_HEAD_REG 0x0001C
34#define HNS3_RING_RX_RING_FBDNUM_REG 0x00020
35#define HNS3_RING_RX_RING_PKTNUM_RECORD_REG 0x0002C
36
37#define HNS3_RING_TX_RING_BASEADDR_L_REG 0x00040
38#define HNS3_RING_TX_RING_BASEADDR_H_REG 0x00044
39#define HNS3_RING_TX_RING_BD_NUM_REG 0x00048
40#define HNS3_RING_TX_RING_TC_REG 0x00050
41#define HNS3_RING_TX_RING_TAIL_REG 0x00058
42#define HNS3_RING_TX_RING_HEAD_REG 0x0005C
43#define HNS3_RING_TX_RING_FBDNUM_REG 0x00060
44#define HNS3_RING_TX_RING_OFFSET_REG 0x00064
45#define HNS3_RING_TX_RING_EBDNUM_REG 0x00068
46#define HNS3_RING_TX_RING_PKTNUM_RECORD_REG 0x0006C
47#define HNS3_RING_TX_RING_EBD_OFFSET_REG 0x00070
48#define HNS3_RING_TX_RING_BD_ERR_REG 0x00074
49#define HNS3_RING_EN_REG 0x00090
50#define HNS3_RING_RX_EN_REG 0x00098
51#define HNS3_RING_TX_EN_REG 0x000D4
52
53#define HNS3_RX_HEAD_SIZE 256
54
55#define HNS3_TX_TIMEOUT (5 * HZ)
56#define HNS3_RING_NAME_LEN 16
57#define HNS3_BUFFER_SIZE_2048 2048
58#define HNS3_RING_MAX_PENDING 32760
59#define HNS3_RING_MIN_PENDING 72
60#define HNS3_RING_BD_MULTIPLE 8
61
62#define HNS3_MAX_MTU(max_frm_size) \
63 ((max_frm_size) - (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN))
64
65#define HNS3_BD_SIZE_512_TYPE 0
66#define HNS3_BD_SIZE_1024_TYPE 1
67#define HNS3_BD_SIZE_2048_TYPE 2
68#define HNS3_BD_SIZE_4096_TYPE 3
69
70#define HNS3_RX_FLAG_VLAN_PRESENT 0x1
71#define HNS3_RX_FLAG_L3ID_IPV4 0x0
72#define HNS3_RX_FLAG_L3ID_IPV6 0x1
73#define HNS3_RX_FLAG_L4ID_UDP 0x0
74#define HNS3_RX_FLAG_L4ID_TCP 0x1
75
76#define HNS3_RXD_DMAC_S 0
77#define HNS3_RXD_DMAC_M (0x3 << HNS3_RXD_DMAC_S)
78#define HNS3_RXD_VLAN_S 2
79#define HNS3_RXD_VLAN_M (0x3 << HNS3_RXD_VLAN_S)
80#define HNS3_RXD_L3ID_S 4
81#define HNS3_RXD_L3ID_M (0xf << HNS3_RXD_L3ID_S)
82#define HNS3_RXD_L4ID_S 8
83#define HNS3_RXD_L4ID_M (0xf << HNS3_RXD_L4ID_S)
84#define HNS3_RXD_FRAG_B 12
85#define HNS3_RXD_STRP_TAGP_S 13
86#define HNS3_RXD_STRP_TAGP_M (0x3 << HNS3_RXD_STRP_TAGP_S)
87
88#define HNS3_RXD_L2E_B 16
89#define HNS3_RXD_L3E_B 17
90#define HNS3_RXD_L4E_B 18
91#define HNS3_RXD_TRUNCAT_B 19
92#define HNS3_RXD_HOI_B 20
93#define HNS3_RXD_DOI_B 21
94#define HNS3_RXD_OL3E_B 22
95#define HNS3_RXD_OL4E_B 23
96#define HNS3_RXD_GRO_COUNT_S 24
97#define HNS3_RXD_GRO_COUNT_M (0x3f << HNS3_RXD_GRO_COUNT_S)
98#define HNS3_RXD_GRO_FIXID_B 30
99#define HNS3_RXD_GRO_ECN_B 31
100
101#define HNS3_RXD_ODMAC_S 0
102#define HNS3_RXD_ODMAC_M (0x3 << HNS3_RXD_ODMAC_S)
103#define HNS3_RXD_OVLAN_S 2
104#define HNS3_RXD_OVLAN_M (0x3 << HNS3_RXD_OVLAN_S)
105#define HNS3_RXD_OL3ID_S 4
106#define HNS3_RXD_OL3ID_M (0xf << HNS3_RXD_OL3ID_S)
107#define HNS3_RXD_OL4ID_S 8
108#define HNS3_RXD_OL4ID_M (0xf << HNS3_RXD_OL4ID_S)
109#define HNS3_RXD_FBHI_S 12
110#define HNS3_RXD_FBHI_M (0x3 << HNS3_RXD_FBHI_S)
111#define HNS3_RXD_FBLI_S 14
112#define HNS3_RXD_FBLI_M (0x3 << HNS3_RXD_FBLI_S)
113
114#define HNS3_RXD_PTYPE_S 4
115#define HNS3_RXD_PTYPE_M GENMASK(11, 4)
116
117#define HNS3_RXD_BDTYPE_S 0
118#define HNS3_RXD_BDTYPE_M (0xf << HNS3_RXD_BDTYPE_S)
119#define HNS3_RXD_VLD_B 4
120#define HNS3_RXD_UDP0_B 5
121#define HNS3_RXD_EXTEND_B 7
122#define HNS3_RXD_FE_B 8
123#define HNS3_RXD_LUM_B 9
124#define HNS3_RXD_CRCP_B 10
125#define HNS3_RXD_L3L4P_B 11
126#define HNS3_RXD_TSIDX_S 12
127#define HNS3_RXD_TSIDX_M (0x3 << HNS3_RXD_TSIDX_S)
128#define HNS3_RXD_TS_VLD_B 14
129#define HNS3_RXD_LKBK_B 15
130#define HNS3_RXD_GRO_SIZE_S 16
131#define HNS3_RXD_GRO_SIZE_M (0x3fff << HNS3_RXD_GRO_SIZE_S)
132
133#define HNS3_TXD_L3T_S 0
134#define HNS3_TXD_L3T_M (0x3 << HNS3_TXD_L3T_S)
135#define HNS3_TXD_L4T_S 2
136#define HNS3_TXD_L4T_M (0x3 << HNS3_TXD_L4T_S)
137#define HNS3_TXD_L3CS_B 4
138#define HNS3_TXD_L4CS_B 5
139#define HNS3_TXD_VLAN_B 6
140#define HNS3_TXD_TSO_B 7
141
142#define HNS3_TXD_L2LEN_S 8
143#define HNS3_TXD_L2LEN_M (0xff << HNS3_TXD_L2LEN_S)
144#define HNS3_TXD_L3LEN_S 16
145#define HNS3_TXD_L3LEN_M (0xff << HNS3_TXD_L3LEN_S)
146#define HNS3_TXD_L4LEN_S 24
147#define HNS3_TXD_L4LEN_M (0xff << HNS3_TXD_L4LEN_S)
148
149#define HNS3_TXD_CSUM_START_S 8
150#define HNS3_TXD_CSUM_START_M (0xffff << HNS3_TXD_CSUM_START_S)
151
152#define HNS3_TXD_OL3T_S 0
153#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
154#define HNS3_TXD_OVLAN_B 2
155#define HNS3_TXD_MACSEC_B 3
156#define HNS3_TXD_TUNTYPE_S 4
157#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
158
159#define HNS3_TXD_CSUM_OFFSET_S 8
160#define HNS3_TXD_CSUM_OFFSET_M (0xffff << HNS3_TXD_CSUM_OFFSET_S)
161
162#define HNS3_TXD_BDTYPE_S 0
163#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
164#define HNS3_TXD_FE_B 4
165#define HNS3_TXD_SC_S 5
166#define HNS3_TXD_SC_M (0x3 << HNS3_TXD_SC_S)
167#define HNS3_TXD_EXTEND_B 7
168#define HNS3_TXD_VLD_B 8
169#define HNS3_TXD_RI_B 9
170#define HNS3_TXD_RA_B 10
171#define HNS3_TXD_TSYN_B 11
172#define HNS3_TXD_DECTTL_S 12
173#define HNS3_TXD_DECTTL_M (0xf << HNS3_TXD_DECTTL_S)
174
175#define HNS3_TXD_OL4CS_B 22
176
177#define HNS3_TXD_MSS_S 0
178#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
179#define HNS3_TXD_HW_CS_B 14
180
181#define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
182#define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
183
184#define HNS3_VECTOR_NOT_INITED 0
185#define HNS3_VECTOR_INITED 1
186
187#define HNS3_MAX_BD_SIZE 65535
188#define HNS3_MAX_TSO_BD_NUM 63U
189#define HNS3_MAX_TSO_SIZE 1048576U
190#define HNS3_MAX_NON_TSO_SIZE 9728U
191
192
193#define HNS3_VECTOR_GL0_OFFSET 0x100
194#define HNS3_VECTOR_GL1_OFFSET 0x200
195#define HNS3_VECTOR_GL2_OFFSET 0x300
196#define HNS3_VECTOR_RL_OFFSET 0x900
197#define HNS3_VECTOR_RL_EN_B 6
198#define HNS3_VECTOR_TX_QL_OFFSET 0xe00
199#define HNS3_VECTOR_RX_QL_OFFSET 0xf00
200
201#define HNS3_RING_EN_B 0
202
203#define HNS3_GL0_CQ_MODE_REG 0x20d00
204#define HNS3_GL1_CQ_MODE_REG 0x20d04
205#define HNS3_GL2_CQ_MODE_REG 0x20d08
206#define HNS3_CQ_MODE_EQE 1U
207#define HNS3_CQ_MODE_CQE 0U
208
209enum hns3_pkt_l2t_type {
210 HNS3_L2_TYPE_UNICAST,
211 HNS3_L2_TYPE_MULTICAST,
212 HNS3_L2_TYPE_BROADCAST,
213 HNS3_L2_TYPE_INVALID,
214};
215
216enum hns3_pkt_l3t_type {
217 HNS3_L3T_NONE,
218 HNS3_L3T_IPV6,
219 HNS3_L3T_IPV4,
220 HNS3_L3T_RESERVED
221};
222
223enum hns3_pkt_l4t_type {
224 HNS3_L4T_UNKNOWN,
225 HNS3_L4T_TCP,
226 HNS3_L4T_UDP,
227 HNS3_L4T_SCTP
228};
229
230enum hns3_pkt_ol3t_type {
231 HNS3_OL3T_NONE,
232 HNS3_OL3T_IPV6,
233 HNS3_OL3T_IPV4_NO_CSUM,
234 HNS3_OL3T_IPV4_CSUM
235};
236
237enum hns3_pkt_tun_type {
238 HNS3_TUN_NONE,
239 HNS3_TUN_MAC_IN_UDP,
240 HNS3_TUN_NVGRE,
241 HNS3_TUN_OTHER
242};
243
244
245struct __packed hns3_desc {
246 union {
247 __le64 addr;
248 __le16 csum;
249 struct {
250 __le32 ts_nsec;
251 __le32 ts_sec;
252 };
253 };
254 union {
255 struct {
256 __le16 vlan_tag;
257 __le16 send_size;
258 union {
259 __le32 type_cs_vlan_tso_len;
260 struct {
261 __u8 type_cs_vlan_tso;
262 __u8 l2_len;
263 __u8 l3_len;
264 __u8 l4_len;
265 };
266 };
267 __le16 outer_vlan_tag;
268 __le16 tv;
269
270 union {
271 __le32 ol_type_vlan_len_msec;
272 struct {
273 __u8 ol_type_vlan_msec;
274 __u8 ol2_len;
275 __u8 ol3_len;
276 __u8 ol4_len;
277 };
278 };
279
280 __le32 paylen_ol4cs;
281 __le16 bdtp_fe_sc_vld_ra_ri;
282 __le16 mss_hw_csum;
283 } tx;
284
285 struct {
286 __le32 l234_info;
287 __le16 pkt_len;
288 __le16 size;
289
290 __le32 rss_hash;
291 __le16 fd_id;
292 __le16 vlan_tag;
293
294 union {
295 __le32 ol_info;
296 struct {
297 __le16 o_dm_vlan_id_fb;
298 __le16 ot_vlan_tag;
299 };
300 };
301
302 __le32 bd_base_info;
303 } rx;
304 };
305};
306
307enum hns3_desc_type {
308 DESC_TYPE_UNKNOWN = 0,
309 DESC_TYPE_SKB = 1 << 0,
310 DESC_TYPE_FRAGLIST_SKB = 1 << 1,
311 DESC_TYPE_PAGE = 1 << 2,
312 DESC_TYPE_BOUNCE_ALL = 1 << 3,
313 DESC_TYPE_BOUNCE_HEAD = 1 << 4,
314 DESC_TYPE_SGL_SKB = 1 << 5,
315 DESC_TYPE_PP_FRAG = 1 << 6,
316};
317
318struct hns3_desc_cb {
319 dma_addr_t dma;
320 void *buf;
321
322
323 void *priv;
324
325 union {
326 u32 page_offset;
327 u32 send_bytes;
328 };
329
330 u32 length;
331
332 u16 reuse_flag;
333 u16 refill;
334
335
336 u16 type;
337 u16 pagecnt_bias;
338};
339
340enum hns3_pkt_l3type {
341 HNS3_L3_TYPE_IPV4,
342 HNS3_L3_TYPE_IPV6,
343 HNS3_L3_TYPE_ARP,
344 HNS3_L3_TYPE_RARP,
345 HNS3_L3_TYPE_IPV4_OPT,
346 HNS3_L3_TYPE_IPV6_EXT,
347 HNS3_L3_TYPE_LLDP,
348 HNS3_L3_TYPE_BPDU,
349 HNS3_L3_TYPE_MAC_PAUSE,
350 HNS3_L3_TYPE_PFC_PAUSE,
351
352
353
354 HNS3_L3_TYPE_CNM = 0xc,
355
356
357
358 HNS3_L3_TYPE_PARSE_FAIL = 0xf
359};
360
361enum hns3_pkt_l4type {
362 HNS3_L4_TYPE_UDP,
363 HNS3_L4_TYPE_TCP,
364 HNS3_L4_TYPE_GRE,
365 HNS3_L4_TYPE_SCTP,
366 HNS3_L4_TYPE_IGMP,
367 HNS3_L4_TYPE_ICMP,
368
369
370
371 HNS3_L4_TYPE_PARSE_FAIL = 0xf
372};
373
374enum hns3_pkt_ol3type {
375 HNS3_OL3_TYPE_IPV4 = 0,
376 HNS3_OL3_TYPE_IPV6,
377
378 HNS3_OL3_TYPE_IPV4_OPT = 4,
379 HNS3_OL3_TYPE_IPV6_EXT,
380
381
382
383 HNS3_OL3_TYPE_PARSE_FAIL = 0xf
384};
385
386enum hns3_pkt_ol4type {
387 HNS3_OL4_TYPE_NO_TUN,
388 HNS3_OL4_TYPE_MAC_IN_UDP,
389 HNS3_OL4_TYPE_NVGRE,
390 HNS3_OL4_TYPE_UNKNOWN
391};
392
393struct hns3_rx_ptype {
394 u32 ptype : 8;
395 u32 csum_level : 2;
396 u32 ip_summed : 2;
397 u32 l3_type : 4;
398 u32 valid : 1;
399};
400
401struct ring_stats {
402 u64 sw_err_cnt;
403 u64 seg_pkt_cnt;
404 union {
405 struct {
406 u64 tx_pkts;
407 u64 tx_bytes;
408 u64 tx_more;
409 u64 restart_queue;
410 u64 tx_busy;
411 u64 tx_copy;
412 u64 tx_vlan_err;
413 u64 tx_l4_proto_err;
414 u64 tx_l2l3l4_err;
415 u64 tx_tso_err;
416 u64 over_max_recursion;
417 u64 hw_limitation;
418 u64 tx_bounce;
419 u64 tx_spare_full;
420 u64 copy_bits_err;
421 u64 tx_sgl;
422 u64 skb2sgl_err;
423 u64 map_sg_err;
424 };
425 struct {
426 u64 rx_pkts;
427 u64 rx_bytes;
428 u64 rx_err_cnt;
429 u64 reuse_pg_cnt;
430 u64 err_pkt_len;
431 u64 err_bd_num;
432 u64 l2_err;
433 u64 l3l4_csum_err;
434 u64 csum_complete;
435 u64 rx_multicast;
436 u64 non_reuse_pg;
437 u64 frag_alloc_err;
438 u64 frag_alloc;
439 };
440 __le16 csum;
441 };
442};
443
444struct hns3_tx_spare {
445 dma_addr_t dma;
446 void *buf;
447 u32 next_to_use;
448 u32 next_to_clean;
449 u32 last_to_clean;
450 u32 len;
451};
452
453struct hns3_enet_ring {
454 struct hns3_desc *desc;
455 struct hns3_desc_cb *desc_cb;
456 struct hns3_enet_ring *next;
457 struct hns3_enet_tqp_vector *tqp_vector;
458 struct hnae3_queue *tqp;
459 int queue_index;
460 struct device *dev;
461 struct page_pool *page_pool;
462
463
464 struct ring_stats stats;
465 struct u64_stats_sync syncp;
466
467 dma_addr_t desc_dma_addr;
468 u32 buf_size;
469 u16 desc_num;
470 int next_to_use;
471
472
473
474
475 int next_to_clean;
476 u32 flag;
477
478 int pending_buf;
479 union {
480
481 struct {
482 u32 fd_qb_tx_sample;
483 int last_to_use;
484 u32 tx_copybreak;
485 struct hns3_tx_spare *tx_spare;
486 };
487
488
489 struct {
490 u32 pull_len;
491 u32 rx_copybreak;
492 u32 frag_num;
493
494 unsigned char *va;
495 struct sk_buff *skb;
496 struct sk_buff *tail_skb;
497 };
498 };
499} ____cacheline_internodealigned_in_smp;
500
501enum hns3_flow_level_range {
502 HNS3_FLOW_LOW = 0,
503 HNS3_FLOW_MID = 1,
504 HNS3_FLOW_HIGH = 2,
505 HNS3_FLOW_ULTRA = 3,
506};
507
508#define HNS3_INT_GL_50K 0x0014
509#define HNS3_INT_GL_20K 0x0032
510#define HNS3_INT_GL_18K 0x0036
511#define HNS3_INT_GL_8K 0x007C
512
513#define HNS3_INT_GL_1US BIT(31)
514
515#define HNS3_INT_RL_MAX 0x00EC
516#define HNS3_INT_RL_ENABLE_MASK 0x40
517
518#define HNS3_INT_QL_DEFAULT_CFG 0x20
519
520struct hns3_enet_coalesce {
521 u16 int_gl;
522 u16 int_ql;
523 u16 int_ql_max;
524 u8 adapt_enable : 1;
525 u8 ql_enable : 1;
526 u8 unit_1us : 1;
527 enum hns3_flow_level_range flow_level;
528};
529
530struct hns3_enet_ring_group {
531
532 struct hns3_enet_ring *ring;
533 u64 total_bytes;
534 u64 total_packets;
535 u16 count;
536 struct hns3_enet_coalesce coal;
537 struct dim dim;
538};
539
540struct hns3_enet_tqp_vector {
541 struct hnae3_handle *handle;
542 u8 __iomem *mask_addr;
543 int vector_irq;
544 int irq_init_flag;
545
546 u16 idx;
547
548 struct napi_struct napi;
549
550 struct hns3_enet_ring_group rx_group;
551 struct hns3_enet_ring_group tx_group;
552
553 cpumask_t affinity_mask;
554 u16 num_tqps;
555 struct irq_affinity_notify affinity_notify;
556
557 char name[HNAE3_INT_NAME_LEN];
558
559 u64 event_cnt;
560} ____cacheline_internodealigned_in_smp;
561
562struct hns3_nic_priv {
563 struct hnae3_handle *ae_handle;
564 struct net_device *netdev;
565 struct device *dev;
566
567
568
569
570
571 struct hns3_enet_ring *ring;
572 struct hns3_enet_tqp_vector *tqp_vector;
573 u16 vector_num;
574 u8 max_non_tso_bd_num;
575
576 u64 tx_timeout_count;
577
578 unsigned long state;
579
580 enum dim_cq_period_mode tx_cqe_mode;
581 enum dim_cq_period_mode rx_cqe_mode;
582 struct hns3_enet_coalesce tx_coal;
583 struct hns3_enet_coalesce rx_coal;
584 u32 tx_copybreak;
585 u32 rx_copybreak;
586};
587
588union l3_hdr_info {
589 struct iphdr *v4;
590 struct ipv6hdr *v6;
591 unsigned char *hdr;
592};
593
594union l4_hdr_info {
595 struct tcphdr *tcp;
596 struct udphdr *udp;
597 struct gre_base_hdr *gre;
598 unsigned char *hdr;
599};
600
601struct hns3_hw_error_info {
602 enum hnae3_hw_error_type type;
603 const char *msg;
604};
605
606struct hns3_reset_type_map {
607 enum ethtool_reset_flags rst_flags;
608 enum hnae3_reset_type rst_type;
609};
610
611static inline int ring_space(struct hns3_enet_ring *ring)
612{
613
614
615
616 int begin = smp_load_acquire(&ring->next_to_clean);
617 int end = READ_ONCE(ring->next_to_use);
618
619 return ((end >= begin) ? (ring->desc_num - end + begin) :
620 (begin - end)) - 1;
621}
622
623static inline u32 hns3_read_reg(void __iomem *base, u32 reg)
624{
625 return readl(base + reg);
626}
627
628static inline void hns3_write_reg(void __iomem *base, u32 reg, u32 value)
629{
630 u8 __iomem *reg_addr = READ_ONCE(base);
631
632 writel(value, reg_addr + reg);
633}
634
635#define hns3_read_dev(a, reg) \
636 hns3_read_reg((a)->io_base, reg)
637
638static inline bool hns3_nic_resetting(struct net_device *netdev)
639{
640 struct hns3_nic_priv *priv = netdev_priv(netdev);
641
642 return test_bit(HNS3_NIC_STATE_RESETTING, &priv->state);
643}
644
645#define hns3_write_dev(a, reg, value) \
646 hns3_write_reg((a)->io_base, reg, value)
647
648#define ring_to_dev(ring) ((ring)->dev)
649
650#define ring_to_netdev(ring) ((ring)->tqp_vector->napi.dev)
651
652#define ring_to_dma_dir(ring) (HNAE3_IS_TX_RING(ring) ? \
653 DMA_TO_DEVICE : DMA_FROM_DEVICE)
654
655#define hns3_buf_size(_ring) ((_ring)->buf_size)
656
657static inline unsigned int hns3_page_order(struct hns3_enet_ring *ring)
658{
659#if (PAGE_SIZE < 8192)
660 if (ring->buf_size > (PAGE_SIZE / 2))
661 return 1;
662#endif
663 return 0;
664}
665
666#define hns3_page_size(_ring) (PAGE_SIZE << hns3_page_order(_ring))
667
668
669#define hns3_for_each_ring(pos, head) \
670 for (pos = (head).ring; (pos); pos = (pos)->next)
671
672#define hns3_get_handle(ndev) \
673 (((struct hns3_nic_priv *)netdev_priv(ndev))->ae_handle)
674
675#define hns3_gl_usec_to_reg(int_gl) ((int_gl) >> 1)
676#define hns3_gl_round_down(int_gl) round_down(int_gl, 2)
677
678#define hns3_rl_usec_to_reg(int_rl) ((int_rl) >> 2)
679#define hns3_rl_round_down(int_rl) round_down(int_rl, 4)
680
681void hns3_ethtool_set_ops(struct net_device *netdev);
682int hns3_set_channels(struct net_device *netdev,
683 struct ethtool_channels *ch);
684
685void hns3_clean_tx_ring(struct hns3_enet_ring *ring, int budget);
686int hns3_init_all_ring(struct hns3_nic_priv *priv);
687int hns3_nic_reset_all_ring(struct hnae3_handle *h);
688void hns3_fini_ring(struct hns3_enet_ring *ring);
689netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
690bool hns3_is_phys_func(struct pci_dev *pdev);
691int hns3_clean_rx_ring(
692 struct hns3_enet_ring *ring, int budget,
693 void (*rx_fn)(struct hns3_enet_ring *, struct sk_buff *));
694
695void hns3_set_vector_coalesce_rx_gl(struct hns3_enet_tqp_vector *tqp_vector,
696 u32 gl_value);
697void hns3_set_vector_coalesce_tx_gl(struct hns3_enet_tqp_vector *tqp_vector,
698 u32 gl_value);
699void hns3_set_vector_coalesce_rl(struct hns3_enet_tqp_vector *tqp_vector,
700 u32 rl_value);
701void hns3_set_vector_coalesce_rx_ql(struct hns3_enet_tqp_vector *tqp_vector,
702 u32 ql_value);
703void hns3_set_vector_coalesce_tx_ql(struct hns3_enet_tqp_vector *tqp_vector,
704 u32 ql_value);
705
706void hns3_request_update_promisc_mode(struct hnae3_handle *handle);
707
708#ifdef CONFIG_HNS3_DCB
709void hns3_dcbnl_setup(struct hnae3_handle *handle);
710#else
711static inline void hns3_dcbnl_setup(struct hnae3_handle *handle) {}
712#endif
713
714int hns3_dbg_init(struct hnae3_handle *handle);
715void hns3_dbg_uninit(struct hnae3_handle *handle);
716void hns3_dbg_register_debugfs(const char *debugfs_dir_name);
717void hns3_dbg_unregister_debugfs(void);
718void hns3_shinfo_pack(struct skb_shared_info *shinfo, __u32 *size);
719u16 hns3_get_max_available_channels(struct hnae3_handle *h);
720void hns3_cq_period_mode_init(struct hns3_nic_priv *priv,
721 enum dim_cq_period_mode tx_mode,
722 enum dim_cq_period_mode rx_mode);
723#endif
724