1
2
3
4#ifndef __HCLGE_CMD_H
5#define __HCLGE_CMD_H
6#include <linux/types.h>
7#include <linux/io.h>
8#include <linux/etherdevice.h>
9#include "hnae3.h"
10
11#define HCLGE_CMDQ_TX_TIMEOUT 30000
12#define HCLGE_CMDQ_CLEAR_WAIT_TIME 200
13#define HCLGE_DESC_DATA_LEN 6
14
15struct hclge_dev;
16struct hclge_desc {
17 __le16 opcode;
18
19#define HCLGE_CMDQ_RX_INVLD_B 0
20#define HCLGE_CMDQ_RX_OUTVLD_B 1
21
22 __le16 flag;
23 __le16 retval;
24 __le16 rsv;
25 __le32 data[HCLGE_DESC_DATA_LEN];
26};
27
28struct hclge_cmq_ring {
29 dma_addr_t desc_dma_addr;
30 struct hclge_desc *desc;
31 struct hclge_dev *dev;
32 u32 head;
33 u32 tail;
34
35 u16 buf_size;
36 u16 desc_num;
37 int next_to_use;
38 int next_to_clean;
39 u8 ring_type;
40 spinlock_t lock;
41};
42
43enum hclge_cmd_return_status {
44 HCLGE_CMD_EXEC_SUCCESS = 0,
45 HCLGE_CMD_NO_AUTH = 1,
46 HCLGE_CMD_NOT_SUPPORTED = 2,
47 HCLGE_CMD_QUEUE_FULL = 3,
48 HCLGE_CMD_NEXT_ERR = 4,
49 HCLGE_CMD_UNEXE_ERR = 5,
50 HCLGE_CMD_PARA_ERR = 6,
51 HCLGE_CMD_RESULT_ERR = 7,
52 HCLGE_CMD_TIMEOUT = 8,
53 HCLGE_CMD_HILINK_ERR = 9,
54 HCLGE_CMD_QUEUE_ILLEGAL = 10,
55 HCLGE_CMD_INVALID = 11,
56};
57
58enum hclge_cmd_status {
59 HCLGE_STATUS_SUCCESS = 0,
60 HCLGE_ERR_CSQ_FULL = -1,
61 HCLGE_ERR_CSQ_TIMEOUT = -2,
62 HCLGE_ERR_CSQ_ERROR = -3,
63};
64
65struct hclge_misc_vector {
66 u8 __iomem *addr;
67 int vector_irq;
68 char name[HNAE3_INT_NAME_LEN];
69};
70
71struct hclge_cmq {
72 struct hclge_cmq_ring csq;
73 struct hclge_cmq_ring crq;
74 u16 tx_timeout;
75 enum hclge_cmd_status last_status;
76};
77
78#define HCLGE_CMD_FLAG_IN BIT(0)
79#define HCLGE_CMD_FLAG_OUT BIT(1)
80#define HCLGE_CMD_FLAG_NEXT BIT(2)
81#define HCLGE_CMD_FLAG_WR BIT(3)
82#define HCLGE_CMD_FLAG_NO_INTR BIT(4)
83#define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
84
85enum hclge_opcode_type {
86
87 HCLGE_OPC_QUERY_FW_VER = 0x0001,
88 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
89 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
90 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
91 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
92 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
93 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
94 HCLGE_OPC_PF_RST_DONE = 0x0026,
95 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
96
97 HCLGE_OPC_STATS_64_BIT = 0x0030,
98 HCLGE_OPC_STATS_32_BIT = 0x0031,
99 HCLGE_OPC_STATS_MAC = 0x0032,
100 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
101 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
102
103 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
104 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
105 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
106 HCLGE_OPC_DFX_BD_NUM = 0x0043,
107 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
108 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
109 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
110 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
111 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
112 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
113 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
114 HCLGE_OPC_DFX_RTC_REG = 0x004B,
115 HCLGE_OPC_DFX_PPP_REG = 0x004C,
116 HCLGE_OPC_DFX_RCB_REG = 0x004D,
117 HCLGE_OPC_DFX_TQP_REG = 0x004E,
118 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
119
120 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
121
122
123 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
124 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
125 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
126 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
127 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
128 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
129 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
130 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
131 HCLGE_OPC_COMMON_LOOPBACK = 0x0315,
132 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
133
134
135 HCLGE_OPC_PTP_INT_EN = 0x0501,
136 HCLGE_OPC_PTP_MODE_CFG = 0x0507,
137
138
139 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
140 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
141 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
142 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
143 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
144 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
145 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
146 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
147 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
148 HCLGE_OPC_QOS_MAP = 0x070A,
149
150
151 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
152 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
153 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
154 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
155 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
156 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
157 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
158 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
159 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
160 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
161 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
162 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
163 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
164 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
165 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
166 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
167 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
168 HCLGE_OPC_TM_NODES = 0x0816,
169 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
170 HCLGE_OPC_QSET_DFX_STS = 0x0844,
171 HCLGE_OPC_PRI_DFX_STS = 0x0845,
172 HCLGE_OPC_PG_DFX_STS = 0x0846,
173 HCLGE_OPC_PORT_DFX_STS = 0x0847,
174 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
175 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
176 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
177 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
178 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
179
180
181 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
182 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
183 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
184 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
185 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
186 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
187
188
189 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
190
191
192 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
193 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
194 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
195 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
196 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
197 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
198 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
199 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
200 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
201 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
202 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
203
204
205 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
206
207
208 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
209 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
210
211
212 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
213 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
214 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
215 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
216
217
218 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
219
220
221 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
222 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
223
224
225 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
226 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
227
228
229 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
230 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
231 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
232 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
233 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
234 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
235 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
236
237
238 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
239
240
241 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
242 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
243 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
244 HCLGE_OPC_PORT_VLAN_BYPASS = 0x1103,
245
246
247 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
248 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
249 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
250 HCLGE_OPC_FD_TCAM_OP = 0x1203,
251 HCLGE_OPC_FD_AD_OP = 0x1204,
252 HCLGE_OPC_FD_CNT_OP = 0x1205,
253 HCLGE_OPC_FD_USER_DEF_OP = 0x1207,
254
255
256 HCLGE_OPC_MDIO_CONFIG = 0x1900,
257
258
259 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
260 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
261 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
262 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
263 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
264 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
265 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
266 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
267
268
269 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
270
271
272 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
273
274
275 HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,
276
277
278 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
279
280
281 HCLGE_OPC_IMP_STATS_BD = 0x7012,
282 HCLGE_OPC_IMP_STATS_INFO = 0x7013,
283 HCLGE_OPC_IMP_COMPAT_CFG = 0x701A,
284
285
286 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
287 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
288 HCLGE_OPC_GET_SFP_INFO = 0x7104,
289
290
291 HCLGE_MAC_COMMON_INT_EN = 0x030E,
292 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
293 HCLGE_SSU_ECC_INT_CMD = 0x0989,
294 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
295 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
296 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
297 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
298 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
299 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
300 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
301 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
302 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
303 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
304 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
305 HCLGE_QUERY_ALL_ERR_BD_NUM = 0x1516,
306 HCLGE_QUERY_ALL_ERR_INFO = 0x1517,
307 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
308 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
309 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
310 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
311 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
312 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
313 HCLGE_IGU_COMMON_INT_EN = 0x1806,
314 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
315 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
316 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
317 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
318 HCLGE_NCSI_INT_EN = 0x2401,
319
320
321 HCLGE_OPC_PHY_LINK_KSETTING = 0x7025,
322 HCLGE_OPC_PHY_REG = 0x7026,
323
324
325 HCLGE_OPC_QUERY_LINK_DIAGNOSIS = 0x702A,
326};
327
328#define HCLGE_TQP_REG_OFFSET 0x80000
329#define HCLGE_TQP_REG_SIZE 0x200
330
331#define HCLGE_TQP_MAX_SIZE_DEV_V2 1024
332#define HCLGE_TQP_EXT_REG_OFFSET 0x100
333
334#define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
335#define HCLGE_RCB_INIT_FLAG_EN_B 0
336#define HCLGE_RCB_INIT_FLAG_FINI_B 8
337struct hclge_config_rcb_init_cmd {
338 __le16 rcb_init_flag;
339 u8 rsv[22];
340};
341
342struct hclge_tqp_map_cmd {
343 __le16 tqp_id;
344 u8 tqp_vf;
345#define HCLGE_TQP_MAP_TYPE_PF 0
346#define HCLGE_TQP_MAP_TYPE_VF 1
347#define HCLGE_TQP_MAP_TYPE_B 0
348#define HCLGE_TQP_MAP_EN_B 1
349 u8 tqp_flag;
350 __le16 tqp_vid;
351 u8 rsv[18];
352};
353
354#define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
355
356enum hclge_int_type {
357 HCLGE_INT_TX,
358 HCLGE_INT_RX,
359 HCLGE_INT_EVENT,
360};
361
362struct hclge_ctrl_vector_chain_cmd {
363#define HCLGE_VECTOR_ID_L_S 0
364#define HCLGE_VECTOR_ID_L_M GENMASK(7, 0)
365 u8 int_vector_id_l;
366 u8 int_cause_num;
367#define HCLGE_INT_TYPE_S 0
368#define HCLGE_INT_TYPE_M GENMASK(1, 0)
369#define HCLGE_TQP_ID_S 2
370#define HCLGE_TQP_ID_M GENMASK(12, 2)
371#define HCLGE_INT_GL_IDX_S 13
372#define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
373 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
374 u8 vfid;
375#define HCLGE_VECTOR_ID_H_S 8
376#define HCLGE_VECTOR_ID_H_M GENMASK(15, 8)
377 u8 int_vector_id_h;
378};
379
380#define HCLGE_MAX_TC_NUM 8
381#define HCLGE_TC0_PRI_BUF_EN_B 15
382#define HCLGE_BUF_UNIT_S 7
383struct hclge_tx_buff_alloc_cmd {
384 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
385 u8 tx_buff_rsv[8];
386};
387
388struct hclge_rx_priv_buff_cmd {
389 __le16 buf_num[HCLGE_MAX_TC_NUM];
390 __le16 shared_buf;
391 u8 rsv[6];
392};
393
394enum HCLGE_CAP_BITS {
395 HCLGE_CAP_UDP_GSO_B,
396 HCLGE_CAP_QB_B,
397 HCLGE_CAP_FD_FORWARD_TC_B,
398 HCLGE_CAP_PTP_B,
399 HCLGE_CAP_INT_QL_B,
400 HCLGE_CAP_HW_TX_CSUM_B,
401 HCLGE_CAP_TX_PUSH_B,
402 HCLGE_CAP_PHY_IMP_B,
403 HCLGE_CAP_TQP_TXRX_INDEP_B,
404 HCLGE_CAP_HW_PAD_B,
405 HCLGE_CAP_STASH_B,
406 HCLGE_CAP_UDP_TUNNEL_CSUM_B,
407 HCLGE_CAP_RAS_IMP_B = 12,
408 HCLGE_CAP_FEC_B = 13,
409 HCLGE_CAP_PAUSE_B = 14,
410 HCLGE_CAP_RXD_ADV_LAYOUT_B = 15,
411 HCLGE_CAP_PORT_VLAN_BYPASS_B = 17,
412};
413
414enum HCLGE_API_CAP_BITS {
415 HCLGE_API_CAP_FLEX_RSS_TBL_B,
416};
417
418#define HCLGE_QUERY_CAP_LENGTH 3
419struct hclge_query_version_cmd {
420 __le32 firmware;
421 __le32 hardware;
422 __le32 api_caps;
423 __le32 caps[HCLGE_QUERY_CAP_LENGTH];
424};
425
426#define HCLGE_RX_PRIV_EN_B 15
427#define HCLGE_TC_NUM_ONE_DESC 4
428struct hclge_priv_wl {
429 __le16 high;
430 __le16 low;
431};
432
433struct hclge_rx_priv_wl_buf {
434 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
435};
436
437struct hclge_rx_com_thrd {
438 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
439};
440
441struct hclge_rx_com_wl {
442 struct hclge_priv_wl com_wl;
443};
444
445struct hclge_waterline {
446 u32 low;
447 u32 high;
448};
449
450struct hclge_tc_thrd {
451 u32 low;
452 u32 high;
453};
454
455struct hclge_priv_buf {
456 struct hclge_waterline wl;
457 u32 buf_size;
458 u32 tx_buf_size;
459 u32 enable;
460};
461
462struct hclge_shared_buf {
463 struct hclge_waterline self;
464 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
465 u32 buf_size;
466};
467
468struct hclge_pkt_buf_alloc {
469 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
470 struct hclge_shared_buf s_buf;
471};
472
473#define HCLGE_RX_COM_WL_EN_B 15
474struct hclge_rx_com_wl_buf_cmd {
475 __le16 high_wl;
476 __le16 low_wl;
477 u8 rsv[20];
478};
479
480#define HCLGE_RX_PKT_EN_B 15
481struct hclge_rx_pkt_buf_cmd {
482 __le16 high_pkt;
483 __le16 low_pkt;
484 u8 rsv[20];
485};
486
487#define HCLGE_PF_STATE_DONE_B 0
488#define HCLGE_PF_STATE_MAIN_B 1
489#define HCLGE_PF_STATE_BOND_B 2
490#define HCLGE_PF_STATE_MAC_N_B 6
491#define HCLGE_PF_MAC_NUM_MASK 0x3
492#define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
493#define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
494#define HCLGE_VF_RST_STATUS_CMD 4
495
496struct hclge_func_status_cmd {
497 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
498 u8 pf_state;
499 u8 mac_id;
500 u8 rsv1;
501 u8 pf_cnt_in_mac;
502 u8 pf_num;
503 u8 vf_num;
504 u8 rsv[2];
505};
506
507struct hclge_pf_res_cmd {
508 __le16 tqp_num;
509 __le16 buf_size;
510 __le16 msixcap_localid_ba_nic;
511 __le16 msixcap_localid_number_nic;
512 __le16 pf_intr_vector_number_roce;
513 __le16 pf_own_fun_number;
514 __le16 tx_buf_size;
515 __le16 dv_buf_size;
516 __le16 ext_tqp_num;
517 u8 rsv[6];
518};
519
520#define HCLGE_CFG_OFFSET_S 0
521#define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
522#define HCLGE_CFG_RD_LEN_S 24
523#define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
524#define HCLGE_CFG_RD_LEN_BYTES 16
525#define HCLGE_CFG_RD_LEN_UNIT 4
526
527#define HCLGE_CFG_TC_NUM_S 8
528#define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
529#define HCLGE_CFG_TQP_DESC_N_S 16
530#define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
531#define HCLGE_CFG_PHY_ADDR_S 0
532#define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
533#define HCLGE_CFG_MEDIA_TP_S 8
534#define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
535#define HCLGE_CFG_RX_BUF_LEN_S 16
536#define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
537#define HCLGE_CFG_MAC_ADDR_H_S 0
538#define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
539#define HCLGE_CFG_DEFAULT_SPEED_S 16
540#define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
541#define HCLGE_CFG_RSS_SIZE_S 24
542#define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
543#define HCLGE_CFG_SPEED_ABILITY_S 0
544#define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
545#define HCLGE_CFG_SPEED_ABILITY_EXT_S 10
546#define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)
547#define HCLGE_CFG_VLAN_FLTR_CAP_S 8
548#define HCLGE_CFG_VLAN_FLTR_CAP_M GENMASK(9, 8)
549#define HCLGE_CFG_UMV_TBL_SPACE_S 16
550#define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
551#define HCLGE_CFG_PF_RSS_SIZE_S 0
552#define HCLGE_CFG_PF_RSS_SIZE_M GENMASK(3, 0)
553#define HCLGE_CFG_TX_SPARE_BUF_SIZE_S 4
554#define HCLGE_CFG_TX_SPARE_BUF_SIZE_M GENMASK(15, 4)
555
556#define HCLGE_CFG_CMD_CNT 4
557
558struct hclge_cfg_param_cmd {
559 __le32 offset;
560 __le32 rsv;
561 __le32 param[HCLGE_CFG_CMD_CNT];
562};
563
564#define HCLGE_MAC_MODE 0x0
565#define HCLGE_DESC_NUM 0x40
566
567#define HCLGE_ALLOC_VALID_B 0
568struct hclge_vf_num_cmd {
569 u8 alloc_valid;
570 u8 rsv[23];
571};
572
573#define HCLGE_RSS_DEFAULT_OUTPORT_B 4
574#define HCLGE_RSS_HASH_KEY_OFFSET_B 4
575#define HCLGE_RSS_HASH_KEY_NUM 16
576struct hclge_rss_config_cmd {
577 u8 hash_config;
578 u8 rsv[7];
579 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
580};
581
582struct hclge_rss_input_tuple_cmd {
583 u8 ipv4_tcp_en;
584 u8 ipv4_udp_en;
585 u8 ipv4_sctp_en;
586 u8 ipv4_fragment_en;
587 u8 ipv6_tcp_en;
588 u8 ipv6_udp_en;
589 u8 ipv6_sctp_en;
590 u8 ipv6_fragment_en;
591 u8 rsv[16];
592};
593
594#define HCLGE_RSS_CFG_TBL_SIZE 16
595#define HCLGE_RSS_CFG_TBL_SIZE_H 4
596#define HCLGE_RSS_CFG_TBL_BW_H 2U
597#define HCLGE_RSS_CFG_TBL_BW_L 8U
598
599struct hclge_rss_indirection_table_cmd {
600 __le16 start_table_index;
601 __le16 rss_set_bitmap;
602 u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H];
603 u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE];
604};
605
606#define HCLGE_RSS_TC_OFFSET_S 0
607#define HCLGE_RSS_TC_OFFSET_M GENMASK(10, 0)
608#define HCLGE_RSS_TC_SIZE_MSB_B 11
609#define HCLGE_RSS_TC_SIZE_S 12
610#define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
611#define HCLGE_RSS_TC_SIZE_MSB_OFFSET 3
612#define HCLGE_RSS_TC_VALID_B 15
613struct hclge_rss_tc_mode_cmd {
614 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
615 u8 rsv[8];
616};
617
618#define HCLGE_LINK_STATUS_UP_B 0
619#define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
620struct hclge_link_status_cmd {
621 u8 status;
622 u8 rsv[23];
623};
624
625
626#define HCLGE_PROMISC_EN_UC 1
627#define HCLGE_PROMISC_EN_MC 2
628#define HCLGE_PROMISC_EN_BC 3
629#define HCLGE_PROMISC_TX_EN 4
630#define HCLGE_PROMISC_RX_EN 5
631
632
633#define HCLGE_PROMISC_UC_RX_EN 2
634#define HCLGE_PROMISC_MC_RX_EN 3
635#define HCLGE_PROMISC_BC_RX_EN 4
636#define HCLGE_PROMISC_UC_TX_EN 5
637#define HCLGE_PROMISC_MC_TX_EN 6
638#define HCLGE_PROMISC_BC_TX_EN 7
639
640struct hclge_promisc_cfg_cmd {
641 u8 promisc;
642 u8 vf_id;
643 u8 extend_promisc;
644 u8 rsv0[21];
645};
646
647enum hclge_promisc_type {
648 HCLGE_UNICAST = 1,
649 HCLGE_MULTICAST = 2,
650 HCLGE_BROADCAST = 3,
651};
652
653#define HCLGE_MAC_TX_EN_B 6
654#define HCLGE_MAC_RX_EN_B 7
655#define HCLGE_MAC_PAD_TX_B 11
656#define HCLGE_MAC_PAD_RX_B 12
657#define HCLGE_MAC_1588_TX_B 13
658#define HCLGE_MAC_1588_RX_B 14
659#define HCLGE_MAC_APP_LP_B 15
660#define HCLGE_MAC_LINE_LP_B 16
661#define HCLGE_MAC_FCS_TX_B 17
662#define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
663#define HCLGE_MAC_RX_FCS_STRIP_B 19
664#define HCLGE_MAC_RX_FCS_B 20
665#define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
666#define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
667
668struct hclge_config_mac_mode_cmd {
669 __le32 txrx_pad_fcs_loop_en;
670 u8 rsv[20];
671};
672
673struct hclge_pf_rst_sync_cmd {
674#define HCLGE_PF_RST_ALL_VF_RDY_B 0
675 u8 all_vf_ready;
676 u8 rsv[23];
677};
678
679#define HCLGE_CFG_SPEED_S 0
680#define HCLGE_CFG_SPEED_M GENMASK(5, 0)
681
682#define HCLGE_CFG_DUPLEX_B 7
683#define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
684
685struct hclge_config_mac_speed_dup_cmd {
686 u8 speed_dup;
687
688#define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
689 u8 mac_change_fec_en;
690 u8 rsv[22];
691};
692
693#define HCLGE_TQP_ENABLE_B 0
694
695#define HCLGE_MAC_CFG_AN_EN_B 0
696#define HCLGE_MAC_CFG_AN_INT_EN_B 1
697#define HCLGE_MAC_CFG_AN_INT_MSK_B 2
698#define HCLGE_MAC_CFG_AN_INT_CLR_B 3
699#define HCLGE_MAC_CFG_AN_RST_B 4
700
701#define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
702
703struct hclge_config_auto_neg_cmd {
704 __le32 cfg_an_cmd_flag;
705 u8 rsv[20];
706};
707
708struct hclge_sfp_info_cmd {
709 __le32 speed;
710 u8 query_type;
711 u8 active_fec;
712 u8 autoneg;
713 u8 autoneg_ability;
714 __le32 speed_ability;
715 __le32 module_type;
716 u8 rsv[8];
717};
718
719#define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
720#define HCLGE_MAC_CFG_FEC_MODE_S 1
721#define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
722#define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
723#define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
724
725#define HCLGE_MAC_FEC_OFF 0
726#define HCLGE_MAC_FEC_BASER 1
727#define HCLGE_MAC_FEC_RS 2
728struct hclge_config_fec_cmd {
729 u8 fec_mode;
730 u8 default_config;
731 u8 rsv[22];
732};
733
734#define HCLGE_MAC_UPLINK_PORT 0x100
735
736struct hclge_config_max_frm_size_cmd {
737 __le16 max_frm_size;
738 u8 min_frm_size;
739 u8 rsv[21];
740};
741
742enum hclge_mac_vlan_tbl_opcode {
743 HCLGE_MAC_VLAN_ADD,
744 HCLGE_MAC_VLAN_UPDATE,
745 HCLGE_MAC_VLAN_REMOVE,
746 HCLGE_MAC_VLAN_LKUP,
747};
748
749enum hclge_mac_vlan_add_resp_code {
750 HCLGE_ADD_UC_OVERFLOW = 2,
751 HCLGE_ADD_MC_OVERFLOW,
752};
753
754#define HCLGE_MAC_VLAN_BIT0_EN_B 0
755#define HCLGE_MAC_VLAN_BIT1_EN_B 1
756#define HCLGE_MAC_EPORT_SW_EN_B 12
757#define HCLGE_MAC_EPORT_TYPE_B 11
758#define HCLGE_MAC_EPORT_VFID_S 3
759#define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
760#define HCLGE_MAC_EPORT_PFID_S 0
761#define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
762struct hclge_mac_vlan_tbl_entry_cmd {
763 u8 flags;
764 u8 resp_code;
765 __le16 vlan_tag;
766 __le32 mac_addr_hi32;
767 __le16 mac_addr_lo16;
768 __le16 rsv1;
769 u8 entry_type;
770 u8 mc_mac_en;
771 __le16 egress_port;
772 __le16 egress_queue;
773 u8 rsv2[6];
774};
775
776#define HCLGE_UMV_SPC_ALC_B 0
777struct hclge_umv_spc_alc_cmd {
778 u8 allocate;
779 u8 rsv1[3];
780 __le32 space_size;
781 u8 rsv2[16];
782};
783
784#define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
785#define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
786#define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
787
788struct hclge_mac_mgr_tbl_entry_cmd {
789 u8 flags;
790 u8 resp_code;
791 __le16 vlan_tag;
792 u8 mac_addr[ETH_ALEN];
793 __le16 rsv1;
794 __le16 ethter_type;
795 __le16 egress_port;
796 __le16 egress_queue;
797 u8 sw_port_id_aware;
798 u8 rsv2;
799 u8 i_port_bitmap;
800 u8 i_port_direction;
801 u8 rsv3[2];
802};
803
804struct hclge_vlan_filter_ctrl_cmd {
805 u8 vlan_type;
806 u8 vlan_fe;
807 u8 rsv1[2];
808 u8 vf_id;
809 u8 rsv2[19];
810};
811
812#define HCLGE_VLAN_ID_OFFSET_STEP 160
813#define HCLGE_VLAN_BYTE_SIZE 8
814#define HCLGE_VLAN_OFFSET_BITMAP \
815 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
816
817struct hclge_vlan_filter_pf_cfg_cmd {
818 u8 vlan_offset;
819 u8 vlan_cfg;
820 u8 rsv[2];
821 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
822};
823
824#define HCLGE_MAX_VF_BYTES 16
825
826struct hclge_vlan_filter_vf_cfg_cmd {
827 __le16 vlan_id;
828 u8 resp_code;
829 u8 rsv;
830 u8 vlan_cfg;
831 u8 rsv1[3];
832 u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
833};
834
835#define HCLGE_INGRESS_BYPASS_B 0
836struct hclge_port_vlan_filter_bypass_cmd {
837 u8 bypass_state;
838 u8 rsv1[3];
839 u8 vf_id;
840 u8 rsv2[19];
841};
842
843#define HCLGE_SWITCH_ANTI_SPOOF_B 0U
844#define HCLGE_SWITCH_ALW_LPBK_B 1U
845#define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
846#define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
847#define HCLGE_SWITCH_NO_MASK 0x0
848#define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
849#define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
850#define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
851#define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
852
853struct hclge_mac_vlan_switch_cmd {
854 u8 roce_sel;
855 u8 rsv1[3];
856 __le32 func_id;
857 u8 switch_param;
858 u8 rsv2[3];
859 u8 param_mask;
860 u8 rsv3[11];
861};
862
863enum hclge_mac_vlan_cfg_sel {
864 HCLGE_MAC_VLAN_NIC_SEL = 0,
865 HCLGE_MAC_VLAN_ROCE_SEL,
866};
867
868#define HCLGE_ACCEPT_TAG1_B 0
869#define HCLGE_ACCEPT_UNTAG1_B 1
870#define HCLGE_PORT_INS_TAG1_EN_B 2
871#define HCLGE_PORT_INS_TAG2_EN_B 3
872#define HCLGE_CFG_NIC_ROCE_SEL_B 4
873#define HCLGE_ACCEPT_TAG2_B 5
874#define HCLGE_ACCEPT_UNTAG2_B 6
875#define HCLGE_TAG_SHIFT_MODE_EN_B 7
876#define HCLGE_VF_NUM_PER_BYTE 8
877
878struct hclge_vport_vtag_tx_cfg_cmd {
879 u8 vport_vlan_cfg;
880 u8 vf_offset;
881 u8 rsv1[2];
882 __le16 def_vlan_tag1;
883 __le16 def_vlan_tag2;
884 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
885 u8 rsv2[8];
886};
887
888#define HCLGE_REM_TAG1_EN_B 0
889#define HCLGE_REM_TAG2_EN_B 1
890#define HCLGE_SHOW_TAG1_EN_B 2
891#define HCLGE_SHOW_TAG2_EN_B 3
892#define HCLGE_DISCARD_TAG1_EN_B 5
893#define HCLGE_DISCARD_TAG2_EN_B 6
894struct hclge_vport_vtag_rx_cfg_cmd {
895 u8 vport_vlan_cfg;
896 u8 vf_offset;
897 u8 rsv1[6];
898 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
899 u8 rsv2[8];
900};
901
902struct hclge_tx_vlan_type_cfg_cmd {
903 __le16 ot_vlan_type;
904 __le16 in_vlan_type;
905 u8 rsv[20];
906};
907
908struct hclge_rx_vlan_type_cfg_cmd {
909 __le16 ot_fst_vlan_type;
910 __le16 ot_sec_vlan_type;
911 __le16 in_fst_vlan_type;
912 __le16 in_sec_vlan_type;
913 u8 rsv[16];
914};
915
916struct hclge_cfg_com_tqp_queue_cmd {
917 __le16 tqp_id;
918 __le16 stream_id;
919 u8 enable;
920 u8 rsv[19];
921};
922
923struct hclge_cfg_tx_queue_pointer_cmd {
924 __le16 tqp_id;
925 __le16 tx_tail;
926 __le16 tx_head;
927 __le16 fbd_num;
928 __le16 ring_offset;
929 u8 rsv[14];
930};
931
932#pragma pack(1)
933struct hclge_mac_ethertype_idx_rd_cmd {
934 u8 flags;
935 u8 resp_code;
936 __le16 vlan_tag;
937 u8 mac_addr[ETH_ALEN];
938 __le16 index;
939 __le16 ethter_type;
940 __le16 egress_port;
941 __le16 egress_queue;
942 __le16 rev0;
943 u8 i_port_bitmap;
944 u8 i_port_direction;
945 u8 rev1[2];
946};
947
948#pragma pack()
949
950#define HCLGE_TSO_MSS_MIN_S 0
951#define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
952
953#define HCLGE_TSO_MSS_MAX_S 16
954#define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
955
956struct hclge_cfg_tso_status_cmd {
957 __le16 tso_mss_min;
958 __le16 tso_mss_max;
959 u8 rsv[20];
960};
961
962#define HCLGE_GRO_EN_B 0
963struct hclge_cfg_gro_status_cmd {
964 u8 gro_en;
965 u8 rsv[23];
966};
967
968#define HCLGE_TSO_MSS_MIN 256
969#define HCLGE_TSO_MSS_MAX 9668
970
971#define HCLGE_TQP_RESET_B 0
972struct hclge_reset_tqp_queue_cmd {
973 __le16 tqp_id;
974 u8 reset_req;
975 u8 ready_to_reset;
976 u8 rsv[20];
977};
978
979#define HCLGE_CFG_RESET_MAC_B 3
980#define HCLGE_CFG_RESET_FUNC_B 7
981#define HCLGE_CFG_RESET_RCB_B 1
982struct hclge_reset_cmd {
983 u8 mac_func_reset;
984 u8 fun_reset_vfid;
985 u8 fun_reset_rcb;
986 u8 rsv;
987 __le16 fun_reset_rcb_vqid_start;
988 __le16 fun_reset_rcb_vqid_num;
989 u8 fun_reset_rcb_return_status;
990 u8 rsv1[15];
991};
992
993#define HCLGE_PF_RESET_DONE_BIT BIT(0)
994
995struct hclge_pf_rst_done_cmd {
996 u8 pf_rst_done;
997 u8 rsv[23];
998};
999
1000#define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
1001#define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
1002#define HCLGE_CMD_GE_PHY_INNER_LOOP_B BIT(3)
1003#define HCLGE_CMD_COMMON_LB_DONE_B BIT(0)
1004#define HCLGE_CMD_COMMON_LB_SUCCESS_B BIT(1)
1005struct hclge_common_lb_cmd {
1006 u8 mask;
1007 u8 enable;
1008 u8 result;
1009 u8 rsv[21];
1010};
1011
1012#define HCLGE_DEFAULT_TX_BUF 0x4000
1013#define HCLGE_TOTAL_PKT_BUF 0x108000
1014#define HCLGE_DEFAULT_DV 0xA000
1015#define HCLGE_DEFAULT_NON_DCB_DV 0x7800
1016#define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400
1017
1018#define HCLGE_TYPE_CRQ 0
1019#define HCLGE_TYPE_CSQ 1
1020
1021
1022#define HCLGE_NIC_SW_RST_RDY_B 16
1023#define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
1024
1025#define HCLGE_NIC_CMQ_DESC_NUM 1024
1026#define HCLGE_NIC_CMQ_DESC_NUM_S 3
1027
1028#define HCLGE_LED_LOCATE_STATE_S 0
1029#define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
1030
1031struct hclge_set_led_state_cmd {
1032 u8 rsv1[3];
1033 u8 locate_led_config;
1034 u8 rsv2[20];
1035};
1036
1037struct hclge_get_fd_mode_cmd {
1038 u8 mode;
1039 u8 enable;
1040 u8 rsv[22];
1041};
1042
1043struct hclge_get_fd_allocation_cmd {
1044 __le32 stage1_entry_num;
1045 __le32 stage2_entry_num;
1046 __le16 stage1_counter_num;
1047 __le16 stage2_counter_num;
1048 u8 rsv[12];
1049};
1050
1051struct hclge_set_fd_key_config_cmd {
1052 u8 stage;
1053 u8 key_select;
1054 u8 inner_sipv6_word_en;
1055 u8 inner_dipv6_word_en;
1056 u8 outer_sipv6_word_en;
1057 u8 outer_dipv6_word_en;
1058 u8 rsv1[2];
1059 __le32 tuple_mask;
1060 __le32 meta_data_mask;
1061 u8 rsv2[8];
1062};
1063
1064#define HCLGE_FD_EPORT_SW_EN_B 0
1065struct hclge_fd_tcam_config_1_cmd {
1066 u8 stage;
1067 u8 xy_sel;
1068 u8 port_info;
1069 u8 rsv1[1];
1070 __le32 index;
1071 u8 entry_vld;
1072 u8 rsv2[7];
1073 u8 tcam_data[8];
1074};
1075
1076struct hclge_fd_tcam_config_2_cmd {
1077 u8 tcam_data[24];
1078};
1079
1080struct hclge_fd_tcam_config_3_cmd {
1081 u8 tcam_data[20];
1082 u8 rsv[4];
1083};
1084
1085#define HCLGE_FD_AD_DROP_B 0
1086#define HCLGE_FD_AD_DIRECT_QID_B 1
1087#define HCLGE_FD_AD_QID_S 2
1088#define HCLGE_FD_AD_QID_M GENMASK(11, 2)
1089#define HCLGE_FD_AD_USE_COUNTER_B 12
1090#define HCLGE_FD_AD_COUNTER_NUM_S 13
1091#define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
1092#define HCLGE_FD_AD_NXT_STEP_B 20
1093#define HCLGE_FD_AD_NXT_KEY_S 21
1094#define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)
1095#define HCLGE_FD_AD_WR_RULE_ID_B 0
1096#define HCLGE_FD_AD_RULE_ID_S 1
1097#define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)
1098#define HCLGE_FD_AD_TC_OVRD_B 16
1099#define HCLGE_FD_AD_TC_SIZE_S 17
1100#define HCLGE_FD_AD_TC_SIZE_M GENMASK(20, 17)
1101
1102struct hclge_fd_ad_config_cmd {
1103 u8 stage;
1104 u8 rsv1[3];
1105 __le32 index;
1106 __le64 ad_data;
1107 u8 rsv2[8];
1108};
1109
1110struct hclge_fd_ad_cnt_read_cmd {
1111 u8 rsv0[4];
1112 __le16 index;
1113 u8 rsv1[2];
1114 __le64 cnt;
1115 u8 rsv2[8];
1116};
1117
1118#define HCLGE_FD_USER_DEF_OFT_S 0
1119#define HCLGE_FD_USER_DEF_OFT_M GENMASK(14, 0)
1120#define HCLGE_FD_USER_DEF_EN_B 15
1121struct hclge_fd_user_def_cfg_cmd {
1122 __le16 ol2_cfg;
1123 __le16 l2_cfg;
1124 __le16 ol3_cfg;
1125 __le16 l3_cfg;
1126 __le16 ol4_cfg;
1127 __le16 l4_cfg;
1128 u8 rsv[12];
1129};
1130
1131struct hclge_get_imp_bd_cmd {
1132 __le32 bd_num;
1133 u8 rsv[20];
1134};
1135
1136struct hclge_query_ppu_pf_other_int_dfx_cmd {
1137 __le16 over_8bd_no_fe_qid;
1138 __le16 over_8bd_no_fe_vf_id;
1139 __le16 tso_mss_cmp_min_err_qid;
1140 __le16 tso_mss_cmp_min_err_vf_id;
1141 __le16 tso_mss_cmp_max_err_qid;
1142 __le16 tso_mss_cmp_max_err_vf_id;
1143 __le16 tx_rd_fbd_poison_qid;
1144 __le16 tx_rd_fbd_poison_vf_id;
1145 __le16 rx_rd_fbd_poison_qid;
1146 __le16 rx_rd_fbd_poison_vf_id;
1147 u8 rsv[4];
1148};
1149
1150#define HCLGE_LINK_EVENT_REPORT_EN_B 0
1151#define HCLGE_NCSI_ERROR_REPORT_EN_B 1
1152#define HCLGE_PHY_IMP_EN_B 2
1153struct hclge_firmware_compat_cmd {
1154 __le32 compat;
1155 u8 rsv[20];
1156};
1157
1158#define HCLGE_SFP_INFO_CMD_NUM 6
1159#define HCLGE_SFP_INFO_BD0_LEN 20
1160#define HCLGE_SFP_INFO_BDX_LEN 24
1161#define HCLGE_SFP_INFO_MAX_LEN \
1162 (HCLGE_SFP_INFO_BD0_LEN + \
1163 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1164
1165struct hclge_sfp_info_bd0_cmd {
1166 __le16 offset;
1167 __le16 read_len;
1168 u8 data[HCLGE_SFP_INFO_BD0_LEN];
1169};
1170
1171#define HCLGE_QUERY_DEV_SPECS_BD_NUM 4
1172
1173struct hclge_dev_specs_0_cmd {
1174 __le32 rsv0;
1175 __le32 mac_entry_num;
1176 __le32 mng_entry_num;
1177 __le16 rss_ind_tbl_size;
1178 __le16 rss_key_size;
1179 __le16 int_ql_max;
1180 u8 max_non_tso_bd_num;
1181 u8 rsv1;
1182 __le32 max_tm_rate;
1183};
1184
1185#define HCLGE_DEF_MAX_INT_GL 0x1FE0U
1186
1187struct hclge_dev_specs_1_cmd {
1188 __le16 max_frm_size;
1189 __le16 max_qset_num;
1190 __le16 max_int_gl;
1191 u8 rsv1[18];
1192};
1193
1194
1195enum HCLGE_FIRMWARE_MAC_SPEED {
1196 HCLGE_FW_MAC_SPEED_1G,
1197 HCLGE_FW_MAC_SPEED_10G,
1198 HCLGE_FW_MAC_SPEED_25G,
1199 HCLGE_FW_MAC_SPEED_40G,
1200 HCLGE_FW_MAC_SPEED_50G,
1201 HCLGE_FW_MAC_SPEED_100G,
1202 HCLGE_FW_MAC_SPEED_10M,
1203 HCLGE_FW_MAC_SPEED_100M,
1204 HCLGE_FW_MAC_SPEED_200G,
1205};
1206
1207#define HCLGE_PHY_LINK_SETTING_BD_NUM 2
1208
1209struct hclge_phy_link_ksetting_0_cmd {
1210 __le32 speed;
1211 u8 duplex;
1212 u8 autoneg;
1213 u8 eth_tp_mdix;
1214 u8 eth_tp_mdix_ctrl;
1215 u8 port;
1216 u8 transceiver;
1217 u8 phy_address;
1218 u8 rsv;
1219 __le32 supported;
1220 __le32 advertising;
1221 __le32 lp_advertising;
1222};
1223
1224struct hclge_phy_link_ksetting_1_cmd {
1225 u8 master_slave_cfg;
1226 u8 master_slave_state;
1227 u8 rsv[22];
1228};
1229
1230struct hclge_phy_reg_cmd {
1231 __le16 reg_addr;
1232 u8 rsv0[2];
1233 __le16 reg_val;
1234 u8 rsv1[18];
1235};
1236
1237
1238struct hclge_caps_bit_map {
1239 u16 imp_bit;
1240 u16 local_bit;
1241};
1242
1243int hclge_cmd_init(struct hclge_dev *hdev);
1244static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1245{
1246 writel(value, base + reg);
1247}
1248
1249#define hclge_write_dev(a, reg, value) \
1250 hclge_write_reg((a)->io_base, reg, value)
1251#define hclge_read_dev(a, reg) \
1252 hclge_read_reg((a)->io_base, reg)
1253
1254static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1255{
1256 u8 __iomem *reg_addr = READ_ONCE(base);
1257
1258 return readl(reg_addr + reg);
1259}
1260
1261#define HCLGE_SEND_SYNC(flag) \
1262 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1263
1264struct hclge_hw;
1265int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1266void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1267 enum hclge_opcode_type opcode, bool is_read);
1268void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1269
1270enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1271 struct hclge_desc *desc);
1272enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1273 struct hclge_desc *desc);
1274
1275void hclge_cmd_uninit(struct hclge_dev *hdev);
1276int hclge_cmd_queue_init(struct hclge_dev *hdev);
1277#endif
1278
