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7
8#include "e1000.h"
9
10static s32 e1000_check_downshift(struct e1000_hw *hw);
11static s32 e1000_check_polarity(struct e1000_hw *hw,
12 e1000_rev_polarity *polarity);
13static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
14static void e1000_clear_vfta(struct e1000_hw *hw);
15static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
16 bool link_up);
17static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
18static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
19static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
20static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
21 u16 *max_length);
22static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
23static s32 e1000_id_led_init(struct e1000_hw *hw);
24static void e1000_init_rx_addrs(struct e1000_hw *hw);
25static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
26 struct e1000_phy_info *phy_info);
27static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
28 struct e1000_phy_info *phy_info);
29static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
30static s32 e1000_wait_autoneg(struct e1000_hw *hw);
31static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
32static s32 e1000_set_phy_type(struct e1000_hw *hw);
33static void e1000_phy_init_script(struct e1000_hw *hw);
34static s32 e1000_setup_copper_link(struct e1000_hw *hw);
35static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
36static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
37static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
38static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
39static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
40static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
41static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
42static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
43static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
44static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
45 u16 words, u16 *data);
46static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
47 u16 words, u16 *data);
48static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
49static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
50static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
51static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
52static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
53 u16 phy_data);
54static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
55 u16 *phy_data);
56static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
57static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
58static void e1000_release_eeprom(struct e1000_hw *hw);
59static void e1000_standby_eeprom(struct e1000_hw *hw);
60static s32 e1000_set_vco_speed(struct e1000_hw *hw);
61static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
62static s32 e1000_set_phy_mode(struct e1000_hw *hw);
63static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
64 u16 *data);
65static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
66 u16 *data);
67
68
69static const
70u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
71 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
72 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
73 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
74 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
75 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
76 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
77 100,
78 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
79 110, 110,
80 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
81 120, 120
82};
83
84static DEFINE_MUTEX(e1000_eeprom_lock);
85static DEFINE_SPINLOCK(e1000_phy_lock);
86
87
88
89
90
91static s32 e1000_set_phy_type(struct e1000_hw *hw)
92{
93 if (hw->mac_type == e1000_undefined)
94 return -E1000_ERR_PHY_TYPE;
95
96 switch (hw->phy_id) {
97 case M88E1000_E_PHY_ID:
98 case M88E1000_I_PHY_ID:
99 case M88E1011_I_PHY_ID:
100 case M88E1111_I_PHY_ID:
101 case M88E1118_E_PHY_ID:
102 hw->phy_type = e1000_phy_m88;
103 break;
104 case IGP01E1000_I_PHY_ID:
105 if (hw->mac_type == e1000_82541 ||
106 hw->mac_type == e1000_82541_rev_2 ||
107 hw->mac_type == e1000_82547 ||
108 hw->mac_type == e1000_82547_rev_2)
109 hw->phy_type = e1000_phy_igp;
110 break;
111 case RTL8211B_PHY_ID:
112 hw->phy_type = e1000_phy_8211;
113 break;
114 case RTL8201N_PHY_ID:
115 hw->phy_type = e1000_phy_8201;
116 break;
117 default:
118
119 hw->phy_type = e1000_phy_undefined;
120 return -E1000_ERR_PHY_TYPE;
121 }
122
123 return E1000_SUCCESS;
124}
125
126
127
128
129
130static void e1000_phy_init_script(struct e1000_hw *hw)
131{
132 u16 phy_saved_data;
133
134 if (hw->phy_init_script) {
135 msleep(20);
136
137
138
139
140 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
141
142
143 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
144 msleep(20);
145
146 e1000_write_phy_reg(hw, 0x0000, 0x0140);
147 msleep(5);
148
149 switch (hw->mac_type) {
150 case e1000_82541:
151 case e1000_82547:
152 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
153 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
154 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
155 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
156 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
157 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
158 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
159 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
160 e1000_write_phy_reg(hw, 0x2010, 0x0008);
161 break;
162
163 case e1000_82541_rev_2:
164 case e1000_82547_rev_2:
165 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
166 break;
167 default:
168 break;
169 }
170
171 e1000_write_phy_reg(hw, 0x0000, 0x3300);
172 msleep(20);
173
174
175 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
176
177 if (hw->mac_type == e1000_82547) {
178 u16 fused, fine, coarse;
179
180
181 e1000_read_phy_reg(hw,
182 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
183 &fused);
184
185 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
186 e1000_read_phy_reg(hw,
187 IGP01E1000_ANALOG_FUSE_STATUS,
188 &fused);
189
190 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
191 coarse =
192 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
193
194 if (coarse >
195 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
196 coarse -=
197 IGP01E1000_ANALOG_FUSE_COARSE_10;
198 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
199 } else if (coarse ==
200 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
201 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
202
203 fused =
204 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
205 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
206 (coarse &
207 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
208
209 e1000_write_phy_reg(hw,
210 IGP01E1000_ANALOG_FUSE_CONTROL,
211 fused);
212 e1000_write_phy_reg(hw,
213 IGP01E1000_ANALOG_FUSE_BYPASS,
214 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
215 }
216 }
217 }
218}
219
220
221
222
223
224s32 e1000_set_mac_type(struct e1000_hw *hw)
225{
226 switch (hw->device_id) {
227 case E1000_DEV_ID_82542:
228 switch (hw->revision_id) {
229 case E1000_82542_2_0_REV_ID:
230 hw->mac_type = e1000_82542_rev2_0;
231 break;
232 case E1000_82542_2_1_REV_ID:
233 hw->mac_type = e1000_82542_rev2_1;
234 break;
235 default:
236
237 return -E1000_ERR_MAC_TYPE;
238 }
239 break;
240 case E1000_DEV_ID_82543GC_FIBER:
241 case E1000_DEV_ID_82543GC_COPPER:
242 hw->mac_type = e1000_82543;
243 break;
244 case E1000_DEV_ID_82544EI_COPPER:
245 case E1000_DEV_ID_82544EI_FIBER:
246 case E1000_DEV_ID_82544GC_COPPER:
247 case E1000_DEV_ID_82544GC_LOM:
248 hw->mac_type = e1000_82544;
249 break;
250 case E1000_DEV_ID_82540EM:
251 case E1000_DEV_ID_82540EM_LOM:
252 case E1000_DEV_ID_82540EP:
253 case E1000_DEV_ID_82540EP_LOM:
254 case E1000_DEV_ID_82540EP_LP:
255 hw->mac_type = e1000_82540;
256 break;
257 case E1000_DEV_ID_82545EM_COPPER:
258 case E1000_DEV_ID_82545EM_FIBER:
259 hw->mac_type = e1000_82545;
260 break;
261 case E1000_DEV_ID_82545GM_COPPER:
262 case E1000_DEV_ID_82545GM_FIBER:
263 case E1000_DEV_ID_82545GM_SERDES:
264 hw->mac_type = e1000_82545_rev_3;
265 break;
266 case E1000_DEV_ID_82546EB_COPPER:
267 case E1000_DEV_ID_82546EB_FIBER:
268 case E1000_DEV_ID_82546EB_QUAD_COPPER:
269 hw->mac_type = e1000_82546;
270 break;
271 case E1000_DEV_ID_82546GB_COPPER:
272 case E1000_DEV_ID_82546GB_FIBER:
273 case E1000_DEV_ID_82546GB_SERDES:
274 case E1000_DEV_ID_82546GB_PCIE:
275 case E1000_DEV_ID_82546GB_QUAD_COPPER:
276 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
277 hw->mac_type = e1000_82546_rev_3;
278 break;
279 case E1000_DEV_ID_82541EI:
280 case E1000_DEV_ID_82541EI_MOBILE:
281 case E1000_DEV_ID_82541ER_LOM:
282 hw->mac_type = e1000_82541;
283 break;
284 case E1000_DEV_ID_82541ER:
285 case E1000_DEV_ID_82541GI:
286 case E1000_DEV_ID_82541GI_LF:
287 case E1000_DEV_ID_82541GI_MOBILE:
288 hw->mac_type = e1000_82541_rev_2;
289 break;
290 case E1000_DEV_ID_82547EI:
291 case E1000_DEV_ID_82547EI_MOBILE:
292 hw->mac_type = e1000_82547;
293 break;
294 case E1000_DEV_ID_82547GI:
295 hw->mac_type = e1000_82547_rev_2;
296 break;
297 case E1000_DEV_ID_INTEL_CE4100_GBE:
298 hw->mac_type = e1000_ce4100;
299 break;
300 default:
301
302 return -E1000_ERR_MAC_TYPE;
303 }
304
305 switch (hw->mac_type) {
306 case e1000_82541:
307 case e1000_82547:
308 case e1000_82541_rev_2:
309 case e1000_82547_rev_2:
310 hw->asf_firmware_present = true;
311 break;
312 default:
313 break;
314 }
315
316
317
318
319 if (hw->mac_type == e1000_82543)
320 hw->bad_tx_carr_stats_fd = true;
321
322 if (hw->mac_type > e1000_82544)
323 hw->has_smbus = true;
324
325 return E1000_SUCCESS;
326}
327
328
329
330
331
332void e1000_set_media_type(struct e1000_hw *hw)
333{
334 u32 status;
335
336 if (hw->mac_type != e1000_82543) {
337
338 hw->tbi_compatibility_en = false;
339 }
340
341 switch (hw->device_id) {
342 case E1000_DEV_ID_82545GM_SERDES:
343 case E1000_DEV_ID_82546GB_SERDES:
344 hw->media_type = e1000_media_type_internal_serdes;
345 break;
346 default:
347 switch (hw->mac_type) {
348 case e1000_82542_rev2_0:
349 case e1000_82542_rev2_1:
350 hw->media_type = e1000_media_type_fiber;
351 break;
352 case e1000_ce4100:
353 hw->media_type = e1000_media_type_copper;
354 break;
355 default:
356 status = er32(STATUS);
357 if (status & E1000_STATUS_TBIMODE) {
358 hw->media_type = e1000_media_type_fiber;
359
360 hw->tbi_compatibility_en = false;
361 } else {
362 hw->media_type = e1000_media_type_copper;
363 }
364 break;
365 }
366 }
367}
368
369
370
371
372
373
374
375s32 e1000_reset_hw(struct e1000_hw *hw)
376{
377 u32 ctrl;
378 u32 ctrl_ext;
379 u32 manc;
380 u32 led_ctrl;
381 s32 ret_val;
382
383
384 if (hw->mac_type == e1000_82542_rev2_0) {
385 e_dbg("Disabling MWI on 82542 rev 2.0\n");
386 e1000_pci_clear_mwi(hw);
387 }
388
389
390 e_dbg("Masking off all interrupts\n");
391 ew32(IMC, 0xffffffff);
392
393
394
395
396
397 ew32(RCTL, 0);
398 ew32(TCTL, E1000_TCTL_PSP);
399 E1000_WRITE_FLUSH();
400
401
402 hw->tbi_compatibility_on = false;
403
404
405
406
407 msleep(10);
408
409 ctrl = er32(CTRL);
410
411
412 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
413 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
414 E1000_WRITE_FLUSH();
415 msleep(5);
416 }
417
418
419
420
421
422
423 e_dbg("Issuing a global reset to MAC\n");
424
425 switch (hw->mac_type) {
426 case e1000_82544:
427 case e1000_82540:
428 case e1000_82545:
429 case e1000_82546:
430 case e1000_82541:
431 case e1000_82541_rev_2:
432
433
434
435 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
436 break;
437 case e1000_82545_rev_3:
438 case e1000_82546_rev_3:
439
440 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
441 break;
442 case e1000_ce4100:
443 default:
444 ew32(CTRL, (ctrl | E1000_CTRL_RST));
445 break;
446 }
447
448
449
450
451
452 switch (hw->mac_type) {
453 case e1000_82542_rev2_0:
454 case e1000_82542_rev2_1:
455 case e1000_82543:
456 case e1000_82544:
457
458 udelay(10);
459 ctrl_ext = er32(CTRL_EXT);
460 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
461 ew32(CTRL_EXT, ctrl_ext);
462 E1000_WRITE_FLUSH();
463
464 msleep(2);
465 break;
466 case e1000_82541:
467 case e1000_82541_rev_2:
468 case e1000_82547:
469 case e1000_82547_rev_2:
470
471 msleep(20);
472 break;
473 default:
474
475 ret_val = e1000_get_auto_rd_done(hw);
476 if (ret_val)
477 return ret_val;
478 break;
479 }
480
481
482 if (hw->mac_type >= e1000_82540) {
483 manc = er32(MANC);
484 manc &= ~(E1000_MANC_ARP_EN);
485 ew32(MANC, manc);
486 }
487
488 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
489 e1000_phy_init_script(hw);
490
491
492 led_ctrl = er32(LEDCTL);
493 led_ctrl &= IGP_ACTIVITY_LED_MASK;
494 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
495 ew32(LEDCTL, led_ctrl);
496 }
497
498
499 e_dbg("Masking off all interrupts\n");
500 ew32(IMC, 0xffffffff);
501
502
503 er32(ICR);
504
505
506 if (hw->mac_type == e1000_82542_rev2_0) {
507 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
508 e1000_pci_set_mwi(hw);
509 }
510
511 return E1000_SUCCESS;
512}
513
514
515
516
517
518
519
520
521
522
523
524s32 e1000_init_hw(struct e1000_hw *hw)
525{
526 u32 ctrl;
527 u32 i;
528 s32 ret_val;
529 u32 mta_size;
530 u32 ctrl_ext;
531
532
533 ret_val = e1000_id_led_init(hw);
534 if (ret_val) {
535 e_dbg("Error Initializing Identification LED\n");
536 return ret_val;
537 }
538
539
540 e1000_set_media_type(hw);
541
542
543 e_dbg("Initializing the IEEE VLAN\n");
544 if (hw->mac_type < e1000_82545_rev_3)
545 ew32(VET, 0);
546 e1000_clear_vfta(hw);
547
548
549 if (hw->mac_type == e1000_82542_rev2_0) {
550 e_dbg("Disabling MWI on 82542 rev 2.0\n");
551 e1000_pci_clear_mwi(hw);
552 ew32(RCTL, E1000_RCTL_RST);
553 E1000_WRITE_FLUSH();
554 msleep(5);
555 }
556
557
558
559
560 e1000_init_rx_addrs(hw);
561
562
563 if (hw->mac_type == e1000_82542_rev2_0) {
564 ew32(RCTL, 0);
565 E1000_WRITE_FLUSH();
566 msleep(1);
567 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
568 e1000_pci_set_mwi(hw);
569 }
570
571
572 e_dbg("Zeroing the MTA\n");
573 mta_size = E1000_MC_TBL_SIZE;
574 for (i = 0; i < mta_size; i++) {
575 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
576
577
578
579 E1000_WRITE_FLUSH();
580 }
581
582
583
584
585
586
587 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
588 ctrl = er32(CTRL);
589 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
590 }
591
592 switch (hw->mac_type) {
593 case e1000_82545_rev_3:
594 case e1000_82546_rev_3:
595 break;
596 default:
597
598
599
600 if (hw->bus_type == e1000_bus_type_pcix &&
601 e1000_pcix_get_mmrbc(hw) > 2048)
602 e1000_pcix_set_mmrbc(hw, 2048);
603 break;
604 }
605
606
607 ret_val = e1000_setup_link(hw);
608
609
610 if (hw->mac_type > e1000_82544) {
611 ctrl = er32(TXDCTL);
612 ctrl =
613 (ctrl & ~E1000_TXDCTL_WTHRESH) |
614 E1000_TXDCTL_FULL_TX_DESC_WB;
615 ew32(TXDCTL, ctrl);
616 }
617
618
619
620
621
622
623 e1000_clear_hw_cntrs(hw);
624
625 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
626 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
627 ctrl_ext = er32(CTRL_EXT);
628
629
630
631 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
632 ew32(CTRL_EXT, ctrl_ext);
633 }
634
635 return ret_val;
636}
637
638
639
640
641
642static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
643{
644 u16 eeprom_data;
645 s32 ret_val;
646
647 if (hw->media_type != e1000_media_type_internal_serdes)
648 return E1000_SUCCESS;
649
650 switch (hw->mac_type) {
651 case e1000_82545_rev_3:
652 case e1000_82546_rev_3:
653 break;
654 default:
655 return E1000_SUCCESS;
656 }
657
658 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
659 &eeprom_data);
660 if (ret_val)
661 return ret_val;
662
663 if (eeprom_data != EEPROM_RESERVED_WORD) {
664
665 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
666 ret_val =
667 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
668 if (ret_val)
669 return ret_val;
670 }
671
672 return E1000_SUCCESS;
673}
674
675
676
677
678
679
680
681
682
683
684
685s32 e1000_setup_link(struct e1000_hw *hw)
686{
687 u32 ctrl_ext;
688 s32 ret_val;
689 u16 eeprom_data;
690
691
692
693
694
695
696
697
698
699 if (hw->fc == E1000_FC_DEFAULT) {
700 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
701 1, &eeprom_data);
702 if (ret_val) {
703 e_dbg("EEPROM Read Error\n");
704 return -E1000_ERR_EEPROM;
705 }
706 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
707 hw->fc = E1000_FC_NONE;
708 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
709 EEPROM_WORD0F_ASM_DIR)
710 hw->fc = E1000_FC_TX_PAUSE;
711 else
712 hw->fc = E1000_FC_FULL;
713 }
714
715
716
717
718
719 if (hw->mac_type == e1000_82542_rev2_0)
720 hw->fc &= (~E1000_FC_TX_PAUSE);
721
722 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
723 hw->fc &= (~E1000_FC_RX_PAUSE);
724
725 hw->original_fc = hw->fc;
726
727 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
728
729
730
731
732
733
734
735
736 if (hw->mac_type == e1000_82543) {
737 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
738 1, &eeprom_data);
739 if (ret_val) {
740 e_dbg("EEPROM Read Error\n");
741 return -E1000_ERR_EEPROM;
742 }
743 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
744 SWDPIO__EXT_SHIFT);
745 ew32(CTRL_EXT, ctrl_ext);
746 }
747
748
749 ret_val = (hw->media_type == e1000_media_type_copper) ?
750 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
751
752
753
754
755
756
757 e_dbg("Initializing the Flow Control address, type and timer regs\n");
758
759 ew32(FCT, FLOW_CONTROL_TYPE);
760 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
761 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
762
763 ew32(FCTTV, hw->fc_pause_time);
764
765
766
767
768
769
770
771 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
772 ew32(FCRTL, 0);
773 ew32(FCRTH, 0);
774 } else {
775
776
777
778
779 if (hw->fc_send_xon) {
780 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
781 ew32(FCRTH, hw->fc_high_water);
782 } else {
783 ew32(FCRTL, hw->fc_low_water);
784 ew32(FCRTH, hw->fc_high_water);
785 }
786 }
787 return ret_val;
788}
789
790
791
792
793
794
795
796
797
798static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
799{
800 u32 ctrl;
801 u32 status;
802 u32 txcw = 0;
803 u32 i;
804 u32 signal = 0;
805 s32 ret_val;
806
807
808
809
810
811
812
813 ctrl = er32(CTRL);
814 if (hw->media_type == e1000_media_type_fiber)
815 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
816
817 ret_val = e1000_adjust_serdes_amplitude(hw);
818 if (ret_val)
819 return ret_val;
820
821
822 ctrl &= ~(E1000_CTRL_LRST);
823
824
825 ret_val = e1000_set_vco_speed(hw);
826 if (ret_val)
827 return ret_val;
828
829 e1000_config_collision_dist(hw);
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847 switch (hw->fc) {
848 case E1000_FC_NONE:
849
850 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
851 break;
852 case E1000_FC_RX_PAUSE:
853
854
855
856
857
858
859
860 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
861 break;
862 case E1000_FC_TX_PAUSE:
863
864
865
866 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
867 break;
868 case E1000_FC_FULL:
869
870
871
872 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
873 break;
874 default:
875 e_dbg("Flow control param set incorrectly\n");
876 return -E1000_ERR_CONFIG;
877 }
878
879
880
881
882
883
884
885 e_dbg("Auto-negotiation enabled\n");
886
887 ew32(TXCW, txcw);
888 ew32(CTRL, ctrl);
889 E1000_WRITE_FLUSH();
890
891 hw->txcw = txcw;
892 msleep(1);
893
894
895
896
897
898
899
900
901 if (hw->media_type == e1000_media_type_internal_serdes ||
902 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
903 e_dbg("Looking for Link\n");
904 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
905 msleep(10);
906 status = er32(STATUS);
907 if (status & E1000_STATUS_LU)
908 break;
909 }
910 if (i == (LINK_UP_TIMEOUT / 10)) {
911 e_dbg("Never got a valid link from auto-neg!!!\n");
912 hw->autoneg_failed = 1;
913
914
915
916
917
918 ret_val = e1000_check_for_link(hw);
919 if (ret_val) {
920 e_dbg("Error while checking for link\n");
921 return ret_val;
922 }
923 hw->autoneg_failed = 0;
924 } else {
925 hw->autoneg_failed = 0;
926 e_dbg("Valid Link Found\n");
927 }
928 } else {
929 e_dbg("No Signal Detected\n");
930 }
931 return E1000_SUCCESS;
932}
933
934
935
936
937
938
939
940static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
941{
942 s32 ret_val;
943
944
945 ret_val = e1000_phy_reset(hw);
946 if (ret_val) {
947 e_dbg("Error Resetting the PHY\n");
948 return ret_val;
949 }
950
951 return E1000_SUCCESS;
952}
953
954static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
955{
956 s32 ret_val;
957 u32 ctrl_aux;
958
959 switch (hw->phy_type) {
960 case e1000_phy_8211:
961 ret_val = e1000_copper_link_rtl_setup(hw);
962 if (ret_val) {
963 e_dbg("e1000_copper_link_rtl_setup failed!\n");
964 return ret_val;
965 }
966 break;
967 case e1000_phy_8201:
968
969 ctrl_aux = er32(CTL_AUX);
970 ctrl_aux |= E1000_CTL_AUX_RMII;
971 ew32(CTL_AUX, ctrl_aux);
972 E1000_WRITE_FLUSH();
973
974
975 ctrl_aux = er32(CTL_AUX);
976 ctrl_aux |= 0x4;
977 ctrl_aux &= ~0x2;
978 ew32(CTL_AUX, ctrl_aux);
979 E1000_WRITE_FLUSH();
980 ret_val = e1000_copper_link_rtl_setup(hw);
981
982 if (ret_val) {
983 e_dbg("e1000_copper_link_rtl_setup failed!\n");
984 return ret_val;
985 }
986 break;
987 default:
988 e_dbg("Error Resetting the PHY\n");
989 return E1000_ERR_PHY_TYPE;
990 }
991
992 return E1000_SUCCESS;
993}
994
995
996
997
998
999
1000
1001static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1002{
1003 u32 ctrl;
1004 s32 ret_val;
1005 u16 phy_data;
1006
1007 ctrl = er32(CTRL);
1008
1009
1010
1011
1012 if (hw->mac_type > e1000_82543) {
1013 ctrl |= E1000_CTRL_SLU;
1014 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1015 ew32(CTRL, ctrl);
1016 } else {
1017 ctrl |=
1018 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1019 ew32(CTRL, ctrl);
1020 ret_val = e1000_phy_hw_reset(hw);
1021 if (ret_val)
1022 return ret_val;
1023 }
1024
1025
1026 ret_val = e1000_detect_gig_phy(hw);
1027 if (ret_val) {
1028 e_dbg("Error, did not detect valid phy.\n");
1029 return ret_val;
1030 }
1031 e_dbg("Phy ID = %x\n", hw->phy_id);
1032
1033
1034 ret_val = e1000_set_phy_mode(hw);
1035 if (ret_val)
1036 return ret_val;
1037
1038 if ((hw->mac_type == e1000_82545_rev_3) ||
1039 (hw->mac_type == e1000_82546_rev_3)) {
1040 ret_val =
1041 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1042 phy_data |= 0x00000008;
1043 ret_val =
1044 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1045 }
1046
1047 if (hw->mac_type <= e1000_82543 ||
1048 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1049 hw->mac_type == e1000_82541_rev_2 ||
1050 hw->mac_type == e1000_82547_rev_2)
1051 hw->phy_reset_disable = false;
1052
1053 return E1000_SUCCESS;
1054}
1055
1056
1057
1058
1059
1060static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1061{
1062 u32 led_ctrl;
1063 s32 ret_val;
1064 u16 phy_data;
1065
1066 if (hw->phy_reset_disable)
1067 return E1000_SUCCESS;
1068
1069 ret_val = e1000_phy_reset(hw);
1070 if (ret_val) {
1071 e_dbg("Error Resetting the PHY\n");
1072 return ret_val;
1073 }
1074
1075
1076 msleep(15);
1077
1078 led_ctrl = er32(LEDCTL);
1079 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1080 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1081 ew32(LEDCTL, led_ctrl);
1082
1083
1084 if (hw->phy_type == e1000_phy_igp) {
1085
1086 ret_val = e1000_set_d3_lplu_state(hw, false);
1087 if (ret_val) {
1088 e_dbg("Error Disabling LPLU D3\n");
1089 return ret_val;
1090 }
1091 }
1092
1093
1094 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1095 if (ret_val)
1096 return ret_val;
1097
1098 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1099 hw->dsp_config_state = e1000_dsp_config_disabled;
1100
1101 phy_data &=
1102 ~(IGP01E1000_PSCR_AUTO_MDIX |
1103 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1104 hw->mdix = 1;
1105
1106 } else {
1107 hw->dsp_config_state = e1000_dsp_config_enabled;
1108 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1109
1110 switch (hw->mdix) {
1111 case 1:
1112 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1113 break;
1114 case 2:
1115 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1116 break;
1117 case 0:
1118 default:
1119 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1120 break;
1121 }
1122 }
1123 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1124 if (ret_val)
1125 return ret_val;
1126
1127
1128 if (hw->autoneg) {
1129 e1000_ms_type phy_ms_setting = hw->master_slave;
1130
1131 if (hw->ffe_config_state == e1000_ffe_config_active)
1132 hw->ffe_config_state = e1000_ffe_config_enabled;
1133
1134 if (hw->dsp_config_state == e1000_dsp_config_activated)
1135 hw->dsp_config_state = e1000_dsp_config_enabled;
1136
1137
1138
1139
1140
1141 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1142
1143 ret_val =
1144 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1145 &phy_data);
1146 if (ret_val)
1147 return ret_val;
1148 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1149 ret_val =
1150 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1151 phy_data);
1152 if (ret_val)
1153 return ret_val;
1154
1155 ret_val =
1156 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1157 if (ret_val)
1158 return ret_val;
1159 phy_data &= ~CR_1000T_MS_ENABLE;
1160 ret_val =
1161 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1162 if (ret_val)
1163 return ret_val;
1164 }
1165
1166 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1167 if (ret_val)
1168 return ret_val;
1169
1170
1171 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1172 ((phy_data & CR_1000T_MS_VALUE) ?
1173 e1000_ms_force_master :
1174 e1000_ms_force_slave) : e1000_ms_auto;
1175
1176 switch (phy_ms_setting) {
1177 case e1000_ms_force_master:
1178 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1179 break;
1180 case e1000_ms_force_slave:
1181 phy_data |= CR_1000T_MS_ENABLE;
1182 phy_data &= ~(CR_1000T_MS_VALUE);
1183 break;
1184 case e1000_ms_auto:
1185 phy_data &= ~CR_1000T_MS_ENABLE;
1186 break;
1187 default:
1188 break;
1189 }
1190 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1191 if (ret_val)
1192 return ret_val;
1193 }
1194
1195 return E1000_SUCCESS;
1196}
1197
1198
1199
1200
1201
1202static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1203{
1204 s32 ret_val;
1205 u16 phy_data;
1206
1207 if (hw->phy_reset_disable)
1208 return E1000_SUCCESS;
1209
1210
1211 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1212 if (ret_val)
1213 return ret_val;
1214
1215 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1216
1217
1218
1219
1220
1221
1222
1223
1224 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1225
1226 switch (hw->mdix) {
1227 case 1:
1228 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1229 break;
1230 case 2:
1231 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1232 break;
1233 case 3:
1234 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1235 break;
1236 case 0:
1237 default:
1238 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1239 break;
1240 }
1241
1242
1243
1244
1245
1246
1247
1248 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1249 if (hw->disable_polarity_correction == 1)
1250 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1251 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1252 if (ret_val)
1253 return ret_val;
1254
1255 if (hw->phy_revision < M88E1011_I_REV_4) {
1256
1257
1258
1259 ret_val =
1260 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1261 &phy_data);
1262 if (ret_val)
1263 return ret_val;
1264
1265 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1266
1267 if ((hw->phy_revision == E1000_REVISION_2) &&
1268 (hw->phy_id == M88E1111_I_PHY_ID)) {
1269
1270 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1271 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1272 ret_val = e1000_write_phy_reg(hw,
1273 M88E1000_EXT_PHY_SPEC_CTRL,
1274 phy_data);
1275 if (ret_val)
1276 return ret_val;
1277 } else {
1278
1279 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1280 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1281 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1282 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1283 ret_val = e1000_write_phy_reg(hw,
1284 M88E1000_EXT_PHY_SPEC_CTRL,
1285 phy_data);
1286 if (ret_val)
1287 return ret_val;
1288 }
1289 }
1290
1291
1292 ret_val = e1000_phy_reset(hw);
1293 if (ret_val) {
1294 e_dbg("Error Resetting the PHY\n");
1295 return ret_val;
1296 }
1297
1298 return E1000_SUCCESS;
1299}
1300
1301
1302
1303
1304
1305
1306
1307
1308static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1309{
1310 s32 ret_val;
1311 u16 phy_data;
1312
1313
1314
1315
1316 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1317
1318
1319
1320
1321 if (hw->autoneg_advertised == 0)
1322 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1323
1324
1325 if (hw->phy_type == e1000_phy_8201)
1326 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1327
1328 e_dbg("Reconfiguring auto-neg advertisement params\n");
1329 ret_val = e1000_phy_setup_autoneg(hw);
1330 if (ret_val) {
1331 e_dbg("Error Setting up Auto-Negotiation\n");
1332 return ret_val;
1333 }
1334 e_dbg("Restarting Auto-Neg\n");
1335
1336
1337
1338
1339 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1340 if (ret_val)
1341 return ret_val;
1342
1343 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1344 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1345 if (ret_val)
1346 return ret_val;
1347
1348
1349
1350
1351 if (hw->wait_autoneg_complete) {
1352 ret_val = e1000_wait_autoneg(hw);
1353 if (ret_val) {
1354 e_dbg
1355 ("Error while waiting for autoneg to complete\n");
1356 return ret_val;
1357 }
1358 }
1359
1360 hw->get_link_status = true;
1361
1362 return E1000_SUCCESS;
1363}
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1379{
1380 s32 ret_val;
1381
1382 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
1383 e1000_config_collision_dist(hw);
1384 } else {
1385 ret_val = e1000_config_mac_to_phy(hw);
1386 if (ret_val) {
1387 e_dbg("Error configuring MAC to PHY settings\n");
1388 return ret_val;
1389 }
1390 }
1391 ret_val = e1000_config_fc_after_link_up(hw);
1392 if (ret_val) {
1393 e_dbg("Error Configuring Flow Control\n");
1394 return ret_val;
1395 }
1396
1397
1398 if (hw->phy_type == e1000_phy_igp) {
1399 ret_val = e1000_config_dsp_after_link_change(hw, true);
1400 if (ret_val) {
1401 e_dbg("Error Configuring DSP after link up\n");
1402 return ret_val;
1403 }
1404 }
1405
1406 return E1000_SUCCESS;
1407}
1408
1409
1410
1411
1412
1413
1414
1415static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1416{
1417 s32 ret_val;
1418 u16 i;
1419 u16 phy_data;
1420
1421
1422 ret_val = e1000_copper_link_preconfig(hw);
1423 if (ret_val)
1424 return ret_val;
1425
1426 if (hw->phy_type == e1000_phy_igp) {
1427 ret_val = e1000_copper_link_igp_setup(hw);
1428 if (ret_val)
1429 return ret_val;
1430 } else if (hw->phy_type == e1000_phy_m88) {
1431 ret_val = e1000_copper_link_mgp_setup(hw);
1432 if (ret_val)
1433 return ret_val;
1434 } else {
1435 ret_val = gbe_dhg_phy_setup(hw);
1436 if (ret_val) {
1437 e_dbg("gbe_dhg_phy_setup failed!\n");
1438 return ret_val;
1439 }
1440 }
1441
1442 if (hw->autoneg) {
1443
1444
1445
1446 ret_val = e1000_copper_link_autoneg(hw);
1447 if (ret_val)
1448 return ret_val;
1449 } else {
1450
1451
1452
1453 e_dbg("Forcing speed and duplex\n");
1454 ret_val = e1000_phy_force_speed_duplex(hw);
1455 if (ret_val) {
1456 e_dbg("Error Forcing Speed and Duplex\n");
1457 return ret_val;
1458 }
1459 }
1460
1461
1462
1463
1464 for (i = 0; i < 10; i++) {
1465 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1466 if (ret_val)
1467 return ret_val;
1468 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1469 if (ret_val)
1470 return ret_val;
1471
1472 if (phy_data & MII_SR_LINK_STATUS) {
1473
1474 ret_val = e1000_copper_link_postconfig(hw);
1475 if (ret_val)
1476 return ret_val;
1477
1478 e_dbg("Valid link established!!!\n");
1479 return E1000_SUCCESS;
1480 }
1481 udelay(10);
1482 }
1483
1484 e_dbg("Unable to establish link!!!\n");
1485 return E1000_SUCCESS;
1486}
1487
1488
1489
1490
1491
1492
1493
1494s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1495{
1496 s32 ret_val;
1497 u16 mii_autoneg_adv_reg;
1498 u16 mii_1000t_ctrl_reg;
1499
1500
1501 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1502 if (ret_val)
1503 return ret_val;
1504
1505
1506 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
1507 if (ret_val)
1508 return ret_val;
1509 else if (hw->phy_type == e1000_phy_8201)
1510 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1524 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1525
1526 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
1527
1528
1529 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1530 e_dbg("Advertise 10mb Half duplex\n");
1531 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1532 }
1533
1534
1535 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1536 e_dbg("Advertise 10mb Full duplex\n");
1537 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1538 }
1539
1540
1541 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1542 e_dbg("Advertise 100mb Half duplex\n");
1543 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1544 }
1545
1546
1547 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1548 e_dbg("Advertise 100mb Full duplex\n");
1549 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1550 }
1551
1552
1553 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1554 e_dbg
1555 ("Advertise 1000mb Half duplex requested, request denied!\n");
1556 }
1557
1558
1559 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1560 e_dbg("Advertise 1000mb Full duplex\n");
1561 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1562 }
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581 switch (hw->fc) {
1582 case E1000_FC_NONE:
1583
1584
1585
1586 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1587 break;
1588 case E1000_FC_RX_PAUSE:
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1599 break;
1600 case E1000_FC_TX_PAUSE:
1601
1602
1603
1604 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1605 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1606 break;
1607 case E1000_FC_FULL:
1608
1609
1610
1611 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1612 break;
1613 default:
1614 e_dbg("Flow control param set incorrectly\n");
1615 return -E1000_ERR_CONFIG;
1616 }
1617
1618 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1619 if (ret_val)
1620 return ret_val;
1621
1622 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1623
1624 if (hw->phy_type == e1000_phy_8201) {
1625 mii_1000t_ctrl_reg = 0;
1626 } else {
1627 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1628 mii_1000t_ctrl_reg);
1629 if (ret_val)
1630 return ret_val;
1631 }
1632
1633 return E1000_SUCCESS;
1634}
1635
1636
1637
1638
1639
1640
1641
1642static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1643{
1644 u32 ctrl;
1645 s32 ret_val;
1646 u16 mii_ctrl_reg;
1647 u16 mii_status_reg;
1648 u16 phy_data;
1649 u16 i;
1650
1651
1652 hw->fc = E1000_FC_NONE;
1653
1654 e_dbg("hw->fc = %d\n", hw->fc);
1655
1656
1657 ctrl = er32(CTRL);
1658
1659
1660 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1661 ctrl &= ~(DEVICE_SPEED_MASK);
1662
1663
1664 ctrl &= ~E1000_CTRL_ASDE;
1665
1666
1667 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1668 if (ret_val)
1669 return ret_val;
1670
1671
1672
1673 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1674
1675
1676 if (hw->forced_speed_duplex == e1000_100_full ||
1677 hw->forced_speed_duplex == e1000_10_full) {
1678
1679
1680
1681 ctrl |= E1000_CTRL_FD;
1682 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
1683 e_dbg("Full Duplex\n");
1684 } else {
1685
1686
1687
1688 ctrl &= ~E1000_CTRL_FD;
1689 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
1690 e_dbg("Half Duplex\n");
1691 }
1692
1693
1694 if (hw->forced_speed_duplex == e1000_100_full ||
1695 hw->forced_speed_duplex == e1000_100_half) {
1696
1697 ctrl |= E1000_CTRL_SPD_100;
1698 mii_ctrl_reg |= MII_CR_SPEED_100;
1699 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1700 e_dbg("Forcing 100mb ");
1701 } else {
1702
1703 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1704 mii_ctrl_reg |= MII_CR_SPEED_10;
1705 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1706 e_dbg("Forcing 10mb ");
1707 }
1708
1709 e1000_config_collision_dist(hw);
1710
1711
1712 ew32(CTRL, ctrl);
1713
1714 if (hw->phy_type == e1000_phy_m88) {
1715 ret_val =
1716 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1717 if (ret_val)
1718 return ret_val;
1719
1720
1721
1722
1723 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1724 ret_val =
1725 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1726 if (ret_val)
1727 return ret_val;
1728
1729 e_dbg("M88E1000 PSCR: %x\n", phy_data);
1730
1731
1732 mii_ctrl_reg |= MII_CR_RESET;
1733
1734
1735 } else {
1736
1737
1738
1739 ret_val =
1740 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1741 if (ret_val)
1742 return ret_val;
1743
1744 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1745 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1746
1747 ret_val =
1748 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1749 if (ret_val)
1750 return ret_val;
1751 }
1752
1753
1754 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1755 if (ret_val)
1756 return ret_val;
1757
1758 udelay(1);
1759
1760
1761
1762
1763
1764
1765
1766
1767 if (hw->wait_autoneg_complete) {
1768
1769 e_dbg("Waiting for forced speed/duplex link.\n");
1770 mii_status_reg = 0;
1771
1772
1773 for (i = PHY_FORCE_TIME; i > 0; i--) {
1774
1775
1776
1777 ret_val =
1778 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1779 if (ret_val)
1780 return ret_val;
1781
1782 ret_val =
1783 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1784 if (ret_val)
1785 return ret_val;
1786
1787 if (mii_status_reg & MII_SR_LINK_STATUS)
1788 break;
1789 msleep(100);
1790 }
1791 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1792
1793
1794
1795 ret_val = e1000_phy_reset_dsp(hw);
1796 if (ret_val) {
1797 e_dbg("Error Resetting PHY DSP\n");
1798 return ret_val;
1799 }
1800 }
1801
1802
1803
1804 for (i = PHY_FORCE_TIME; i > 0; i--) {
1805 if (mii_status_reg & MII_SR_LINK_STATUS)
1806 break;
1807 msleep(100);
1808
1809
1810
1811 ret_val =
1812 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1813 if (ret_val)
1814 return ret_val;
1815
1816 ret_val =
1817 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1818 if (ret_val)
1819 return ret_val;
1820 }
1821 }
1822
1823 if (hw->phy_type == e1000_phy_m88) {
1824
1825
1826
1827
1828
1829 ret_val =
1830 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1831 &phy_data);
1832 if (ret_val)
1833 return ret_val;
1834
1835 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1836 ret_val =
1837 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1838 phy_data);
1839 if (ret_val)
1840 return ret_val;
1841
1842
1843
1844
1845
1846 ret_val =
1847 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1848 if (ret_val)
1849 return ret_val;
1850
1851 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1852 ret_val =
1853 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1854 if (ret_val)
1855 return ret_val;
1856
1857 if ((hw->mac_type == e1000_82544 ||
1858 hw->mac_type == e1000_82543) &&
1859 (!hw->autoneg) &&
1860 (hw->forced_speed_duplex == e1000_10_full ||
1861 hw->forced_speed_duplex == e1000_10_half)) {
1862 ret_val = e1000_polarity_reversal_workaround(hw);
1863 if (ret_val)
1864 return ret_val;
1865 }
1866 }
1867 return E1000_SUCCESS;
1868}
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878void e1000_config_collision_dist(struct e1000_hw *hw)
1879{
1880 u32 tctl, coll_dist;
1881
1882 if (hw->mac_type < e1000_82543)
1883 coll_dist = E1000_COLLISION_DISTANCE_82542;
1884 else
1885 coll_dist = E1000_COLLISION_DISTANCE;
1886
1887 tctl = er32(TCTL);
1888
1889 tctl &= ~E1000_TCTL_COLD;
1890 tctl |= coll_dist << E1000_COLD_SHIFT;
1891
1892 ew32(TCTL, tctl);
1893 E1000_WRITE_FLUSH();
1894}
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1905{
1906 u32 ctrl;
1907 s32 ret_val;
1908 u16 phy_data;
1909
1910
1911
1912
1913 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
1914 return E1000_SUCCESS;
1915
1916
1917
1918
1919 ctrl = er32(CTRL);
1920 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1921 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1922
1923 switch (hw->phy_type) {
1924 case e1000_phy_8201:
1925 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1926 if (ret_val)
1927 return ret_val;
1928
1929 if (phy_data & RTL_PHY_CTRL_FD)
1930 ctrl |= E1000_CTRL_FD;
1931 else
1932 ctrl &= ~E1000_CTRL_FD;
1933
1934 if (phy_data & RTL_PHY_CTRL_SPD_100)
1935 ctrl |= E1000_CTRL_SPD_100;
1936 else
1937 ctrl |= E1000_CTRL_SPD_10;
1938
1939 e1000_config_collision_dist(hw);
1940 break;
1941 default:
1942
1943
1944
1945 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1946 &phy_data);
1947 if (ret_val)
1948 return ret_val;
1949
1950 if (phy_data & M88E1000_PSSR_DPLX)
1951 ctrl |= E1000_CTRL_FD;
1952 else
1953 ctrl &= ~E1000_CTRL_FD;
1954
1955 e1000_config_collision_dist(hw);
1956
1957
1958
1959
1960 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1961 ctrl |= E1000_CTRL_SPD_1000;
1962 else if ((phy_data & M88E1000_PSSR_SPEED) ==
1963 M88E1000_PSSR_100MBS)
1964 ctrl |= E1000_CTRL_SPD_100;
1965 }
1966
1967
1968 ew32(CTRL, ctrl);
1969 return E1000_SUCCESS;
1970}
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983s32 e1000_force_mac_fc(struct e1000_hw *hw)
1984{
1985 u32 ctrl;
1986
1987
1988 ctrl = er32(CTRL);
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008 switch (hw->fc) {
2009 case E1000_FC_NONE:
2010 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2011 break;
2012 case E1000_FC_RX_PAUSE:
2013 ctrl &= (~E1000_CTRL_TFCE);
2014 ctrl |= E1000_CTRL_RFCE;
2015 break;
2016 case E1000_FC_TX_PAUSE:
2017 ctrl &= (~E1000_CTRL_RFCE);
2018 ctrl |= E1000_CTRL_TFCE;
2019 break;
2020 case E1000_FC_FULL:
2021 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2022 break;
2023 default:
2024 e_dbg("Flow control param set incorrectly\n");
2025 return -E1000_ERR_CONFIG;
2026 }
2027
2028
2029 if (hw->mac_type == e1000_82542_rev2_0)
2030 ctrl &= (~E1000_CTRL_TFCE);
2031
2032 ew32(CTRL, ctrl);
2033 return E1000_SUCCESS;
2034}
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2048{
2049 s32 ret_val;
2050 u16 mii_status_reg;
2051 u16 mii_nway_adv_reg;
2052 u16 mii_nway_lp_ability_reg;
2053 u16 speed;
2054 u16 duplex;
2055
2056
2057
2058
2059
2060 if (((hw->media_type == e1000_media_type_fiber) &&
2061 (hw->autoneg_failed)) ||
2062 ((hw->media_type == e1000_media_type_internal_serdes) &&
2063 (hw->autoneg_failed)) ||
2064 ((hw->media_type == e1000_media_type_copper) &&
2065 (!hw->autoneg))) {
2066 ret_val = e1000_force_mac_fc(hw);
2067 if (ret_val) {
2068 e_dbg("Error forcing flow control settings\n");
2069 return ret_val;
2070 }
2071 }
2072
2073
2074
2075
2076
2077
2078 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2079
2080
2081
2082
2083 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2084 if (ret_val)
2085 return ret_val;
2086 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2087 if (ret_val)
2088 return ret_val;
2089
2090 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2091
2092
2093
2094
2095
2096
2097 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2098 &mii_nway_adv_reg);
2099 if (ret_val)
2100 return ret_val;
2101 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2102 &mii_nway_lp_ability_reg);
2103 if (ret_val)
2104 return ret_val;
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2142 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2143
2144
2145
2146
2147
2148
2149
2150 if (hw->original_fc == E1000_FC_FULL) {
2151 hw->fc = E1000_FC_FULL;
2152 e_dbg("Flow Control = FULL.\n");
2153 } else {
2154 hw->fc = E1000_FC_RX_PAUSE;
2155 e_dbg
2156 ("Flow Control = RX PAUSE frames only.\n");
2157 }
2158 }
2159
2160
2161
2162
2163
2164
2165
2166
2167 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2168 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2169 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2170 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2171 hw->fc = E1000_FC_TX_PAUSE;
2172 e_dbg
2173 ("Flow Control = TX PAUSE frames only.\n");
2174 }
2175
2176
2177
2178
2179
2180
2181
2182
2183 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2184 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2185 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2186 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2187 hw->fc = E1000_FC_RX_PAUSE;
2188 e_dbg
2189 ("Flow Control = RX PAUSE frames only.\n");
2190 }
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213 else if ((hw->original_fc == E1000_FC_NONE ||
2214 hw->original_fc == E1000_FC_TX_PAUSE) ||
2215 hw->fc_strict_ieee) {
2216 hw->fc = E1000_FC_NONE;
2217 e_dbg("Flow Control = NONE.\n");
2218 } else {
2219 hw->fc = E1000_FC_RX_PAUSE;
2220 e_dbg
2221 ("Flow Control = RX PAUSE frames only.\n");
2222 }
2223
2224
2225
2226
2227
2228 ret_val =
2229 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2230 if (ret_val) {
2231 e_dbg
2232 ("Error getting link speed and duplex\n");
2233 return ret_val;
2234 }
2235
2236 if (duplex == HALF_DUPLEX)
2237 hw->fc = E1000_FC_NONE;
2238
2239
2240
2241
2242 ret_val = e1000_force_mac_fc(hw);
2243 if (ret_val) {
2244 e_dbg
2245 ("Error forcing flow control settings\n");
2246 return ret_val;
2247 }
2248 } else {
2249 e_dbg
2250 ("Copper PHY and Auto Neg has not completed.\n");
2251 }
2252 }
2253 return E1000_SUCCESS;
2254}
2255
2256
2257
2258
2259
2260
2261
2262
2263static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
2264{
2265 u32 rxcw;
2266 u32 ctrl;
2267 u32 status;
2268 s32 ret_val = E1000_SUCCESS;
2269
2270 ctrl = er32(CTRL);
2271 status = er32(STATUS);
2272 rxcw = er32(RXCW);
2273
2274
2275
2276
2277
2278
2279
2280
2281 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2282 if (hw->autoneg_failed == 0) {
2283 hw->autoneg_failed = 1;
2284 goto out;
2285 }
2286 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
2287
2288
2289 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2290
2291
2292 ctrl = er32(CTRL);
2293 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2294 ew32(CTRL, ctrl);
2295
2296
2297 ret_val = e1000_config_fc_after_link_up(hw);
2298 if (ret_val) {
2299 e_dbg("Error configuring flow control\n");
2300 goto out;
2301 }
2302 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2303
2304
2305
2306
2307
2308 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
2309 ew32(TXCW, hw->txcw);
2310 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2311
2312 hw->serdes_has_link = true;
2313 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2314
2315
2316
2317
2318
2319 udelay(10);
2320 rxcw = er32(RXCW);
2321 if (rxcw & E1000_RXCW_SYNCH) {
2322 if (!(rxcw & E1000_RXCW_IV)) {
2323 hw->serdes_has_link = true;
2324 e_dbg("SERDES: Link up - forced.\n");
2325 }
2326 } else {
2327 hw->serdes_has_link = false;
2328 e_dbg("SERDES: Link down - force failed.\n");
2329 }
2330 }
2331
2332 if (E1000_TXCW_ANE & er32(TXCW)) {
2333 status = er32(STATUS);
2334 if (status & E1000_STATUS_LU) {
2335
2336 udelay(10);
2337 rxcw = er32(RXCW);
2338 if (rxcw & E1000_RXCW_SYNCH) {
2339 if (!(rxcw & E1000_RXCW_IV)) {
2340 hw->serdes_has_link = true;
2341 e_dbg("SERDES: Link up - autoneg "
2342 "completed successfully.\n");
2343 } else {
2344 hw->serdes_has_link = false;
2345 e_dbg("SERDES: Link down - invalid"
2346 "codewords detected in autoneg.\n");
2347 }
2348 } else {
2349 hw->serdes_has_link = false;
2350 e_dbg("SERDES: Link down - no sync.\n");
2351 }
2352 } else {
2353 hw->serdes_has_link = false;
2354 e_dbg("SERDES: Link down - autoneg failed\n");
2355 }
2356 }
2357
2358 out:
2359 return ret_val;
2360}
2361
2362
2363
2364
2365
2366
2367
2368
2369s32 e1000_check_for_link(struct e1000_hw *hw)
2370{
2371 u32 status;
2372 u32 rctl;
2373 u32 icr;
2374 s32 ret_val;
2375 u16 phy_data;
2376
2377 er32(CTRL);
2378 status = er32(STATUS);
2379
2380
2381
2382
2383
2384 if ((hw->media_type == e1000_media_type_fiber) ||
2385 (hw->media_type == e1000_media_type_internal_serdes)) {
2386 er32(RXCW);
2387
2388 if (hw->media_type == e1000_media_type_fiber) {
2389 if (status & E1000_STATUS_LU)
2390 hw->get_link_status = false;
2391 }
2392 }
2393
2394
2395
2396
2397
2398
2399
2400 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2401
2402
2403
2404
2405
2406 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2407 if (ret_val)
2408 return ret_val;
2409 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2410 if (ret_val)
2411 return ret_val;
2412
2413 if (phy_data & MII_SR_LINK_STATUS) {
2414 hw->get_link_status = false;
2415
2416
2417
2418 e1000_check_downshift(hw);
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429 if ((hw->mac_type == e1000_82544 ||
2430 hw->mac_type == e1000_82543) &&
2431 (!hw->autoneg) &&
2432 (hw->forced_speed_duplex == e1000_10_full ||
2433 hw->forced_speed_duplex == e1000_10_half)) {
2434 ew32(IMC, 0xffffffff);
2435 ret_val =
2436 e1000_polarity_reversal_workaround(hw);
2437 icr = er32(ICR);
2438 ew32(ICS, (icr & ~E1000_ICS_LSC));
2439 ew32(IMS, IMS_ENABLE_MASK);
2440 }
2441
2442 } else {
2443
2444 e1000_config_dsp_after_link_change(hw, false);
2445 return 0;
2446 }
2447
2448
2449
2450
2451 if (!hw->autoneg)
2452 return -E1000_ERR_CONFIG;
2453
2454
2455 e1000_config_dsp_after_link_change(hw, true);
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465 if ((hw->mac_type >= e1000_82544) &&
2466 (hw->mac_type != e1000_ce4100))
2467 e1000_config_collision_dist(hw);
2468 else {
2469 ret_val = e1000_config_mac_to_phy(hw);
2470 if (ret_val) {
2471 e_dbg
2472 ("Error configuring MAC to PHY settings\n");
2473 return ret_val;
2474 }
2475 }
2476
2477
2478
2479
2480
2481
2482 ret_val = e1000_config_fc_after_link_up(hw);
2483 if (ret_val) {
2484 e_dbg("Error configuring flow control\n");
2485 return ret_val;
2486 }
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496 if (hw->tbi_compatibility_en) {
2497 u16 speed, duplex;
2498
2499 ret_val =
2500 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2501
2502 if (ret_val) {
2503 e_dbg
2504 ("Error getting link speed and duplex\n");
2505 return ret_val;
2506 }
2507 if (speed != SPEED_1000) {
2508
2509
2510
2511 if (hw->tbi_compatibility_on) {
2512
2513
2514
2515 rctl = er32(RCTL);
2516 rctl &= ~E1000_RCTL_SBP;
2517 ew32(RCTL, rctl);
2518 hw->tbi_compatibility_on = false;
2519 }
2520 } else {
2521
2522
2523
2524
2525
2526
2527 if (!hw->tbi_compatibility_on) {
2528 hw->tbi_compatibility_on = true;
2529 rctl = er32(RCTL);
2530 rctl |= E1000_RCTL_SBP;
2531 ew32(RCTL, rctl);
2532 }
2533 }
2534 }
2535 }
2536
2537 if ((hw->media_type == e1000_media_type_fiber) ||
2538 (hw->media_type == e1000_media_type_internal_serdes))
2539 e1000_check_for_serdes_link_generic(hw);
2540
2541 return E1000_SUCCESS;
2542}
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
2553{
2554 u32 status;
2555 s32 ret_val;
2556 u16 phy_data;
2557
2558 if (hw->mac_type >= e1000_82543) {
2559 status = er32(STATUS);
2560 if (status & E1000_STATUS_SPEED_1000) {
2561 *speed = SPEED_1000;
2562 e_dbg("1000 Mbs, ");
2563 } else if (status & E1000_STATUS_SPEED_100) {
2564 *speed = SPEED_100;
2565 e_dbg("100 Mbs, ");
2566 } else {
2567 *speed = SPEED_10;
2568 e_dbg("10 Mbs, ");
2569 }
2570
2571 if (status & E1000_STATUS_FD) {
2572 *duplex = FULL_DUPLEX;
2573 e_dbg("Full Duplex\n");
2574 } else {
2575 *duplex = HALF_DUPLEX;
2576 e_dbg(" Half Duplex\n");
2577 }
2578 } else {
2579 e_dbg("1000 Mbs, Full Duplex\n");
2580 *speed = SPEED_1000;
2581 *duplex = FULL_DUPLEX;
2582 }
2583
2584
2585
2586
2587
2588 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2589 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2590 if (ret_val)
2591 return ret_val;
2592
2593 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2594 *duplex = HALF_DUPLEX;
2595 else {
2596 ret_val =
2597 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2598 if (ret_val)
2599 return ret_val;
2600 if ((*speed == SPEED_100 &&
2601 !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
2602 (*speed == SPEED_10 &&
2603 !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2604 *duplex = HALF_DUPLEX;
2605 }
2606 }
2607
2608 return E1000_SUCCESS;
2609}
2610
2611
2612
2613
2614
2615
2616
2617static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2618{
2619 s32 ret_val;
2620 u16 i;
2621 u16 phy_data;
2622
2623 e_dbg("Waiting for Auto-Neg to complete.\n");
2624
2625
2626 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2627
2628
2629
2630 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2631 if (ret_val)
2632 return ret_val;
2633 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2634 if (ret_val)
2635 return ret_val;
2636 if (phy_data & MII_SR_AUTONEG_COMPLETE)
2637 return E1000_SUCCESS;
2638
2639 msleep(100);
2640 }
2641 return E1000_SUCCESS;
2642}
2643
2644
2645
2646
2647
2648
2649static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2650{
2651
2652
2653
2654 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2655 E1000_WRITE_FLUSH();
2656 udelay(10);
2657}
2658
2659
2660
2661
2662
2663
2664static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
2665{
2666
2667
2668
2669 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2670 E1000_WRITE_FLUSH();
2671 udelay(10);
2672}
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
2683{
2684 u32 ctrl;
2685 u32 mask;
2686
2687
2688
2689
2690
2691 mask = 0x01;
2692 mask <<= (count - 1);
2693
2694 ctrl = er32(CTRL);
2695
2696
2697 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2698
2699 while (mask) {
2700
2701
2702
2703
2704
2705 if (data & mask)
2706 ctrl |= E1000_CTRL_MDIO;
2707 else
2708 ctrl &= ~E1000_CTRL_MDIO;
2709
2710 ew32(CTRL, ctrl);
2711 E1000_WRITE_FLUSH();
2712
2713 udelay(10);
2714
2715 e1000_raise_mdi_clk(hw, &ctrl);
2716 e1000_lower_mdi_clk(hw, &ctrl);
2717
2718 mask = mask >> 1;
2719 }
2720}
2721
2722
2723
2724
2725
2726
2727
2728static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2729{
2730 u32 ctrl;
2731 u16 data = 0;
2732 u8 i;
2733
2734
2735
2736
2737
2738
2739
2740
2741 ctrl = er32(CTRL);
2742
2743
2744
2745
2746 ctrl &= ~E1000_CTRL_MDIO_DIR;
2747 ctrl &= ~E1000_CTRL_MDIO;
2748
2749 ew32(CTRL, ctrl);
2750 E1000_WRITE_FLUSH();
2751
2752
2753
2754
2755
2756 e1000_raise_mdi_clk(hw, &ctrl);
2757 e1000_lower_mdi_clk(hw, &ctrl);
2758
2759 for (data = 0, i = 0; i < 16; i++) {
2760 data = data << 1;
2761 e1000_raise_mdi_clk(hw, &ctrl);
2762 ctrl = er32(CTRL);
2763
2764 if (ctrl & E1000_CTRL_MDIO)
2765 data |= 1;
2766 e1000_lower_mdi_clk(hw, &ctrl);
2767 }
2768
2769 e1000_raise_mdi_clk(hw, &ctrl);
2770 e1000_lower_mdi_clk(hw, &ctrl);
2771
2772 return data;
2773}
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
2785{
2786 u32 ret_val;
2787 unsigned long flags;
2788
2789 spin_lock_irqsave(&e1000_phy_lock, flags);
2790
2791 if ((hw->phy_type == e1000_phy_igp) &&
2792 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2793 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2794 (u16) reg_addr);
2795 if (ret_val)
2796 goto out;
2797 }
2798
2799 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2800 phy_data);
2801out:
2802 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2803
2804 return ret_val;
2805}
2806
2807static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2808 u16 *phy_data)
2809{
2810 u32 i;
2811 u32 mdic = 0;
2812 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2813
2814 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2815 e_dbg("PHY Address %d is out of range\n", reg_addr);
2816 return -E1000_ERR_PARAM;
2817 }
2818
2819 if (hw->mac_type > e1000_82543) {
2820
2821
2822
2823
2824 if (hw->mac_type == e1000_ce4100) {
2825 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2826 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2827 (INTEL_CE_GBE_MDIC_OP_READ) |
2828 (INTEL_CE_GBE_MDIC_GO));
2829
2830 writel(mdic, E1000_MDIO_CMD);
2831
2832
2833
2834
2835 for (i = 0; i < 64; i++) {
2836 udelay(50);
2837 mdic = readl(E1000_MDIO_CMD);
2838 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2839 break;
2840 }
2841
2842 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2843 e_dbg("MDI Read did not complete\n");
2844 return -E1000_ERR_PHY;
2845 }
2846
2847 mdic = readl(E1000_MDIO_STS);
2848 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2849 e_dbg("MDI Read Error\n");
2850 return -E1000_ERR_PHY;
2851 }
2852 *phy_data = (u16)mdic;
2853 } else {
2854 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2855 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2856 (E1000_MDIC_OP_READ));
2857
2858 ew32(MDIC, mdic);
2859
2860
2861
2862
2863 for (i = 0; i < 64; i++) {
2864 udelay(50);
2865 mdic = er32(MDIC);
2866 if (mdic & E1000_MDIC_READY)
2867 break;
2868 }
2869 if (!(mdic & E1000_MDIC_READY)) {
2870 e_dbg("MDI Read did not complete\n");
2871 return -E1000_ERR_PHY;
2872 }
2873 if (mdic & E1000_MDIC_ERROR) {
2874 e_dbg("MDI Error\n");
2875 return -E1000_ERR_PHY;
2876 }
2877 *phy_data = (u16)mdic;
2878 }
2879 } else {
2880
2881
2882
2883
2884 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898 mdic = ((reg_addr) | (phy_addr << 5) |
2899 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2900
2901 e1000_shift_out_mdi_bits(hw, mdic, 14);
2902
2903
2904
2905
2906
2907 *phy_data = e1000_shift_in_mdi_bits(hw);
2908 }
2909 return E1000_SUCCESS;
2910}
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
2922{
2923 u32 ret_val;
2924 unsigned long flags;
2925
2926 spin_lock_irqsave(&e1000_phy_lock, flags);
2927
2928 if ((hw->phy_type == e1000_phy_igp) &&
2929 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2930 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2931 (u16)reg_addr);
2932 if (ret_val) {
2933 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2934 return ret_val;
2935 }
2936 }
2937
2938 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2939 phy_data);
2940 spin_unlock_irqrestore(&e1000_phy_lock, flags);
2941
2942 return ret_val;
2943}
2944
2945static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2946 u16 phy_data)
2947{
2948 u32 i;
2949 u32 mdic = 0;
2950 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
2951
2952 if (reg_addr > MAX_PHY_REG_ADDRESS) {
2953 e_dbg("PHY Address %d is out of range\n", reg_addr);
2954 return -E1000_ERR_PARAM;
2955 }
2956
2957 if (hw->mac_type > e1000_82543) {
2958
2959
2960
2961
2962
2963 if (hw->mac_type == e1000_ce4100) {
2964 mdic = (((u32)phy_data) |
2965 (reg_addr << E1000_MDIC_REG_SHIFT) |
2966 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2967 (INTEL_CE_GBE_MDIC_OP_WRITE) |
2968 (INTEL_CE_GBE_MDIC_GO));
2969
2970 writel(mdic, E1000_MDIO_CMD);
2971
2972
2973
2974
2975 for (i = 0; i < 640; i++) {
2976 udelay(5);
2977 mdic = readl(E1000_MDIO_CMD);
2978 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2979 break;
2980 }
2981 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2982 e_dbg("MDI Write did not complete\n");
2983 return -E1000_ERR_PHY;
2984 }
2985 } else {
2986 mdic = (((u32)phy_data) |
2987 (reg_addr << E1000_MDIC_REG_SHIFT) |
2988 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2989 (E1000_MDIC_OP_WRITE));
2990
2991 ew32(MDIC, mdic);
2992
2993
2994
2995
2996 for (i = 0; i < 641; i++) {
2997 udelay(5);
2998 mdic = er32(MDIC);
2999 if (mdic & E1000_MDIC_READY)
3000 break;
3001 }
3002 if (!(mdic & E1000_MDIC_READY)) {
3003 e_dbg("MDI Write did not complete\n");
3004 return -E1000_ERR_PHY;
3005 }
3006 }
3007 } else {
3008
3009
3010
3011
3012
3013 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3014
3015
3016
3017
3018
3019
3020
3021 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3022 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3023 mdic <<= 16;
3024 mdic |= (u32)phy_data;
3025
3026 e1000_shift_out_mdi_bits(hw, mdic, 32);
3027 }
3028
3029 return E1000_SUCCESS;
3030}
3031
3032
3033
3034
3035
3036
3037
3038s32 e1000_phy_hw_reset(struct e1000_hw *hw)
3039{
3040 u32 ctrl, ctrl_ext;
3041 u32 led_ctrl;
3042
3043 e_dbg("Resetting Phy...\n");
3044
3045 if (hw->mac_type > e1000_82543) {
3046
3047
3048
3049
3050
3051 ctrl = er32(CTRL);
3052 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3053 E1000_WRITE_FLUSH();
3054
3055 msleep(10);
3056
3057 ew32(CTRL, ctrl);
3058 E1000_WRITE_FLUSH();
3059
3060 } else {
3061
3062
3063
3064
3065 ctrl_ext = er32(CTRL_EXT);
3066 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3067 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3068 ew32(CTRL_EXT, ctrl_ext);
3069 E1000_WRITE_FLUSH();
3070 msleep(10);
3071 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3072 ew32(CTRL_EXT, ctrl_ext);
3073 E1000_WRITE_FLUSH();
3074 }
3075 udelay(150);
3076
3077 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3078
3079 led_ctrl = er32(LEDCTL);
3080 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3081 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3082 ew32(LEDCTL, led_ctrl);
3083 }
3084
3085
3086 return e1000_get_phy_cfg_done(hw);
3087}
3088
3089
3090
3091
3092
3093
3094
3095
3096s32 e1000_phy_reset(struct e1000_hw *hw)
3097{
3098 s32 ret_val;
3099 u16 phy_data;
3100
3101 switch (hw->phy_type) {
3102 case e1000_phy_igp:
3103 ret_val = e1000_phy_hw_reset(hw);
3104 if (ret_val)
3105 return ret_val;
3106 break;
3107 default:
3108 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3109 if (ret_val)
3110 return ret_val;
3111
3112 phy_data |= MII_CR_RESET;
3113 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3114 if (ret_val)
3115 return ret_val;
3116
3117 udelay(1);
3118 break;
3119 }
3120
3121 if (hw->phy_type == e1000_phy_igp)
3122 e1000_phy_init_script(hw);
3123
3124 return E1000_SUCCESS;
3125}
3126
3127
3128
3129
3130
3131
3132
3133static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
3134{
3135 s32 phy_init_status, ret_val;
3136 u16 phy_id_high, phy_id_low;
3137 bool match = false;
3138
3139 if (hw->phy_id != 0)
3140 return E1000_SUCCESS;
3141
3142
3143 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3144 if (ret_val)
3145 return ret_val;
3146
3147 hw->phy_id = (u32)(phy_id_high << 16);
3148 udelay(20);
3149 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3150 if (ret_val)
3151 return ret_val;
3152
3153 hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
3154 hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
3155
3156 switch (hw->mac_type) {
3157 case e1000_82543:
3158 if (hw->phy_id == M88E1000_E_PHY_ID)
3159 match = true;
3160 break;
3161 case e1000_82544:
3162 if (hw->phy_id == M88E1000_I_PHY_ID)
3163 match = true;
3164 break;
3165 case e1000_82540:
3166 case e1000_82545:
3167 case e1000_82545_rev_3:
3168 case e1000_82546:
3169 case e1000_82546_rev_3:
3170 if (hw->phy_id == M88E1011_I_PHY_ID)
3171 match = true;
3172 break;
3173 case e1000_ce4100:
3174 if ((hw->phy_id == RTL8211B_PHY_ID) ||
3175 (hw->phy_id == RTL8201N_PHY_ID) ||
3176 (hw->phy_id == M88E1118_E_PHY_ID))
3177 match = true;
3178 break;
3179 case e1000_82541:
3180 case e1000_82541_rev_2:
3181 case e1000_82547:
3182 case e1000_82547_rev_2:
3183 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3184 match = true;
3185 break;
3186 default:
3187 e_dbg("Invalid MAC type %d\n", hw->mac_type);
3188 return -E1000_ERR_CONFIG;
3189 }
3190 phy_init_status = e1000_set_phy_type(hw);
3191
3192 if ((match) && (phy_init_status == E1000_SUCCESS)) {
3193 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
3194 return E1000_SUCCESS;
3195 }
3196 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
3197 return -E1000_ERR_PHY;
3198}
3199
3200
3201
3202
3203
3204
3205
3206static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
3207{
3208 s32 ret_val;
3209
3210 do {
3211 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3212 if (ret_val)
3213 break;
3214 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3215 if (ret_val)
3216 break;
3217 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3218 if (ret_val)
3219 break;
3220 ret_val = E1000_SUCCESS;
3221 } while (0);
3222
3223 return ret_val;
3224}
3225
3226
3227
3228
3229
3230
3231
3232
3233static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3234 struct e1000_phy_info *phy_info)
3235{
3236 s32 ret_val;
3237 u16 phy_data, min_length, max_length, average;
3238 e1000_rev_polarity polarity;
3239
3240
3241
3242
3243 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3244
3245
3246 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3247
3248
3249 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3250
3251
3252 ret_val = e1000_check_polarity(hw, &polarity);
3253 if (ret_val)
3254 return ret_val;
3255
3256 phy_info->cable_polarity = polarity;
3257
3258 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3259 if (ret_val)
3260 return ret_val;
3261
3262 phy_info->mdix_mode =
3263 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3264 IGP01E1000_PSSR_MDIX_SHIFT);
3265
3266 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3267 IGP01E1000_PSSR_SPEED_1000MBPS) {
3268
3269
3270
3271 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3272 if (ret_val)
3273 return ret_val;
3274
3275 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3276 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3277 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3278 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3279 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3280 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3281
3282
3283 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3284 if (ret_val)
3285 return ret_val;
3286
3287
3288 average = (max_length + min_length) / 2;
3289
3290 if (average <= e1000_igp_cable_length_50)
3291 phy_info->cable_length = e1000_cable_length_50;
3292 else if (average <= e1000_igp_cable_length_80)
3293 phy_info->cable_length = e1000_cable_length_50_80;
3294 else if (average <= e1000_igp_cable_length_110)
3295 phy_info->cable_length = e1000_cable_length_80_110;
3296 else if (average <= e1000_igp_cable_length_140)
3297 phy_info->cable_length = e1000_cable_length_110_140;
3298 else
3299 phy_info->cable_length = e1000_cable_length_140;
3300 }
3301
3302 return E1000_SUCCESS;
3303}
3304
3305
3306
3307
3308
3309
3310
3311
3312static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3313 struct e1000_phy_info *phy_info)
3314{
3315 s32 ret_val;
3316 u16 phy_data;
3317 e1000_rev_polarity polarity;
3318
3319
3320
3321
3322 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3323
3324 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3325 if (ret_val)
3326 return ret_val;
3327
3328 phy_info->extended_10bt_distance =
3329 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3330 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3331 e1000_10bt_ext_dist_enable_lower :
3332 e1000_10bt_ext_dist_enable_normal;
3333
3334 phy_info->polarity_correction =
3335 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3336 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3337 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3338
3339
3340 ret_val = e1000_check_polarity(hw, &polarity);
3341 if (ret_val)
3342 return ret_val;
3343 phy_info->cable_polarity = polarity;
3344
3345 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3346 if (ret_val)
3347 return ret_val;
3348
3349 phy_info->mdix_mode =
3350 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3351 M88E1000_PSSR_MDIX_SHIFT);
3352
3353 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3354
3355
3356
3357 phy_info->cable_length =
3358 (e1000_cable_length) ((phy_data &
3359 M88E1000_PSSR_CABLE_LENGTH) >>
3360 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3361
3362 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3363 if (ret_val)
3364 return ret_val;
3365
3366 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3367 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3368 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3369 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3370 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3371 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3372 }
3373
3374 return E1000_SUCCESS;
3375}
3376
3377
3378
3379
3380
3381
3382
3383
3384s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
3385{
3386 s32 ret_val;
3387 u16 phy_data;
3388
3389 phy_info->cable_length = e1000_cable_length_undefined;
3390 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3391 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3392 phy_info->downshift = e1000_downshift_undefined;
3393 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3394 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3395 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3396 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3397
3398 if (hw->media_type != e1000_media_type_copper) {
3399 e_dbg("PHY info is only valid for copper media\n");
3400 return -E1000_ERR_CONFIG;
3401 }
3402
3403 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3404 if (ret_val)
3405 return ret_val;
3406
3407 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3408 if (ret_val)
3409 return ret_val;
3410
3411 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
3412 e_dbg("PHY info is only valid if link is up\n");
3413 return -E1000_ERR_CONFIG;
3414 }
3415
3416 if (hw->phy_type == e1000_phy_igp)
3417 return e1000_phy_igp_get_info(hw, phy_info);
3418 else if ((hw->phy_type == e1000_phy_8211) ||
3419 (hw->phy_type == e1000_phy_8201))
3420 return E1000_SUCCESS;
3421 else
3422 return e1000_phy_m88_get_info(hw, phy_info);
3423}
3424
3425s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
3426{
3427 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
3428 e_dbg("Invalid MDI setting detected\n");
3429 hw->mdix = 1;
3430 return -E1000_ERR_CONFIG;
3431 }
3432 return E1000_SUCCESS;
3433}
3434
3435
3436
3437
3438
3439
3440
3441
3442s32 e1000_init_eeprom_params(struct e1000_hw *hw)
3443{
3444 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3445 u32 eecd = er32(EECD);
3446 s32 ret_val = E1000_SUCCESS;
3447 u16 eeprom_size;
3448
3449 switch (hw->mac_type) {
3450 case e1000_82542_rev2_0:
3451 case e1000_82542_rev2_1:
3452 case e1000_82543:
3453 case e1000_82544:
3454 eeprom->type = e1000_eeprom_microwire;
3455 eeprom->word_size = 64;
3456 eeprom->opcode_bits = 3;
3457 eeprom->address_bits = 6;
3458 eeprom->delay_usec = 50;
3459 break;
3460 case e1000_82540:
3461 case e1000_82545:
3462 case e1000_82545_rev_3:
3463 case e1000_82546:
3464 case e1000_82546_rev_3:
3465 eeprom->type = e1000_eeprom_microwire;
3466 eeprom->opcode_bits = 3;
3467 eeprom->delay_usec = 50;
3468 if (eecd & E1000_EECD_SIZE) {
3469 eeprom->word_size = 256;
3470 eeprom->address_bits = 8;
3471 } else {
3472 eeprom->word_size = 64;
3473 eeprom->address_bits = 6;
3474 }
3475 break;
3476 case e1000_82541:
3477 case e1000_82541_rev_2:
3478 case e1000_82547:
3479 case e1000_82547_rev_2:
3480 if (eecd & E1000_EECD_TYPE) {
3481 eeprom->type = e1000_eeprom_spi;
3482 eeprom->opcode_bits = 8;
3483 eeprom->delay_usec = 1;
3484 if (eecd & E1000_EECD_ADDR_BITS) {
3485 eeprom->page_size = 32;
3486 eeprom->address_bits = 16;
3487 } else {
3488 eeprom->page_size = 8;
3489 eeprom->address_bits = 8;
3490 }
3491 } else {
3492 eeprom->type = e1000_eeprom_microwire;
3493 eeprom->opcode_bits = 3;
3494 eeprom->delay_usec = 50;
3495 if (eecd & E1000_EECD_ADDR_BITS) {
3496 eeprom->word_size = 256;
3497 eeprom->address_bits = 8;
3498 } else {
3499 eeprom->word_size = 64;
3500 eeprom->address_bits = 6;
3501 }
3502 }
3503 break;
3504 default:
3505 break;
3506 }
3507
3508 if (eeprom->type == e1000_eeprom_spi) {
3509
3510
3511
3512
3513 eeprom->word_size = 64;
3514 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3515 if (ret_val)
3516 return ret_val;
3517 eeprom_size =
3518 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3519
3520
3521
3522
3523 if (eeprom_size)
3524 eeprom_size++;
3525
3526 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3527 }
3528 return ret_val;
3529}
3530
3531
3532
3533
3534
3535
3536static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
3537{
3538
3539
3540
3541 *eecd = *eecd | E1000_EECD_SK;
3542 ew32(EECD, *eecd);
3543 E1000_WRITE_FLUSH();
3544 udelay(hw->eeprom.delay_usec);
3545}
3546
3547
3548
3549
3550
3551
3552static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
3553{
3554
3555
3556
3557 *eecd = *eecd & ~E1000_EECD_SK;
3558 ew32(EECD, *eecd);
3559 E1000_WRITE_FLUSH();
3560 udelay(hw->eeprom.delay_usec);
3561}
3562
3563
3564
3565
3566
3567
3568
3569static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
3570{
3571 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3572 u32 eecd;
3573 u32 mask;
3574
3575
3576
3577
3578
3579 mask = 0x01 << (count - 1);
3580 eecd = er32(EECD);
3581 if (eeprom->type == e1000_eeprom_microwire)
3582 eecd &= ~E1000_EECD_DO;
3583 else if (eeprom->type == e1000_eeprom_spi)
3584 eecd |= E1000_EECD_DO;
3585
3586 do {
3587
3588
3589
3590
3591
3592
3593 eecd &= ~E1000_EECD_DI;
3594
3595 if (data & mask)
3596 eecd |= E1000_EECD_DI;
3597
3598 ew32(EECD, eecd);
3599 E1000_WRITE_FLUSH();
3600
3601 udelay(eeprom->delay_usec);
3602
3603 e1000_raise_ee_clk(hw, &eecd);
3604 e1000_lower_ee_clk(hw, &eecd);
3605
3606 mask = mask >> 1;
3607
3608 } while (mask);
3609
3610
3611 eecd &= ~E1000_EECD_DI;
3612 ew32(EECD, eecd);
3613}
3614
3615
3616
3617
3618
3619
3620static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
3621{
3622 u32 eecd;
3623 u32 i;
3624 u16 data;
3625
3626
3627
3628
3629
3630
3631
3632
3633 eecd = er32(EECD);
3634
3635 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3636 data = 0;
3637
3638 for (i = 0; i < count; i++) {
3639 data = data << 1;
3640 e1000_raise_ee_clk(hw, &eecd);
3641
3642 eecd = er32(EECD);
3643
3644 eecd &= ~(E1000_EECD_DI);
3645 if (eecd & E1000_EECD_DO)
3646 data |= 1;
3647
3648 e1000_lower_ee_clk(hw, &eecd);
3649 }
3650
3651 return data;
3652}
3653
3654
3655
3656
3657
3658
3659
3660
3661static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
3662{
3663 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3664 u32 eecd, i = 0;
3665
3666 eecd = er32(EECD);
3667
3668
3669 if (hw->mac_type > e1000_82544) {
3670 eecd |= E1000_EECD_REQ;
3671 ew32(EECD, eecd);
3672 eecd = er32(EECD);
3673 while ((!(eecd & E1000_EECD_GNT)) &&
3674 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3675 i++;
3676 udelay(5);
3677 eecd = er32(EECD);
3678 }
3679 if (!(eecd & E1000_EECD_GNT)) {
3680 eecd &= ~E1000_EECD_REQ;
3681 ew32(EECD, eecd);
3682 e_dbg("Could not acquire EEPROM grant\n");
3683 return -E1000_ERR_EEPROM;
3684 }
3685 }
3686
3687
3688
3689 if (eeprom->type == e1000_eeprom_microwire) {
3690
3691 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3692 ew32(EECD, eecd);
3693
3694
3695 eecd |= E1000_EECD_CS;
3696 ew32(EECD, eecd);
3697 } else if (eeprom->type == e1000_eeprom_spi) {
3698
3699 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3700 ew32(EECD, eecd);
3701 E1000_WRITE_FLUSH();
3702 udelay(1);
3703 }
3704
3705 return E1000_SUCCESS;
3706}
3707
3708
3709
3710
3711
3712static void e1000_standby_eeprom(struct e1000_hw *hw)
3713{
3714 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3715 u32 eecd;
3716
3717 eecd = er32(EECD);
3718
3719 if (eeprom->type == e1000_eeprom_microwire) {
3720 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3721 ew32(EECD, eecd);
3722 E1000_WRITE_FLUSH();
3723 udelay(eeprom->delay_usec);
3724
3725
3726 eecd |= E1000_EECD_SK;
3727 ew32(EECD, eecd);
3728 E1000_WRITE_FLUSH();
3729 udelay(eeprom->delay_usec);
3730
3731
3732 eecd |= E1000_EECD_CS;
3733 ew32(EECD, eecd);
3734 E1000_WRITE_FLUSH();
3735 udelay(eeprom->delay_usec);
3736
3737
3738 eecd &= ~E1000_EECD_SK;
3739 ew32(EECD, eecd);
3740 E1000_WRITE_FLUSH();
3741 udelay(eeprom->delay_usec);
3742 } else if (eeprom->type == e1000_eeprom_spi) {
3743
3744 eecd |= E1000_EECD_CS;
3745 ew32(EECD, eecd);
3746 E1000_WRITE_FLUSH();
3747 udelay(eeprom->delay_usec);
3748 eecd &= ~E1000_EECD_CS;
3749 ew32(EECD, eecd);
3750 E1000_WRITE_FLUSH();
3751 udelay(eeprom->delay_usec);
3752 }
3753}
3754
3755
3756
3757
3758
3759
3760
3761static void e1000_release_eeprom(struct e1000_hw *hw)
3762{
3763 u32 eecd;
3764
3765 eecd = er32(EECD);
3766
3767 if (hw->eeprom.type == e1000_eeprom_spi) {
3768 eecd |= E1000_EECD_CS;
3769 eecd &= ~E1000_EECD_SK;
3770
3771 ew32(EECD, eecd);
3772 E1000_WRITE_FLUSH();
3773
3774 udelay(hw->eeprom.delay_usec);
3775 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3776
3777
3778
3779 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
3780
3781 ew32(EECD, eecd);
3782
3783
3784 eecd |= E1000_EECD_SK;
3785 ew32(EECD, eecd);
3786 E1000_WRITE_FLUSH();
3787 udelay(hw->eeprom.delay_usec);
3788
3789
3790 eecd &= ~E1000_EECD_SK;
3791 ew32(EECD, eecd);
3792 E1000_WRITE_FLUSH();
3793 udelay(hw->eeprom.delay_usec);
3794 }
3795
3796
3797 if (hw->mac_type > e1000_82544) {
3798 eecd &= ~E1000_EECD_REQ;
3799 ew32(EECD, eecd);
3800 }
3801}
3802
3803
3804
3805
3806
3807static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3808{
3809 u16 retry_count = 0;
3810 u8 spi_stat_reg;
3811
3812
3813
3814
3815
3816
3817 retry_count = 0;
3818 do {
3819 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3820 hw->eeprom.opcode_bits);
3821 spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
3822 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3823 break;
3824
3825 udelay(5);
3826 retry_count += 5;
3827
3828 e1000_standby_eeprom(hw);
3829 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3830
3831
3832
3833
3834 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
3835 e_dbg("SPI EEPROM Status error\n");
3836 return -E1000_ERR_EEPROM;
3837 }
3838
3839 return E1000_SUCCESS;
3840}
3841
3842
3843
3844
3845
3846
3847
3848
3849s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
3850{
3851 s32 ret;
3852
3853 mutex_lock(&e1000_eeprom_lock);
3854 ret = e1000_do_read_eeprom(hw, offset, words, data);
3855 mutex_unlock(&e1000_eeprom_lock);
3856 return ret;
3857}
3858
3859static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3860 u16 *data)
3861{
3862 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3863 u32 i = 0;
3864
3865 if (hw->mac_type == e1000_ce4100) {
3866 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3867 data);
3868 return E1000_SUCCESS;
3869 }
3870
3871
3872
3873
3874 if ((offset >= eeprom->word_size) ||
3875 (words > eeprom->word_size - offset) ||
3876 (words == 0)) {
3877 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3878 "size = %d\n", offset, eeprom->word_size);
3879 return -E1000_ERR_EEPROM;
3880 }
3881
3882
3883
3884
3885
3886
3887 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3888 return -E1000_ERR_EEPROM;
3889
3890
3891
3892
3893 if (eeprom->type == e1000_eeprom_spi) {
3894 u16 word_in;
3895 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3896
3897 if (e1000_spi_eeprom_ready(hw)) {
3898 e1000_release_eeprom(hw);
3899 return -E1000_ERR_EEPROM;
3900 }
3901
3902 e1000_standby_eeprom(hw);
3903
3904
3905
3906
3907 if ((eeprom->address_bits == 8) && (offset >= 128))
3908 read_opcode |= EEPROM_A8_OPCODE_SPI;
3909
3910
3911 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3912 e1000_shift_out_ee_bits(hw, (u16)(offset * 2),
3913 eeprom->address_bits);
3914
3915
3916
3917
3918
3919
3920
3921
3922 for (i = 0; i < words; i++) {
3923 word_in = e1000_shift_in_ee_bits(hw, 16);
3924 data[i] = (word_in >> 8) | (word_in << 8);
3925 }
3926 } else if (eeprom->type == e1000_eeprom_microwire) {
3927 for (i = 0; i < words; i++) {
3928
3929 e1000_shift_out_ee_bits(hw,
3930 EEPROM_READ_OPCODE_MICROWIRE,
3931 eeprom->opcode_bits);
3932 e1000_shift_out_ee_bits(hw, (u16)(offset + i),
3933 eeprom->address_bits);
3934
3935
3936
3937
3938 data[i] = e1000_shift_in_ee_bits(hw, 16);
3939 e1000_standby_eeprom(hw);
3940 cond_resched();
3941 }
3942 }
3943
3944
3945 e1000_release_eeprom(hw);
3946
3947 return E1000_SUCCESS;
3948}
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3959{
3960 u16 checksum = 0;
3961 u16 i, eeprom_data;
3962
3963 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3964 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3965 e_dbg("EEPROM Read Error\n");
3966 return -E1000_ERR_EEPROM;
3967 }
3968 checksum += eeprom_data;
3969 }
3970
3971#ifdef CONFIG_PARISC
3972
3973 if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6))
3974 return E1000_SUCCESS;
3975
3976#endif
3977 if (checksum == (u16)EEPROM_SUM)
3978 return E1000_SUCCESS;
3979 else {
3980 e_dbg("EEPROM Checksum Invalid\n");
3981 return -E1000_ERR_EEPROM;
3982 }
3983}
3984
3985
3986
3987
3988
3989
3990
3991
3992s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
3993{
3994 u16 checksum = 0;
3995 u16 i, eeprom_data;
3996
3997 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
3998 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3999 e_dbg("EEPROM Read Error\n");
4000 return -E1000_ERR_EEPROM;
4001 }
4002 checksum += eeprom_data;
4003 }
4004 checksum = (u16)EEPROM_SUM - checksum;
4005 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
4006 e_dbg("EEPROM Write Error\n");
4007 return -E1000_ERR_EEPROM;
4008 }
4009 return E1000_SUCCESS;
4010}
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
4023{
4024 s32 ret;
4025
4026 mutex_lock(&e1000_eeprom_lock);
4027 ret = e1000_do_write_eeprom(hw, offset, words, data);
4028 mutex_unlock(&e1000_eeprom_lock);
4029 return ret;
4030}
4031
4032static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4033 u16 *data)
4034{
4035 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4036 s32 status = 0;
4037
4038 if (hw->mac_type == e1000_ce4100) {
4039 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4040 data);
4041 return E1000_SUCCESS;
4042 }
4043
4044
4045
4046
4047 if ((offset >= eeprom->word_size) ||
4048 (words > eeprom->word_size - offset) ||
4049 (words == 0)) {
4050 e_dbg("\"words\" parameter out of bounds\n");
4051 return -E1000_ERR_EEPROM;
4052 }
4053
4054
4055 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4056 return -E1000_ERR_EEPROM;
4057
4058 if (eeprom->type == e1000_eeprom_microwire) {
4059 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4060 } else {
4061 status = e1000_write_eeprom_spi(hw, offset, words, data);
4062 msleep(10);
4063 }
4064
4065
4066 e1000_release_eeprom(hw);
4067
4068 return status;
4069}
4070
4071
4072
4073
4074
4075
4076
4077
4078static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4079 u16 *data)
4080{
4081 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4082 u16 widx = 0;
4083
4084 while (widx < words) {
4085 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
4086
4087 if (e1000_spi_eeprom_ready(hw))
4088 return -E1000_ERR_EEPROM;
4089
4090 e1000_standby_eeprom(hw);
4091 cond_resched();
4092
4093
4094 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4095 eeprom->opcode_bits);
4096
4097 e1000_standby_eeprom(hw);
4098
4099
4100
4101
4102 if ((eeprom->address_bits == 8) && (offset >= 128))
4103 write_opcode |= EEPROM_A8_OPCODE_SPI;
4104
4105
4106 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
4107
4108 e1000_shift_out_ee_bits(hw, (u16)((offset + widx) * 2),
4109 eeprom->address_bits);
4110
4111
4112
4113
4114
4115
4116 while (widx < words) {
4117 u16 word_out = data[widx];
4118
4119 word_out = (word_out >> 8) | (word_out << 8);
4120 e1000_shift_out_ee_bits(hw, word_out, 16);
4121 widx++;
4122
4123
4124
4125
4126
4127
4128 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4129 e1000_standby_eeprom(hw);
4130 break;
4131 }
4132 }
4133 }
4134
4135 return E1000_SUCCESS;
4136}
4137
4138
4139
4140
4141
4142
4143
4144
4145static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4146 u16 words, u16 *data)
4147{
4148 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4149 u32 eecd;
4150 u16 words_written = 0;
4151 u16 i = 0;
4152
4153
4154
4155
4156
4157
4158
4159 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4160 (u16)(eeprom->opcode_bits + 2));
4161
4162 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4163
4164
4165 e1000_standby_eeprom(hw);
4166
4167 while (words_written < words) {
4168
4169 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4170 eeprom->opcode_bits);
4171
4172 e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
4173 eeprom->address_bits);
4174
4175
4176 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4177
4178
4179
4180
4181 e1000_standby_eeprom(hw);
4182
4183
4184
4185
4186
4187
4188 for (i = 0; i < 200; i++) {
4189 eecd = er32(EECD);
4190 if (eecd & E1000_EECD_DO)
4191 break;
4192 udelay(50);
4193 }
4194 if (i == 200) {
4195 e_dbg("EEPROM Write did not complete\n");
4196 return -E1000_ERR_EEPROM;
4197 }
4198
4199
4200 e1000_standby_eeprom(hw);
4201 cond_resched();
4202
4203 words_written++;
4204 }
4205
4206
4207
4208
4209
4210
4211
4212 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4213 (u16)(eeprom->opcode_bits + 2));
4214
4215 e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
4216
4217 return E1000_SUCCESS;
4218}
4219
4220
4221
4222
4223
4224
4225
4226
4227s32 e1000_read_mac_addr(struct e1000_hw *hw)
4228{
4229 u16 offset;
4230 u16 eeprom_data, i;
4231
4232 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4233 offset = i >> 1;
4234 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
4235 e_dbg("EEPROM Read Error\n");
4236 return -E1000_ERR_EEPROM;
4237 }
4238 hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
4239 hw->perm_mac_addr[i + 1] = (u8)(eeprom_data >> 8);
4240 }
4241
4242 switch (hw->mac_type) {
4243 default:
4244 break;
4245 case e1000_82546:
4246 case e1000_82546_rev_3:
4247 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4248 hw->perm_mac_addr[5] ^= 0x01;
4249 break;
4250 }
4251
4252 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4253 hw->mac_addr[i] = hw->perm_mac_addr[i];
4254 return E1000_SUCCESS;
4255}
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265static void e1000_init_rx_addrs(struct e1000_hw *hw)
4266{
4267 u32 i;
4268 u32 rar_num;
4269
4270
4271 e_dbg("Programming MAC Address into RAR[0]\n");
4272
4273 e1000_rar_set(hw, hw->mac_addr, 0);
4274
4275 rar_num = E1000_RAR_ENTRIES;
4276
4277
4278
4279
4280 e_dbg("Clearing RAR[1-14]\n");
4281 for (i = 1; i < rar_num; i++) {
4282 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4283 E1000_WRITE_FLUSH();
4284 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4285 E1000_WRITE_FLUSH();
4286 }
4287}
4288
4289
4290
4291
4292
4293
4294u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
4295{
4296 u32 hash_value = 0;
4297
4298
4299
4300
4301 switch (hw->mc_filter_type) {
4302
4303
4304
4305
4306 case 0:
4307
4308 hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
4309 break;
4310 case 1:
4311
4312 hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
4313 break;
4314 case 2:
4315
4316 hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
4317 break;
4318 case 3:
4319
4320 hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
4321 break;
4322 }
4323
4324 hash_value &= 0xFFF;
4325 return hash_value;
4326}
4327
4328
4329
4330
4331
4332
4333
4334void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
4335{
4336 u32 rar_low, rar_high;
4337
4338
4339
4340
4341 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
4342 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
4343 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363 switch (hw->mac_type) {
4364 default:
4365
4366 rar_high |= E1000_RAH_AV;
4367 break;
4368 }
4369
4370 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4371 E1000_WRITE_FLUSH();
4372 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4373 E1000_WRITE_FLUSH();
4374}
4375
4376
4377
4378
4379
4380
4381
4382void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
4383{
4384 u32 temp;
4385
4386 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4387 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4388 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4389 E1000_WRITE_FLUSH();
4390 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4391 E1000_WRITE_FLUSH();
4392 } else {
4393 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4394 E1000_WRITE_FLUSH();
4395 }
4396}
4397
4398
4399
4400
4401
4402static void e1000_clear_vfta(struct e1000_hw *hw)
4403{
4404 u32 offset;
4405
4406 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4407 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
4408 E1000_WRITE_FLUSH();
4409 }
4410}
4411
4412static s32 e1000_id_led_init(struct e1000_hw *hw)
4413{
4414 u32 ledctl;
4415 const u32 ledctl_mask = 0x000000FF;
4416 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4417 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4418 u16 eeprom_data, i, temp;
4419 const u16 led_mask = 0x0F;
4420
4421 if (hw->mac_type < e1000_82540) {
4422
4423 return E1000_SUCCESS;
4424 }
4425
4426 ledctl = er32(LEDCTL);
4427 hw->ledctl_default = ledctl;
4428 hw->ledctl_mode1 = hw->ledctl_default;
4429 hw->ledctl_mode2 = hw->ledctl_default;
4430
4431 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
4432 e_dbg("EEPROM Read Error\n");
4433 return -E1000_ERR_EEPROM;
4434 }
4435
4436 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4437 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4438 eeprom_data = ID_LED_DEFAULT;
4439 }
4440
4441 for (i = 0; i < 4; i++) {
4442 temp = (eeprom_data >> (i << 2)) & led_mask;
4443 switch (temp) {
4444 case ID_LED_ON1_DEF2:
4445 case ID_LED_ON1_ON2:
4446 case ID_LED_ON1_OFF2:
4447 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4448 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4449 break;
4450 case ID_LED_OFF1_DEF2:
4451 case ID_LED_OFF1_ON2:
4452 case ID_LED_OFF1_OFF2:
4453 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4454 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4455 break;
4456 default:
4457
4458 break;
4459 }
4460 switch (temp) {
4461 case ID_LED_DEF1_ON2:
4462 case ID_LED_ON1_ON2:
4463 case ID_LED_OFF1_ON2:
4464 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4465 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4466 break;
4467 case ID_LED_DEF1_OFF2:
4468 case ID_LED_ON1_OFF2:
4469 case ID_LED_OFF1_OFF2:
4470 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4471 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4472 break;
4473 default:
4474
4475 break;
4476 }
4477 }
4478 return E1000_SUCCESS;
4479}
4480
4481
4482
4483
4484
4485
4486
4487s32 e1000_setup_led(struct e1000_hw *hw)
4488{
4489 u32 ledctl;
4490 s32 ret_val = E1000_SUCCESS;
4491
4492 switch (hw->mac_type) {
4493 case e1000_82542_rev2_0:
4494 case e1000_82542_rev2_1:
4495 case e1000_82543:
4496 case e1000_82544:
4497
4498 break;
4499 case e1000_82541:
4500 case e1000_82547:
4501 case e1000_82541_rev_2:
4502 case e1000_82547_rev_2:
4503
4504 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4505 &hw->phy_spd_default);
4506 if (ret_val)
4507 return ret_val;
4508 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4509 (u16)(hw->phy_spd_default &
4510 ~IGP01E1000_GMII_SPD));
4511 if (ret_val)
4512 return ret_val;
4513 fallthrough;
4514 default:
4515 if (hw->media_type == e1000_media_type_fiber) {
4516 ledctl = er32(LEDCTL);
4517
4518 hw->ledctl_default = ledctl;
4519
4520 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4521 E1000_LEDCTL_LED0_BLINK |
4522 E1000_LEDCTL_LED0_MODE_MASK);
4523 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4524 E1000_LEDCTL_LED0_MODE_SHIFT);
4525 ew32(LEDCTL, ledctl);
4526 } else if (hw->media_type == e1000_media_type_copper)
4527 ew32(LEDCTL, hw->ledctl_mode1);
4528 break;
4529 }
4530
4531 return E1000_SUCCESS;
4532}
4533
4534
4535
4536
4537
4538s32 e1000_cleanup_led(struct e1000_hw *hw)
4539{
4540 s32 ret_val = E1000_SUCCESS;
4541
4542 switch (hw->mac_type) {
4543 case e1000_82542_rev2_0:
4544 case e1000_82542_rev2_1:
4545 case e1000_82543:
4546 case e1000_82544:
4547
4548 break;
4549 case e1000_82541:
4550 case e1000_82547:
4551 case e1000_82541_rev_2:
4552 case e1000_82547_rev_2:
4553
4554 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4555 hw->phy_spd_default);
4556 if (ret_val)
4557 return ret_val;
4558 fallthrough;
4559 default:
4560
4561 ew32(LEDCTL, hw->ledctl_default);
4562 break;
4563 }
4564
4565 return E1000_SUCCESS;
4566}
4567
4568
4569
4570
4571
4572s32 e1000_led_on(struct e1000_hw *hw)
4573{
4574 u32 ctrl = er32(CTRL);
4575
4576 switch (hw->mac_type) {
4577 case e1000_82542_rev2_0:
4578 case e1000_82542_rev2_1:
4579 case e1000_82543:
4580
4581 ctrl |= E1000_CTRL_SWDPIN0;
4582 ctrl |= E1000_CTRL_SWDPIO0;
4583 break;
4584 case e1000_82544:
4585 if (hw->media_type == e1000_media_type_fiber) {
4586
4587 ctrl |= E1000_CTRL_SWDPIN0;
4588 ctrl |= E1000_CTRL_SWDPIO0;
4589 } else {
4590
4591 ctrl &= ~E1000_CTRL_SWDPIN0;
4592 ctrl |= E1000_CTRL_SWDPIO0;
4593 }
4594 break;
4595 default:
4596 if (hw->media_type == e1000_media_type_fiber) {
4597
4598 ctrl &= ~E1000_CTRL_SWDPIN0;
4599 ctrl |= E1000_CTRL_SWDPIO0;
4600 } else if (hw->media_type == e1000_media_type_copper) {
4601 ew32(LEDCTL, hw->ledctl_mode2);
4602 return E1000_SUCCESS;
4603 }
4604 break;
4605 }
4606
4607 ew32(CTRL, ctrl);
4608
4609 return E1000_SUCCESS;
4610}
4611
4612
4613
4614
4615
4616s32 e1000_led_off(struct e1000_hw *hw)
4617{
4618 u32 ctrl = er32(CTRL);
4619
4620 switch (hw->mac_type) {
4621 case e1000_82542_rev2_0:
4622 case e1000_82542_rev2_1:
4623 case e1000_82543:
4624
4625 ctrl &= ~E1000_CTRL_SWDPIN0;
4626 ctrl |= E1000_CTRL_SWDPIO0;
4627 break;
4628 case e1000_82544:
4629 if (hw->media_type == e1000_media_type_fiber) {
4630
4631 ctrl &= ~E1000_CTRL_SWDPIN0;
4632 ctrl |= E1000_CTRL_SWDPIO0;
4633 } else {
4634
4635 ctrl |= E1000_CTRL_SWDPIN0;
4636 ctrl |= E1000_CTRL_SWDPIO0;
4637 }
4638 break;
4639 default:
4640 if (hw->media_type == e1000_media_type_fiber) {
4641
4642 ctrl |= E1000_CTRL_SWDPIN0;
4643 ctrl |= E1000_CTRL_SWDPIO0;
4644 } else if (hw->media_type == e1000_media_type_copper) {
4645 ew32(LEDCTL, hw->ledctl_mode1);
4646 return E1000_SUCCESS;
4647 }
4648 break;
4649 }
4650
4651 ew32(CTRL, ctrl);
4652
4653 return E1000_SUCCESS;
4654}
4655
4656
4657
4658
4659
4660static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
4661{
4662 er32(CRCERRS);
4663 er32(SYMERRS);
4664 er32(MPC);
4665 er32(SCC);
4666 er32(ECOL);
4667 er32(MCC);
4668 er32(LATECOL);
4669 er32(COLC);
4670 er32(DC);
4671 er32(SEC);
4672 er32(RLEC);
4673 er32(XONRXC);
4674 er32(XONTXC);
4675 er32(XOFFRXC);
4676 er32(XOFFTXC);
4677 er32(FCRUC);
4678
4679 er32(PRC64);
4680 er32(PRC127);
4681 er32(PRC255);
4682 er32(PRC511);
4683 er32(PRC1023);
4684 er32(PRC1522);
4685
4686 er32(GPRC);
4687 er32(BPRC);
4688 er32(MPRC);
4689 er32(GPTC);
4690 er32(GORCL);
4691 er32(GORCH);
4692 er32(GOTCL);
4693 er32(GOTCH);
4694 er32(RNBC);
4695 er32(RUC);
4696 er32(RFC);
4697 er32(ROC);
4698 er32(RJC);
4699 er32(TORL);
4700 er32(TORH);
4701 er32(TOTL);
4702 er32(TOTH);
4703 er32(TPR);
4704 er32(TPT);
4705
4706 er32(PTC64);
4707 er32(PTC127);
4708 er32(PTC255);
4709 er32(PTC511);
4710 er32(PTC1023);
4711 er32(PTC1522);
4712
4713 er32(MPTC);
4714 er32(BPTC);
4715
4716 if (hw->mac_type < e1000_82543)
4717 return;
4718
4719 er32(ALGNERRC);
4720 er32(RXERRC);
4721 er32(TNCRS);
4722 er32(CEXTERR);
4723 er32(TSCTC);
4724 er32(TSCTFC);
4725
4726 if (hw->mac_type <= e1000_82544)
4727 return;
4728
4729 er32(MGTPRC);
4730 er32(MGTPDC);
4731 er32(MGTPTC);
4732}
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743void e1000_reset_adaptive(struct e1000_hw *hw)
4744{
4745 if (hw->adaptive_ifs) {
4746 if (!hw->ifs_params_forced) {
4747 hw->current_ifs_val = 0;
4748 hw->ifs_min_val = IFS_MIN;
4749 hw->ifs_max_val = IFS_MAX;
4750 hw->ifs_step_size = IFS_STEP;
4751 hw->ifs_ratio = IFS_RATIO;
4752 }
4753 hw->in_ifs_mode = false;
4754 ew32(AIT, 0);
4755 } else {
4756 e_dbg("Not in Adaptive IFS mode!\n");
4757 }
4758}
4759
4760
4761
4762
4763
4764
4765
4766
4767void e1000_update_adaptive(struct e1000_hw *hw)
4768{
4769 if (hw->adaptive_ifs) {
4770 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
4771 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4772 hw->in_ifs_mode = true;
4773 if (hw->current_ifs_val < hw->ifs_max_val) {
4774 if (hw->current_ifs_val == 0)
4775 hw->current_ifs_val =
4776 hw->ifs_min_val;
4777 else
4778 hw->current_ifs_val +=
4779 hw->ifs_step_size;
4780 ew32(AIT, hw->current_ifs_val);
4781 }
4782 }
4783 } else {
4784 if (hw->in_ifs_mode &&
4785 (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4786 hw->current_ifs_val = 0;
4787 hw->in_ifs_mode = false;
4788 ew32(AIT, 0);
4789 }
4790 }
4791 } else {
4792 e_dbg("Not in Adaptive IFS mode!\n");
4793 }
4794}
4795
4796
4797
4798
4799
4800
4801
4802void e1000_get_bus_info(struct e1000_hw *hw)
4803{
4804 u32 status;
4805
4806 switch (hw->mac_type) {
4807 case e1000_82542_rev2_0:
4808 case e1000_82542_rev2_1:
4809 hw->bus_type = e1000_bus_type_pci;
4810 hw->bus_speed = e1000_bus_speed_unknown;
4811 hw->bus_width = e1000_bus_width_unknown;
4812 break;
4813 default:
4814 status = er32(STATUS);
4815 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4816 e1000_bus_type_pcix : e1000_bus_type_pci;
4817
4818 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4819 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4820 e1000_bus_speed_66 : e1000_bus_speed_120;
4821 } else if (hw->bus_type == e1000_bus_type_pci) {
4822 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4823 e1000_bus_speed_66 : e1000_bus_speed_33;
4824 } else {
4825 switch (status & E1000_STATUS_PCIX_SPEED) {
4826 case E1000_STATUS_PCIX_SPEED_66:
4827 hw->bus_speed = e1000_bus_speed_66;
4828 break;
4829 case E1000_STATUS_PCIX_SPEED_100:
4830 hw->bus_speed = e1000_bus_speed_100;
4831 break;
4832 case E1000_STATUS_PCIX_SPEED_133:
4833 hw->bus_speed = e1000_bus_speed_133;
4834 break;
4835 default:
4836 hw->bus_speed = e1000_bus_speed_reserved;
4837 break;
4838 }
4839 }
4840 hw->bus_width = (status & E1000_STATUS_BUS64) ?
4841 e1000_bus_width_64 : e1000_bus_width_32;
4842 break;
4843 }
4844}
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
4856{
4857 unsigned long io_addr = hw->io_base;
4858 unsigned long io_data = hw->io_base + 4;
4859
4860 e1000_io_write(hw, io_addr, offset);
4861 e1000_io_write(hw, io_data, value);
4862}
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
4879 u16 *max_length)
4880{
4881 s32 ret_val;
4882 u16 agc_value = 0;
4883 u16 i, phy_data;
4884 u16 cable_length;
4885
4886 *min_length = *max_length = 0;
4887
4888
4889 if (hw->phy_type == e1000_phy_m88) {
4890 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
4891 &phy_data);
4892 if (ret_val)
4893 return ret_val;
4894 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4895 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
4896
4897
4898 switch (cable_length) {
4899 case e1000_cable_length_50:
4900 *min_length = 0;
4901 *max_length = e1000_igp_cable_length_50;
4902 break;
4903 case e1000_cable_length_50_80:
4904 *min_length = e1000_igp_cable_length_50;
4905 *max_length = e1000_igp_cable_length_80;
4906 break;
4907 case e1000_cable_length_80_110:
4908 *min_length = e1000_igp_cable_length_80;
4909 *max_length = e1000_igp_cable_length_110;
4910 break;
4911 case e1000_cable_length_110_140:
4912 *min_length = e1000_igp_cable_length_110;
4913 *max_length = e1000_igp_cable_length_140;
4914 break;
4915 case e1000_cable_length_140:
4916 *min_length = e1000_igp_cable_length_140;
4917 *max_length = e1000_igp_cable_length_170;
4918 break;
4919 default:
4920 return -E1000_ERR_PHY;
4921 }
4922 } else if (hw->phy_type == e1000_phy_igp) {
4923 u16 cur_agc_value;
4924 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
4925 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
4926 IGP01E1000_PHY_AGC_A,
4927 IGP01E1000_PHY_AGC_B,
4928 IGP01E1000_PHY_AGC_C,
4929 IGP01E1000_PHY_AGC_D
4930 };
4931
4932 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
4933 ret_val =
4934 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
4935 if (ret_val)
4936 return ret_val;
4937
4938 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
4939
4940
4941 if ((cur_agc_value >=
4942 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
4943 (cur_agc_value == 0))
4944 return -E1000_ERR_PHY;
4945
4946 agc_value += cur_agc_value;
4947
4948
4949 if (min_agc_value > cur_agc_value)
4950 min_agc_value = cur_agc_value;
4951 }
4952
4953
4954 if (agc_value <
4955 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
4956 agc_value -= min_agc_value;
4957
4958
4959 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
4960 } else {
4961
4962 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
4963 }
4964
4965
4966 *min_length = ((e1000_igp_cable_length_table[agc_value] -
4967 IGP01E1000_AGC_RANGE) > 0) ?
4968 (e1000_igp_cable_length_table[agc_value] -
4969 IGP01E1000_AGC_RANGE) : 0;
4970 *max_length = e1000_igp_cable_length_table[agc_value] +
4971 IGP01E1000_AGC_RANGE;
4972 }
4973
4974 return E1000_SUCCESS;
4975}
4976
4977
4978
4979
4980
4981
4982
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992static s32 e1000_check_polarity(struct e1000_hw *hw,
4993 e1000_rev_polarity *polarity)
4994{
4995 s32 ret_val;
4996 u16 phy_data;
4997
4998 if (hw->phy_type == e1000_phy_m88) {
4999
5000 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5001 &phy_data);
5002 if (ret_val)
5003 return ret_val;
5004 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5005 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5006 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5007
5008 } else if (hw->phy_type == e1000_phy_igp) {
5009
5010 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5011 &phy_data);
5012 if (ret_val)
5013 return ret_val;
5014
5015
5016
5017
5018 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5019 IGP01E1000_PSSR_SPEED_1000MBPS) {
5020
5021 ret_val =
5022 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5023 &phy_data);
5024 if (ret_val)
5025 return ret_val;
5026
5027
5028 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5029 e1000_rev_polarity_reversed :
5030 e1000_rev_polarity_normal;
5031 } else {
5032
5033
5034
5035 *polarity =
5036 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5037 e1000_rev_polarity_reversed :
5038 e1000_rev_polarity_normal;
5039 }
5040 }
5041 return E1000_SUCCESS;
5042}
5043
5044
5045
5046
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056static s32 e1000_check_downshift(struct e1000_hw *hw)
5057{
5058 s32 ret_val;
5059 u16 phy_data;
5060
5061 if (hw->phy_type == e1000_phy_igp) {
5062 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5063 &phy_data);
5064 if (ret_val)
5065 return ret_val;
5066
5067 hw->speed_downgraded =
5068 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5069 } else if (hw->phy_type == e1000_phy_m88) {
5070 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5071 &phy_data);
5072 if (ret_val)
5073 return ret_val;
5074
5075 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5076 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5077 }
5078
5079 return E1000_SUCCESS;
5080}
5081
5082static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5083 IGP01E1000_PHY_AGC_PARAM_A,
5084 IGP01E1000_PHY_AGC_PARAM_B,
5085 IGP01E1000_PHY_AGC_PARAM_C,
5086 IGP01E1000_PHY_AGC_PARAM_D
5087};
5088
5089static s32 e1000_1000Mb_check_cable_length(struct e1000_hw *hw)
5090{
5091 u16 min_length, max_length;
5092 u16 phy_data, i;
5093 s32 ret_val;
5094
5095 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
5096 if (ret_val)
5097 return ret_val;
5098
5099 if (hw->dsp_config_state != e1000_dsp_config_enabled)
5100 return 0;
5101
5102 if (min_length >= e1000_igp_cable_length_50) {
5103 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5104 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
5105 &phy_data);
5106 if (ret_val)
5107 return ret_val;
5108
5109 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5110
5111 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
5112 phy_data);
5113 if (ret_val)
5114 return ret_val;
5115 }
5116 hw->dsp_config_state = e1000_dsp_config_activated;
5117 } else {
5118 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5119 u32 idle_errs = 0;
5120
5121
5122 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
5123 if (ret_val)
5124 return ret_val;
5125
5126 for (i = 0; i < ffe_idle_err_timeout; i++) {
5127 udelay(1000);
5128 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5129 &phy_data);
5130 if (ret_val)
5131 return ret_val;
5132
5133 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
5134 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
5135 hw->ffe_config_state = e1000_ffe_config_active;
5136
5137 ret_val = e1000_write_phy_reg(hw,
5138 IGP01E1000_PHY_DSP_FFE,
5139 IGP01E1000_PHY_DSP_FFE_CM_CP);
5140 if (ret_val)
5141 return ret_val;
5142 break;
5143 }
5144
5145 if (idle_errs)
5146 ffe_idle_err_timeout =
5147 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5148 }
5149 }
5150
5151 return 0;
5152}
5153
5154
5155
5156
5157
5158
5159
5160
5161
5162
5163
5164
5165
5166static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
5167{
5168 s32 ret_val;
5169 u16 phy_data, phy_saved_data, speed, duplex, i;
5170
5171 if (hw->phy_type != e1000_phy_igp)
5172 return E1000_SUCCESS;
5173
5174 if (link_up) {
5175 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5176 if (ret_val) {
5177 e_dbg("Error getting link speed and duplex\n");
5178 return ret_val;
5179 }
5180
5181 if (speed == SPEED_1000) {
5182 ret_val = e1000_1000Mb_check_cable_length(hw);
5183 if (ret_val)
5184 return ret_val;
5185 }
5186 } else {
5187 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5188
5189
5190
5191 ret_val =
5192 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5193
5194 if (ret_val)
5195 return ret_val;
5196
5197
5198 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5199
5200 if (ret_val)
5201 return ret_val;
5202
5203 msleep(20);
5204
5205 ret_val = e1000_write_phy_reg(hw, 0x0000,
5206 IGP01E1000_IEEE_FORCE_GIGA);
5207 if (ret_val)
5208 return ret_val;
5209 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5210 ret_val =
5211 e1000_read_phy_reg(hw, dsp_reg_array[i],
5212 &phy_data);
5213 if (ret_val)
5214 return ret_val;
5215
5216 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5217 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5218
5219 ret_val =
5220 e1000_write_phy_reg(hw, dsp_reg_array[i],
5221 phy_data);
5222 if (ret_val)
5223 return ret_val;
5224 }
5225
5226 ret_val = e1000_write_phy_reg(hw, 0x0000,
5227 IGP01E1000_IEEE_RESTART_AUTONEG);
5228 if (ret_val)
5229 return ret_val;
5230
5231 msleep(20);
5232
5233
5234 ret_val =
5235 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5236
5237 if (ret_val)
5238 return ret_val;
5239
5240 hw->dsp_config_state = e1000_dsp_config_enabled;
5241 }
5242
5243 if (hw->ffe_config_state == e1000_ffe_config_active) {
5244
5245
5246
5247 ret_val =
5248 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5249
5250 if (ret_val)
5251 return ret_val;
5252
5253
5254 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5255
5256 if (ret_val)
5257 return ret_val;
5258
5259 msleep(20);
5260
5261 ret_val = e1000_write_phy_reg(hw, 0x0000,
5262 IGP01E1000_IEEE_FORCE_GIGA);
5263 if (ret_val)
5264 return ret_val;
5265 ret_val =
5266 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5267 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5268 if (ret_val)
5269 return ret_val;
5270
5271 ret_val = e1000_write_phy_reg(hw, 0x0000,
5272 IGP01E1000_IEEE_RESTART_AUTONEG);
5273 if (ret_val)
5274 return ret_val;
5275
5276 msleep(20);
5277
5278
5279 ret_val =
5280 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5281
5282 if (ret_val)
5283 return ret_val;
5284
5285 hw->ffe_config_state = e1000_ffe_config_enabled;
5286 }
5287 }
5288 return E1000_SUCCESS;
5289}
5290
5291
5292
5293
5294
5295
5296
5297
5298
5299static s32 e1000_set_phy_mode(struct e1000_hw *hw)
5300{
5301 s32 ret_val;
5302 u16 eeprom_data;
5303
5304 if ((hw->mac_type == e1000_82545_rev_3) &&
5305 (hw->media_type == e1000_media_type_copper)) {
5306 ret_val =
5307 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5308 &eeprom_data);
5309 if (ret_val)
5310 return ret_val;
5311
5312 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5313 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5314 ret_val =
5315 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5316 0x000B);
5317 if (ret_val)
5318 return ret_val;
5319 ret_val =
5320 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5321 0x8104);
5322 if (ret_val)
5323 return ret_val;
5324
5325 hw->phy_reset_disable = false;
5326 }
5327 }
5328
5329 return E1000_SUCCESS;
5330}
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340
5341
5342
5343
5344
5345static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
5346{
5347 s32 ret_val;
5348 u16 phy_data;
5349
5350 if (hw->phy_type != e1000_phy_igp)
5351 return E1000_SUCCESS;
5352
5353
5354
5355
5356
5357 if (hw->mac_type == e1000_82541_rev_2 ||
5358 hw->mac_type == e1000_82547_rev_2) {
5359 ret_val =
5360 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5361 if (ret_val)
5362 return ret_val;
5363 }
5364
5365 if (!active) {
5366 if (hw->mac_type == e1000_82541_rev_2 ||
5367 hw->mac_type == e1000_82547_rev_2) {
5368 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5369 ret_val =
5370 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5371 phy_data);
5372 if (ret_val)
5373 return ret_val;
5374 }
5375
5376
5377
5378
5379
5380
5381 if (hw->smart_speed == e1000_smart_speed_on) {
5382 ret_val =
5383 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5384 &phy_data);
5385 if (ret_val)
5386 return ret_val;
5387
5388 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5389 ret_val =
5390 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5391 phy_data);
5392 if (ret_val)
5393 return ret_val;
5394 } else if (hw->smart_speed == e1000_smart_speed_off) {
5395 ret_val =
5396 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5397 &phy_data);
5398 if (ret_val)
5399 return ret_val;
5400
5401 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5402 ret_val =
5403 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5404 phy_data);
5405 if (ret_val)
5406 return ret_val;
5407 }
5408 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
5409 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
5410 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
5411 if (hw->mac_type == e1000_82541_rev_2 ||
5412 hw->mac_type == e1000_82547_rev_2) {
5413 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5414 ret_val =
5415 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5416 phy_data);
5417 if (ret_val)
5418 return ret_val;
5419 }
5420
5421
5422 ret_val =
5423 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5424 &phy_data);
5425 if (ret_val)
5426 return ret_val;
5427
5428 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5429 ret_val =
5430 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5431 phy_data);
5432 if (ret_val)
5433 return ret_val;
5434 }
5435 return E1000_SUCCESS;
5436}
5437
5438
5439
5440
5441
5442
5443
5444static s32 e1000_set_vco_speed(struct e1000_hw *hw)
5445{
5446 s32 ret_val;
5447 u16 default_page = 0;
5448 u16 phy_data;
5449
5450 switch (hw->mac_type) {
5451 case e1000_82545_rev_3:
5452 case e1000_82546_rev_3:
5453 break;
5454 default:
5455 return E1000_SUCCESS;
5456 }
5457
5458
5459
5460 ret_val =
5461 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5462 if (ret_val)
5463 return ret_val;
5464
5465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5466 if (ret_val)
5467 return ret_val;
5468
5469 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5470 if (ret_val)
5471 return ret_val;
5472
5473 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5474 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5475 if (ret_val)
5476 return ret_val;
5477
5478
5479
5480 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5481 if (ret_val)
5482 return ret_val;
5483
5484 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5485 if (ret_val)
5486 return ret_val;
5487
5488 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5489 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5490 if (ret_val)
5491 return ret_val;
5492
5493 ret_val =
5494 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5495 if (ret_val)
5496 return ret_val;
5497
5498 return E1000_SUCCESS;
5499}
5500
5501
5502
5503
5504
5505
5506
5507
5508u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
5509{
5510 u32 manc;
5511
5512 if (hw->asf_firmware_present) {
5513 manc = er32(MANC);
5514
5515 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5516 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5517 return false;
5518 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5519 return true;
5520 }
5521 return false;
5522}
5523
5524static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
5525{
5526 s32 ret_val;
5527 u16 mii_status_reg;
5528 u16 i;
5529
5530
5531
5532
5533
5534 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5535 if (ret_val)
5536 return ret_val;
5537 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5538 if (ret_val)
5539 return ret_val;
5540
5541 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5542 if (ret_val)
5543 return ret_val;
5544
5545
5546 for (i = PHY_FORCE_TIME; i > 0; i--) {
5547
5548
5549
5550
5551 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5552 if (ret_val)
5553 return ret_val;
5554
5555 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5556 if (ret_val)
5557 return ret_val;
5558
5559 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5560 break;
5561 msleep(100);
5562 }
5563
5564
5565 msleep(1000);
5566
5567
5568
5569 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5570 if (ret_val)
5571 return ret_val;
5572 msleep(50);
5573 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5574 if (ret_val)
5575 return ret_val;
5576 msleep(50);
5577 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5578 if (ret_val)
5579 return ret_val;
5580 msleep(50);
5581 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5582 if (ret_val)
5583 return ret_val;
5584
5585 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5586 if (ret_val)
5587 return ret_val;
5588
5589
5590 for (i = PHY_FORCE_TIME; i > 0; i--) {
5591
5592
5593
5594
5595 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5596 if (ret_val)
5597 return ret_val;
5598
5599 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5600 if (ret_val)
5601 return ret_val;
5602
5603 if (mii_status_reg & MII_SR_LINK_STATUS)
5604 break;
5605 msleep(100);
5606 }
5607 return E1000_SUCCESS;
5608}
5609
5610
5611
5612
5613
5614
5615
5616
5617
5618static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
5619{
5620 msleep(5);
5621 return E1000_SUCCESS;
5622}
5623
5624
5625
5626
5627
5628
5629
5630
5631
5632static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5633{
5634 msleep(10);
5635 return E1000_SUCCESS;
5636}
5637