1
2
3
4#ifndef _I40E_H_
5#define _I40E_H_
6
7#include <net/tcp.h>
8#include <net/udp.h>
9#include <linux/types.h>
10#include <linux/errno.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/aer.h>
14#include <linux/netdevice.h>
15#include <linux/ioport.h>
16#include <linux/iommu.h>
17#include <linux/slab.h>
18#include <linux/list.h>
19#include <linux/hashtable.h>
20#include <linux/string.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/sctp.h>
24#include <linux/pkt_sched.h>
25#include <linux/ipv6.h>
26#include <net/checksum.h>
27#include <net/ip6_checksum.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
30#include <linux/if_macvlan.h>
31#include <linux/if_bridge.h>
32#include <linux/clocksource.h>
33#include <linux/net_tstamp.h>
34#include <linux/ptp_clock_kernel.h>
35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
37#include <net/tc_act/tc_mirred.h>
38#include <net/udp_tunnel.h>
39#include <net/xdp_sock.h>
40#include "i40e_type.h"
41#include "i40e_prototype.h"
42#include <linux/net/intel/i40e_client.h>
43#include <linux/avf/virtchnl.h>
44#include "i40e_virtchnl_pf.h"
45#include "i40e_txrx.h"
46#include "i40e_dcb.h"
47
48
49#define I40E_MAX_VEB 16
50
51#define I40E_MAX_NUM_DESCRIPTORS 4096
52#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
53#define I40E_DEFAULT_NUM_DESCRIPTORS 512
54#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
55#define I40E_MIN_NUM_DESCRIPTORS 64
56#define I40E_MIN_MSIX 2
57#define I40E_DEFAULT_NUM_VMDQ_VSI 8
58#define I40E_MIN_VSI_ALLOC 83
59
60#define i40e_default_queues_per_vmdq(pf) \
61 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
62#define I40E_DEFAULT_QUEUES_PER_VF 4
63#define I40E_MAX_VF_QUEUES 16
64#define i40e_pf_get_max_q_per_tc(pf) \
65 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
66#define I40E_FDIR_RING_COUNT 32
67#define I40E_MAX_AQ_BUF_SIZE 4096
68#define I40E_AQ_LEN 256
69#define I40E_MIN_ARQ_LEN 1
70#define I40E_MIN_ASQ_LEN 2
71#define I40E_AQ_WORK_LIMIT 66
72#define I40E_MAX_USER_PRIORITY 8
73#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
74#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
75#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
76
77#define I40E_NVM_VERSION_LO_SHIFT 0
78#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
79#define I40E_NVM_VERSION_HI_SHIFT 12
80#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
81#define I40E_OEM_VER_BUILD_MASK 0xffff
82#define I40E_OEM_VER_PATCH_MASK 0xff
83#define I40E_OEM_VER_BUILD_SHIFT 8
84#define I40E_OEM_VER_SHIFT 24
85#define I40E_PHY_DEBUG_ALL \
86 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
87 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
88
89#define I40E_OEM_EETRACK_ID 0xffffffff
90#define I40E_OEM_GEN_SHIFT 24
91#define I40E_OEM_SNAP_MASK 0x00ff0000
92#define I40E_OEM_SNAP_SHIFT 16
93#define I40E_OEM_RELEASE_MASK 0x0000ffff
94
95#define I40E_RX_DESC(R, i) \
96 (&(((union i40e_rx_desc *)((R)->desc))[i]))
97#define I40E_TX_DESC(R, i) \
98 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
99#define I40E_TX_CTXTDESC(R, i) \
100 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
101#define I40E_TX_FDIRDESC(R, i) \
102 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
103
104
105#define I40E_BW_CREDIT_DIVISOR 50
106#define I40E_BW_MBPS_DIVISOR 125000
107#define I40E_MAX_BW_INACTIVE_ACCUM 4
108
109
110enum i40e_state_t {
111 __I40E_TESTING,
112 __I40E_CONFIG_BUSY,
113 __I40E_CONFIG_DONE,
114 __I40E_DOWN,
115 __I40E_SERVICE_SCHED,
116 __I40E_ADMINQ_EVENT_PENDING,
117 __I40E_MDD_EVENT_PENDING,
118 __I40E_VFLR_EVENT_PENDING,
119 __I40E_RESET_RECOVERY_PENDING,
120 __I40E_TIMEOUT_RECOVERY_PENDING,
121 __I40E_MISC_IRQ_REQUESTED,
122 __I40E_RESET_INTR_RECEIVED,
123 __I40E_REINIT_REQUESTED,
124 __I40E_PF_RESET_REQUESTED,
125 __I40E_PF_RESET_AND_REBUILD_REQUESTED,
126 __I40E_CORE_RESET_REQUESTED,
127 __I40E_GLOBAL_RESET_REQUESTED,
128 __I40E_EMP_RESET_INTR_RECEIVED,
129 __I40E_SUSPENDED,
130 __I40E_PTP_TX_IN_PROGRESS,
131 __I40E_BAD_EEPROM,
132 __I40E_DOWN_REQUESTED,
133 __I40E_FD_FLUSH_REQUESTED,
134 __I40E_FD_ATR_AUTO_DISABLED,
135 __I40E_FD_SB_AUTO_DISABLED,
136 __I40E_RESET_FAILED,
137 __I40E_PORT_SUSPENDED,
138 __I40E_VF_DISABLE,
139 __I40E_MACVLAN_SYNC_PENDING,
140 __I40E_TEMP_LINK_POLLING,
141 __I40E_CLIENT_SERVICE_REQUESTED,
142 __I40E_CLIENT_L2_CHANGE,
143 __I40E_CLIENT_RESET,
144 __I40E_VIRTCHNL_OP_PENDING,
145 __I40E_RECOVERY_MODE,
146 __I40E_VF_RESETS_DISABLED,
147 __I40E_VFS_RELEASING,
148
149 __I40E_STATE_SIZE__,
150};
151
152#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
153#define I40E_PF_RESET_AND_REBUILD_FLAG \
154 BIT_ULL(__I40E_PF_RESET_AND_REBUILD_REQUESTED)
155
156
157enum i40e_vsi_state_t {
158 __I40E_VSI_DOWN,
159 __I40E_VSI_NEEDS_RESTART,
160 __I40E_VSI_SYNCING_FILTERS,
161 __I40E_VSI_OVERFLOW_PROMISC,
162 __I40E_VSI_REINIT_REQUESTED,
163 __I40E_VSI_DOWN_REQUESTED,
164
165 __I40E_VSI_STATE_SIZE__,
166};
167
168enum i40e_interrupt_policy {
169 I40E_INTERRUPT_BEST_CASE,
170 I40E_INTERRUPT_MEDIUM,
171 I40E_INTERRUPT_LOWEST
172};
173
174struct i40e_lump_tracking {
175 u16 num_entries;
176 u16 search_hint;
177 u16 list[0];
178#define I40E_PILE_VALID_BIT 0x8000
179#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
180};
181
182#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
183#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
184#define I40E_FDIR_BUFFER_FULL_MARGIN 10
185#define I40E_FDIR_BUFFER_HEAD_ROOM 32
186#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
187
188#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
189#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
190#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
191
192enum i40e_fd_stat_idx {
193 I40E_FD_STAT_ATR,
194 I40E_FD_STAT_SB,
195 I40E_FD_STAT_ATR_TUNNEL,
196 I40E_FD_STAT_PF_COUNT
197};
198#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
199#define I40E_FD_ATR_STAT_IDX(pf_id) \
200 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
201#define I40E_FD_SB_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
203#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
205
206
207
208
209struct i40e_rx_flow_userdef {
210 bool flex_filter;
211 u16 flex_word;
212 u16 flex_offset;
213};
214
215struct i40e_fdir_filter {
216 struct hlist_node fdir_node;
217
218 u8 flow_type;
219 u8 ipl4_proto;
220
221 __be32 dst_ip;
222 __be32 src_ip;
223 __be32 dst_ip6[4];
224 __be32 src_ip6[4];
225 __be16 src_port;
226 __be16 dst_port;
227 __be32 sctp_v_tag;
228
229 __be16 vlan_etype;
230 __be16 vlan_tag;
231
232 __be16 flex_word;
233 u16 flex_offset;
234 bool flex_filter;
235
236
237 u16 q_index;
238 u8 flex_off;
239 u8 pctype;
240 u16 dest_vsi;
241 u8 dest_ctl;
242 u8 fd_status;
243 u16 cnt_index;
244 u32 fd_id;
245};
246
247#define I40E_CLOUD_FIELD_OMAC BIT(0)
248#define I40E_CLOUD_FIELD_IMAC BIT(1)
249#define I40E_CLOUD_FIELD_IVLAN BIT(2)
250#define I40E_CLOUD_FIELD_TEN_ID BIT(3)
251#define I40E_CLOUD_FIELD_IIP BIT(4)
252
253#define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
254#define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
255#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
256 I40E_CLOUD_FIELD_IVLAN)
257#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
258 I40E_CLOUD_FIELD_TEN_ID)
259#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
260 I40E_CLOUD_FIELD_IMAC | \
261 I40E_CLOUD_FIELD_TEN_ID)
262#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
263 I40E_CLOUD_FIELD_IVLAN | \
264 I40E_CLOUD_FIELD_TEN_ID)
265#define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
266
267struct i40e_cloud_filter {
268 struct hlist_node cloud_node;
269 unsigned long cookie;
270
271 u8 dst_mac[ETH_ALEN];
272 u8 src_mac[ETH_ALEN];
273 __be16 vlan_id;
274 u16 seid;
275 __be16 dst_port;
276 __be16 src_port;
277 u32 tenant_id;
278 union {
279 struct {
280 struct in_addr dst_ip;
281 struct in_addr src_ip;
282 } v4;
283 struct {
284 struct in6_addr dst_ip6;
285 struct in6_addr src_ip6;
286 } v6;
287 } ip;
288#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
289#define src_ipv6 ip.v6.src_ip6.s6_addr32
290#define dst_ipv4 ip.v4.dst_ip.s_addr
291#define src_ipv4 ip.v4.src_ip.s_addr
292 u16 n_proto;
293 u8 ip_proto;
294 u8 flags;
295#define I40E_CLOUD_TNL_TYPE_NONE 0xff
296 u8 tunnel_type;
297};
298
299#define I40E_DCB_PRIO_TYPE_STRICT 0
300#define I40E_DCB_PRIO_TYPE_ETS 1
301#define I40E_DCB_STRICT_PRIO_CREDITS 127
302
303struct i40e_tc_info {
304 u16 qoffset;
305 u16 qcount;
306 u8 netdev_tc;
307};
308
309
310struct i40e_tc_configuration {
311 u8 numtc;
312 u8 enabled_tc;
313 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
314};
315
316#define I40E_UDP_PORT_INDEX_UNUSED 255
317struct i40e_udp_port_config {
318
319 u16 port;
320 u8 type;
321 u8 filter_index;
322};
323
324#define I40_DDP_FLASH_REGION 100
325#define I40E_PROFILE_INFO_SIZE 48
326#define I40E_MAX_PROFILE_NUM 16
327#define I40E_PROFILE_LIST_SIZE \
328 (I40E_PROFILE_INFO_SIZE * I40E_MAX_PROFILE_NUM + 4)
329#define I40E_DDP_PROFILE_PATH "intel/i40e/ddp/"
330#define I40E_DDP_PROFILE_NAME_MAX 64
331
332int i40e_ddp_load(struct net_device *netdev, const u8 *data, size_t size,
333 bool is_add);
334int i40e_ddp_flash(struct net_device *netdev, struct ethtool_flash *flash);
335
336struct i40e_ddp_profile_list {
337 u32 p_count;
338 struct i40e_profile_info p_info[];
339};
340
341struct i40e_ddp_old_profile_list {
342 struct list_head list;
343 size_t old_ddp_size;
344 u8 old_ddp_buf[];
345};
346
347
348#define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
349 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
350 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
351#define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
352 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
353 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
354#define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
355 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
356 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
357#define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
358 I40E_FLEX_SET_FSIZE(fsize) | \
359 I40E_FLEX_SET_SRC_WORD(src))
360
361
362#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
363
364
365#define I40E_ORT_SET_IDX(idx) (((idx) << \
366 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
367 I40E_GLQF_ORT_PIT_INDX_MASK)
368
369#define I40E_ORT_SET_COUNT(count) (((count) << \
370 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
371 I40E_GLQF_ORT_FIELD_CNT_MASK)
372
373#define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
374 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
375 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
376
377#define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
378 I40E_ORT_SET_COUNT(count) | \
379 I40E_ORT_SET_PAYLOAD(payload))
380
381#define I40E_L3_GLQF_ORT_IDX 34
382#define I40E_L4_GLQF_ORT_IDX 35
383
384
385#define I40E_FLEX_PIT_IDX_START_L3 3
386#define I40E_FLEX_PIT_IDX_START_L4 6
387
388#define I40E_FLEX_PIT_TABLE_SIZE 3
389
390#define I40E_FLEX_DEST_UNUSED 63
391
392#define I40E_FLEX_INDEX_ENTRIES 8
393
394
395#define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
396 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
397 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
398 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
399
400struct i40e_flex_pit {
401 struct list_head list;
402 u16 src_offset;
403 u8 pit_index;
404};
405
406struct i40e_fwd_adapter {
407 struct net_device *netdev;
408 int bit_no;
409};
410
411struct i40e_channel {
412 struct list_head list;
413 bool initialized;
414 u8 type;
415 u16 vsi_number;
416 u16 stat_counter_idx;
417 u16 base_queue;
418 u16 num_queue_pairs;
419 u16 seid;
420
421 u8 enabled_tc;
422 struct i40e_aqc_vsi_properties_data info;
423
424 u64 max_tx_rate;
425 struct i40e_fwd_adapter *fwd;
426
427
428 struct i40e_vsi *parent_vsi;
429};
430
431struct i40e_ptp_pins_settings;
432
433static inline bool i40e_is_channel_macvlan(struct i40e_channel *ch)
434{
435 return !!ch->fwd;
436}
437
438static inline u8 *i40e_channel_mac(struct i40e_channel *ch)
439{
440 if (i40e_is_channel_macvlan(ch))
441 return ch->fwd->netdev->dev_addr;
442 else
443 return NULL;
444}
445
446
447struct i40e_pf {
448 struct pci_dev *pdev;
449 struct i40e_hw hw;
450 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
451 struct msix_entry *msix_entries;
452 bool fc_autoneg_status;
453
454 u16 eeprom_version;
455 u16 num_vmdq_vsis;
456 u16 num_vmdq_qps;
457 u16 num_vmdq_msix;
458 u16 num_req_vfs;
459 u16 num_vf_qps;
460 u16 num_lan_qps;
461 u16 num_lan_msix;
462 u16 num_fdsb_msix;
463 u16 num_iwarp_msix;
464 int iwarp_base_vector;
465 int queues_left;
466 u16 alloc_rss_size;
467 u16 rss_size_max;
468 u16 fdir_pf_filter_count;
469 u16 num_alloc_vsi;
470 u8 atr_sample_rate;
471 bool wol_en;
472
473 struct hlist_head fdir_filter_list;
474 u16 fdir_pf_active_filters;
475 unsigned long fd_flush_timestamp;
476 u32 fd_flush_cnt;
477 u32 fd_add_err;
478 u32 fd_atr_cnt;
479
480
481
482
483
484 u16 fd_tcp4_filter_cnt;
485 u16 fd_udp4_filter_cnt;
486 u16 fd_sctp4_filter_cnt;
487 u16 fd_ip4_filter_cnt;
488
489 u16 fd_tcp6_filter_cnt;
490 u16 fd_udp6_filter_cnt;
491 u16 fd_sctp6_filter_cnt;
492 u16 fd_ip6_filter_cnt;
493
494
495
496
497
498
499 struct list_head l3_flex_pit_list;
500 struct list_head l4_flex_pit_list;
501
502 struct udp_tunnel_nic_shared udp_tunnel_shared;
503 struct udp_tunnel_nic_info udp_tunnel_nic;
504
505 struct hlist_head cloud_filter_list;
506 u16 num_cloud_filters;
507
508 enum i40e_interrupt_policy int_policy;
509 u16 rx_itr_default;
510 u16 tx_itr_default;
511 u32 msg_enable;
512 char int_name[I40E_INT_NAME_STR_LEN];
513 u16 adminq_work_limit;
514 unsigned long service_timer_period;
515 unsigned long service_timer_previous;
516 struct timer_list service_timer;
517 struct work_struct service_task;
518
519 u32 hw_features;
520#define I40E_HW_RSS_AQ_CAPABLE BIT(0)
521#define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
522#define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
523#define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
524#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
525#define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
526#define I40E_HW_100M_SGMII_CAPABLE BIT(6)
527#define I40E_HW_NO_DCB_SUPPORT BIT(7)
528#define I40E_HW_USE_SET_LLDP_MIB BIT(8)
529#define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
530#define I40E_HW_PTP_L4_CAPABLE BIT(10)
531#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
532#define I40E_HW_HAVE_CRT_RETIMER BIT(13)
533#define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
534#define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
535#define I40E_HW_STOP_FW_LLDP BIT(16)
536#define I40E_HW_PORT_ID_VALID BIT(17)
537#define I40E_HW_RESTART_AUTONEG BIT(18)
538
539 u32 flags;
540#define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
541#define I40E_FLAG_MSI_ENABLED BIT(1)
542#define I40E_FLAG_MSIX_ENABLED BIT(2)
543#define I40E_FLAG_RSS_ENABLED BIT(3)
544#define I40E_FLAG_VMDQ_ENABLED BIT(4)
545#define I40E_FLAG_SRIOV_ENABLED BIT(5)
546#define I40E_FLAG_DCB_CAPABLE BIT(6)
547#define I40E_FLAG_DCB_ENABLED BIT(7)
548#define I40E_FLAG_FD_SB_ENABLED BIT(8)
549#define I40E_FLAG_FD_ATR_ENABLED BIT(9)
550#define I40E_FLAG_MFP_ENABLED BIT(10)
551#define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
552#define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
553#define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
554#define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
555#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
556#define I40E_FLAG_LEGACY_RX BIT(16)
557#define I40E_FLAG_PTP BIT(17)
558#define I40E_FLAG_IWARP_ENABLED BIT(18)
559#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
560#define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
561#define I40E_FLAG_TC_MQPRIO BIT(21)
562#define I40E_FLAG_FD_SB_INACTIVE BIT(22)
563#define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
564#define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
565#define I40E_FLAG_RS_FEC BIT(25)
566#define I40E_FLAG_BASE_R_FEC BIT(26)
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588#define I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED BIT(27)
589
590 struct i40e_client_instance *cinst;
591 bool stat_offsets_loaded;
592 struct i40e_hw_port_stats stats;
593 struct i40e_hw_port_stats stats_offsets;
594 u32 tx_timeout_count;
595 u32 tx_timeout_recovery_level;
596 unsigned long tx_timeout_last_recovery;
597 u32 tx_sluggish_count;
598 u32 hw_csum_rx_error;
599 u32 led_status;
600 u16 corer_count;
601 u16 globr_count;
602 u16 empr_count;
603 u16 pfr_count;
604 u16 sw_int_count;
605
606 struct mutex switch_mutex;
607 u16 lan_vsi;
608 u16 lan_veb;
609#define I40E_NO_VEB 0xffff
610#define I40E_NO_VSI 0xffff
611 u16 next_vsi;
612 struct i40e_vsi **vsi;
613 struct i40e_veb *veb[I40E_MAX_VEB];
614
615 struct i40e_lump_tracking *qp_pile;
616 struct i40e_lump_tracking *irq_pile;
617
618
619 u16 pf_seid;
620 u16 main_vsi_seid;
621 u16 mac_seid;
622 struct kobject *switch_kobj;
623#ifdef CONFIG_DEBUG_FS
624 struct dentry *i40e_dbg_pf;
625#endif
626 bool cur_promisc;
627
628 u16 instance;
629
630
631 struct i40e_vf *vf;
632 int num_alloc_vfs;
633 u32 vf_aq_requests;
634 u32 arq_overflows;
635
636
637
638
639
640
641
642
643 u16 dcbx_cap;
644
645 struct i40e_filter_control_settings filter_settings;
646 struct i40e_rx_pb_config pb_cfg;
647 struct i40e_dcbx_config tmp_cfg;
648
649
650#define I40E_SDP3_2 18
651#define I40E_SDP3_3 19
652#define I40E_GPIO_4 20
653#define I40E_LED2_0 26
654#define I40E_LED2_1 27
655#define I40E_LED3_0 28
656#define I40E_LED3_1 29
657#define I40E_GLGEN_GPIO_SET_SDP_DATA_HI \
658 (1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
659#define I40E_GLGEN_GPIO_SET_DRV_SDP_DATA \
660 (1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
661#define I40E_GLGEN_GPIO_CTL_PRT_NUM_0 \
662 (0 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
663#define I40E_GLGEN_GPIO_CTL_PRT_NUM_1 \
664 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
665#define I40E_GLGEN_GPIO_CTL_RESERVED BIT(2)
666#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z \
667 (1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
668#define I40E_GLGEN_GPIO_CTL_DIR_OUT \
669 (1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
670#define I40E_GLGEN_GPIO_CTL_TRI_DRV_HI \
671 (1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
672#define I40E_GLGEN_GPIO_CTL_OUT_HI_RST \
673 (1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
674#define I40E_GLGEN_GPIO_CTL_TIMESYNC_0 \
675 (3 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
676#define I40E_GLGEN_GPIO_CTL_TIMESYNC_1 \
677 (4 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
678#define I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN \
679 (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
680#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT \
681 (1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
682#define I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0 \
683 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
684 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
685 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
686#define I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0 \
687 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
688 I40E_GLGEN_GPIO_CTL_TIMESYNC_0 | \
689 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
690#define I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1 \
691 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
692 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
693 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
694 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_0)
695#define I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1 \
696 (I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN | \
697 I40E_GLGEN_GPIO_CTL_TIMESYNC_1 | I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
698 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | I40E_GLGEN_GPIO_CTL_DIR_OUT | \
699 I40E_GLGEN_GPIO_CTL_RESERVED | I40E_GLGEN_GPIO_CTL_PRT_NUM_1)
700#define I40E_GLGEN_GPIO_CTL_LED_INIT \
701 (I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_Z | \
702 I40E_GLGEN_GPIO_CTL_DIR_OUT | \
703 I40E_GLGEN_GPIO_CTL_TRI_DRV_HI | \
704 I40E_GLGEN_GPIO_CTL_OUT_HI_RST | \
705 I40E_GLGEN_GPIO_CTL_OUT_DEFAULT | \
706 I40E_GLGEN_GPIO_CTL_NOT_FOR_PHY_CONN)
707#define I40E_PRTTSYN_AUX_1_INSTNT \
708 (1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
709#define I40E_PRTTSYN_AUX_0_OUT_ENABLE \
710 (1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
711#define I40E_PRTTSYN_AUX_0_OUT_CLK_MOD (3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
712#define I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD \
713 (I40E_PRTTSYN_AUX_0_OUT_ENABLE | I40E_PRTTSYN_AUX_0_OUT_CLK_MOD)
714#define I40E_PTP_HALF_SECOND 500000000LL
715#define I40E_PTP_2_SEC_DELAY 2
716
717 struct ptp_clock *ptp_clock;
718 struct ptp_clock_info ptp_caps;
719 struct sk_buff *ptp_tx_skb;
720 unsigned long ptp_tx_start;
721 struct hwtstamp_config tstamp_config;
722 struct timespec64 ptp_prev_hw_time;
723 struct work_struct ptp_pps_work;
724 struct work_struct ptp_extts0_work;
725 struct work_struct ptp_extts1_work;
726 ktime_t ptp_reset_start;
727 struct mutex tmreg_lock;
728 u32 ptp_adj_mult;
729 u32 tx_hwtstamp_timeouts;
730 u32 tx_hwtstamp_skipped;
731 u32 rx_hwtstamp_cleared;
732 u32 latch_event_flags;
733 u64 ptp_pps_start;
734 u32 pps_delay;
735 spinlock_t ptp_rx_lock;
736 struct ptp_pin_desc ptp_pin[3];
737 unsigned long latch_events[4];
738 bool ptp_tx;
739 bool ptp_rx;
740 struct i40e_ptp_pins_settings *ptp_pins;
741 u16 rss_table_size;
742 u32 max_bw;
743 u32 min_bw;
744
745 u32 ioremap_len;
746 u32 fd_inv;
747 u16 phy_led_val;
748
749 u16 override_q_count;
750 u16 last_sw_conf_flags;
751 u16 last_sw_conf_valid_flags;
752
753 struct list_head ddp_old_prof;
754};
755
756
757
758
759
760
761
762static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
763{
764 u64 key = 0;
765
766 ether_addr_copy((u8 *)&key, macaddr);
767 return key;
768}
769
770enum i40e_filter_state {
771 I40E_FILTER_INVALID = 0,
772 I40E_FILTER_NEW,
773 I40E_FILTER_ACTIVE,
774 I40E_FILTER_FAILED,
775 I40E_FILTER_REMOVE,
776
777};
778struct i40e_mac_filter {
779 struct hlist_node hlist;
780 u8 macaddr[ETH_ALEN];
781#define I40E_VLAN_ANY -1
782 s16 vlan;
783 enum i40e_filter_state state;
784};
785
786
787
788
789
790
791
792
793
794struct i40e_new_mac_filter {
795 struct hlist_node hlist;
796 struct i40e_mac_filter *f;
797
798
799 enum i40e_filter_state state;
800};
801
802struct i40e_veb {
803 struct i40e_pf *pf;
804 u16 idx;
805 u16 veb_idx;
806 u16 seid;
807 u16 uplink_seid;
808 u16 stats_idx;
809 u8 enabled_tc;
810 u16 bridge_mode;
811 u16 flags;
812 u16 bw_limit;
813 u8 bw_max_quanta;
814 bool is_abs_credits;
815 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
816 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
817 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
818 struct kobject *kobj;
819 bool stat_offsets_loaded;
820 struct i40e_eth_stats stats;
821 struct i40e_eth_stats stats_offsets;
822 struct i40e_veb_tc_stats tc_stats;
823 struct i40e_veb_tc_stats tc_stats_offsets;
824};
825
826
827struct i40e_vsi {
828 struct net_device *netdev;
829 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
830 bool netdev_registered;
831 bool stat_offsets_loaded;
832
833 u32 current_netdev_flags;
834 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
835#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
836#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
837 unsigned long flags;
838
839
840 spinlock_t mac_filter_hash_lock;
841
842 DECLARE_HASHTABLE(mac_filter_hash, 8);
843 bool has_vlan_filter;
844
845
846 struct rtnl_link_stats64 net_stats;
847 struct rtnl_link_stats64 net_stats_offsets;
848 struct i40e_eth_stats eth_stats;
849 struct i40e_eth_stats eth_stats_offsets;
850 u32 tx_restart;
851 u32 tx_busy;
852 u64 tx_linearize;
853 u64 tx_force_wb;
854 u32 rx_buf_failed;
855 u32 rx_page_failed;
856
857
858 struct i40e_ring **rx_rings;
859 struct i40e_ring **tx_rings;
860 struct i40e_ring **xdp_rings;
861
862 u32 active_filters;
863 u32 promisc_threshold;
864
865 u16 work_limit;
866 u16 int_rate_limit;
867
868 u16 rss_table_size;
869 u16 rss_size;
870 u8 *rss_hkey_user;
871 u8 *rss_lut_user;
872
873
874 u16 max_frame;
875 u16 rx_buf_len;
876
877 struct bpf_prog *xdp_prog;
878
879
880 struct i40e_q_vector **q_vectors;
881 int num_q_vectors;
882 int base_vector;
883 bool irqs_ready;
884
885 u16 seid;
886 u16 id;
887 u16 uplink_seid;
888
889 u16 base_queue;
890 u16 alloc_queue_pairs;
891 u16 req_queue_pairs;
892 u16 num_queue_pairs;
893 u16 num_tx_desc;
894 u16 num_rx_desc;
895 enum i40e_vsi_type type;
896 s16 vf_id;
897
898 struct tc_mqprio_qopt_offload mqprio_qopt;
899 struct i40e_tc_configuration tc_config;
900 struct i40e_aqc_vsi_properties_data info;
901
902
903 u16 bw_limit;
904 u8 bw_max_quanta;
905
906
907 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
908
909 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
910
911 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
912
913 struct i40e_pf *back;
914 u16 idx;
915 u16 veb_idx;
916 struct kobject *kobj;
917 bool current_isup;
918 enum i40e_aq_link_speed current_speed;
919
920
921 u16 cnt_q_avail;
922 u16 orig_rss_size;
923 u16 current_rss_size;
924 bool reconfig_rss;
925
926 u16 next_base_queue;
927
928 struct list_head ch_list;
929 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
930
931
932#define I40E_MAX_MACVLANS 128
933#define I40E_MIN_MACVLAN_VECTORS 2
934 DECLARE_BITMAP(fwd_bitmask, I40E_MAX_MACVLANS);
935 struct list_head macvlan_list;
936 int macvlan_cnt;
937
938 void *priv;
939
940
941 irqreturn_t (*irq_handler)(int irq, void *data);
942
943 unsigned long *af_xdp_zc_qps;
944} ____cacheline_internodealigned_in_smp;
945
946struct i40e_netdev_priv {
947 struct i40e_vsi *vsi;
948};
949
950extern struct ida i40e_client_ida;
951
952
953struct i40e_q_vector {
954 struct i40e_vsi *vsi;
955
956 u16 v_idx;
957 u16 reg_idx;
958
959 struct napi_struct napi;
960
961 struct i40e_ring_container rx;
962 struct i40e_ring_container tx;
963
964 u8 itr_countdown;
965 u8 num_ringpairs;
966
967 cpumask_t affinity_mask;
968 struct irq_affinity_notify affinity_notify;
969
970 struct rcu_head rcu;
971 char name[I40E_INT_NAME_STR_LEN];
972 bool arm_wb_state;
973} ____cacheline_internodealigned_in_smp;
974
975
976struct i40e_device {
977 struct list_head list;
978 struct i40e_pf *pf;
979};
980
981
982
983
984
985static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
986{
987 static char buf[32];
988 u32 full_ver;
989
990 full_ver = hw->nvm.oem_ver;
991
992 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
993 u8 gen, snap;
994 u16 release;
995
996 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
997 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
998 I40E_OEM_SNAP_SHIFT);
999 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
1000
1001 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
1002 } else {
1003 u8 ver, patch;
1004 u16 build;
1005
1006 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
1007 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
1008 I40E_OEM_VER_BUILD_MASK);
1009 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
1010
1011 snprintf(buf, sizeof(buf),
1012 "%x.%02x 0x%x %d.%d.%d",
1013 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
1014 I40E_NVM_VERSION_HI_SHIFT,
1015 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
1016 I40E_NVM_VERSION_LO_SHIFT,
1017 hw->nvm.eetrack, ver, build, patch);
1018 }
1019
1020 return buf;
1021}
1022
1023
1024
1025
1026
1027
1028
1029static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
1030{
1031 struct i40e_netdev_priv *np = netdev_priv(netdev);
1032 struct i40e_vsi *vsi = np->vsi;
1033
1034 return vsi->back;
1035}
1036
1037static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
1038 irqreturn_t (*irq_handler)(int, void *))
1039{
1040 vsi->irq_handler = irq_handler;
1041}
1042
1043
1044
1045
1046
1047static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
1048{
1049 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
1050}
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
1061{
1062 u64 val;
1063
1064 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
1065 val <<= 32;
1066 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
1067
1068 return val;
1069}
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
1081 u16 addr, u64 val)
1082{
1083 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
1084 (u32)(val >> 32));
1085 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
1086 (u32)(val & 0xFFFFFFFFULL));
1087}
1088
1089
1090int i40e_up(struct i40e_vsi *vsi);
1091void i40e_down(struct i40e_vsi *vsi);
1092extern const char i40e_driver_name[];
1093void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
1094void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
1095int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1096int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
1097void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
1098 u16 rss_table_size, u16 rss_size);
1099struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
1100
1101
1102
1103
1104
1105static inline struct i40e_vsi *
1106i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
1107{
1108 int i;
1109
1110 for (i = 0; i < pf->num_alloc_vsi; i++) {
1111 struct i40e_vsi *vsi = pf->vsi[i];
1112
1113 if (vsi && vsi->type == type)
1114 return vsi;
1115 }
1116
1117 return NULL;
1118}
1119void i40e_update_stats(struct i40e_vsi *vsi);
1120void i40e_update_veb_stats(struct i40e_veb *veb);
1121void i40e_update_eth_stats(struct i40e_vsi *vsi);
1122struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
1123int i40e_fetch_switch_configuration(struct i40e_pf *pf,
1124 bool printconfig);
1125
1126int i40e_add_del_fdir(struct i40e_vsi *vsi,
1127 struct i40e_fdir_filter *input, bool add);
1128void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
1129u32 i40e_get_current_fd_count(struct i40e_pf *pf);
1130u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1131u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
1132u32 i40e_get_global_fd_count(struct i40e_pf *pf);
1133bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
1134void i40e_set_ethtool_ops(struct net_device *netdev);
1135struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1136 const u8 *macaddr, s16 vlan);
1137void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
1138void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
1139int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
1140struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
1141 u16 uplink, u32 param1);
1142int i40e_vsi_release(struct i40e_vsi *vsi);
1143void i40e_service_event_schedule(struct i40e_pf *pf);
1144void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
1145 u8 *msg, u16 len);
1146
1147int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
1148 bool enable);
1149int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
1150int i40e_vsi_start_rings(struct i40e_vsi *vsi);
1151void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
1152void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
1153int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
1154int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
1155struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1156 u16 downlink_seid, u8 enabled_tc);
1157void i40e_veb_release(struct i40e_veb *veb);
1158
1159int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1160int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1161void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1162void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1163void i40e_pf_reset_stats(struct i40e_pf *pf);
1164#ifdef CONFIG_DEBUG_FS
1165void i40e_dbg_pf_init(struct i40e_pf *pf);
1166void i40e_dbg_pf_exit(struct i40e_pf *pf);
1167void i40e_dbg_init(void);
1168void i40e_dbg_exit(void);
1169#else
1170static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1171static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1172static inline void i40e_dbg_init(void) {}
1173static inline void i40e_dbg_exit(void) {}
1174#endif
1175
1176int i40e_lan_add_device(struct i40e_pf *pf);
1177int i40e_lan_del_device(struct i40e_pf *pf);
1178void i40e_client_subtask(struct i40e_pf *pf);
1179void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1180void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1181void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1182void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1183void i40e_client_update_msix_info(struct i40e_pf *pf);
1184int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1185
1186
1187
1188
1189
1190static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1191{
1192 struct i40e_pf *pf = vsi->back;
1193 struct i40e_hw *hw = &pf->hw;
1194 u32 val;
1195
1196 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1197 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1198 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1199 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1200
1201}
1202
1203void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1204void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1205int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1206int i40e_open(struct net_device *netdev);
1207int i40e_close(struct net_device *netdev);
1208int i40e_vsi_open(struct i40e_vsi *vsi);
1209void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1210int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1211int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1212void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1213void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1214struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1215 const u8 *macaddr);
1216int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1217bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1218int i40e_count_filters(struct i40e_vsi *vsi);
1219struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1220void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1221static inline bool i40e_is_sw_dcb(struct i40e_pf *pf)
1222{
1223 return !!(pf->flags & I40E_FLAG_DISABLE_FW_LLDP);
1224}
1225
1226#ifdef CONFIG_I40E_DCB
1227void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1228 struct i40e_dcbx_config *old_cfg,
1229 struct i40e_dcbx_config *new_cfg);
1230void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1231void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1232bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1233 struct i40e_dcbx_config *old_cfg,
1234 struct i40e_dcbx_config *new_cfg);
1235int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg);
1236int i40e_dcb_sw_default_config(struct i40e_pf *pf);
1237#endif
1238void i40e_ptp_rx_hang(struct i40e_pf *pf);
1239void i40e_ptp_tx_hang(struct i40e_pf *pf);
1240void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1241void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1242void i40e_ptp_set_increment(struct i40e_pf *pf);
1243int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1244int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1245void i40e_ptp_save_hw_time(struct i40e_pf *pf);
1246void i40e_ptp_restore_hw_time(struct i40e_pf *pf);
1247void i40e_ptp_init(struct i40e_pf *pf);
1248void i40e_ptp_stop(struct i40e_pf *pf);
1249int i40e_ptp_alloc_pins(struct i40e_pf *pf);
1250int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1251i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1252i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1253i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1254void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1255
1256void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags);
1257
1258static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1259{
1260 return !!READ_ONCE(vsi->xdp_prog);
1261}
1262
1263int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1264int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1265int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1266 struct i40e_cloud_filter *filter,
1267 bool add);
1268int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1269 struct i40e_cloud_filter *filter,
1270 bool add);
1271#endif
1272