1
2
3
4#include "i40e.h"
5#include <linux/ptp_classify.h>
6#include <linux/posix-clock.h>
7
8
9
10
11
12
13
14
15
16
17
18
19
20#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
21#define I40E_PTP_10GB_INCVAL_MULT 2
22#define I40E_PTP_5GB_INCVAL_MULT 2
23#define I40E_PTP_1GB_INCVAL_MULT 20
24#define I40E_ISGN 0x80000000
25
26#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
27#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
28 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
29#define I40E_SUBDEV_ID_25G_PTP_PIN 0xB
30#define to_dev(obj) container_of(obj, struct device, kobj)
31
32enum i40e_ptp_pin {
33 SDP3_2 = 0,
34 SDP3_3,
35 GPIO_4
36};
37
38enum i40e_can_set_pins_t {
39 CANT_DO_PINS = -1,
40 CAN_SET_PINS,
41 CAN_DO_PINS
42};
43
44static struct ptp_pin_desc sdp_desc[] = {
45
46 {"SDP3_2", SDP3_2, PTP_PF_NONE, 0},
47 {"SDP3_3", SDP3_3, PTP_PF_NONE, 1},
48 {"GPIO_4", GPIO_4, PTP_PF_NONE, 1},
49};
50
51enum i40e_ptp_gpio_pin_state {
52 end = -2,
53 invalid,
54 off,
55 in_A,
56 in_B,
57 out_A,
58 out_B,
59};
60
61static const char * const i40e_ptp_gpio_pin_state2str[] = {
62 "off", "in_A", "in_B", "out_A", "out_B"
63};
64
65enum i40e_ptp_led_pin_state {
66 led_end = -2,
67 low = 0,
68 high,
69};
70
71struct i40e_ptp_pins_settings {
72 enum i40e_ptp_gpio_pin_state sdp3_2;
73 enum i40e_ptp_gpio_pin_state sdp3_3;
74 enum i40e_ptp_gpio_pin_state gpio_4;
75 enum i40e_ptp_led_pin_state led2_0;
76 enum i40e_ptp_led_pin_state led2_1;
77 enum i40e_ptp_led_pin_state led3_0;
78 enum i40e_ptp_led_pin_state led3_1;
79};
80
81static const struct i40e_ptp_pins_settings
82 i40e_ptp_pin_led_allowed_states[] = {
83 {off, off, off, high, high, high, high},
84 {off, in_A, off, high, high, high, low},
85 {off, out_A, off, high, low, high, high},
86 {off, in_B, off, high, high, high, low},
87 {off, out_B, off, high, low, high, high},
88 {in_A, off, off, high, high, high, low},
89 {in_A, in_B, off, high, high, high, low},
90 {in_A, out_B, off, high, low, high, high},
91 {out_A, off, off, high, low, high, high},
92 {out_A, in_B, off, high, low, high, high},
93 {in_B, off, off, high, high, high, low},
94 {in_B, in_A, off, high, high, high, low},
95 {in_B, out_A, off, high, low, high, high},
96 {out_B, off, off, high, low, high, high},
97 {out_B, in_A, off, high, low, high, high},
98 {off, off, in_A, high, high, low, high},
99 {off, out_A, in_A, high, low, low, high},
100 {off, in_B, in_A, high, high, low, low},
101 {off, out_B, in_A, high, low, low, high},
102 {out_A, off, in_A, high, low, low, high},
103 {out_A, in_B, in_A, high, low, low, high},
104 {in_B, off, in_A, high, high, low, low},
105 {in_B, out_A, in_A, high, low, low, high},
106 {out_B, off, in_A, high, low, low, high},
107 {off, off, out_A, low, high, high, high},
108 {off, in_A, out_A, low, high, high, low},
109 {off, in_B, out_A, low, high, high, low},
110 {off, out_B, out_A, low, low, high, high},
111 {in_A, off, out_A, low, high, high, low},
112 {in_A, in_B, out_A, low, high, high, low},
113 {in_A, out_B, out_A, low, low, high, high},
114 {in_B, off, out_A, low, high, high, low},
115 {in_B, in_A, out_A, low, high, high, low},
116 {out_B, off, out_A, low, low, high, high},
117 {out_B, in_A, out_A, low, low, high, high},
118 {off, off, in_B, high, high, low, high},
119 {off, in_A, in_B, high, high, low, low},
120 {off, out_A, in_B, high, low, low, high},
121 {off, out_B, in_B, high, low, low, high},
122 {in_A, off, in_B, high, high, low, low},
123 {in_A, out_B, in_B, high, low, low, high},
124 {out_A, off, in_B, high, low, low, high},
125 {out_B, off, in_B, high, low, low, high},
126 {out_B, in_A, in_B, high, low, low, high},
127 {off, off, out_B, low, high, high, high},
128 {off, in_A, out_B, low, high, high, low},
129 {off, out_A, out_B, low, low, high, high},
130 {off, in_B, out_B, low, high, high, low},
131 {in_A, off, out_B, low, high, high, low},
132 {in_A, in_B, out_B, low, high, high, low},
133 {out_A, off, out_B, low, low, high, high},
134 {out_A, in_B, out_B, low, low, high, high},
135 {in_B, off, out_B, low, high, high, low},
136 {in_B, in_A, out_B, low, high, high, low},
137 {in_B, out_A, out_B, low, low, high, high},
138 {end, end, end, led_end, led_end, led_end, led_end}
139};
140
141static int i40e_ptp_set_pins(struct i40e_pf *pf,
142 struct i40e_ptp_pins_settings *pins);
143
144
145
146
147
148
149
150static void i40e_ptp_extts0_work(struct work_struct *work)
151{
152 struct i40e_pf *pf = container_of(work, struct i40e_pf,
153 ptp_extts0_work);
154 struct i40e_hw *hw = &pf->hw;
155 struct ptp_clock_event event;
156 u32 hi, lo;
157
158
159
160
161
162
163 lo = rd32(hw, I40E_PRTTSYN_EVNT_L(0));
164 hi = rd32(hw, I40E_PRTTSYN_EVNT_H(0));
165
166 event.timestamp = (((u64)hi) << 32) | lo;
167
168 event.type = PTP_CLOCK_EXTTS;
169 event.index = hw->pf_id;
170
171
172 ptp_clock_event(pf->ptp_clock, &event);
173}
174
175
176
177
178
179
180
181static bool i40e_is_ptp_pin_dev(struct i40e_hw *hw)
182{
183 return hw->device_id == I40E_DEV_ID_25G_SFP28 &&
184 hw->subsystem_device_id == I40E_SUBDEV_ID_25G_PTP_PIN;
185}
186
187
188
189
190
191
192
193
194
195
196static enum i40e_can_set_pins_t i40e_can_set_pins(struct i40e_pf *pf)
197{
198 if (!i40e_is_ptp_pin_dev(&pf->hw)) {
199 dev_warn(&pf->pdev->dev,
200 "PTP external clock not supported.\n");
201 return CANT_DO_PINS;
202 }
203
204 if (!pf->ptp_pins) {
205 dev_warn(&pf->pdev->dev,
206 "PTP PIN manipulation not allowed.\n");
207 return CANT_DO_PINS;
208 }
209
210 if (pf->hw.pf_id) {
211 dev_warn(&pf->pdev->dev,
212 "PTP PINs should be accessed via PF0.\n");
213 return CAN_DO_PINS;
214 }
215
216 return CAN_SET_PINS;
217}
218
219
220
221
222
223
224
225static void i40_ptp_reset_timing_events(struct i40e_pf *pf)
226{
227 u32 i;
228
229 spin_lock_bh(&pf->ptp_rx_lock);
230 for (i = 0; i <= I40E_PRTTSYN_RXTIME_L_MAX_INDEX; i++) {
231
232 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_L(i));
233 rd32(&pf->hw, I40E_PRTTSYN_RXTIME_H(i));
234 pf->latch_events[i] = 0;
235 }
236
237 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_L);
238 rd32(&pf->hw, I40E_PRTTSYN_TXTIME_H);
239
240 pf->tx_hwtstamp_timeouts = 0;
241 pf->tx_hwtstamp_skipped = 0;
242 pf->rx_hwtstamp_cleared = 0;
243 pf->latch_event_flags = 0;
244 spin_unlock_bh(&pf->ptp_rx_lock);
245}
246
247
248
249
250
251
252
253
254
255
256
257static int i40e_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
258 enum ptp_pin_function func, unsigned int chan)
259{
260 switch (func) {
261 case PTP_PF_NONE:
262 case PTP_PF_EXTTS:
263 case PTP_PF_PEROUT:
264 break;
265 case PTP_PF_PHYSYNC:
266 return -EOPNOTSUPP;
267 }
268 return 0;
269}
270
271
272
273
274
275
276
277
278
279
280
281static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts,
282 struct ptp_system_timestamp *sts)
283{
284 struct i40e_hw *hw = &pf->hw;
285 u32 hi, lo;
286 u64 ns;
287
288
289 ptp_read_system_prets(sts);
290 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
291 ptp_read_system_postts(sts);
292 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
293
294 ns = (((u64)hi) << 32) | lo;
295
296 *ts = ns_to_timespec64(ns);
297}
298
299
300
301
302
303
304
305
306
307
308static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
309{
310 struct i40e_hw *hw = &pf->hw;
311 u64 ns = timespec64_to_ns(ts);
312
313
314
315
316 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
317 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
318}
319
320
321
322
323
324
325
326
327
328
329static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
330 u64 timestamp)
331{
332 memset(hwtstamps, 0, sizeof(*hwtstamps));
333
334 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
335}
336
337
338
339
340
341
342
343
344
345static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
346{
347 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
348 struct i40e_hw *hw = &pf->hw;
349 u64 adj, freq, diff;
350 int neg_adj = 0;
351
352 if (ppb < 0) {
353 neg_adj = 1;
354 ppb = -ppb;
355 }
356
357 freq = I40E_PTP_40GB_INCVAL;
358 freq *= ppb;
359 diff = div_u64(freq, 1000000000ULL);
360
361 if (neg_adj)
362 adj = I40E_PTP_40GB_INCVAL - diff;
363 else
364 adj = I40E_PTP_40GB_INCVAL + diff;
365
366
367
368
369
370
371
372
373 smp_mb();
374 adj *= READ_ONCE(pf->ptp_adj_mult);
375
376 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
377 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
378
379 return 0;
380}
381
382
383
384
385
386
387
388static void i40e_ptp_set_1pps_signal_hw(struct i40e_pf *pf)
389{
390 struct i40e_hw *hw = &pf->hw;
391 struct timespec64 now;
392 u64 ns;
393
394 wr32(hw, I40E_PRTTSYN_AUX_0(1), 0);
395 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT);
396 wr32(hw, I40E_PRTTSYN_AUX_0(1), I40E_PRTTSYN_AUX_0_OUT_ENABLE);
397
398 i40e_ptp_read(pf, &now, NULL);
399 now.tv_sec += I40E_PTP_2_SEC_DELAY;
400 now.tv_nsec = 0;
401 ns = timespec64_to_ns(&now);
402
403
404 wr32(hw, I40E_PRTTSYN_TGT_L(1), ns & 0xFFFFFFFF);
405
406 wr32(hw, I40E_PRTTSYN_TGT_H(1), ns >> 32);
407 wr32(hw, I40E_PRTTSYN_CLKO(1), I40E_PTP_HALF_SECOND);
408 wr32(hw, I40E_PRTTSYN_AUX_1(1), I40E_PRTTSYN_AUX_1_INSTNT);
409 wr32(hw, I40E_PRTTSYN_AUX_0(1),
410 I40E_PRTTSYN_AUX_0_OUT_ENABLE_CLK_MOD);
411}
412
413
414
415
416
417
418
419
420static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
421{
422 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
423 struct i40e_hw *hw = &pf->hw;
424
425 mutex_lock(&pf->tmreg_lock);
426
427 if (delta > -999999900LL && delta < 999999900LL) {
428 int neg_adj = 0;
429 u32 timadj;
430 u64 tohw;
431
432 if (delta < 0) {
433 neg_adj = 1;
434 tohw = -delta;
435 } else {
436 tohw = delta;
437 }
438
439 timadj = tohw & 0x3FFFFFFF;
440 if (neg_adj)
441 timadj |= I40E_ISGN;
442 wr32(hw, I40E_PRTTSYN_ADJ, timadj);
443 } else {
444 struct timespec64 then, now;
445
446 then = ns_to_timespec64(delta);
447 i40e_ptp_read(pf, &now, NULL);
448 now = timespec64_add(now, then);
449 i40e_ptp_write(pf, (const struct timespec64 *)&now);
450 i40e_ptp_set_1pps_signal_hw(pf);
451 }
452
453 mutex_unlock(&pf->tmreg_lock);
454
455 return 0;
456}
457
458
459
460
461
462
463
464
465
466
467static int i40e_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts,
468 struct ptp_system_timestamp *sts)
469{
470 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
471
472 mutex_lock(&pf->tmreg_lock);
473 i40e_ptp_read(pf, ts, sts);
474 mutex_unlock(&pf->tmreg_lock);
475
476 return 0;
477}
478
479
480
481
482
483
484
485
486
487static int i40e_ptp_settime(struct ptp_clock_info *ptp,
488 const struct timespec64 *ts)
489{
490 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
491
492 mutex_lock(&pf->tmreg_lock);
493 i40e_ptp_write(pf, ts);
494 mutex_unlock(&pf->tmreg_lock);
495
496 return 0;
497}
498
499
500
501
502
503
504
505
506
507
508static int i40e_pps_configure(struct ptp_clock_info *ptp,
509 struct ptp_clock_request *rq,
510 int on)
511{
512 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
513
514 if (!!on)
515 i40e_ptp_set_1pps_signal_hw(pf);
516
517 return 0;
518}
519
520
521
522
523
524
525
526
527
528static enum i40e_ptp_gpio_pin_state i40e_pin_state(int index, int func)
529{
530 enum i40e_ptp_gpio_pin_state state = off;
531
532 if (index == 0 && func == PTP_PF_EXTTS)
533 state = in_A;
534 if (index == 1 && func == PTP_PF_EXTTS)
535 state = in_B;
536 if (index == 0 && func == PTP_PF_PEROUT)
537 state = out_A;
538 if (index == 1 && func == PTP_PF_PEROUT)
539 state = out_B;
540
541 return state;
542}
543
544
545
546
547
548
549
550
551
552
553
554static int i40e_ptp_enable_pin(struct i40e_pf *pf, unsigned int chan,
555 enum ptp_pin_function func, int on)
556{
557 enum i40e_ptp_gpio_pin_state *pin = NULL;
558 struct i40e_ptp_pins_settings pins;
559 int pin_index;
560
561
562 if (pf->hw.pf_id)
563 return 0;
564
565
566 pins.sdp3_2 = pf->ptp_pins->sdp3_2;
567 pins.sdp3_3 = pf->ptp_pins->sdp3_3;
568 pins.gpio_4 = pf->ptp_pins->gpio_4;
569
570
571
572
573
574
575
576 if (on) {
577 pin_index = ptp_find_pin(pf->ptp_clock, func, chan);
578 if (pin_index < 0)
579 return -EBUSY;
580
581 switch (pin_index) {
582 case SDP3_2:
583 pin = &pins.sdp3_2;
584 break;
585 case SDP3_3:
586 pin = &pins.sdp3_3;
587 break;
588 case GPIO_4:
589 pin = &pins.gpio_4;
590 break;
591 default:
592 return -EINVAL;
593 }
594
595 *pin = i40e_pin_state(chan, func);
596 } else {
597 pins.sdp3_2 = off;
598 pins.sdp3_3 = off;
599 pins.gpio_4 = off;
600 }
601
602 return i40e_ptp_set_pins(pf, &pins) ? -EINVAL : 0;
603}
604
605
606
607
608
609
610
611
612
613static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
614 struct ptp_clock_request *rq,
615 int on)
616{
617 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
618
619 enum ptp_pin_function func;
620 unsigned int chan;
621
622
623 switch (rq->type) {
624 case PTP_CLK_REQ_EXTTS:
625 func = PTP_PF_EXTTS;
626 chan = rq->extts.index;
627 break;
628 case PTP_CLK_REQ_PEROUT:
629 func = PTP_PF_PEROUT;
630 chan = rq->perout.index;
631 break;
632 case PTP_CLK_REQ_PPS:
633 return i40e_pps_configure(ptp, rq, on);
634 default:
635 return -EOPNOTSUPP;
636 }
637
638 return i40e_ptp_enable_pin(pf, chan, func, on);
639}
640
641
642
643
644
645
646
647
648
649
650
651
652
653static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf)
654{
655 struct i40e_hw *hw = &pf->hw;
656 u32 prttsyn_stat, new_latch_events;
657 int i;
658
659 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
660 new_latch_events = prttsyn_stat & ~pf->latch_event_flags;
661
662
663
664
665
666
667
668
669
670
671 for (i = 0; i < 4; i++) {
672 if (new_latch_events & BIT(i))
673 pf->latch_events[i] = jiffies;
674 }
675
676
677 pf->latch_event_flags = prttsyn_stat;
678
679 return prttsyn_stat;
680}
681
682
683
684
685
686
687
688
689
690
691void i40e_ptp_rx_hang(struct i40e_pf *pf)
692{
693 struct i40e_hw *hw = &pf->hw;
694 unsigned int i, cleared = 0;
695
696
697
698
699
700
701 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
702 return;
703
704 spin_lock_bh(&pf->ptp_rx_lock);
705
706
707 i40e_ptp_get_rx_events(pf);
708
709
710
711
712
713
714
715 for (i = 0; i < 4; i++) {
716 if ((pf->latch_event_flags & BIT(i)) &&
717 time_is_before_jiffies(pf->latch_events[i] + HZ)) {
718 rd32(hw, I40E_PRTTSYN_RXTIME_H(i));
719 pf->latch_event_flags &= ~BIT(i);
720 cleared++;
721 }
722 }
723
724 spin_unlock_bh(&pf->ptp_rx_lock);
725
726
727
728
729
730
731
732 if (cleared > 2)
733 dev_dbg(&pf->pdev->dev,
734 "Dropped %d missed RXTIME timestamp events\n",
735 cleared);
736
737
738 pf->rx_hwtstamp_cleared += cleared;
739}
740
741
742
743
744
745
746
747
748
749
750void i40e_ptp_tx_hang(struct i40e_pf *pf)
751{
752 struct sk_buff *skb;
753
754 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
755 return;
756
757
758 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state))
759 return;
760
761
762
763
764
765 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) {
766 skb = pf->ptp_tx_skb;
767 pf->ptp_tx_skb = NULL;
768 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
769
770
771 dev_kfree_skb_any(skb);
772 pf->tx_hwtstamp_timeouts++;
773 }
774}
775
776
777
778
779
780
781
782
783
784void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
785{
786 struct skb_shared_hwtstamps shhwtstamps;
787 struct sk_buff *skb = pf->ptp_tx_skb;
788 struct i40e_hw *hw = &pf->hw;
789 u32 hi, lo;
790 u64 ns;
791
792 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
793 return;
794
795
796 if (!pf->ptp_tx_skb)
797 return;
798
799 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
800 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
801
802 ns = (((u64)hi) << 32) | lo;
803 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
804
805
806
807
808
809
810 pf->ptp_tx_skb = NULL;
811 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
812
813
814 skb_tstamp_tx(skb, &shhwtstamps);
815 dev_kfree_skb_any(skb);
816}
817
818
819
820
821
822
823
824
825
826
827
828
829
830void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
831{
832 u32 prttsyn_stat, hi, lo;
833 struct i40e_hw *hw;
834 u64 ns;
835
836
837
838
839 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
840 return;
841
842 hw = &pf->hw;
843
844 spin_lock_bh(&pf->ptp_rx_lock);
845
846
847 prttsyn_stat = i40e_ptp_get_rx_events(pf);
848
849
850 if (!(prttsyn_stat & BIT(index))) {
851 spin_unlock_bh(&pf->ptp_rx_lock);
852 return;
853 }
854
855
856 pf->latch_event_flags &= ~BIT(index);
857
858 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
859 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
860
861 spin_unlock_bh(&pf->ptp_rx_lock);
862
863 ns = (((u64)hi) << 32) | lo;
864
865 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
866}
867
868
869
870
871
872
873
874
875
876void i40e_ptp_set_increment(struct i40e_pf *pf)
877{
878 struct i40e_link_status *hw_link_info;
879 struct i40e_hw *hw = &pf->hw;
880 u64 incval;
881 u32 mult;
882
883 hw_link_info = &hw->phy.link_info;
884
885 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
886
887 switch (hw_link_info->link_speed) {
888 case I40E_LINK_SPEED_10GB:
889 mult = I40E_PTP_10GB_INCVAL_MULT;
890 break;
891 case I40E_LINK_SPEED_5GB:
892 mult = I40E_PTP_5GB_INCVAL_MULT;
893 break;
894 case I40E_LINK_SPEED_1GB:
895 mult = I40E_PTP_1GB_INCVAL_MULT;
896 break;
897 case I40E_LINK_SPEED_100MB:
898 {
899 static int warn_once;
900
901 if (!warn_once) {
902 dev_warn(&pf->pdev->dev,
903 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
904 warn_once++;
905 }
906 mult = 0;
907 break;
908 }
909 case I40E_LINK_SPEED_40GB:
910 default:
911 mult = 1;
912 break;
913 }
914
915
916
917
918 incval = I40E_PTP_40GB_INCVAL * mult;
919
920
921
922
923
924 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
925 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
926
927
928 WRITE_ONCE(pf->ptp_adj_mult, mult);
929 smp_mb();
930}
931
932
933
934
935
936
937
938
939
940
941int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
942{
943 struct hwtstamp_config *config = &pf->tstamp_config;
944
945 if (!(pf->flags & I40E_FLAG_PTP))
946 return -EOPNOTSUPP;
947
948 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
949 -EFAULT : 0;
950}
951
952
953
954
955
956
957
958static void i40e_ptp_free_pins(struct i40e_pf *pf)
959{
960 if (i40e_is_ptp_pin_dev(&pf->hw)) {
961 kfree(pf->ptp_pins);
962 kfree(pf->ptp_caps.pin_config);
963 pf->ptp_pins = NULL;
964 }
965}
966
967
968
969
970
971
972
973
974
975static void i40e_ptp_set_pin_hw(struct i40e_hw *hw,
976 unsigned int pin,
977 enum i40e_ptp_gpio_pin_state state)
978{
979 switch (state) {
980 case off:
981 wr32(hw, I40E_GLGEN_GPIO_CTL(pin), 0);
982 break;
983 case in_A:
984 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
985 I40E_GLGEN_GPIO_CTL_PORT_0_IN_TIMESYNC_0);
986 break;
987 case in_B:
988 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
989 I40E_GLGEN_GPIO_CTL_PORT_1_IN_TIMESYNC_0);
990 break;
991 case out_A:
992 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
993 I40E_GLGEN_GPIO_CTL_PORT_0_OUT_TIMESYNC_1);
994 break;
995 case out_B:
996 wr32(hw, I40E_GLGEN_GPIO_CTL(pin),
997 I40E_GLGEN_GPIO_CTL_PORT_1_OUT_TIMESYNC_1);
998 break;
999 default:
1000 break;
1001 }
1002}
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012static void i40e_ptp_set_led_hw(struct i40e_hw *hw,
1013 unsigned int led,
1014 enum i40e_ptp_led_pin_state state)
1015{
1016 switch (state) {
1017 case low:
1018 wr32(hw, I40E_GLGEN_GPIO_SET,
1019 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA | led);
1020 break;
1021 case high:
1022 wr32(hw, I40E_GLGEN_GPIO_SET,
1023 I40E_GLGEN_GPIO_SET_DRV_SDP_DATA |
1024 I40E_GLGEN_GPIO_SET_SDP_DATA_HI | led);
1025 break;
1026 default:
1027 break;
1028 }
1029}
1030
1031
1032
1033
1034
1035
1036
1037static void i40e_ptp_init_leds_hw(struct i40e_hw *hw)
1038{
1039 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_0),
1040 I40E_GLGEN_GPIO_CTL_LED_INIT);
1041 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED2_1),
1042 I40E_GLGEN_GPIO_CTL_LED_INIT);
1043 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_0),
1044 I40E_GLGEN_GPIO_CTL_LED_INIT);
1045 wr32(hw, I40E_GLGEN_GPIO_CTL(I40E_LED3_1),
1046 I40E_GLGEN_GPIO_CTL_LED_INIT);
1047}
1048
1049
1050
1051
1052
1053
1054
1055static void i40e_ptp_set_pins_hw(struct i40e_pf *pf)
1056{
1057 const struct i40e_ptp_pins_settings *pins = pf->ptp_pins;
1058 struct i40e_hw *hw = &pf->hw;
1059
1060
1061 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off);
1062 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off);
1063 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off);
1064
1065 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, pins->sdp3_2);
1066 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, pins->sdp3_3);
1067 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, pins->gpio_4);
1068
1069 i40e_ptp_set_led_hw(hw, I40E_LED2_0, pins->led2_0);
1070 i40e_ptp_set_led_hw(hw, I40E_LED2_1, pins->led2_1);
1071 i40e_ptp_set_led_hw(hw, I40E_LED3_0, pins->led3_0);
1072 i40e_ptp_set_led_hw(hw, I40E_LED3_1, pins->led3_1);
1073
1074 dev_info(&pf->pdev->dev,
1075 "PTP configuration set to: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n",
1076 i40e_ptp_gpio_pin_state2str[pins->sdp3_2],
1077 i40e_ptp_gpio_pin_state2str[pins->sdp3_3],
1078 i40e_ptp_gpio_pin_state2str[pins->gpio_4]);
1079}
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089static int i40e_ptp_set_pins(struct i40e_pf *pf,
1090 struct i40e_ptp_pins_settings *pins)
1091{
1092 enum i40e_can_set_pins_t pin_caps = i40e_can_set_pins(pf);
1093 int i = 0;
1094
1095 if (pin_caps == CANT_DO_PINS)
1096 return -EOPNOTSUPP;
1097 else if (pin_caps == CAN_DO_PINS)
1098 return 0;
1099
1100 if (pins->sdp3_2 == invalid)
1101 pins->sdp3_2 = pf->ptp_pins->sdp3_2;
1102 if (pins->sdp3_3 == invalid)
1103 pins->sdp3_3 = pf->ptp_pins->sdp3_3;
1104 if (pins->gpio_4 == invalid)
1105 pins->gpio_4 = pf->ptp_pins->gpio_4;
1106 while (i40e_ptp_pin_led_allowed_states[i].sdp3_2 != end) {
1107 if (pins->sdp3_2 == i40e_ptp_pin_led_allowed_states[i].sdp3_2 &&
1108 pins->sdp3_3 == i40e_ptp_pin_led_allowed_states[i].sdp3_3 &&
1109 pins->gpio_4 == i40e_ptp_pin_led_allowed_states[i].gpio_4) {
1110 pins->led2_0 =
1111 i40e_ptp_pin_led_allowed_states[i].led2_0;
1112 pins->led2_1 =
1113 i40e_ptp_pin_led_allowed_states[i].led2_1;
1114 pins->led3_0 =
1115 i40e_ptp_pin_led_allowed_states[i].led3_0;
1116 pins->led3_1 =
1117 i40e_ptp_pin_led_allowed_states[i].led3_1;
1118 break;
1119 }
1120 i++;
1121 }
1122 if (i40e_ptp_pin_led_allowed_states[i].sdp3_2 == end) {
1123 dev_warn(&pf->pdev->dev,
1124 "Unsupported PTP pin configuration: SDP3_2: %s, SDP3_3: %s, GPIO_4: %s.\n",
1125 i40e_ptp_gpio_pin_state2str[pins->sdp3_2],
1126 i40e_ptp_gpio_pin_state2str[pins->sdp3_3],
1127 i40e_ptp_gpio_pin_state2str[pins->gpio_4]);
1128
1129 return -EPERM;
1130 }
1131 memcpy(pf->ptp_pins, pins, sizeof(*pins));
1132 i40e_ptp_set_pins_hw(pf);
1133 i40_ptp_reset_timing_events(pf);
1134
1135 return 0;
1136}
1137
1138
1139
1140
1141
1142
1143
1144int i40e_ptp_alloc_pins(struct i40e_pf *pf)
1145{
1146 if (!i40e_is_ptp_pin_dev(&pf->hw))
1147 return 0;
1148
1149 pf->ptp_pins =
1150 kzalloc(sizeof(struct i40e_ptp_pins_settings), GFP_KERNEL);
1151
1152 if (!pf->ptp_pins) {
1153 dev_warn(&pf->pdev->dev, "Cannot allocate memory for PTP pins structure.\n");
1154 return -I40E_ERR_NO_MEMORY;
1155 }
1156
1157 pf->ptp_pins->sdp3_2 = off;
1158 pf->ptp_pins->sdp3_3 = off;
1159 pf->ptp_pins->gpio_4 = off;
1160 pf->ptp_pins->led2_0 = high;
1161 pf->ptp_pins->led2_1 = high;
1162 pf->ptp_pins->led3_0 = high;
1163 pf->ptp_pins->led3_1 = high;
1164
1165
1166 if (pf->hw.pf_id)
1167 return 0;
1168
1169 i40e_ptp_init_leds_hw(&pf->hw);
1170 i40e_ptp_set_pins_hw(pf);
1171
1172 return 0;
1173}
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
1188 struct hwtstamp_config *config)
1189{
1190 struct i40e_hw *hw = &pf->hw;
1191 u32 tsyntype, regval;
1192
1193
1194 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));
1195
1196 regval &= 0;
1197 regval |= (1 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT);
1198
1199 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);
1200
1201
1202 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1203 regval |= 1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT;
1204 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1205
1206 INIT_WORK(&pf->ptp_extts0_work, i40e_ptp_extts0_work);
1207
1208
1209 if (config->flags)
1210 return -EINVAL;
1211
1212 switch (config->tx_type) {
1213 case HWTSTAMP_TX_OFF:
1214 pf->ptp_tx = false;
1215 break;
1216 case HWTSTAMP_TX_ON:
1217 pf->ptp_tx = true;
1218 break;
1219 default:
1220 return -ERANGE;
1221 }
1222
1223 switch (config->rx_filter) {
1224 case HWTSTAMP_FILTER_NONE:
1225 pf->ptp_rx = false;
1226
1227
1228
1229
1230
1231 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
1232 break;
1233 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1234 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1235 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1236 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
1237 return -ERANGE;
1238 pf->ptp_rx = true;
1239 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
1240 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
1241 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
1242 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1243 break;
1244 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1245 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1246 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1247 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1248 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1249 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1250 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
1251 return -ERANGE;
1252 fallthrough;
1253 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1254 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1255 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1256 pf->ptp_rx = true;
1257 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
1258 I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
1259 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
1260 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
1261 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1262 } else {
1263 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1264 }
1265 break;
1266 case HWTSTAMP_FILTER_NTP_ALL:
1267 case HWTSTAMP_FILTER_ALL:
1268 default:
1269 return -ERANGE;
1270 }
1271
1272
1273 spin_lock_bh(&pf->ptp_rx_lock);
1274 rd32(hw, I40E_PRTTSYN_STAT_0);
1275 rd32(hw, I40E_PRTTSYN_TXTIME_H);
1276 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
1277 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
1278 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
1279 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
1280 pf->latch_event_flags = 0;
1281 spin_unlock_bh(&pf->ptp_rx_lock);
1282
1283
1284 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1285 if (pf->ptp_tx)
1286 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
1287 else
1288 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
1289 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1290
1291 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
1292 if (pf->ptp_tx)
1293 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
1294 else
1295 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
1296 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
1297
1298
1299
1300
1301
1302
1303
1304 regval = rd32(hw, I40E_PRTTSYN_CTL1);
1305
1306 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
1307
1308 regval |= tsyntype;
1309 wr32(hw, I40E_PRTTSYN_CTL1, regval);
1310
1311 return 0;
1312}
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
1329{
1330 struct hwtstamp_config config;
1331 int err;
1332
1333 if (!(pf->flags & I40E_FLAG_PTP))
1334 return -EOPNOTSUPP;
1335
1336 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1337 return -EFAULT;
1338
1339 err = i40e_ptp_set_timestamp_mode(pf, &config);
1340 if (err)
1341 return err;
1342
1343
1344 pf->tstamp_config = config;
1345
1346 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1347 -EFAULT : 0;
1348}
1349
1350
1351
1352
1353
1354
1355
1356
1357static int i40e_init_pin_config(struct i40e_pf *pf)
1358{
1359 int i;
1360
1361 pf->ptp_caps.n_pins = 3;
1362 pf->ptp_caps.n_ext_ts = 2;
1363 pf->ptp_caps.pps = 1;
1364 pf->ptp_caps.n_per_out = 2;
1365
1366 pf->ptp_caps.pin_config = kcalloc(pf->ptp_caps.n_pins,
1367 sizeof(*pf->ptp_caps.pin_config),
1368 GFP_KERNEL);
1369 if (!pf->ptp_caps.pin_config)
1370 return -ENOMEM;
1371
1372 for (i = 0; i < pf->ptp_caps.n_pins; i++) {
1373 snprintf(pf->ptp_caps.pin_config[i].name,
1374 sizeof(pf->ptp_caps.pin_config[i].name),
1375 "%s", sdp_desc[i].name);
1376 pf->ptp_caps.pin_config[i].index = sdp_desc[i].index;
1377 pf->ptp_caps.pin_config[i].func = PTP_PF_NONE;
1378 pf->ptp_caps.pin_config[i].chan = sdp_desc[i].chan;
1379 }
1380
1381 pf->ptp_caps.verify = i40e_ptp_verify;
1382 pf->ptp_caps.enable = i40e_ptp_feature_enable;
1383
1384 pf->ptp_caps.pps = 1;
1385
1386 return 0;
1387}
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399static long i40e_ptp_create_clock(struct i40e_pf *pf)
1400{
1401
1402 if (!IS_ERR_OR_NULL(pf->ptp_clock))
1403 return 0;
1404
1405 strlcpy(pf->ptp_caps.name, i40e_driver_name,
1406 sizeof(pf->ptp_caps.name) - 1);
1407 pf->ptp_caps.owner = THIS_MODULE;
1408 pf->ptp_caps.max_adj = 999999999;
1409 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
1410 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
1411 pf->ptp_caps.gettimex64 = i40e_ptp_gettimex;
1412 pf->ptp_caps.settime64 = i40e_ptp_settime;
1413 if (i40e_is_ptp_pin_dev(&pf->hw)) {
1414 int err = i40e_init_pin_config(pf);
1415
1416 if (err)
1417 return err;
1418 }
1419
1420
1421 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
1422 if (IS_ERR(pf->ptp_clock))
1423 return PTR_ERR(pf->ptp_clock);
1424
1425
1426
1427
1428
1429 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1430 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1431
1432
1433 ktime_get_real_ts64(&pf->ptp_prev_hw_time);
1434 pf->ptp_reset_start = ktime_get();
1435
1436 return 0;
1437}
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448void i40e_ptp_save_hw_time(struct i40e_pf *pf)
1449{
1450
1451 if (!(pf->flags & I40E_FLAG_PTP))
1452 return;
1453
1454 i40e_ptp_gettimex(&pf->ptp_caps, &pf->ptp_prev_hw_time, NULL);
1455
1456 pf->ptp_reset_start = ktime_get();
1457}
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471void i40e_ptp_restore_hw_time(struct i40e_pf *pf)
1472{
1473 ktime_t delta = ktime_sub(ktime_get(), pf->ptp_reset_start);
1474
1475
1476 timespec64_add_ns(&pf->ptp_prev_hw_time, ktime_to_ns(delta));
1477
1478
1479 i40e_ptp_settime(&pf->ptp_caps, &pf->ptp_prev_hw_time);
1480}
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495void i40e_ptp_init(struct i40e_pf *pf)
1496{
1497 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
1498 struct i40e_hw *hw = &pf->hw;
1499 u32 pf_id;
1500 long err;
1501
1502
1503
1504
1505 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
1506 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
1507 if (hw->pf_id != pf_id) {
1508 pf->flags &= ~I40E_FLAG_PTP;
1509 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
1510 __func__,
1511 netdev->name);
1512 return;
1513 }
1514
1515 mutex_init(&pf->tmreg_lock);
1516 spin_lock_init(&pf->ptp_rx_lock);
1517
1518
1519 err = i40e_ptp_create_clock(pf);
1520 if (err) {
1521 pf->ptp_clock = NULL;
1522 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
1523 __func__);
1524 } else if (pf->ptp_clock) {
1525 u32 regval;
1526
1527 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
1528 dev_info(&pf->pdev->dev, "PHC enabled\n");
1529 pf->flags |= I40E_FLAG_PTP;
1530
1531
1532 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1533 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
1534 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1535 regval = rd32(hw, I40E_PRTTSYN_CTL1);
1536 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
1537 wr32(hw, I40E_PRTTSYN_CTL1, regval);
1538
1539
1540 i40e_ptp_set_increment(pf);
1541
1542
1543 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
1544
1545
1546 i40e_ptp_restore_hw_time(pf);
1547 }
1548
1549 i40e_ptp_set_1pps_signal_hw(pf);
1550}
1551
1552
1553
1554
1555
1556
1557
1558
1559void i40e_ptp_stop(struct i40e_pf *pf)
1560{
1561 struct i40e_hw *hw = &pf->hw;
1562 u32 regval;
1563
1564 pf->flags &= ~I40E_FLAG_PTP;
1565 pf->ptp_tx = false;
1566 pf->ptp_rx = false;
1567
1568 if (pf->ptp_tx_skb) {
1569 struct sk_buff *skb = pf->ptp_tx_skb;
1570
1571 pf->ptp_tx_skb = NULL;
1572 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
1573 dev_kfree_skb_any(skb);
1574 }
1575
1576 if (pf->ptp_clock) {
1577 ptp_clock_unregister(pf->ptp_clock);
1578 pf->ptp_clock = NULL;
1579 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
1580 pf->vsi[pf->lan_vsi]->netdev->name);
1581 }
1582
1583 if (i40e_is_ptp_pin_dev(&pf->hw)) {
1584 i40e_ptp_set_pin_hw(hw, I40E_SDP3_2, off);
1585 i40e_ptp_set_pin_hw(hw, I40E_SDP3_3, off);
1586 i40e_ptp_set_pin_hw(hw, I40E_GPIO_4, off);
1587 }
1588
1589 regval = rd32(hw, I40E_PRTTSYN_AUX_0(0));
1590 regval &= ~I40E_PRTTSYN_AUX_0_PTPFLAG_MASK;
1591 wr32(hw, I40E_PRTTSYN_AUX_0(0), regval);
1592
1593
1594 regval = rd32(hw, I40E_PRTTSYN_CTL0);
1595 regval &= ~I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK;
1596 wr32(hw, I40E_PRTTSYN_CTL0, regval);
1597
1598 i40e_ptp_free_pins(pf);
1599}
1600