1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4#ifndef _E1000_DEFINES_H_ 5#define _E1000_DEFINES_H_ 6 7/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 8#define REQ_TX_DESCRIPTOR_MULTIPLE 8 9#define REQ_RX_DESCRIPTOR_MULTIPLE 8 10 11/* IVAR valid bit */ 12#define E1000_IVAR_VALID 0x80 13 14/* Receive Descriptor bit definitions */ 15#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 16#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 17#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 18#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 19#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 20#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 21#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 22#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 23#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 24 25#define E1000_RXDEXT_STATERR_LB 0x00040000 26#define E1000_RXDEXT_STATERR_CE 0x01000000 27#define E1000_RXDEXT_STATERR_SE 0x02000000 28#define E1000_RXDEXT_STATERR_SEQ 0x04000000 29#define E1000_RXDEXT_STATERR_CXE 0x10000000 30#define E1000_RXDEXT_STATERR_TCPE 0x20000000 31#define E1000_RXDEXT_STATERR_IPE 0x40000000 32#define E1000_RXDEXT_STATERR_RXE 0x80000000 33 34/* Same mask, but for extended and packet split descriptors */ 35#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 36 E1000_RXDEXT_STATERR_CE | \ 37 E1000_RXDEXT_STATERR_SE | \ 38 E1000_RXDEXT_STATERR_SEQ | \ 39 E1000_RXDEXT_STATERR_CXE | \ 40 E1000_RXDEXT_STATERR_RXE) 41 42/* Device Control */ 43#define E1000_CTRL_RST 0x04000000 /* Global reset */ 44 45/* Device Status */ 46#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 47#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 48#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 49#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 50#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 51#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 52 53#define SPEED_10 10 54#define SPEED_100 100 55#define SPEED_1000 1000 56#define HALF_DUPLEX 1 57#define FULL_DUPLEX 2 58 59/* Transmit Descriptor bit definitions */ 60#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 61#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 62#define E1000_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 63#define E1000_TXD_STAT_DD 0x00000001 /* Desc Done */ 64 65#define MAX_JUMBO_FRAME_SIZE 0x3F00 66#define MAX_STD_JUMBO_FRAME_SIZE 9216 67 68/* 802.1q VLAN Packet Size */ 69#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 70 71/* Error Codes */ 72#define E1000_SUCCESS 0 73#define E1000_ERR_CONFIG 3 74#define E1000_ERR_MAC_INIT 5 75#define E1000_ERR_MBX 15 76 77/* SRRCTL bit definitions */ 78#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 79#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 80#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 81#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 82#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 83#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 84#define E1000_SRRCTL_DROP_EN 0x80000000 85 86#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F 87#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 88 89/* Additional Descriptor Control definitions */ 90#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Que */ 91#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Que */ 92 93/* Direct Cache Access (DCA) definitions */ 94#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ 95 96#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 97 98#endif /* _E1000_DEFINES_H_ */ 99