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12#ifndef __JME_H_INCLUDED__
13#define __JME_H_INCLUDED__
14#include <linux/interrupt.h>
15
16#define DRV_NAME "jme"
17#define DRV_VERSION "1.0.8"
18
19#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
20#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
21
22
23
24
25#define JME_DEF_MSG_ENABLE \
26 (NETIF_MSG_PROBE | \
27 NETIF_MSG_LINK | \
28 NETIF_MSG_RX_ERR | \
29 NETIF_MSG_TX_ERR | \
30 NETIF_MSG_HW)
31
32#ifdef TX_DEBUG
33#define tx_dbg(priv, fmt, args...) \
34 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
35#else
36#define tx_dbg(priv, fmt, args...) \
37do { \
38 if (0) \
39 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
40} while (0)
41#endif
42
43
44
45
46#define PCI_DCSR_MRRS 0x59
47#define PCI_DCSR_MRRS_MASK 0x70
48
49enum pci_dcsr_mrrs_vals {
50 MRRS_128B = 0x00,
51 MRRS_256B = 0x10,
52 MRRS_512B = 0x20,
53 MRRS_1024B = 0x30,
54 MRRS_2048B = 0x40,
55 MRRS_4096B = 0x50,
56};
57
58#define PCI_SPI 0xB0
59
60enum pci_spi_bits {
61 SPI_EN = 0x10,
62 SPI_MISO = 0x08,
63 SPI_MOSI = 0x04,
64 SPI_SCLK = 0x02,
65 SPI_CS = 0x01,
66};
67
68struct jme_spi_op {
69 void __user *uwbuf;
70 void __user *urbuf;
71 __u8 wn;
72 __u8 rn;
73 __u8 bitn;
74 __u8 spd;
75 __u8 mode;
76
77
78 u8 *kwbuf;
79 u8 *krbuf;
80 u8 sr;
81 u16 halfclk;
82};
83
84enum jme_spi_op_bits {
85 SPI_MODE_CPHA = 0x01,
86 SPI_MODE_CPOL = 0x02,
87 SPI_MODE_DUP = 0x80,
88};
89
90#define HALF_US 500
91
92#define PCI_PRIV_PE1 0xE4
93
94enum pci_priv_pe1_bit_masks {
95 PE1_ASPMSUPRT = 0x00000003,
96
97
98
99
100 PE1_MULTIFUN = 0x00000004,
101 PE1_RDYDMA = 0x00000008,
102 PE1_ASPMOPTL = 0x00000030,
103 PE1_ASPMOPTH = 0x000000C0,
104 PE1_GPREG0 = 0x0000FF00,
105
106
107
108
109
110
111 PE1_GPREG0_PBG = 0x0000C000,
112 PE1_GPREG1 = 0x00FF0000,
113 PE1_REVID = 0xFF000000,
114};
115
116enum pci_priv_pe1_values {
117 PE1_GPREG0_ENBG = 0x00000000,
118 PE1_GPREG0_PDD3COLD = 0x00004000,
119 PE1_GPREG0_PDPCIESD = 0x00008000,
120 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000,
121};
122
123
124
125
126enum dynamic_pcc_values {
127 PCC_OFF = 0,
128 PCC_P1 = 1,
129 PCC_P2 = 2,
130 PCC_P3 = 3,
131
132 PCC_OFF_TO = 0,
133 PCC_P1_TO = 1,
134 PCC_P2_TO = 64,
135 PCC_P3_TO = 128,
136
137 PCC_OFF_CNT = 0,
138 PCC_P1_CNT = 1,
139 PCC_P2_CNT = 16,
140 PCC_P3_CNT = 32,
141};
142struct dynpcc_info {
143 unsigned long last_bytes;
144 unsigned long last_pkts;
145 unsigned long intr_cnt;
146 unsigned char cur;
147 unsigned char attempt;
148 unsigned char cnt;
149};
150#define PCC_INTERVAL_US 100000
151#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
152#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
153#define PCC_P2_THRESHOLD 800
154#define PCC_INTR_THRESHOLD 800
155#define PCC_TX_TO 1000
156#define PCC_TX_CNT 8
157
158
159
160
161
162
163#define RING_DESC_ALIGN 16
164#define TX_DESC_SIZE 16
165#define TX_RING_NR 8
166#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
167
168struct txdesc {
169 union {
170 __u8 all[16];
171 __le32 dw[4];
172 struct {
173
174 __le16 vlan;
175 __u8 rsv1;
176 __u8 flags;
177
178
179 __le16 datalen;
180 __le16 mss;
181
182
183 __le16 pktsize;
184 __le16 rsv2;
185
186
187 __le32 bufaddr;
188 } desc1;
189 struct {
190
191 __le16 rsv1;
192 __u8 rsv2;
193 __u8 flags;
194
195
196 __le16 datalen;
197 __le16 rsv3;
198
199
200 __le32 bufaddrh;
201
202
203 __le32 bufaddrl;
204 } desc2;
205 struct {
206
207 __u8 ehdrsz;
208 __u8 rsv1;
209 __u8 rsv2;
210 __u8 flags;
211
212
213 __le16 trycnt;
214 __le16 segcnt;
215
216
217 __le16 pktsz;
218 __le16 rsv3;
219
220
221 __le32 bufaddrl;
222 } descwb;
223 };
224};
225
226enum jme_txdesc_flags_bits {
227 TXFLAG_OWN = 0x80,
228 TXFLAG_INT = 0x40,
229 TXFLAG_64BIT = 0x20,
230 TXFLAG_TCPCS = 0x10,
231 TXFLAG_UDPCS = 0x08,
232 TXFLAG_IPCS = 0x04,
233 TXFLAG_LSEN = 0x02,
234 TXFLAG_TAGON = 0x01,
235};
236
237#define TXDESC_MSS_SHIFT 2
238enum jme_txwbdesc_flags_bits {
239 TXWBFLAG_OWN = 0x80,
240 TXWBFLAG_INT = 0x40,
241 TXWBFLAG_TMOUT = 0x20,
242 TXWBFLAG_TRYOUT = 0x10,
243 TXWBFLAG_COL = 0x08,
244
245 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
246 TXWBFLAG_TRYOUT |
247 TXWBFLAG_COL,
248};
249
250#define RX_DESC_SIZE 16
251#define RX_RING_NR 4
252#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
253#define RX_BUF_DMA_ALIGN 8
254#define RX_PREPAD_SIZE 10
255#define ETH_CRC_LEN 2
256#define RX_VLANHDR_LEN 2
257#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
258 ETH_HLEN + \
259 ETH_CRC_LEN + \
260 RX_VLANHDR_LEN + \
261 RX_BUF_DMA_ALIGN)
262
263struct rxdesc {
264 union {
265 __u8 all[16];
266 __le32 dw[4];
267 struct {
268
269 __le16 rsv2;
270 __u8 rsv1;
271 __u8 flags;
272
273
274 __le16 datalen;
275 __le16 wbcpl;
276
277
278 __le32 bufaddrh;
279
280
281 __le32 bufaddrl;
282 } desc1;
283 struct {
284
285 __le16 vlan;
286 __le16 flags;
287
288
289 __le16 framesize;
290 __u8 errstat;
291 __u8 desccnt;
292
293
294 __le32 rsshash;
295
296
297 __u8 hashfun;
298 __u8 hashtype;
299 __le16 resrv;
300 } descwb;
301 };
302};
303
304enum jme_rxdesc_flags_bits {
305 RXFLAG_OWN = 0x80,
306 RXFLAG_INT = 0x40,
307 RXFLAG_64BIT = 0x20,
308};
309
310enum jme_rxwbdesc_flags_bits {
311 RXWBFLAG_OWN = 0x8000,
312 RXWBFLAG_INT = 0x4000,
313 RXWBFLAG_MF = 0x2000,
314 RXWBFLAG_64BIT = 0x2000,
315 RXWBFLAG_TCPON = 0x1000,
316 RXWBFLAG_UDPON = 0x0800,
317 RXWBFLAG_IPCS = 0x0400,
318 RXWBFLAG_TCPCS = 0x0200,
319 RXWBFLAG_UDPCS = 0x0100,
320 RXWBFLAG_TAGON = 0x0080,
321 RXWBFLAG_IPV4 = 0x0040,
322 RXWBFLAG_IPV6 = 0x0020,
323 RXWBFLAG_PAUSE = 0x0010,
324 RXWBFLAG_MAGIC = 0x0008,
325 RXWBFLAG_WAKEUP = 0x0004,
326 RXWBFLAG_DEST = 0x0003,
327 RXWBFLAG_DEST_UNI = 0x0001,
328 RXWBFLAG_DEST_MUL = 0x0002,
329 RXWBFLAG_DEST_BRO = 0x0003,
330};
331
332enum jme_rxwbdesc_desccnt_mask {
333 RXWBDCNT_WBCPL = 0x80,
334 RXWBDCNT_DCNT = 0x7F,
335};
336
337enum jme_rxwbdesc_errstat_bits {
338 RXWBERR_LIMIT = 0x80,
339 RXWBERR_MIIER = 0x40,
340 RXWBERR_NIBON = 0x20,
341 RXWBERR_COLON = 0x10,
342 RXWBERR_ABORT = 0x08,
343 RXWBERR_SHORT = 0x04,
344 RXWBERR_OVERUN = 0x02,
345 RXWBERR_CRCERR = 0x01,
346 RXWBERR_ALLERR = 0xFF,
347};
348
349
350
351
352struct jme_buffer_info {
353 struct sk_buff *skb;
354 dma_addr_t mapping;
355 int len;
356 int nr_desc;
357 unsigned long start_xmit;
358};
359
360
361
362
363struct jme_ring {
364 void *alloc;
365 void *desc;
366 dma_addr_t dmaalloc;
367 dma_addr_t dma;
368
369
370 struct jme_buffer_info *bufinf;
371
372 int next_to_use;
373 atomic_t next_to_clean;
374 atomic_t nr_free;
375};
376
377#define NET_STAT(priv) (priv->dev->stats)
378#define NETDEV_GET_STATS(netdev, fun_ptr)
379#define DECLARE_NET_DEVICE_STATS
380
381#define DECLARE_NAPI_STRUCT struct napi_struct napi;
382#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
383 netif_napi_add(dev, napis, pollfn, q);
384#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
385#define JME_NAPI_WEIGHT(w) int w
386#define JME_NAPI_WEIGHT_VAL(w) w
387#define JME_NAPI_WEIGHT_SET(w, r)
388#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
389#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
390#define JME_NAPI_DISABLE(priv) \
391 if (!napi_disable_pending(&priv->napi)) \
392 napi_disable(&priv->napi);
393#define JME_RX_SCHEDULE_PREP(priv) \
394 napi_schedule_prep(&priv->napi)
395#define JME_RX_SCHEDULE(priv) \
396 __napi_schedule(&priv->napi);
397
398
399
400
401struct jme_adapter {
402 struct pci_dev *pdev;
403 struct net_device *dev;
404 void __iomem *regs;
405 struct mii_if_info mii_if;
406 struct jme_ring rxring[RX_RING_NR];
407 struct jme_ring txring[TX_RING_NR];
408 spinlock_t phy_lock;
409 spinlock_t macaddr_lock;
410 spinlock_t rxmcs_lock;
411 struct tasklet_struct rxempty_task;
412 struct tasklet_struct rxclean_task;
413 struct tasklet_struct txclean_task;
414 struct work_struct linkch_task;
415 struct tasklet_struct pcc_task;
416 unsigned long flags;
417 u32 reg_txcs;
418 u32 reg_txpfc;
419 u32 reg_rxcs;
420 u32 reg_rxmcs;
421 u32 reg_ghc;
422 u32 reg_pmcs;
423 u32 reg_gpreg1;
424 u32 phylink;
425 u32 tx_ring_size;
426 u32 tx_ring_mask;
427 u32 tx_wake_threshold;
428 u32 rx_ring_size;
429 u32 rx_ring_mask;
430 u8 mrrs;
431 unsigned int fpgaver;
432 u8 chiprev;
433 u8 chip_main_rev;
434 u8 chip_sub_rev;
435 u8 pcirev;
436 u32 msg_enable;
437 struct ethtool_link_ksettings old_cmd;
438 unsigned int old_mtu;
439 struct dynpcc_info dpi;
440 atomic_t intr_sem;
441 atomic_t link_changing;
442 atomic_t tx_cleaning;
443 atomic_t rx_cleaning;
444 atomic_t rx_empty;
445 int (*jme_rx)(struct sk_buff *skb);
446 DECLARE_NAPI_STRUCT
447 DECLARE_NET_DEVICE_STATS
448};
449
450enum jme_flags_bits {
451 JME_FLAG_MSI = 1,
452 JME_FLAG_SSET = 2,
453 JME_FLAG_POLL = 5,
454 JME_FLAG_SHUTDOWN = 6,
455};
456
457#define TX_TIMEOUT (5 * HZ)
458#define JME_REG_LEN 0x500
459#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
460
461static inline struct jme_adapter*
462jme_napi_priv(struct napi_struct *napi)
463{
464 struct jme_adapter *jme;
465 jme = container_of(napi, struct jme_adapter, napi);
466 return jme;
467}
468
469
470
471
472enum jme_iomap_offsets {
473 JME_MAC = 0x0000,
474 JME_PHY = 0x0400,
475 JME_MISC = 0x0800,
476 JME_RSS = 0x0C00,
477};
478
479enum jme_iomap_lens {
480 JME_MAC_LEN = 0x80,
481 JME_PHY_LEN = 0x58,
482 JME_MISC_LEN = 0x98,
483 JME_RSS_LEN = 0xFF,
484};
485
486enum jme_iomap_regs {
487 JME_TXCS = JME_MAC | 0x00,
488 JME_TXDBA_LO = JME_MAC | 0x04,
489 JME_TXDBA_HI = JME_MAC | 0x08,
490 JME_TXQDC = JME_MAC | 0x0C,
491 JME_TXNDA = JME_MAC | 0x10,
492 JME_TXMCS = JME_MAC | 0x14,
493 JME_TXPFC = JME_MAC | 0x18,
494 JME_TXTRHD = JME_MAC | 0x1C,
495
496 JME_RXCS = JME_MAC | 0x20,
497 JME_RXDBA_LO = JME_MAC | 0x24,
498 JME_RXDBA_HI = JME_MAC | 0x28,
499 JME_RXQDC = JME_MAC | 0x2C,
500 JME_RXNDA = JME_MAC | 0x30,
501 JME_RXMCS = JME_MAC | 0x34,
502 JME_RXUMA_LO = JME_MAC | 0x38,
503 JME_RXUMA_HI = JME_MAC | 0x3C,
504 JME_RXMCHT_LO = JME_MAC | 0x40,
505 JME_RXMCHT_HI = JME_MAC | 0x44,
506 JME_WFODP = JME_MAC | 0x48,
507 JME_WFOI = JME_MAC | 0x4C,
508
509 JME_SMI = JME_MAC | 0x50,
510 JME_GHC = JME_MAC | 0x54,
511 JME_PMCS = JME_MAC | 0x60,
512
513
514 JME_PHY_PWR = JME_PHY | 0x24,
515 JME_PHY_CS = JME_PHY | 0x28,
516 JME_PHY_LINK = JME_PHY | 0x30,
517 JME_SMBCSR = JME_PHY | 0x40,
518 JME_SMBINTF = JME_PHY | 0x44,
519
520
521 JME_TMCSR = JME_MISC | 0x00,
522 JME_GPREG0 = JME_MISC | 0x08,
523 JME_GPREG1 = JME_MISC | 0x0C,
524 JME_IEVE = JME_MISC | 0x20,
525 JME_IREQ = JME_MISC | 0x24,
526 JME_IENS = JME_MISC | 0x28,
527 JME_IENC = JME_MISC | 0x2C,
528 JME_PCCRX0 = JME_MISC | 0x30,
529 JME_PCCTX = JME_MISC | 0x40,
530 JME_CHIPMODE = JME_MISC | 0x44,
531 JME_SHBA_HI = JME_MISC | 0x48,
532 JME_SHBA_LO = JME_MISC | 0x4C,
533 JME_TIMER1 = JME_MISC | 0x70,
534 JME_TIMER2 = JME_MISC | 0x74,
535 JME_APMC = JME_MISC | 0x7C,
536 JME_PCCSRX0 = JME_MISC | 0x80,
537};
538
539
540
541
542enum jme_txcs_bits {
543 TXCS_QUEUE7S = 0x00008000,
544 TXCS_QUEUE6S = 0x00004000,
545 TXCS_QUEUE5S = 0x00002000,
546 TXCS_QUEUE4S = 0x00001000,
547 TXCS_QUEUE3S = 0x00000800,
548 TXCS_QUEUE2S = 0x00000400,
549 TXCS_QUEUE1S = 0x00000200,
550 TXCS_QUEUE0S = 0x00000100,
551 TXCS_FIFOTH = 0x000000C0,
552 TXCS_DMASIZE = 0x00000030,
553 TXCS_BURST = 0x00000004,
554 TXCS_ENABLE = 0x00000001,
555};
556
557enum jme_txcs_value {
558 TXCS_FIFOTH_16QW = 0x000000C0,
559 TXCS_FIFOTH_12QW = 0x00000080,
560 TXCS_FIFOTH_8QW = 0x00000040,
561 TXCS_FIFOTH_4QW = 0x00000000,
562
563 TXCS_DMASIZE_64B = 0x00000000,
564 TXCS_DMASIZE_128B = 0x00000010,
565 TXCS_DMASIZE_256B = 0x00000020,
566 TXCS_DMASIZE_512B = 0x00000030,
567
568 TXCS_SELECT_QUEUE0 = 0x00000000,
569 TXCS_SELECT_QUEUE1 = 0x00010000,
570 TXCS_SELECT_QUEUE2 = 0x00020000,
571 TXCS_SELECT_QUEUE3 = 0x00030000,
572 TXCS_SELECT_QUEUE4 = 0x00040000,
573 TXCS_SELECT_QUEUE5 = 0x00050000,
574 TXCS_SELECT_QUEUE6 = 0x00060000,
575 TXCS_SELECT_QUEUE7 = 0x00070000,
576
577 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
578 TXCS_BURST,
579};
580
581#define JME_TX_DISABLE_TIMEOUT 10
582
583
584
585
586enum jme_txmcs_bit_masks {
587 TXMCS_IFG2 = 0xC0000000,
588 TXMCS_IFG1 = 0x30000000,
589 TXMCS_TTHOLD = 0x00000300,
590 TXMCS_FBURST = 0x00000080,
591 TXMCS_CARRIEREXT = 0x00000040,
592 TXMCS_DEFER = 0x00000020,
593 TXMCS_BACKOFF = 0x00000010,
594 TXMCS_CARRIERSENSE = 0x00000008,
595 TXMCS_COLLISION = 0x00000004,
596 TXMCS_CRC = 0x00000002,
597 TXMCS_PADDING = 0x00000001,
598};
599
600enum jme_txmcs_values {
601 TXMCS_IFG2_6_4 = 0x00000000,
602 TXMCS_IFG2_8_5 = 0x40000000,
603 TXMCS_IFG2_10_6 = 0x80000000,
604 TXMCS_IFG2_12_7 = 0xC0000000,
605
606 TXMCS_IFG1_8_4 = 0x00000000,
607 TXMCS_IFG1_12_6 = 0x10000000,
608 TXMCS_IFG1_16_8 = 0x20000000,
609 TXMCS_IFG1_20_10 = 0x30000000,
610
611 TXMCS_TTHOLD_1_8 = 0x00000000,
612 TXMCS_TTHOLD_1_4 = 0x00000100,
613 TXMCS_TTHOLD_1_2 = 0x00000200,
614 TXMCS_TTHOLD_FULL = 0x00000300,
615
616 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
617 TXMCS_IFG1_16_8 |
618 TXMCS_TTHOLD_FULL |
619 TXMCS_DEFER |
620 TXMCS_CRC |
621 TXMCS_PADDING,
622};
623
624enum jme_txpfc_bits_masks {
625 TXPFC_VLAN_TAG = 0xFFFF0000,
626 TXPFC_VLAN_EN = 0x00008000,
627 TXPFC_PF_EN = 0x00000001,
628};
629
630enum jme_txtrhd_bits_masks {
631 TXTRHD_TXPEN = 0x80000000,
632 TXTRHD_TXP = 0x7FFFFF00,
633 TXTRHD_TXREN = 0x00000080,
634 TXTRHD_TXRL = 0x0000007F,
635};
636
637enum jme_txtrhd_shifts {
638 TXTRHD_TXP_SHIFT = 8,
639 TXTRHD_TXRL_SHIFT = 0,
640};
641
642enum jme_txtrhd_values {
643 TXTRHD_FULLDUPLEX = 0x00000000,
644 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
645 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
646 TXTRHD_TXREN |
647 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
648};
649
650
651
652
653enum jme_rxcs_bit_masks {
654
655 RXCS_FIFOTHTP = 0x30000000,
656
657 RXCS_FIFOTHNP = 0x0C000000,
658 RXCS_DMAREQSZ = 0x03000000,
659 RXCS_QUEUESEL = 0x00030000,
660 RXCS_RETRYGAP = 0x0000F000,
661 RXCS_RETRYCNT = 0x00000F00,
662 RXCS_WAKEUP = 0x00000040,
663 RXCS_MAGIC = 0x00000020,
664 RXCS_SHORT = 0x00000010,
665 RXCS_ABORT = 0x00000008,
666 RXCS_QST = 0x00000004,
667 RXCS_SUSPEND = 0x00000002,
668 RXCS_ENABLE = 0x00000001,
669};
670
671enum jme_rxcs_values {
672 RXCS_FIFOTHTP_16T = 0x00000000,
673 RXCS_FIFOTHTP_32T = 0x10000000,
674 RXCS_FIFOTHTP_64T = 0x20000000,
675 RXCS_FIFOTHTP_128T = 0x30000000,
676
677 RXCS_FIFOTHNP_16QW = 0x00000000,
678 RXCS_FIFOTHNP_32QW = 0x04000000,
679 RXCS_FIFOTHNP_64QW = 0x08000000,
680 RXCS_FIFOTHNP_128QW = 0x0C000000,
681
682 RXCS_DMAREQSZ_16B = 0x00000000,
683 RXCS_DMAREQSZ_32B = 0x01000000,
684 RXCS_DMAREQSZ_64B = 0x02000000,
685 RXCS_DMAREQSZ_128B = 0x03000000,
686
687 RXCS_QUEUESEL_Q0 = 0x00000000,
688 RXCS_QUEUESEL_Q1 = 0x00010000,
689 RXCS_QUEUESEL_Q2 = 0x00020000,
690 RXCS_QUEUESEL_Q3 = 0x00030000,
691
692 RXCS_RETRYGAP_256ns = 0x00000000,
693 RXCS_RETRYGAP_512ns = 0x00001000,
694 RXCS_RETRYGAP_1024ns = 0x00002000,
695 RXCS_RETRYGAP_2048ns = 0x00003000,
696 RXCS_RETRYGAP_4096ns = 0x00004000,
697 RXCS_RETRYGAP_8192ns = 0x00005000,
698 RXCS_RETRYGAP_16384ns = 0x00006000,
699 RXCS_RETRYGAP_32768ns = 0x00007000,
700
701 RXCS_RETRYCNT_0 = 0x00000000,
702 RXCS_RETRYCNT_4 = 0x00000100,
703 RXCS_RETRYCNT_8 = 0x00000200,
704 RXCS_RETRYCNT_12 = 0x00000300,
705 RXCS_RETRYCNT_16 = 0x00000400,
706 RXCS_RETRYCNT_20 = 0x00000500,
707 RXCS_RETRYCNT_24 = 0x00000600,
708 RXCS_RETRYCNT_28 = 0x00000700,
709 RXCS_RETRYCNT_32 = 0x00000800,
710 RXCS_RETRYCNT_36 = 0x00000900,
711 RXCS_RETRYCNT_40 = 0x00000A00,
712 RXCS_RETRYCNT_44 = 0x00000B00,
713 RXCS_RETRYCNT_48 = 0x00000C00,
714 RXCS_RETRYCNT_52 = 0x00000D00,
715 RXCS_RETRYCNT_56 = 0x00000E00,
716 RXCS_RETRYCNT_60 = 0x00000F00,
717
718 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
719 RXCS_FIFOTHNP_16QW |
720 RXCS_DMAREQSZ_128B |
721 RXCS_RETRYGAP_256ns |
722 RXCS_RETRYCNT_32,
723};
724
725#define JME_RX_DISABLE_TIMEOUT 10
726
727
728
729
730enum jme_rxmcs_bits {
731 RXMCS_ALLFRAME = 0x00000800,
732 RXMCS_BRDFRAME = 0x00000400,
733 RXMCS_MULFRAME = 0x00000200,
734 RXMCS_UNIFRAME = 0x00000100,
735 RXMCS_ALLMULFRAME = 0x00000080,
736 RXMCS_MULFILTERED = 0x00000040,
737 RXMCS_RXCOLLDEC = 0x00000020,
738 RXMCS_FLOWCTRL = 0x00000008,
739 RXMCS_VTAGRM = 0x00000004,
740 RXMCS_PREPAD = 0x00000002,
741 RXMCS_CHECKSUM = 0x00000001,
742
743 RXMCS_DEFAULT = RXMCS_VTAGRM |
744 RXMCS_PREPAD |
745 RXMCS_FLOWCTRL |
746 RXMCS_CHECKSUM,
747};
748
749
750
751#define PHY_GAD_TEST_MODE_1 0x00002000
752#define PHY_GAD_TEST_MODE_MSK 0x0000E000
753#define JM_PHY_SPEC_REG_READ 0x00004000
754#define JM_PHY_SPEC_REG_WRITE 0x00008000
755#define PHY_CALIBRATION_DELAY 20
756#define JM_PHY_SPEC_ADDR_REG 0x1E
757#define JM_PHY_SPEC_DATA_REG 0x1F
758
759#define JM_PHY_EXT_COMM_0_REG 0x30
760#define JM_PHY_EXT_COMM_1_REG 0x31
761#define JM_PHY_EXT_COMM_2_REG 0x32
762#define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
763#define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
764#define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
765#define PCI_PRIV_SHARE_NICCTRL 0xF5
766#define JME_FLAG_PHYEA_ENABLE 0x2
767
768
769
770
771#define WAKEUP_FRAME_NR 8
772#define WAKEUP_FRAME_MASK_DWNR 4
773
774enum jme_wfoi_bit_masks {
775 WFOI_MASK_SEL = 0x00000070,
776 WFOI_CRC_SEL = 0x00000008,
777 WFOI_FRAME_SEL = 0x00000007,
778};
779
780enum jme_wfoi_shifts {
781 WFOI_MASK_SHIFT = 4,
782};
783
784
785
786
787enum jme_smi_bit_mask {
788 SMI_DATA_MASK = 0xFFFF0000,
789 SMI_REG_ADDR_MASK = 0x0000F800,
790 SMI_PHY_ADDR_MASK = 0x000007C0,
791 SMI_OP_WRITE = 0x00000020,
792
793 SMI_OP_REQ = 0x00000010,
794 SMI_OP_MDIO = 0x00000008,
795 SMI_OP_MDOE = 0x00000004,
796 SMI_OP_MDC = 0x00000002,
797 SMI_OP_MDEN = 0x00000001,
798};
799
800enum jme_smi_bit_shift {
801 SMI_DATA_SHIFT = 16,
802 SMI_REG_ADDR_SHIFT = 11,
803 SMI_PHY_ADDR_SHIFT = 6,
804};
805
806static inline u32 smi_reg_addr(int x)
807{
808 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
809}
810
811static inline u32 smi_phy_addr(int x)
812{
813 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
814}
815
816#define JME_PHY_TIMEOUT 100
817#define JME_PHY_REG_NR 32
818
819
820
821
822enum jme_ghc_bit_mask {
823 GHC_SWRST = 0x40000000,
824 GHC_TO_CLK_SRC = 0x00C00000,
825 GHC_TXMAC_CLK_SRC = 0x00300000,
826 GHC_DPX = 0x00000040,
827 GHC_SPEED = 0x00000030,
828 GHC_LINK_POLL = 0x00000001,
829};
830
831enum jme_ghc_speed_val {
832 GHC_SPEED_10M = 0x00000010,
833 GHC_SPEED_100M = 0x00000020,
834 GHC_SPEED_1000M = 0x00000030,
835};
836
837enum jme_ghc_to_clk {
838 GHC_TO_CLK_OFF = 0x00000000,
839 GHC_TO_CLK_GPHY = 0x00400000,
840 GHC_TO_CLK_PCIE = 0x00800000,
841 GHC_TO_CLK_INVALID = 0x00C00000,
842};
843
844enum jme_ghc_txmac_clk {
845 GHC_TXMAC_CLK_OFF = 0x00000000,
846 GHC_TXMAC_CLK_GPHY = 0x00100000,
847 GHC_TXMAC_CLK_PCIE = 0x00200000,
848 GHC_TXMAC_CLK_INVALID = 0x00300000,
849};
850
851
852
853
854enum jme_pmcs_bit_masks {
855 PMCS_STMASK = 0xFFFF0000,
856 PMCS_WF7DET = 0x80000000,
857 PMCS_WF6DET = 0x40000000,
858 PMCS_WF5DET = 0x20000000,
859 PMCS_WF4DET = 0x10000000,
860 PMCS_WF3DET = 0x08000000,
861 PMCS_WF2DET = 0x04000000,
862 PMCS_WF1DET = 0x02000000,
863 PMCS_WF0DET = 0x01000000,
864 PMCS_LFDET = 0x00040000,
865 PMCS_LRDET = 0x00020000,
866 PMCS_MFDET = 0x00010000,
867 PMCS_ENMASK = 0x0000FFFF,
868 PMCS_WF7EN = 0x00008000,
869 PMCS_WF6EN = 0x00004000,
870 PMCS_WF5EN = 0x00002000,
871 PMCS_WF4EN = 0x00001000,
872 PMCS_WF3EN = 0x00000800,
873 PMCS_WF2EN = 0x00000400,
874 PMCS_WF1EN = 0x00000200,
875 PMCS_WF0EN = 0x00000100,
876 PMCS_LFEN = 0x00000004,
877 PMCS_LREN = 0x00000002,
878 PMCS_MFEN = 0x00000001,
879};
880
881
882
883
884enum jme_phy_pwr_bit_masks {
885 PHY_PWR_DWN1SEL = 0x01000000,
886 PHY_PWR_DWN1SW = 0x02000000,
887 PHY_PWR_DWN2 = 0x04000000,
888 PHY_PWR_CLKSEL = 0x08000000,
889
890
891
892
893
894};
895
896
897
898
899enum jme_phy_link_bit_mask {
900 PHY_LINK_SPEED_MASK = 0x0000C000,
901 PHY_LINK_DUPLEX = 0x00002000,
902 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
903 PHY_LINK_UP = 0x00000400,
904 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
905 PHY_LINK_MDI_STAT = 0x00000040,
906};
907
908enum jme_phy_link_speed_val {
909 PHY_LINK_SPEED_10M = 0x00000000,
910 PHY_LINK_SPEED_100M = 0x00004000,
911 PHY_LINK_SPEED_1000M = 0x00008000,
912};
913
914#define JME_SPDRSV_TIMEOUT 500
915
916
917
918
919enum jme_smbcsr_bit_mask {
920 SMBCSR_CNACK = 0x00020000,
921 SMBCSR_RELOAD = 0x00010000,
922 SMBCSR_EEPROMD = 0x00000020,
923 SMBCSR_INITDONE = 0x00000010,
924 SMBCSR_BUSY = 0x0000000F,
925};
926
927enum jme_smbintf_bit_mask {
928 SMBINTF_HWDATR = 0xFF000000,
929 SMBINTF_HWDATW = 0x00FF0000,
930 SMBINTF_HWADDR = 0x0000FF00,
931 SMBINTF_HWRWN = 0x00000020,
932 SMBINTF_HWCMD = 0x00000010,
933 SMBINTF_FASTM = 0x00000008,
934 SMBINTF_GPIOSCL = 0x00000004,
935 SMBINTF_GPIOSDA = 0x00000002,
936 SMBINTF_GPIOEN = 0x00000001,
937};
938
939enum jme_smbintf_vals {
940 SMBINTF_HWRWN_READ = 0x00000020,
941 SMBINTF_HWRWN_WRITE = 0x00000000,
942};
943
944enum jme_smbintf_shifts {
945 SMBINTF_HWDATR_SHIFT = 24,
946 SMBINTF_HWDATW_SHIFT = 16,
947 SMBINTF_HWADDR_SHIFT = 8,
948};
949
950#define JME_EEPROM_RELOAD_TIMEOUT 2000
951#define JME_SMB_BUSY_TIMEOUT 20
952#define JME_SMB_LEN 256
953#define JME_EEPROM_MAGIC 0x250
954
955
956
957
958enum jme_tmcsr_bit_masks {
959 TMCSR_SWIT = 0x80000000,
960 TMCSR_EN = 0x01000000,
961 TMCSR_CNT = 0x00FFFFFF,
962};
963
964
965
966
967enum jme_gpreg0_masks {
968 GPREG0_DISSH = 0xFF000000,
969 GPREG0_PCIRLMT = 0x00300000,
970 GPREG0_PCCNOMUTCLR = 0x00040000,
971 GPREG0_LNKINTPOLL = 0x00001000,
972 GPREG0_PCCTMR = 0x00000300,
973 GPREG0_PHYADDR = 0x0000001F,
974};
975
976enum jme_gpreg0_vals {
977 GPREG0_DISSH_DW7 = 0x80000000,
978 GPREG0_DISSH_DW6 = 0x40000000,
979 GPREG0_DISSH_DW5 = 0x20000000,
980 GPREG0_DISSH_DW4 = 0x10000000,
981 GPREG0_DISSH_DW3 = 0x08000000,
982 GPREG0_DISSH_DW2 = 0x04000000,
983 GPREG0_DISSH_DW1 = 0x02000000,
984 GPREG0_DISSH_DW0 = 0x01000000,
985 GPREG0_DISSH_ALL = 0xFF000000,
986
987 GPREG0_PCIRLMT_8 = 0x00000000,
988 GPREG0_PCIRLMT_6 = 0x00100000,
989 GPREG0_PCIRLMT_5 = 0x00200000,
990 GPREG0_PCIRLMT_4 = 0x00300000,
991
992 GPREG0_PCCTMR_16ns = 0x00000000,
993 GPREG0_PCCTMR_256ns = 0x00000100,
994 GPREG0_PCCTMR_1us = 0x00000200,
995 GPREG0_PCCTMR_1ms = 0x00000300,
996
997 GPREG0_PHYADDR_1 = 0x00000001,
998
999 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1000 GPREG0_PCCTMR_1us |
1001 GPREG0_PHYADDR_1,
1002};
1003
1004
1005
1006
1007enum jme_gpreg1_bit_masks {
1008 GPREG1_RXCLKOFF = 0x04000000,
1009 GPREG1_PCREQN = 0x00020000,
1010 GPREG1_HALFMODEPATCH = 0x00000040,
1011 GPREG1_RSSPATCH = 0x00000020,
1012 GPREG1_INTRDELAYUNIT = 0x00000018,
1013 GPREG1_INTRDELAYENABLE = 0x00000007,
1014};
1015
1016enum jme_gpreg1_vals {
1017 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1018 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1019 GPREG1_INTDLYUNIT_1US = 0x00000010,
1020 GPREG1_INTDLYUNIT_16US = 0x00000018,
1021
1022 GPREG1_INTDLYEN_1U = 0x00000001,
1023 GPREG1_INTDLYEN_2U = 0x00000002,
1024 GPREG1_INTDLYEN_3U = 0x00000003,
1025 GPREG1_INTDLYEN_4U = 0x00000004,
1026 GPREG1_INTDLYEN_5U = 0x00000005,
1027 GPREG1_INTDLYEN_6U = 0x00000006,
1028 GPREG1_INTDLYEN_7U = 0x00000007,
1029
1030 GPREG1_DEFAULT = GPREG1_PCREQN,
1031};
1032
1033
1034
1035
1036enum jme_interrupt_bits {
1037 INTR_SWINTR = 0x80000000,
1038 INTR_TMINTR = 0x40000000,
1039 INTR_LINKCH = 0x20000000,
1040 INTR_PAUSERCV = 0x10000000,
1041 INTR_MAGICRCV = 0x08000000,
1042 INTR_WAKERCV = 0x04000000,
1043 INTR_PCCRX0TO = 0x02000000,
1044 INTR_PCCRX1TO = 0x01000000,
1045 INTR_PCCRX2TO = 0x00800000,
1046 INTR_PCCRX3TO = 0x00400000,
1047 INTR_PCCTXTO = 0x00200000,
1048 INTR_PCCRX0 = 0x00100000,
1049 INTR_PCCRX1 = 0x00080000,
1050 INTR_PCCRX2 = 0x00040000,
1051 INTR_PCCRX3 = 0x00020000,
1052 INTR_PCCTX = 0x00010000,
1053 INTR_RX3EMP = 0x00008000,
1054 INTR_RX2EMP = 0x00004000,
1055 INTR_RX1EMP = 0x00002000,
1056 INTR_RX0EMP = 0x00001000,
1057 INTR_RX3 = 0x00000800,
1058 INTR_RX2 = 0x00000400,
1059 INTR_RX1 = 0x00000200,
1060 INTR_RX0 = 0x00000100,
1061 INTR_TX7 = 0x00000080,
1062 INTR_TX6 = 0x00000040,
1063 INTR_TX5 = 0x00000020,
1064 INTR_TX4 = 0x00000010,
1065 INTR_TX3 = 0x00000008,
1066 INTR_TX2 = 0x00000004,
1067 INTR_TX1 = 0x00000002,
1068 INTR_TX0 = 0x00000001,
1069};
1070
1071static const u32 INTR_ENABLE = INTR_SWINTR |
1072 INTR_TMINTR |
1073 INTR_LINKCH |
1074 INTR_PCCRX0TO |
1075 INTR_PCCRX0 |
1076 INTR_PCCTXTO |
1077 INTR_PCCTX |
1078 INTR_RX0EMP;
1079
1080
1081
1082
1083enum jme_pccrx_masks {
1084 PCCRXTO_MASK = 0xFFFF0000,
1085 PCCRX_MASK = 0x0000FF00,
1086};
1087
1088enum jme_pcctx_masks {
1089 PCCTXTO_MASK = 0xFFFF0000,
1090 PCCTX_MASK = 0x0000FF00,
1091 PCCTX_QS_MASK = 0x000000FF,
1092};
1093
1094enum jme_pccrx_shifts {
1095 PCCRXTO_SHIFT = 16,
1096 PCCRX_SHIFT = 8,
1097};
1098
1099enum jme_pcctx_shifts {
1100 PCCTXTO_SHIFT = 16,
1101 PCCTX_SHIFT = 8,
1102};
1103
1104enum jme_pcctx_bits {
1105 PCCTXQ0_EN = 0x00000001,
1106 PCCTXQ1_EN = 0x00000002,
1107 PCCTXQ2_EN = 0x00000004,
1108 PCCTXQ3_EN = 0x00000008,
1109 PCCTXQ4_EN = 0x00000010,
1110 PCCTXQ5_EN = 0x00000020,
1111 PCCTXQ6_EN = 0x00000040,
1112 PCCTXQ7_EN = 0x00000080,
1113};
1114
1115
1116
1117
1118enum jme_chipmode_bit_masks {
1119 CM_FPGAVER_MASK = 0xFFFF0000,
1120 CM_CHIPREV_MASK = 0x0000FF00,
1121 CM_CHIPMODE_MASK = 0x0000000F,
1122};
1123
1124enum jme_chipmode_shifts {
1125 CM_FPGAVER_SHIFT = 16,
1126 CM_CHIPREV_SHIFT = 8,
1127};
1128
1129
1130
1131
1132enum jme_apmc_bits {
1133 JME_APMC_PCIE_SD_EN = 0x40000000,
1134 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1135 JME_APMC_EPIEN = 0x04000000,
1136 JME_APMC_EPIEN_CTRL = 0x03000000,
1137};
1138
1139enum jme_apmc_values {
1140 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1141 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1142};
1143
1144#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1145
1146#ifdef REG_DEBUG
1147static char *MAC_REG_NAME[] = {
1148 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1149 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1150 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1151 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1152 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1153 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1154 "JME_PMCS"};
1155
1156static char *PE_REG_NAME[] = {
1157 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1158 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1159 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1160 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1161 "JME_SMBCSR", "JME_SMBINTF"};
1162
1163static char *MISC_REG_NAME[] = {
1164 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1165 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1166 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1167 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1168 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1169 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1170 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1171 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1172 "JME_PCCSRX0"};
1173
1174static inline void reg_dbg(const struct jme_adapter *jme,
1175 const char *msg, u32 val, u32 reg)
1176{
1177 const char *regname;
1178 switch (reg & 0xF00) {
1179 case 0x000:
1180 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1181 break;
1182 case 0x400:
1183 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1184 break;
1185 case 0x800:
1186 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1187 break;
1188 default:
1189 regname = PE_REG_NAME[0];
1190 }
1191 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1192 msg, val, regname);
1193}
1194#else
1195static inline void reg_dbg(const struct jme_adapter *jme,
1196 const char *msg, u32 val, u32 reg) {}
1197#endif
1198
1199
1200
1201
1202static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1203{
1204 return readl(jme->regs + reg);
1205}
1206
1207static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1208{
1209 reg_dbg(jme, "REG WRITE", val, reg);
1210 writel(val, jme->regs + reg);
1211 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1212}
1213
1214static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1215{
1216
1217
1218
1219 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1220 writel(val, jme->regs + reg);
1221 readl(jme->regs + reg);
1222 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1223}
1224
1225
1226
1227
1228enum jme_phy_reg17_bit_masks {
1229 PREG17_SPEED = 0xC000,
1230 PREG17_DUPLEX = 0x2000,
1231 PREG17_SPDRSV = 0x0800,
1232 PREG17_LNKUP = 0x0400,
1233 PREG17_MDI = 0x0040,
1234};
1235
1236enum jme_phy_reg17_vals {
1237 PREG17_SPEED_10M = 0x0000,
1238 PREG17_SPEED_100M = 0x4000,
1239 PREG17_SPEED_1000M = 0x8000,
1240};
1241
1242#define BMSR_ANCOMP 0x0020
1243
1244
1245
1246
1247static inline int is_buggy250(unsigned short device, u8 chiprev)
1248{
1249 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1250}
1251
1252static inline int new_phy_power_ctrl(u8 chip_main_rev)
1253{
1254 return chip_main_rev >= 5;
1255}
1256
1257
1258
1259
1260static int jme_set_link_ksettings(struct net_device *netdev,
1261 const struct ethtool_link_ksettings *cmd);
1262static void jme_set_unicastaddr(struct net_device *netdev);
1263static void jme_set_multi(struct net_device *netdev);
1264
1265#endif
1266
