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8#ifndef CGX_H
9#define CGX_H
10
11#include "mbox.h"
12#include "cgx_fw_if.h"
13#include "rpm.h"
14
15
16#define PCI_DEVID_OCTEONTX2_CGX 0xA059
17
18
19#define PCI_CFG_REG_BAR_NUM 0
20
21#define CGX_ID_MASK 0x7
22#define MAX_LMAC_PER_CGX 4
23#define MAX_DMAC_ENTRIES_PER_CGX 32
24#define CGX_FIFO_LEN 65536
25#define CGX_OFFSET(x) ((x) * MAX_LMAC_PER_CGX)
26
27
28#define CGXX_CMRX_CFG 0x00
29#define CMR_P2X_SEL_MASK GENMASK_ULL(61, 59)
30#define CMR_P2X_SEL_SHIFT 59ULL
31#define CMR_P2X_SEL_NIX0 1ULL
32#define CMR_P2X_SEL_NIX1 2ULL
33#define CMR_EN BIT_ULL(55)
34#define DATA_PKT_TX_EN BIT_ULL(53)
35#define DATA_PKT_RX_EN BIT_ULL(54)
36#define CGX_LMAC_TYPE_SHIFT 40
37#define CGX_LMAC_TYPE_MASK 0xF
38#define CGXX_CMRX_INT 0x040
39#define FW_CGX_INT BIT_ULL(1)
40#define CGXX_CMRX_INT_ENA_W1S 0x058
41#define CGXX_CMRX_RX_ID_MAP 0x060
42#define CGXX_CMRX_RX_STAT0 0x070
43#define CGXX_CMRX_RX_LMACS 0x128
44#define CGXX_CMRX_RX_DMAC_CTL0 (0x1F8 + mac_ops->csr_offset)
45#define CGX_DMAC_CTL0_CAM_ENABLE BIT_ULL(3)
46#define CGX_DMAC_CAM_ACCEPT BIT_ULL(3)
47#define CGX_DMAC_MCAST_MODE_CAM BIT_ULL(2)
48#define CGX_DMAC_MCAST_MODE BIT_ULL(1)
49#define CGX_DMAC_BCAST_MODE BIT_ULL(0)
50#define CGXX_CMRX_RX_DMAC_CAM0 (0x200 + mac_ops->csr_offset)
51#define CGX_DMAC_CAM_ADDR_ENABLE BIT_ULL(48)
52#define CGX_DMAC_CAM_ENTRY_LMACID GENMASK_ULL(50, 49)
53#define CGXX_CMRX_RX_DMAC_CAM1 0x400
54#define CGX_RX_DMAC_ADR_MASK GENMASK_ULL(47, 0)
55#define CGXX_CMRX_TX_STAT0 0x700
56#define CGXX_SCRATCH0_REG 0x1050
57#define CGXX_SCRATCH1_REG 0x1058
58#define CGX_CONST 0x2000
59#define CGX_CONST_RXFIFO_SIZE GENMASK_ULL(23, 0)
60#define CGXX_SPUX_CONTROL1 0x10000
61#define CGXX_SPUX_LNX_FEC_CORR_BLOCKS 0x10700
62#define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS 0x10800
63#define CGXX_SPUX_RSFEC_CORR 0x10088
64#define CGXX_SPUX_RSFEC_UNCORR 0x10090
65
66#define CGXX_SPUX_CONTROL1_LBK BIT_ULL(14)
67#define CGXX_GMP_PCS_MRX_CTL 0x30000
68#define CGXX_GMP_PCS_MRX_CTL_LBK BIT_ULL(14)
69
70#define CGXX_SMUX_RX_FRM_CTL 0x20020
71#define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)
72#define CGX_SMUX_RX_FRM_CTL_PTP_MODE BIT_ULL(12)
73#define CGXX_GMP_GMI_RXX_FRM_CTL 0x38028
74#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)
75#define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
76#define CGXX_SMUX_TX_CTL 0x20178
77#define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110
78#define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120
79#define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME 0x38230
80#define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL 0x38248
81#define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)
82#define CGXX_CMR_RX_OVR_BP 0x130
83#define CGX_CMR_RX_OVR_BP_EN(X) BIT_ULL(((X) + 8))
84#define CGX_CMR_RX_OVR_BP_BP(X) BIT_ULL(((X) + 4))
85
86#define CGX_COMMAND_REG CGXX_SCRATCH1_REG
87#define CGX_EVENT_REG CGXX_SCRATCH0_REG
88#define CGX_CMD_TIMEOUT 2200
89#define DEFAULT_PAUSE_TIME 0x7FF
90
91#define CGX_LMAC_FWI 0
92
93enum cgx_nix_stat_type {
94 NIX_STATS_RX,
95 NIX_STATS_TX,
96};
97
98enum LMAC_TYPE {
99 LMAC_MODE_SGMII = 0,
100 LMAC_MODE_XAUI = 1,
101 LMAC_MODE_RXAUI = 2,
102 LMAC_MODE_10G_R = 3,
103 LMAC_MODE_40G_R = 4,
104 LMAC_MODE_QSGMII = 6,
105 LMAC_MODE_25G_R = 7,
106 LMAC_MODE_50G_R = 8,
107 LMAC_MODE_100G_R = 9,
108 LMAC_MODE_USXGMII = 10,
109 LMAC_MODE_MAX,
110};
111
112struct cgx_link_event {
113 struct cgx_link_user_info link_uinfo;
114 u8 cgx_id;
115 u8 lmac_id;
116};
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122
123struct cgx_event_cb {
124 int (*notify_link_chg)(struct cgx_link_event *event, void *data);
125 void *data;
126};
127
128extern struct pci_driver cgx_driver;
129
130int cgx_get_cgxcnt_max(void);
131int cgx_get_cgxid(void *cgxd);
132int cgx_get_lmac_cnt(void *cgxd);
133void *cgx_get_pdata(int cgx_id);
134int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
135int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
136int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
137int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
138int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
139int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
140int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
141int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
142int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);
143u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
144int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
145int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);
146int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);
147void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
148void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
149int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
150int cgx_get_link_info(void *cgxd, int lmac_id,
151 struct cgx_link_user_info *linfo);
152int cgx_lmac_linkup_start(void *cgxd);
153int cgx_get_fwdata_base(u64 *base);
154int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
155 u8 *tx_pause, u8 *rx_pause);
156int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
157 u8 tx_pause, u8 rx_pause);
158void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
159u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
160int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
161int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
162int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
163int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
164 int cgx_id, int lmac_id);
165u64 cgx_features_get(void *cgxd);
166struct mac_ops *get_mac_ops(void *cgxd);
167int cgx_get_nr_lmacs(void *cgxd);
168u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);
169unsigned long cgx_get_lmac_bmap(void *cgxd);
170void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);
171u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);
172int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);
173u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);
174u64 cgx_read_dmac_entry(void *cgxd, int index);
175#endif
176
