LXR linux/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Marvell OcteonTx2 CGX driver
   3 *
   4 * Copyright (C) 2018 Marvell.
   5 *
   6 */
   7
   8#ifndef __CGX_FW_INTF_H__
   9#define __CGX_FW_INTF_H__
  10
  11#include <linux/bitops.h>
  12#include <linux/bitfield.h>
  13
  14#define CGX_FIRMWARE_MAJOR_VER          1
  15#define CGX_FIRMWARE_MINOR_VER          0
  16
  17#define CGX_EVENT_ACK                   1UL
  18
  19/* CGX error types. set for cmd response status as CGX_STAT_FAIL */
  20enum cgx_error_type {
  21        CGX_ERR_NONE,
  22        CGX_ERR_LMAC_NOT_ENABLED,
  23        CGX_ERR_LMAC_MODE_INVALID,
  24        CGX_ERR_REQUEST_ID_INVALID,
  25        CGX_ERR_PREV_ACK_NOT_CLEAR,
  26        CGX_ERR_PHY_LINK_DOWN,
  27        CGX_ERR_PCS_RESET_FAIL,
  28        CGX_ERR_AN_CPT_FAIL,
  29        CGX_ERR_TX_NOT_IDLE,
  30        CGX_ERR_RX_NOT_IDLE,
  31        CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
  32        CGX_ERR_SPUX_RX_ALIGN_FAIL,
  33        CGX_ERR_SPUX_TX_FAULT,
  34        CGX_ERR_SPUX_RX_FAULT,
  35        CGX_ERR_SPUX_RESET_FAIL,
  36        CGX_ERR_SPUX_AN_RESET_FAIL,
  37        CGX_ERR_SPUX_USX_AN_RESET_FAIL,
  38        CGX_ERR_SMUX_RX_LINK_NOT_OK,
  39        CGX_ERR_PCS_RECV_LINK_FAIL,
  40        CGX_ERR_TRAINING_FAIL,
  41        CGX_ERR_RX_EQU_FAIL,
  42        CGX_ERR_SPUX_BER_FAIL,
  43        CGX_ERR_SPUX_RSFEC_ALGN_FAIL,
  44        CGX_ERR_SPUX_MARKER_LOCK_FAIL,
  45        CGX_ERR_SET_FEC_INVALID,
  46        CGX_ERR_SET_FEC_FAIL,
  47        CGX_ERR_MODULE_INVALID,
  48        CGX_ERR_MODULE_NOT_PRESENT,
  49        CGX_ERR_SPEED_CHANGE_INVALID,
  50};
  51
  52/* LINK speed types */
  53enum cgx_link_speed {
  54        CGX_LINK_NONE,
  55        CGX_LINK_10M,
  56        CGX_LINK_100M,
  57        CGX_LINK_1G,
  58        CGX_LINK_2HG,
  59        CGX_LINK_5G,
  60        CGX_LINK_10G,
  61        CGX_LINK_20G,
  62        CGX_LINK_25G,
  63        CGX_LINK_40G,
  64        CGX_LINK_50G,
  65        CGX_LINK_80G,
  66        CGX_LINK_100G,
  67        CGX_LINK_SPEED_MAX,
  68};
  69
  70enum CGX_MODE_ {
  71        CGX_MODE_SGMII,
  72        CGX_MODE_1000_BASEX,
  73        CGX_MODE_QSGMII,
  74        CGX_MODE_10G_C2C,
  75        CGX_MODE_10G_C2M,
  76        CGX_MODE_10G_KR,
  77        CGX_MODE_20G_C2C,
  78        CGX_MODE_25G_C2C,
  79        CGX_MODE_25G_C2M,
  80        CGX_MODE_25G_2_C2C,
  81        CGX_MODE_25G_CR,
  82        CGX_MODE_25G_KR,
  83        CGX_MODE_40G_C2C,
  84        CGX_MODE_40G_C2M,
  85        CGX_MODE_40G_CR4,
  86        CGX_MODE_40G_KR4,
  87        CGX_MODE_40GAUI_C2C,
  88        CGX_MODE_50G_C2C,
  89        CGX_MODE_50G_C2M,
  90        CGX_MODE_50G_4_C2C,
  91        CGX_MODE_50G_CR,
  92        CGX_MODE_50G_KR,
  93        CGX_MODE_80GAUI_C2C,
  94        CGX_MODE_100G_C2C,
  95        CGX_MODE_100G_C2M,
  96        CGX_MODE_100G_CR4,
  97        CGX_MODE_100G_KR4,
  98        CGX_MODE_MAX /* = 29 */
  99};
 100/* REQUEST ID types. Input to firmware */
 101enum cgx_cmd_id {
 102        CGX_CMD_NONE,
 103        CGX_CMD_GET_FW_VER,
 104        CGX_CMD_GET_MAC_ADDR,
 105        CGX_CMD_SET_MTU,
 106        CGX_CMD_GET_LINK_STS,           /* optional to user */
 107        CGX_CMD_LINK_BRING_UP,
 108        CGX_CMD_LINK_BRING_DOWN,
 109        CGX_CMD_INTERNAL_LBK,
 110        CGX_CMD_EXTERNAL_LBK,
 111        CGX_CMD_HIGIG,
 112        CGX_CMD_LINK_STAT_CHANGE,
 113        CGX_CMD_MODE_CHANGE,            /* hot plug support */
 114        CGX_CMD_INTF_SHUTDOWN,
 115        CGX_CMD_GET_MKEX_PRFL_SIZE,
 116        CGX_CMD_GET_MKEX_PRFL_ADDR,
 117        CGX_CMD_GET_FWD_BASE,           /* get base address of shared FW data */
 118        CGX_CMD_GET_LINK_MODES,         /* Supported Link Modes */
 119        CGX_CMD_SET_LINK_MODE,
 120        CGX_CMD_GET_SUPPORTED_FEC,
 121        CGX_CMD_SET_FEC,
 122        CGX_CMD_GET_AN,
 123        CGX_CMD_SET_AN,
 124        CGX_CMD_GET_ADV_LINK_MODES,
 125        CGX_CMD_GET_ADV_FEC,
 126        CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */
 127        CGX_CMD_SET_PHY_MOD_TYPE,
 128        CGX_CMD_PRBS,
 129        CGX_CMD_DISPLAY_EYE,
 130        CGX_CMD_GET_PHY_FEC_STATS,
 131};
 132
 133/* async event ids */
 134enum cgx_evt_id {
 135        CGX_EVT_NONE,
 136        CGX_EVT_LINK_CHANGE,
 137};
 138
 139/* event types - cause of interrupt */
 140enum cgx_evt_type {
 141        CGX_EVT_ASYNC,
 142        CGX_EVT_CMD_RESP
 143};
 144
 145enum cgx_stat {
 146        CGX_STAT_SUCCESS,
 147        CGX_STAT_FAIL
 148};
 149
 150enum cgx_cmd_own {
 151        CGX_CMD_OWN_NS,
 152        CGX_CMD_OWN_FIRMWARE,
 153};
 154
 155/* m - bit mask
 156 * y - value to be written in the bitrange
 157 * x - input value whose bitrange to be modified
 158 */
 159#define FIELD_SET(m, y, x)              \
 160        (((x) & ~(m)) |                 \
 161        FIELD_PREP((m), (y)))
 162
 163/* scratchx(0) CSR used for ATF->non-secure SW communication.
 164 * This acts as the status register
 165 * Provides details on command ack/status, command response, error details
 166 */
 167#define EVTREG_ACK              BIT_ULL(0)
 168#define EVTREG_EVT_TYPE         BIT_ULL(1)
 169#define EVTREG_STAT             BIT_ULL(2)
 170#define EVTREG_ID               GENMASK_ULL(8, 3)
 171
 172/* Response to command IDs with command status as CGX_STAT_FAIL
 173 *
 174 * Not applicable for commands :
 175 * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
 176 */
 177#define EVTREG_ERRTYPE          GENMASK_ULL(18, 9)
 178
 179/* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
 180 * CGX_STAT_SUCCESS
 181 */
 182#define RESP_MAJOR_VER          GENMASK_ULL(12, 9)
 183#define RESP_MINOR_VER          GENMASK_ULL(16, 13)
 184
 185/* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
 186 * CGX_STAT_SUCCESS
 187 */
 188#define RESP_MAC_ADDR           GENMASK_ULL(56, 9)
 189
 190/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as
 191 * CGX_STAT_SUCCESS
 192 */
 193#define RESP_MKEX_PRFL_SIZE             GENMASK_ULL(63, 9)
 194
 195/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as
 196 * CGX_STAT_SUCCESS
 197 */
 198#define RESP_MKEX_PRFL_ADDR             GENMASK_ULL(63, 9)
 199
 200/* Response to cmd ID as CGX_CMD_GET_FWD_BASE with cmd status as
 201 * CGX_STAT_SUCCESS
 202 */
 203#define RESP_FWD_BASE           GENMASK_ULL(56, 9)
 204#define RESP_LINKSTAT_LMAC_TYPE                GENMASK_ULL(35, 28)
 205
 206/* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
 207 * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
 208 *
 209 * In case of CGX_STAT_FAIL, it indicates CGX configuration failed
 210 * when processing link up/down/change command.
 211 * Both err_type and current link status will be updated
 212 *
 213 * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
 214 * link status will be updated
 215 */
 216struct cgx_lnk_sts {
 217        uint64_t reserved1:9;
 218        uint64_t link_up:1;
 219        uint64_t full_duplex:1;
 220        uint64_t speed:4;               /* cgx_link_speed */
 221        uint64_t err_type:10;
 222        uint64_t an:1;                  /* AN supported or not */
 223        uint64_t fec:2;                 /* FEC type if enabled, if not 0 */
 224        uint64_t port:8;
 225        uint64_t reserved2:28;
 226};
 227
 228#define RESP_LINKSTAT_UP                GENMASK_ULL(9, 9)
 229#define RESP_LINKSTAT_FDUPLEX           GENMASK_ULL(10, 10)
 230#define RESP_LINKSTAT_SPEED             GENMASK_ULL(14, 11)
 231#define RESP_LINKSTAT_ERRTYPE           GENMASK_ULL(24, 15)
 232#define RESP_LINKSTAT_AN                GENMASK_ULL(25, 25)
 233#define RESP_LINKSTAT_FEC               GENMASK_ULL(27, 26)
 234#define RESP_LINKSTAT_PORT              GENMASK_ULL(35, 28)
 235
 236/* scratchx(1) CSR used for non-secure SW->ATF communication
 237 * This CSR acts as a command register
 238 */
 239#define CMDREG_OWN      BIT_ULL(0)
 240#define CMDREG_ID       GENMASK_ULL(7, 2)
 241
 242/* Any command using enable/disable as an argument need
 243 * to set this bitfield.
 244 * Ex: Loopback, HiGig...
 245 */
 246#define CMDREG_ENABLE   BIT_ULL(8)
 247
 248/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
 249#define CMDMTU_SIZE     GENMASK_ULL(23, 8)
 250
 251/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
 252#define CMDLINKCHANGE_LINKUP    BIT_ULL(8)
 253#define CMDLINKCHANGE_FULLDPLX  BIT_ULL(9)
 254#define CMDLINKCHANGE_SPEED     GENMASK_ULL(13, 10)
 255
 256#define CMDSETFEC                       GENMASK_ULL(9, 8)
 257/* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */
 258#define CMDMODECHANGE_SPEED             GENMASK_ULL(11, 8)
 259#define CMDMODECHANGE_DUPLEX            GENMASK_ULL(12, 12)
 260#define CMDMODECHANGE_AN                GENMASK_ULL(13, 13)
 261#define CMDMODECHANGE_PORT              GENMASK_ULL(21, 14)
 262#define CMDMODECHANGE_FLAGS             GENMASK_ULL(63, 22)
 263
 264#endif /* __CGX_FW_INTF_H__ */
 265