linux/drivers/net/ethernet/marvell/sky2.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * New driver for Marvell Yukon 2 chipset.
   4 * Based on earlier sk98lin, and skge driver.
   5 *
   6 * This driver intentionally does not support all the features
   7 * of the original driver such as link fail-over and link management because
   8 * those should be done at higher levels.
   9 *
  10 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
  11 */
  12
  13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15#include <linux/crc32.h>
  16#include <linux/kernel.h>
  17#include <linux/module.h>
  18#include <linux/netdevice.h>
  19#include <linux/dma-mapping.h>
  20#include <linux/etherdevice.h>
  21#include <linux/ethtool.h>
  22#include <linux/pci.h>
  23#include <linux/interrupt.h>
  24#include <linux/ip.h>
  25#include <linux/slab.h>
  26#include <net/ip.h>
  27#include <linux/tcp.h>
  28#include <linux/in.h>
  29#include <linux/delay.h>
  30#include <linux/workqueue.h>
  31#include <linux/if_vlan.h>
  32#include <linux/prefetch.h>
  33#include <linux/debugfs.h>
  34#include <linux/mii.h>
  35#include <linux/of_device.h>
  36#include <linux/of_net.h>
  37#include <linux/dmi.h>
  38
  39#include <asm/irq.h>
  40
  41#include "sky2.h"
  42
  43#define DRV_NAME                "sky2"
  44#define DRV_VERSION             "1.30"
  45
  46/*
  47 * The Yukon II chipset takes 64 bit command blocks (called list elements)
  48 * that are organized into three (receive, transmit, status) different rings
  49 * similar to Tigon3.
  50 */
  51
  52#define RX_LE_SIZE              1024
  53#define RX_LE_BYTES             (RX_LE_SIZE*sizeof(struct sky2_rx_le))
  54#define RX_MAX_PENDING          (RX_LE_SIZE/6 - 2)
  55#define RX_DEF_PENDING          RX_MAX_PENDING
  56
  57/* This is the worst case number of transmit list elements for a single skb:
  58   VLAN:GSO + CKSUM + Data + skb_frags * DMA */
  59#define MAX_SKB_TX_LE   (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
  60#define TX_MIN_PENDING          (MAX_SKB_TX_LE+1)
  61#define TX_MAX_PENDING          1024
  62#define TX_DEF_PENDING          63
  63
  64#define TX_WATCHDOG             (5 * HZ)
  65#define NAPI_WEIGHT             64
  66#define PHY_RETRIES             1000
  67
  68#define SKY2_EEPROM_MAGIC       0x9955aabb
  69
  70#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
  71
  72static const u32 default_msg =
  73    NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  74    | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
  75    | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  76
  77static int debug = -1;          /* defaults above */
  78module_param(debug, int, 0);
  79MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  80
  81static int copybreak __read_mostly = 128;
  82module_param(copybreak, int, 0);
  83MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  84
  85static int disable_msi = -1;
  86module_param(disable_msi, int, 0);
  87MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  88
  89static int legacy_pme = 0;
  90module_param(legacy_pme, int, 0);
  91MODULE_PARM_DESC(legacy_pme, "Legacy power management");
  92
  93static const struct pci_device_id sky2_id_table[] = {
  94        { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
  95        { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
  96        { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
  97        { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },    /* DGE-560T */
  98        { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) },    /* DGE-550SX */
  99        { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) },    /* DGE-560SX */
 100        { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) },    /* DGE-550T */
 101        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
 102        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
 103        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
 104        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
 105        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
 106        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
 107        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
 108        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
 109        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
 110        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
 111        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
 112        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
 113        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
 114        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
 115        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
 116        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
 117        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
 118        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
 119        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
 120        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
 121        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
 122        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
 123        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
 124        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
 125        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
 126        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
 127        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
 128        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
 129        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
 130        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
 131        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
 132        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
 133        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
 134        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
 135        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
 136        { 0 }
 137};
 138
 139MODULE_DEVICE_TABLE(pci, sky2_id_table);
 140
 141/* Avoid conditionals by using array */
 142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
 143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
 144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
 145
 146static void sky2_set_multicast(struct net_device *dev);
 147static irqreturn_t sky2_intr(int irq, void *dev_id);
 148
 149/* Access to PHY via serial interconnect */
 150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
 151{
 152        int i;
 153
 154        gma_write16(hw, port, GM_SMI_DATA, val);
 155        gma_write16(hw, port, GM_SMI_CTRL,
 156                    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
 157
 158        for (i = 0; i < PHY_RETRIES; i++) {
 159                u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
 160                if (ctrl == 0xffff)
 161                        goto io_error;
 162
 163                if (!(ctrl & GM_SMI_CT_BUSY))
 164                        return 0;
 165
 166                udelay(10);
 167        }
 168
 169        dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
 170        return -ETIMEDOUT;
 171
 172io_error:
 173        dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
 174        return -EIO;
 175}
 176
 177static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
 178{
 179        int i;
 180
 181        gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
 182                    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
 183
 184        for (i = 0; i < PHY_RETRIES; i++) {
 185                u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
 186                if (ctrl == 0xffff)
 187                        goto io_error;
 188
 189                if (ctrl & GM_SMI_CT_RD_VAL) {
 190                        *val = gma_read16(hw, port, GM_SMI_DATA);
 191                        return 0;
 192                }
 193
 194                udelay(10);
 195        }
 196
 197        dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
 198        return -ETIMEDOUT;
 199io_error:
 200        dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
 201        return -EIO;
 202}
 203
 204static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
 205{
 206        u16 v;
 207        __gm_phy_read(hw, port, reg, &v);
 208        return v;
 209}
 210
 211
 212static void sky2_power_on(struct sky2_hw *hw)
 213{
 214        /* switch power to VCC (WA for VAUX problem) */
 215        sky2_write8(hw, B0_POWER_CTRL,
 216                    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
 217
 218        /* disable Core Clock Division, */
 219        sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
 220
 221        if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
 222                /* enable bits are inverted */
 223                sky2_write8(hw, B2_Y2_CLK_GATE,
 224                            Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
 225                            Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
 226                            Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
 227        else
 228                sky2_write8(hw, B2_Y2_CLK_GATE, 0);
 229
 230        if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
 231                u32 reg;
 232
 233                sky2_pci_write32(hw, PCI_DEV_REG3, 0);
 234
 235                reg = sky2_pci_read32(hw, PCI_DEV_REG4);
 236                /* set all bits to 0 except bits 15..12 and 8 */
 237                reg &= P_ASPM_CONTROL_MSK;
 238                sky2_pci_write32(hw, PCI_DEV_REG4, reg);
 239
 240                reg = sky2_pci_read32(hw, PCI_DEV_REG5);
 241                /* set all bits to 0 except bits 28 & 27 */
 242                reg &= P_CTL_TIM_VMAIN_AV_MSK;
 243                sky2_pci_write32(hw, PCI_DEV_REG5, reg);
 244
 245                sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
 246
 247                sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
 248
 249                /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
 250                reg = sky2_read32(hw, B2_GP_IO);
 251                reg |= GLB_GPIO_STAT_RACE_DIS;
 252                sky2_write32(hw, B2_GP_IO, reg);
 253
 254                sky2_read32(hw, B2_GP_IO);
 255        }
 256
 257        /* Turn on "driver loaded" LED */
 258        sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
 259}
 260
 261static void sky2_power_aux(struct sky2_hw *hw)
 262{
 263        if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
 264                sky2_write8(hw, B2_Y2_CLK_GATE, 0);
 265        else
 266                /* enable bits are inverted */
 267                sky2_write8(hw, B2_Y2_CLK_GATE,
 268                            Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
 269                            Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
 270                            Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
 271
 272        /* switch power to VAUX if supported and PME from D3cold */
 273        if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
 274             pci_pme_capable(hw->pdev, PCI_D3cold))
 275                sky2_write8(hw, B0_POWER_CTRL,
 276                            (PC_VAUX_ENA | PC_VCC_ENA |
 277                             PC_VAUX_ON | PC_VCC_OFF));
 278
 279        /* turn off "driver loaded LED" */
 280        sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
 281}
 282
 283static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
 284{
 285        u16 reg;
 286
 287        /* disable all GMAC IRQ's */
 288        sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
 289
 290        gma_write16(hw, port, GM_MC_ADDR_H1, 0);        /* clear MC hash */
 291        gma_write16(hw, port, GM_MC_ADDR_H2, 0);
 292        gma_write16(hw, port, GM_MC_ADDR_H3, 0);
 293        gma_write16(hw, port, GM_MC_ADDR_H4, 0);
 294
 295        reg = gma_read16(hw, port, GM_RX_CTRL);
 296        reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
 297        gma_write16(hw, port, GM_RX_CTRL, reg);
 298}
 299
 300/* flow control to advertise bits */
 301static const u16 copper_fc_adv[] = {
 302        [FC_NONE]       = 0,
 303        [FC_TX]         = PHY_M_AN_ASP,
 304        [FC_RX]         = PHY_M_AN_PC,
 305        [FC_BOTH]       = PHY_M_AN_PC | PHY_M_AN_ASP,
 306};
 307
 308/* flow control to advertise bits when using 1000BaseX */
 309static const u16 fiber_fc_adv[] = {
 310        [FC_NONE] = PHY_M_P_NO_PAUSE_X,
 311        [FC_TX]   = PHY_M_P_ASYM_MD_X,
 312        [FC_RX]   = PHY_M_P_SYM_MD_X,
 313        [FC_BOTH] = PHY_M_P_BOTH_MD_X,
 314};
 315
 316/* flow control to GMA disable bits */
 317static const u16 gm_fc_disable[] = {
 318        [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
 319        [FC_TX]   = GM_GPCR_FC_RX_DIS,
 320        [FC_RX]   = GM_GPCR_FC_TX_DIS,
 321        [FC_BOTH] = 0,
 322};
 323
 324
 325static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
 326{
 327        struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
 328        u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
 329
 330        if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
 331            !(hw->flags & SKY2_HW_NEWER_PHY)) {
 332                u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
 333
 334                ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
 335                           PHY_M_EC_MAC_S_MSK);
 336                ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
 337
 338                /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
 339                if (hw->chip_id == CHIP_ID_YUKON_EC)
 340                        /* set downshift counter to 3x and enable downshift */
 341                        ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
 342                else
 343                        /* set master & slave downshift counter to 1x */
 344                        ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
 345
 346                gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
 347        }
 348
 349        ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 350        if (sky2_is_copper(hw)) {
 351                if (!(hw->flags & SKY2_HW_GIGABIT)) {
 352                        /* enable automatic crossover */
 353                        ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
 354
 355                        if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
 356                            hw->chip_rev == CHIP_REV_YU_FE2_A0) {
 357                                u16 spec;
 358
 359                                /* Enable Class A driver for FE+ A0 */
 360                                spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
 361                                spec |= PHY_M_FESC_SEL_CL_A;
 362                                gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
 363                        }
 364                } else {
 365                        /* disable energy detect */
 366                        ctrl &= ~PHY_M_PC_EN_DET_MSK;
 367
 368                        /* enable automatic crossover */
 369                        ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
 370
 371                        /* downshift on PHY 88E1112 and 88E1149 is changed */
 372                        if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
 373                             (hw->flags & SKY2_HW_NEWER_PHY)) {
 374                                /* set downshift counter to 3x and enable downshift */
 375                                ctrl &= ~PHY_M_PC_DSC_MSK;
 376                                ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
 377                        }
 378                }
 379        } else {
 380                /* workaround for deviation #4.88 (CRC errors) */
 381                /* disable Automatic Crossover */
 382
 383                ctrl &= ~PHY_M_PC_MDIX_MSK;
 384        }
 385
 386        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 387
 388        /* special setup for PHY 88E1112 Fiber */
 389        if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
 390                pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 391
 392                /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
 393                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
 394                ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 395                ctrl &= ~PHY_M_MAC_MD_MSK;
 396                ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
 397                gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 398
 399                if (hw->pmd_type  == 'P') {
 400                        /* select page 1 to access Fiber registers */
 401                        gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
 402
 403                        /* for SFP-module set SIGDET polarity to low */
 404                        ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 405                        ctrl |= PHY_M_FIB_SIGD_POL;
 406                        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 407                }
 408
 409                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 410        }
 411
 412        ctrl = PHY_CT_RESET;
 413        ct1000 = 0;
 414        adv = PHY_AN_CSMA;
 415        reg = 0;
 416
 417        if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
 418                if (sky2_is_copper(hw)) {
 419                        if (sky2->advertising & ADVERTISED_1000baseT_Full)
 420                                ct1000 |= PHY_M_1000C_AFD;
 421                        if (sky2->advertising & ADVERTISED_1000baseT_Half)
 422                                ct1000 |= PHY_M_1000C_AHD;
 423                        if (sky2->advertising & ADVERTISED_100baseT_Full)
 424                                adv |= PHY_M_AN_100_FD;
 425                        if (sky2->advertising & ADVERTISED_100baseT_Half)
 426                                adv |= PHY_M_AN_100_HD;
 427                        if (sky2->advertising & ADVERTISED_10baseT_Full)
 428                                adv |= PHY_M_AN_10_FD;
 429                        if (sky2->advertising & ADVERTISED_10baseT_Half)
 430                                adv |= PHY_M_AN_10_HD;
 431
 432                } else {        /* special defines for FIBER (88E1040S only) */
 433                        if (sky2->advertising & ADVERTISED_1000baseT_Full)
 434                                adv |= PHY_M_AN_1000X_AFD;
 435                        if (sky2->advertising & ADVERTISED_1000baseT_Half)
 436                                adv |= PHY_M_AN_1000X_AHD;
 437                }
 438
 439                /* Restart Auto-negotiation */
 440                ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
 441        } else {
 442                /* forced speed/duplex settings */
 443                ct1000 = PHY_M_1000C_MSE;
 444
 445                /* Disable auto update for duplex flow control and duplex */
 446                reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
 447
 448                switch (sky2->speed) {
 449                case SPEED_1000:
 450                        ctrl |= PHY_CT_SP1000;
 451                        reg |= GM_GPCR_SPEED_1000;
 452                        break;
 453                case SPEED_100:
 454                        ctrl |= PHY_CT_SP100;
 455                        reg |= GM_GPCR_SPEED_100;
 456                        break;
 457                }
 458
 459                if (sky2->duplex == DUPLEX_FULL) {
 460                        reg |= GM_GPCR_DUP_FULL;
 461                        ctrl |= PHY_CT_DUP_MD;
 462                } else if (sky2->speed < SPEED_1000)
 463                        sky2->flow_mode = FC_NONE;
 464        }
 465
 466        if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
 467                if (sky2_is_copper(hw))
 468                        adv |= copper_fc_adv[sky2->flow_mode];
 469                else
 470                        adv |= fiber_fc_adv[sky2->flow_mode];
 471        } else {
 472                reg |= GM_GPCR_AU_FCT_DIS;
 473                reg |= gm_fc_disable[sky2->flow_mode];
 474
 475                /* Forward pause packets to GMAC? */
 476                if (sky2->flow_mode & FC_RX)
 477                        sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
 478                else
 479                        sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
 480        }
 481
 482        gma_write16(hw, port, GM_GP_CTRL, reg);
 483
 484        if (hw->flags & SKY2_HW_GIGABIT)
 485                gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
 486
 487        gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
 488        gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
 489
 490        /* Setup Phy LED's */
 491        ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
 492        ledover = 0;
 493
 494        switch (hw->chip_id) {
 495        case CHIP_ID_YUKON_FE:
 496                /* on 88E3082 these bits are at 11..9 (shifted left) */
 497                ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
 498
 499                ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
 500
 501                /* delete ACT LED control bits */
 502                ctrl &= ~PHY_M_FELP_LED1_MSK;
 503                /* change ACT LED control to blink mode */
 504                ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
 505                gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
 506                break;
 507
 508        case CHIP_ID_YUKON_FE_P:
 509                /* Enable Link Partner Next Page */
 510                ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 511                ctrl |= PHY_M_PC_ENA_LIP_NP;
 512
 513                /* disable Energy Detect and enable scrambler */
 514                ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
 515                gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 516
 517                /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
 518                ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
 519                        PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
 520                        PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
 521
 522                gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
 523                break;
 524
 525        case CHIP_ID_YUKON_XL:
 526                pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 527
 528                /* select page 3 to access LED control register */
 529                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
 530
 531                /* set LED Function Control register */
 532                gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
 533                             (PHY_M_LEDC_LOS_CTRL(1) |  /* LINK/ACT */
 534                              PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
 535                              PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
 536                              PHY_M_LEDC_STA0_CTRL(7)));        /* 1000 Mbps */
 537
 538                /* set Polarity Control register */
 539                gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
 540                             (PHY_M_POLC_LS1_P_MIX(4) |
 541                              PHY_M_POLC_IS0_P_MIX(4) |
 542                              PHY_M_POLC_LOS_CTRL(2) |
 543                              PHY_M_POLC_INIT_CTRL(2) |
 544                              PHY_M_POLC_STA1_CTRL(2) |
 545                              PHY_M_POLC_STA0_CTRL(2)));
 546
 547                /* restore page register */
 548                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 549                break;
 550
 551        case CHIP_ID_YUKON_EC_U:
 552        case CHIP_ID_YUKON_EX:
 553        case CHIP_ID_YUKON_SUPR:
 554                pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
 555
 556                /* select page 3 to access LED control register */
 557                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
 558
 559                /* set LED Function Control register */
 560                gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
 561                             (PHY_M_LEDC_LOS_CTRL(1) |  /* LINK/ACT */
 562                              PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
 563                              PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
 564                              PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
 565
 566                /* set Blink Rate in LED Timer Control Register */
 567                gm_phy_write(hw, port, PHY_MARV_INT_MASK,
 568                             ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
 569                /* restore page register */
 570                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
 571                break;
 572
 573        default:
 574                /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
 575                ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
 576
 577                /* turn off the Rx LED (LED_RX) */
 578                ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
 579        }
 580
 581        if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
 582                /* apply fixes in PHY AFE */
 583                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
 584
 585                /* increase differential signal amplitude in 10BASE-T */
 586                gm_phy_write(hw, port, 0x18, 0xaa99);
 587                gm_phy_write(hw, port, 0x17, 0x2011);
 588
 589                if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
 590                        /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
 591                        gm_phy_write(hw, port, 0x18, 0xa204);
 592                        gm_phy_write(hw, port, 0x17, 0x2002);
 593                }
 594
 595                /* set page register to 0 */
 596                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
 597        } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
 598                   hw->chip_rev == CHIP_REV_YU_FE2_A0) {
 599                /* apply workaround for integrated resistors calibration */
 600                gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
 601                gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
 602        } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
 603                /* apply fixes in PHY AFE */
 604                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
 605
 606                /* apply RDAC termination workaround */
 607                gm_phy_write(hw, port, 24, 0x2800);
 608                gm_phy_write(hw, port, 23, 0x2001);
 609
 610                /* set page register back to 0 */
 611                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
 612        } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
 613                   hw->chip_id < CHIP_ID_YUKON_SUPR) {
 614                /* no effect on Yukon-XL */
 615                gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
 616
 617                if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
 618                    sky2->speed == SPEED_100) {
 619                        /* turn on 100 Mbps LED (LED_LINK100) */
 620                        ledover |= PHY_M_LED_MO_100(MO_LED_ON);
 621                }
 622
 623                if (ledover)
 624                        gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
 625
 626        } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
 627                   (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
 628                int i;
 629                /* This a phy register setup workaround copied from vendor driver. */
 630                static const struct {
 631                        u16 reg, val;
 632                } eee_afe[] = {
 633                        { 0x156, 0x58ce },
 634                        { 0x153, 0x99eb },
 635                        { 0x141, 0x8064 },
 636                        /* { 0x155, 0x130b },*/
 637                        { 0x000, 0x0000 },
 638                        { 0x151, 0x8433 },
 639                        { 0x14b, 0x8c44 },
 640                        { 0x14c, 0x0f90 },
 641                        { 0x14f, 0x39aa },
 642                        /* { 0x154, 0x2f39 },*/
 643                        { 0x14d, 0xba33 },
 644                        { 0x144, 0x0048 },
 645                        { 0x152, 0x2010 },
 646                        /* { 0x158, 0x1223 },*/
 647                        { 0x140, 0x4444 },
 648                        { 0x154, 0x2f3b },
 649                        { 0x158, 0xb203 },
 650                        { 0x157, 0x2029 },
 651                };
 652
 653                /* Start Workaround for OptimaEEE Rev.Z0 */
 654                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
 655
 656                gm_phy_write(hw, port,  1, 0x4099);
 657                gm_phy_write(hw, port,  3, 0x1120);
 658                gm_phy_write(hw, port, 11, 0x113c);
 659                gm_phy_write(hw, port, 14, 0x8100);
 660                gm_phy_write(hw, port, 15, 0x112a);
 661                gm_phy_write(hw, port, 17, 0x1008);
 662
 663                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
 664                gm_phy_write(hw, port,  1, 0x20b0);
 665
 666                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
 667
 668                for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
 669                        /* apply AFE settings */
 670                        gm_phy_write(hw, port, 17, eee_afe[i].val);
 671                        gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
 672                }
 673
 674                /* End Workaround for OptimaEEE */
 675                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
 676
 677                /* Enable 10Base-Te (EEE) */
 678                if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
 679                        reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
 680                        gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
 681                                     reg | PHY_M_10B_TE_ENABLE);
 682                }
 683        }
 684
 685        /* Enable phy interrupt on auto-negotiation complete (or link up) */
 686        if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
 687                gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
 688        else
 689                gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
 690}
 691
 692static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
 693static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
 694
 695static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
 696{
 697        u32 reg1;
 698
 699        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 700        reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
 701        reg1 &= ~phy_power[port];
 702
 703        if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
 704                reg1 |= coma_mode[port];
 705
 706        sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
 707        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 708        sky2_pci_read32(hw, PCI_DEV_REG1);
 709
 710        if (hw->chip_id == CHIP_ID_YUKON_FE)
 711                gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
 712        else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
 713                sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
 714}
 715
 716static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
 717{
 718        u32 reg1;
 719        u16 ctrl;
 720
 721        /* release GPHY Control reset */
 722        sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
 723
 724        /* release GMAC reset */
 725        sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
 726
 727        if (hw->flags & SKY2_HW_NEWER_PHY) {
 728                /* select page 2 to access MAC control register */
 729                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
 730
 731                ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 732                /* allow GMII Power Down */
 733                ctrl &= ~PHY_M_MAC_GMIF_PUP;
 734                gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 735
 736                /* set page register back to 0 */
 737                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
 738        }
 739
 740        /* setup General Purpose Control Register */
 741        gma_write16(hw, port, GM_GP_CTRL,
 742                    GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
 743                    GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
 744                    GM_GPCR_AU_SPD_DIS);
 745
 746        if (hw->chip_id != CHIP_ID_YUKON_EC) {
 747                if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
 748                        /* select page 2 to access MAC control register */
 749                        gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
 750
 751                        ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
 752                        /* enable Power Down */
 753                        ctrl |= PHY_M_PC_POW_D_ENA;
 754                        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
 755
 756                        /* set page register back to 0 */
 757                        gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
 758                }
 759
 760                /* set IEEE compatible Power Down Mode (dev. #4.99) */
 761                gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
 762        }
 763
 764        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
 765        reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
 766        reg1 |= phy_power[port];                /* set PHY to PowerDown/COMA Mode */
 767        sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
 768        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
 769}
 770
 771/* configure IPG according to used link speed */
 772static void sky2_set_ipg(struct sky2_port *sky2)
 773{
 774        u16 reg;
 775
 776        reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
 777        reg &= ~GM_SMOD_IPG_MSK;
 778        if (sky2->speed > SPEED_100)
 779                reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
 780        else
 781                reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
 782        gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
 783}
 784
 785/* Enable Rx/Tx */
 786static void sky2_enable_rx_tx(struct sky2_port *sky2)
 787{
 788        struct sky2_hw *hw = sky2->hw;
 789        unsigned port = sky2->port;
 790        u16 reg;
 791
 792        reg = gma_read16(hw, port, GM_GP_CTRL);
 793        reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
 794        gma_write16(hw, port, GM_GP_CTRL, reg);
 795}
 796
 797/* Force a renegotiation */
 798static void sky2_phy_reinit(struct sky2_port *sky2)
 799{
 800        spin_lock_bh(&sky2->phy_lock);
 801        sky2_phy_init(sky2->hw, sky2->port);
 802        sky2_enable_rx_tx(sky2);
 803        spin_unlock_bh(&sky2->phy_lock);
 804}
 805
 806/* Put device in state to listen for Wake On Lan */
 807static void sky2_wol_init(struct sky2_port *sky2)
 808{
 809        struct sky2_hw *hw = sky2->hw;
 810        unsigned port = sky2->port;
 811        enum flow_control save_mode;
 812        u16 ctrl;
 813
 814        /* Bring hardware out of reset */
 815        sky2_write16(hw, B0_CTST, CS_RST_CLR);
 816        sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
 817
 818        sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
 819        sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
 820
 821        /* Force to 10/100
 822         * sky2_reset will re-enable on resume
 823         */
 824        save_mode = sky2->flow_mode;
 825        ctrl = sky2->advertising;
 826
 827        sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
 828        sky2->flow_mode = FC_NONE;
 829
 830        spin_lock_bh(&sky2->phy_lock);
 831        sky2_phy_power_up(hw, port);
 832        sky2_phy_init(hw, port);
 833        spin_unlock_bh(&sky2->phy_lock);
 834
 835        sky2->flow_mode = save_mode;
 836        sky2->advertising = ctrl;
 837
 838        /* Set GMAC to no flow control and auto update for speed/duplex */
 839        gma_write16(hw, port, GM_GP_CTRL,
 840                    GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
 841                    GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
 842
 843        /* Set WOL address */
 844        memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
 845                    sky2->netdev->dev_addr, ETH_ALEN);
 846
 847        /* Turn on appropriate WOL control bits */
 848        sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
 849        ctrl = 0;
 850        if (sky2->wol & WAKE_PHY)
 851                ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
 852        else
 853                ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
 854
 855        if (sky2->wol & WAKE_MAGIC)
 856                ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
 857        else
 858                ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
 859
 860        ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
 861        sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
 862
 863        /* Disable PiG firmware */
 864        sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
 865
 866        /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
 867        if (legacy_pme) {
 868                u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
 869                reg1 |= PCI_Y2_PME_LEGACY;
 870                sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
 871        }
 872
 873        /* block receiver */
 874        sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
 875        sky2_read32(hw, B0_CTST);
 876}
 877
 878static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
 879{
 880        struct net_device *dev = hw->dev[port];
 881
 882        if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
 883              hw->chip_rev != CHIP_REV_YU_EX_A0) ||
 884             hw->chip_id >= CHIP_ID_YUKON_FE_P) {
 885                /* Yukon-Extreme B0 and further Extreme devices */
 886                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
 887        } else if (dev->mtu > ETH_DATA_LEN) {
 888                /* set Tx GMAC FIFO Almost Empty Threshold */
 889                sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
 890                             (ECU_JUMBO_WM << 16) | ECU_AE_THR);
 891
 892                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
 893        } else
 894                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
 895}
 896
 897static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
 898{
 899        struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
 900        u16 reg;
 901        u32 rx_reg;
 902        int i;
 903        const u8 *addr = hw->dev[port]->dev_addr;
 904
 905        sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
 906        sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
 907
 908        sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
 909
 910        if (hw->chip_id == CHIP_ID_YUKON_XL &&
 911            hw->chip_rev == CHIP_REV_YU_XL_A0 &&
 912            port == 1) {
 913                /* WA DEV_472 -- looks like crossed wires on port 2 */
 914                /* clear GMAC 1 Control reset */
 915                sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
 916                do {
 917                        sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
 918                        sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
 919                } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
 920                         gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
 921                         gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
 922        }
 923
 924        sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
 925
 926        /* Enable Transmit FIFO Underrun */
 927        sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
 928
 929        spin_lock_bh(&sky2->phy_lock);
 930        sky2_phy_power_up(hw, port);
 931        sky2_phy_init(hw, port);
 932        spin_unlock_bh(&sky2->phy_lock);
 933
 934        /* MIB clear */
 935        reg = gma_read16(hw, port, GM_PHY_ADDR);
 936        gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
 937
 938        for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
 939                gma_read16(hw, port, i);
 940        gma_write16(hw, port, GM_PHY_ADDR, reg);
 941
 942        /* transmit control */
 943        gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
 944
 945        /* receive control reg: unicast + multicast + no FCS  */
 946        gma_write16(hw, port, GM_RX_CTRL,
 947                    GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
 948
 949        /* transmit flow control */
 950        gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
 951
 952        /* transmit parameter */
 953        gma_write16(hw, port, GM_TX_PARAM,
 954                    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
 955                    TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
 956                    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
 957                    TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
 958
 959        /* serial mode register */
 960        reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
 961                GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
 962
 963        if (hw->dev[port]->mtu > ETH_DATA_LEN)
 964                reg |= GM_SMOD_JUMBO_ENA;
 965
 966        if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
 967            hw->chip_rev == CHIP_REV_YU_EC_U_B1)
 968                reg |= GM_NEW_FLOW_CTRL;
 969
 970        gma_write16(hw, port, GM_SERIAL_MODE, reg);
 971
 972        /* virtual address for data */
 973        gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
 974
 975        /* physical address: used for pause frames */
 976        gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
 977
 978        /* ignore counter overflows */
 979        gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
 980        gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
 981        gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
 982
 983        /* Configure Rx MAC FIFO */
 984        sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
 985        rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
 986        if (hw->chip_id == CHIP_ID_YUKON_EX ||
 987            hw->chip_id == CHIP_ID_YUKON_FE_P)
 988                rx_reg |= GMF_RX_OVER_ON;
 989
 990        sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
 991
 992        if (hw->chip_id == CHIP_ID_YUKON_XL) {
 993                /* Hardware errata - clear flush mask */
 994                sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
 995        } else {
 996                /* Flush Rx MAC FIFO on any flow control or error */
 997                sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
 998        }
 999
1000        /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug  */
1001        reg = RX_GMF_FL_THR_DEF + 1;
1002        /* Another magic mystery workaround from sk98lin */
1003        if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1004            hw->chip_rev == CHIP_REV_YU_FE2_A0)
1005                reg = 0x178;
1006        sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1007
1008        /* Configure Tx MAC FIFO */
1009        sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1010        sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1011
1012        /* On chips without ram buffer, pause is controlled by MAC level */
1013        if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1014                /* Pause threshold is scaled by 8 in bytes */
1015                if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1016                    hw->chip_rev == CHIP_REV_YU_FE2_A0)
1017                        reg = 1568 / 8;
1018                else
1019                        reg = 1024 / 8;
1020                sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1021                sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1022
1023                sky2_set_tx_stfwd(hw, port);
1024        }
1025
1026        if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1027            hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1028                /* disable dynamic watermark */
1029                reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1030                reg &= ~TX_DYN_WM_ENA;
1031                sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1032        }
1033}
1034
1035/* Assign Ram Buffer allocation to queue */
1036static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1037{
1038        u32 end;
1039
1040        /* convert from K bytes to qwords used for hw register */
1041        start *= 1024/8;
1042        space *= 1024/8;
1043        end = start + space - 1;
1044
1045        sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1046        sky2_write32(hw, RB_ADDR(q, RB_START), start);
1047        sky2_write32(hw, RB_ADDR(q, RB_END), end);
1048        sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1049        sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1050
1051        if (q == Q_R1 || q == Q_R2) {
1052                u32 tp = space - space/4;
1053
1054                /* On receive queue's set the thresholds
1055                 * give receiver priority when > 3/4 full
1056                 * send pause when down to 2K
1057                 */
1058                sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1059                sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1060
1061                tp = space - 8192/8;
1062                sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1063                sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1064        } else {
1065                /* Enable store & forward on Tx queue's because
1066                 * Tx FIFO is only 1K on Yukon
1067                 */
1068                sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1069        }
1070
1071        sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1072        sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1073}
1074
1075/* Setup Bus Memory Interface */
1076static void sky2_qset(struct sky2_hw *hw, u16 q)
1077{
1078        sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1079        sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1080        sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1081        sky2_write32(hw, Q_ADDR(q, Q_WM),  BMU_WM_DEFAULT);
1082}
1083
1084/* Setup prefetch unit registers. This is the interface between
1085 * hardware and driver list elements
1086 */
1087static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1088                               dma_addr_t addr, u32 last)
1089{
1090        sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1091        sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1092        sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1093        sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1094        sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1095        sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1096
1097        sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1098}
1099
1100static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1101{
1102        struct sky2_tx_le *le = sky2->tx_le + *slot;
1103
1104        *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1105        le->ctrl = 0;
1106        return le;
1107}
1108
1109static void tx_init(struct sky2_port *sky2)
1110{
1111        struct sky2_tx_le *le;
1112
1113        sky2->tx_prod = sky2->tx_cons = 0;
1114        sky2->tx_tcpsum = 0;
1115        sky2->tx_last_mss = 0;
1116        netdev_reset_queue(sky2->netdev);
1117
1118        le = get_tx_le(sky2, &sky2->tx_prod);
1119        le->addr = 0;
1120        le->opcode = OP_ADDR64 | HW_OWNER;
1121        sky2->tx_last_upper = 0;
1122}
1123
1124/* Update chip's next pointer */
1125static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1126{
1127        /* Make sure write' to descriptors are complete before we tell hardware */
1128        wmb();
1129        sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1130}
1131
1132
1133static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1134{
1135        struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1136        sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1137        le->ctrl = 0;
1138        return le;
1139}
1140
1141static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1142{
1143        unsigned size;
1144
1145        /* Space needed for frame data + headers rounded up */
1146        size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1147
1148        /* Stopping point for hardware truncation */
1149        return (size - 8) / sizeof(u32);
1150}
1151
1152static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1153{
1154        struct rx_ring_info *re;
1155        unsigned size;
1156
1157        /* Space needed for frame data + headers rounded up */
1158        size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1159
1160        sky2->rx_nfrags = size >> PAGE_SHIFT;
1161        BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1162
1163        /* Compute residue after pages */
1164        size -= sky2->rx_nfrags << PAGE_SHIFT;
1165
1166        /* Optimize to handle small packets and headers */
1167        if (size < copybreak)
1168                size = copybreak;
1169        if (size < ETH_HLEN)
1170                size = ETH_HLEN;
1171
1172        return size;
1173}
1174
1175/* Build description to hardware for one receive segment */
1176static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1177                        dma_addr_t map, unsigned len)
1178{
1179        struct sky2_rx_le *le;
1180
1181        if (sizeof(dma_addr_t) > sizeof(u32)) {
1182                le = sky2_next_rx(sky2);
1183                le->addr = cpu_to_le32(upper_32_bits(map));
1184                le->opcode = OP_ADDR64 | HW_OWNER;
1185        }
1186
1187        le = sky2_next_rx(sky2);
1188        le->addr = cpu_to_le32(lower_32_bits(map));
1189        le->length = cpu_to_le16(len);
1190        le->opcode = op | HW_OWNER;
1191}
1192
1193/* Build description to hardware for one possibly fragmented skb */
1194static void sky2_rx_submit(struct sky2_port *sky2,
1195                           const struct rx_ring_info *re)
1196{
1197        int i;
1198
1199        sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1200
1201        for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1202                sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1203}
1204
1205
1206static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1207                            unsigned size)
1208{
1209        struct sk_buff *skb = re->skb;
1210        int i;
1211
1212        re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1213        if (pci_dma_mapping_error(pdev, re->data_addr))
1214                goto mapping_error;
1215
1216        dma_unmap_len_set(re, data_size, size);
1217
1218        for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1219                const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1220
1221                re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1222                                                    skb_frag_size(frag),
1223                                                    DMA_FROM_DEVICE);
1224
1225                if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1226                        goto map_page_error;
1227        }
1228        return 0;
1229
1230map_page_error:
1231        while (--i >= 0) {
1232                pci_unmap_page(pdev, re->frag_addr[i],
1233                               skb_frag_size(&skb_shinfo(skb)->frags[i]),
1234                               PCI_DMA_FROMDEVICE);
1235        }
1236
1237        pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1238                         PCI_DMA_FROMDEVICE);
1239
1240mapping_error:
1241        if (net_ratelimit())
1242                dev_warn(&pdev->dev, "%s: rx mapping error\n",
1243                         skb->dev->name);
1244        return -EIO;
1245}
1246
1247static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1248{
1249        struct sk_buff *skb = re->skb;
1250        int i;
1251
1252        pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1253                         PCI_DMA_FROMDEVICE);
1254
1255        for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1256                pci_unmap_page(pdev, re->frag_addr[i],
1257                               skb_frag_size(&skb_shinfo(skb)->frags[i]),
1258                               PCI_DMA_FROMDEVICE);
1259}
1260
1261/* Tell chip where to start receive checksum.
1262 * Actually has two checksums, but set both same to avoid possible byte
1263 * order problems.
1264 */
1265static void rx_set_checksum(struct sky2_port *sky2)
1266{
1267        struct sky2_rx_le *le = sky2_next_rx(sky2);
1268
1269        le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1270        le->ctrl = 0;
1271        le->opcode = OP_TCPSTART | HW_OWNER;
1272
1273        sky2_write32(sky2->hw,
1274                     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1275                     (sky2->netdev->features & NETIF_F_RXCSUM)
1276                     ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1277}
1278
1279/* Enable/disable receive hash calculation (RSS) */
1280static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1281{
1282        struct sky2_port *sky2 = netdev_priv(dev);
1283        struct sky2_hw *hw = sky2->hw;
1284        int i, nkeys = 4;
1285
1286        /* Supports IPv6 and other modes */
1287        if (hw->flags & SKY2_HW_NEW_LE) {
1288                nkeys = 10;
1289                sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1290        }
1291
1292        /* Program RSS initial values */
1293        if (features & NETIF_F_RXHASH) {
1294                u32 rss_key[10];
1295
1296                netdev_rss_key_fill(rss_key, sizeof(rss_key));
1297                for (i = 0; i < nkeys; i++)
1298                        sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1299                                     rss_key[i]);
1300
1301                /* Need to turn on (undocumented) flag to make hashing work  */
1302                sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1303                             RX_STFW_ENA);
1304
1305                sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1306                             BMU_ENA_RX_RSS_HASH);
1307        } else
1308                sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1309                             BMU_DIS_RX_RSS_HASH);
1310}
1311
1312/*
1313 * The RX Stop command will not work for Yukon-2 if the BMU does not
1314 * reach the end of packet and since we can't make sure that we have
1315 * incoming data, we must reset the BMU while it is not doing a DMA
1316 * transfer. Since it is possible that the RX path is still active,
1317 * the RX RAM buffer will be stopped first, so any possible incoming
1318 * data will not trigger a DMA. After the RAM buffer is stopped, the
1319 * BMU is polled until any DMA in progress is ended and only then it
1320 * will be reset.
1321 */
1322static void sky2_rx_stop(struct sky2_port *sky2)
1323{
1324        struct sky2_hw *hw = sky2->hw;
1325        unsigned rxq = rxqaddr[sky2->port];
1326        int i;
1327
1328        /* disable the RAM Buffer receive queue */
1329        sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1330
1331        for (i = 0; i < 0xffff; i++)
1332                if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1333                    == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1334                        goto stopped;
1335
1336        netdev_warn(sky2->netdev, "receiver stop failed\n");
1337stopped:
1338        sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1339
1340        /* reset the Rx prefetch unit */
1341        sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1342}
1343
1344/* Clean out receive buffer area, assumes receiver hardware stopped */
1345static void sky2_rx_clean(struct sky2_port *sky2)
1346{
1347        unsigned i;
1348
1349        if (sky2->rx_le)
1350                memset(sky2->rx_le, 0, RX_LE_BYTES);
1351
1352        for (i = 0; i < sky2->rx_pending; i++) {
1353                struct rx_ring_info *re = sky2->rx_ring + i;
1354
1355                if (re->skb) {
1356                        sky2_rx_unmap_skb(sky2->hw->pdev, re);
1357                        kfree_skb(re->skb);
1358                        re->skb = NULL;
1359                }
1360        }
1361}
1362
1363/* Basic MII support */
1364static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1365{
1366        struct mii_ioctl_data *data = if_mii(ifr);
1367        struct sky2_port *sky2 = netdev_priv(dev);
1368        struct sky2_hw *hw = sky2->hw;
1369        int err = -EOPNOTSUPP;
1370
1371        if (!netif_running(dev))
1372                return -ENODEV; /* Phy still in reset */
1373
1374        switch (cmd) {
1375        case SIOCGMIIPHY:
1376                data->phy_id = PHY_ADDR_MARV;
1377
1378                /* fallthru */
1379        case SIOCGMIIREG: {
1380                u16 val = 0;
1381
1382                spin_lock_bh(&sky2->phy_lock);
1383                err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1384                spin_unlock_bh(&sky2->phy_lock);
1385
1386                data->val_out = val;
1387                break;
1388        }
1389
1390        case SIOCSMIIREG:
1391                spin_lock_bh(&sky2->phy_lock);
1392                err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1393                                   data->val_in);
1394                spin_unlock_bh(&sky2->phy_lock);
1395                break;
1396        }
1397        return err;
1398}
1399
1400#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1401
1402static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1403{
1404        struct sky2_port *sky2 = netdev_priv(dev);
1405        struct sky2_hw *hw = sky2->hw;
1406        u16 port = sky2->port;
1407
1408        if (features & NETIF_F_HW_VLAN_CTAG_RX)
1409                sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1410                             RX_VLAN_STRIP_ON);
1411        else
1412                sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1413                             RX_VLAN_STRIP_OFF);
1414
1415        if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1416                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1417                             TX_VLAN_TAG_ON);
1418
1419                dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1420        } else {
1421                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1422                             TX_VLAN_TAG_OFF);
1423
1424                /* Can't do transmit offload of vlan without hw vlan */
1425                dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1426        }
1427}
1428
1429/* Amount of required worst case padding in rx buffer */
1430static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1431{
1432        return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1433}
1434
1435/*
1436 * Allocate an skb for receiving. If the MTU is large enough
1437 * make the skb non-linear with a fragment list of pages.
1438 */
1439static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1440{
1441        struct sk_buff *skb;
1442        int i;
1443
1444        skb = __netdev_alloc_skb(sky2->netdev,
1445                                 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1446                                 gfp);
1447        if (!skb)
1448                goto nomem;
1449
1450        if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1451                unsigned char *start;
1452                /*
1453                 * Workaround for a bug in FIFO that cause hang
1454                 * if the FIFO if the receive buffer is not 64 byte aligned.
1455                 * The buffer returned from netdev_alloc_skb is
1456                 * aligned except if slab debugging is enabled.
1457                 */
1458                start = PTR_ALIGN(skb->data, 8);
1459                skb_reserve(skb, start - skb->data);
1460        } else
1461                skb_reserve(skb, NET_IP_ALIGN);
1462
1463        for (i = 0; i < sky2->rx_nfrags; i++) {
1464                struct page *page = alloc_page(gfp);
1465
1466                if (!page)
1467                        goto free_partial;
1468                skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1469        }
1470
1471        return skb;
1472free_partial:
1473        kfree_skb(skb);
1474nomem:
1475        return NULL;
1476}
1477
1478static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1479{
1480        sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1481}
1482
1483static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1484{
1485        struct sky2_hw *hw = sky2->hw;
1486        unsigned i;
1487
1488        sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1489
1490        /* Fill Rx ring */
1491        for (i = 0; i < sky2->rx_pending; i++) {
1492                struct rx_ring_info *re = sky2->rx_ring + i;
1493
1494                re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1495                if (!re->skb)
1496                        return -ENOMEM;
1497
1498                if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1499                        dev_kfree_skb(re->skb);
1500                        re->skb = NULL;
1501                        return -ENOMEM;
1502                }
1503        }
1504        return 0;
1505}
1506
1507/*
1508 * Setup receiver buffer pool.
1509 * Normal case this ends up creating one list element for skb
1510 * in the receive ring. Worst case if using large MTU and each
1511 * allocation falls on a different 64 bit region, that results
1512 * in 6 list elements per ring entry.
1513 * One element is used for checksum enable/disable, and one
1514 * extra to avoid wrap.
1515 */
1516static void sky2_rx_start(struct sky2_port *sky2)
1517{
1518        struct sky2_hw *hw = sky2->hw;
1519        struct rx_ring_info *re;
1520        unsigned rxq = rxqaddr[sky2->port];
1521        unsigned i, thresh;
1522
1523        sky2->rx_put = sky2->rx_next = 0;
1524        sky2_qset(hw, rxq);
1525
1526        /* On PCI express lowering the watermark gives better performance */
1527        if (pci_is_pcie(hw->pdev))
1528                sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1529
1530        /* These chips have no ram buffer?
1531         * MAC Rx RAM Read is controlled by hardware */
1532        if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1533            hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1534                sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1535
1536        sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1537
1538        if (!(hw->flags & SKY2_HW_NEW_LE))
1539                rx_set_checksum(sky2);
1540
1541        if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1542                rx_set_rss(sky2->netdev, sky2->netdev->features);
1543
1544        /* submit Rx ring */
1545        for (i = 0; i < sky2->rx_pending; i++) {
1546                re = sky2->rx_ring + i;
1547                sky2_rx_submit(sky2, re);
1548        }
1549
1550        /*
1551         * The receiver hangs if it receives frames larger than the
1552         * packet buffer. As a workaround, truncate oversize frames, but
1553         * the register is limited to 9 bits, so if you do frames > 2052
1554         * you better get the MTU right!
1555         */
1556        thresh = sky2_get_rx_threshold(sky2);
1557        if (thresh > 0x1ff)
1558                sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1559        else {
1560                sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1561                sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1562        }
1563
1564        /* Tell chip about available buffers */
1565        sky2_rx_update(sky2, rxq);
1566
1567        if (hw->chip_id == CHIP_ID_YUKON_EX ||
1568            hw->chip_id == CHIP_ID_YUKON_SUPR) {
1569                /*
1570                 * Disable flushing of non ASF packets;
1571                 * must be done after initializing the BMUs;
1572                 * drivers without ASF support should do this too, otherwise
1573                 * it may happen that they cannot run on ASF devices;
1574                 * remember that the MAC FIFO isn't reset during initialization.
1575                 */
1576                sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1577        }
1578
1579        if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1580                /* Enable RX Home Address & Routing Header checksum fix */
1581                sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1582                             RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1583
1584                /* Enable TX Home Address & Routing Header checksum fix */
1585                sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1586                             TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1587        }
1588}
1589
1590static int sky2_alloc_buffers(struct sky2_port *sky2)
1591{
1592        struct sky2_hw *hw = sky2->hw;
1593
1594        /* must be power of 2 */
1595        sky2->tx_le = pci_alloc_consistent(hw->pdev,
1596                                           sky2->tx_ring_size *
1597                                           sizeof(struct sky2_tx_le),
1598                                           &sky2->tx_le_map);
1599        if (!sky2->tx_le)
1600                goto nomem;
1601
1602        sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1603                                GFP_KERNEL);
1604        if (!sky2->tx_ring)
1605                goto nomem;
1606
1607        sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES,
1608                                            &sky2->rx_le_map);
1609        if (!sky2->rx_le)
1610                goto nomem;
1611
1612        sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1613                                GFP_KERNEL);
1614        if (!sky2->rx_ring)
1615                goto nomem;
1616
1617        return sky2_alloc_rx_skbs(sky2);
1618nomem:
1619        return -ENOMEM;
1620}
1621
1622static void sky2_free_buffers(struct sky2_port *sky2)
1623{
1624        struct sky2_hw *hw = sky2->hw;
1625
1626        sky2_rx_clean(sky2);
1627
1628        if (sky2->rx_le) {
1629                pci_free_consistent(hw->pdev, RX_LE_BYTES,
1630                                    sky2->rx_le, sky2->rx_le_map);
1631                sky2->rx_le = NULL;
1632        }
1633        if (sky2->tx_le) {
1634                pci_free_consistent(hw->pdev,
1635                                    sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1636                                    sky2->tx_le, sky2->tx_le_map);
1637                sky2->tx_le = NULL;
1638        }
1639        kfree(sky2->tx_ring);
1640        kfree(sky2->rx_ring);
1641
1642        sky2->tx_ring = NULL;
1643        sky2->rx_ring = NULL;
1644}
1645
1646static void sky2_hw_up(struct sky2_port *sky2)
1647{
1648        struct sky2_hw *hw = sky2->hw;
1649        unsigned port = sky2->port;
1650        u32 ramsize;
1651        int cap;
1652        struct net_device *otherdev = hw->dev[sky2->port^1];
1653
1654        tx_init(sky2);
1655
1656        /*
1657         * On dual port PCI-X card, there is an problem where status
1658         * can be received out of order due to split transactions
1659         */
1660        if (otherdev && netif_running(otherdev) &&
1661            (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1662                u16 cmd;
1663
1664                cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1665                cmd &= ~PCI_X_CMD_MAX_SPLIT;
1666                sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1667        }
1668
1669        sky2_mac_init(hw, port);
1670
1671        /* Register is number of 4K blocks on internal RAM buffer. */
1672        ramsize = sky2_read8(hw, B2_E_0) * 4;
1673        if (ramsize > 0) {
1674                u32 rxspace;
1675
1676                netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1677                if (ramsize < 16)
1678                        rxspace = ramsize / 2;
1679                else
1680                        rxspace = 8 + (2*(ramsize - 16))/3;
1681
1682                sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1683                sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1684
1685                /* Make sure SyncQ is disabled */
1686                sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1687                            RB_RST_SET);
1688        }
1689
1690        sky2_qset(hw, txqaddr[port]);
1691
1692        /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1693        if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1694                sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1695
1696        /* Set almost empty threshold */
1697        if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1698            hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1699                sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1700
1701        sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1702                           sky2->tx_ring_size - 1);
1703
1704        sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1705        netdev_update_features(sky2->netdev);
1706
1707        sky2_rx_start(sky2);
1708}
1709
1710/* Setup device IRQ and enable napi to process */
1711static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1712{
1713        struct pci_dev *pdev = hw->pdev;
1714        int err;
1715
1716        err = request_irq(pdev->irq, sky2_intr,
1717                          (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1718                          name, hw);
1719        if (err)
1720                dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1721        else {
1722                hw->flags |= SKY2_HW_IRQ_SETUP;
1723
1724                napi_enable(&hw->napi);
1725                sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1726                sky2_read32(hw, B0_IMSK);
1727        }
1728
1729        return err;
1730}
1731
1732
1733/* Bring up network interface. */
1734static int sky2_open(struct net_device *dev)
1735{
1736        struct sky2_port *sky2 = netdev_priv(dev);
1737        struct sky2_hw *hw = sky2->hw;
1738        unsigned port = sky2->port;
1739        u32 imask;
1740        int err;
1741
1742        netif_carrier_off(dev);
1743
1744        err = sky2_alloc_buffers(sky2);
1745        if (err)
1746                goto err_out;
1747
1748        /* With single port, IRQ is setup when device is brought up */
1749        if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1750                goto err_out;
1751
1752        sky2_hw_up(sky2);
1753
1754        /* Enable interrupts from phy/mac for port */
1755        imask = sky2_read32(hw, B0_IMSK);
1756
1757        if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1758            hw->chip_id == CHIP_ID_YUKON_PRM ||
1759            hw->chip_id == CHIP_ID_YUKON_OP_2)
1760                imask |= Y2_IS_PHY_QLNK;        /* enable PHY Quick Link */
1761
1762        imask |= portirq_msk[port];
1763        sky2_write32(hw, B0_IMSK, imask);
1764        sky2_read32(hw, B0_IMSK);
1765
1766        netif_info(sky2, ifup, dev, "enabling interface\n");
1767
1768        return 0;
1769
1770err_out:
1771        sky2_free_buffers(sky2);
1772        return err;
1773}
1774
1775/* Modular subtraction in ring */
1776static inline int tx_inuse(const struct sky2_port *sky2)
1777{
1778        return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1779}
1780
1781/* Number of list elements available for next tx */
1782static inline int tx_avail(const struct sky2_port *sky2)
1783{
1784        return sky2->tx_pending - tx_inuse(sky2);
1785}
1786
1787/* Estimate of number of transmit list elements required */
1788static unsigned tx_le_req(const struct sk_buff *skb)
1789{
1790        unsigned count;
1791
1792        count = (skb_shinfo(skb)->nr_frags + 1)
1793                * (sizeof(dma_addr_t) / sizeof(u32));
1794
1795        if (skb_is_gso(skb))
1796                ++count;
1797        else if (sizeof(dma_addr_t) == sizeof(u32))
1798                ++count;        /* possible vlan */
1799
1800        if (skb->ip_summed == CHECKSUM_PARTIAL)
1801                ++count;
1802
1803        return count;
1804}
1805
1806static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1807{
1808        if (re->flags & TX_MAP_SINGLE)
1809                pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1810                                 dma_unmap_len(re, maplen),
1811                                 PCI_DMA_TODEVICE);
1812        else if (re->flags & TX_MAP_PAGE)
1813                pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1814                               dma_unmap_len(re, maplen),
1815                               PCI_DMA_TODEVICE);
1816        re->flags = 0;
1817}
1818
1819/*
1820 * Put one packet in ring for transmit.
1821 * A single packet can generate multiple list elements, and
1822 * the number of ring elements will probably be less than the number
1823 * of list elements used.
1824 */
1825static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1826                                   struct net_device *dev)
1827{
1828        struct sky2_port *sky2 = netdev_priv(dev);
1829        struct sky2_hw *hw = sky2->hw;
1830        struct sky2_tx_le *le = NULL;
1831        struct tx_ring_info *re;
1832        unsigned i, len;
1833        dma_addr_t mapping;
1834        u32 upper;
1835        u16 slot;
1836        u16 mss;
1837        u8 ctrl;
1838
1839        if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1840                return NETDEV_TX_BUSY;
1841
1842        len = skb_headlen(skb);
1843        mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1844
1845        if (pci_dma_mapping_error(hw->pdev, mapping))
1846                goto mapping_error;
1847
1848        slot = sky2->tx_prod;
1849        netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1850                     "tx queued, slot %u, len %d\n", slot, skb->len);
1851
1852        /* Send high bits if needed */
1853        upper = upper_32_bits(mapping);
1854        if (upper != sky2->tx_last_upper) {
1855                le = get_tx_le(sky2, &slot);
1856                le->addr = cpu_to_le32(upper);
1857                sky2->tx_last_upper = upper;
1858                le->opcode = OP_ADDR64 | HW_OWNER;
1859        }
1860
1861        /* Check for TCP Segmentation Offload */
1862        mss = skb_shinfo(skb)->gso_size;
1863        if (mss != 0) {
1864
1865                if (!(hw->flags & SKY2_HW_NEW_LE))
1866                        mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1867
1868                if (mss != sky2->tx_last_mss) {
1869                        le = get_tx_le(sky2, &slot);
1870                        le->addr = cpu_to_le32(mss);
1871
1872                        if (hw->flags & SKY2_HW_NEW_LE)
1873                                le->opcode = OP_MSS | HW_OWNER;
1874                        else
1875                                le->opcode = OP_LRGLEN | HW_OWNER;
1876                        sky2->tx_last_mss = mss;
1877                }
1878        }
1879
1880        ctrl = 0;
1881
1882        /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1883        if (skb_vlan_tag_present(skb)) {
1884                if (!le) {
1885                        le = get_tx_le(sky2, &slot);
1886                        le->addr = 0;
1887                        le->opcode = OP_VLAN|HW_OWNER;
1888                } else
1889                        le->opcode |= OP_VLAN;
1890                le->length = cpu_to_be16(skb_vlan_tag_get(skb));
1891                ctrl |= INS_VLAN;
1892        }
1893
1894        /* Handle TCP checksum offload */
1895        if (skb->ip_summed == CHECKSUM_PARTIAL) {
1896                /* On Yukon EX (some versions) encoding change. */
1897                if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1898                        ctrl |= CALSUM; /* auto checksum */
1899                else {
1900                        const unsigned offset = skb_transport_offset(skb);
1901                        u32 tcpsum;
1902
1903                        tcpsum = offset << 16;                  /* sum start */
1904                        tcpsum |= offset + skb->csum_offset;    /* sum write */
1905
1906                        ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1907                        if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1908                                ctrl |= UDPTCP;
1909
1910                        if (tcpsum != sky2->tx_tcpsum) {
1911                                sky2->tx_tcpsum = tcpsum;
1912
1913                                le = get_tx_le(sky2, &slot);
1914                                le->addr = cpu_to_le32(tcpsum);
1915                                le->length = 0; /* initial checksum value */
1916                                le->ctrl = 1;   /* one packet */
1917                                le->opcode = OP_TCPLISW | HW_OWNER;
1918                        }
1919                }
1920        }
1921
1922        re = sky2->tx_ring + slot;
1923        re->flags = TX_MAP_SINGLE;
1924        dma_unmap_addr_set(re, mapaddr, mapping);
1925        dma_unmap_len_set(re, maplen, len);
1926
1927        le = get_tx_le(sky2, &slot);
1928        le->addr = cpu_to_le32(lower_32_bits(mapping));
1929        le->length = cpu_to_le16(len);
1930        le->ctrl = ctrl;
1931        le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1932
1933
1934        for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1935                const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1936
1937                mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1938                                           skb_frag_size(frag), DMA_TO_DEVICE);
1939
1940                if (dma_mapping_error(&hw->pdev->dev, mapping))
1941                        goto mapping_unwind;
1942
1943                upper = upper_32_bits(mapping);
1944                if (upper != sky2->tx_last_upper) {
1945                        le = get_tx_le(sky2, &slot);
1946                        le->addr = cpu_to_le32(upper);
1947                        sky2->tx_last_upper = upper;
1948                        le->opcode = OP_ADDR64 | HW_OWNER;
1949                }
1950
1951                re = sky2->tx_ring + slot;
1952                re->flags = TX_MAP_PAGE;
1953                dma_unmap_addr_set(re, mapaddr, mapping);
1954                dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1955
1956                le = get_tx_le(sky2, &slot);
1957                le->addr = cpu_to_le32(lower_32_bits(mapping));
1958                le->length = cpu_to_le16(skb_frag_size(frag));
1959                le->ctrl = ctrl;
1960                le->opcode = OP_BUFFER | HW_OWNER;
1961        }
1962
1963        re->skb = skb;
1964        le->ctrl |= EOP;
1965
1966        sky2->tx_prod = slot;
1967
1968        if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1969                netif_stop_queue(dev);
1970
1971        netdev_sent_queue(dev, skb->len);
1972        sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1973
1974        return NETDEV_TX_OK;
1975
1976mapping_unwind:
1977        for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1978                re = sky2->tx_ring + i;
1979
1980                sky2_tx_unmap(hw->pdev, re);
1981        }
1982
1983mapping_error:
1984        if (net_ratelimit())
1985                dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1986        dev_kfree_skb_any(skb);
1987        return NETDEV_TX_OK;
1988}
1989
1990/*
1991 * Free ring elements from starting at tx_cons until "done"
1992 *
1993 * NB:
1994 *  1. The hardware will tell us about partial completion of multi-part
1995 *     buffers so make sure not to free skb to early.
1996 *  2. This may run in parallel start_xmit because the it only
1997 *     looks at the tail of the queue of FIFO (tx_cons), not
1998 *     the head (tx_prod)
1999 */
2000static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2001{
2002        struct net_device *dev = sky2->netdev;
2003        u16 idx;
2004        unsigned int bytes_compl = 0, pkts_compl = 0;
2005
2006        BUG_ON(done >= sky2->tx_ring_size);
2007
2008        for (idx = sky2->tx_cons; idx != done;
2009             idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2010                struct tx_ring_info *re = sky2->tx_ring + idx;
2011                struct sk_buff *skb = re->skb;
2012
2013                sky2_tx_unmap(sky2->hw->pdev, re);
2014
2015                if (skb) {
2016                        netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2017                                     "tx done %u\n", idx);
2018
2019                        pkts_compl++;
2020                        bytes_compl += skb->len;
2021
2022                        re->skb = NULL;
2023                        dev_kfree_skb_any(skb);
2024
2025                        sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2026                }
2027        }
2028
2029        sky2->tx_cons = idx;
2030        smp_mb();
2031
2032        netdev_completed_queue(dev, pkts_compl, bytes_compl);
2033
2034        u64_stats_update_begin(&sky2->tx_stats.syncp);
2035        sky2->tx_stats.packets += pkts_compl;
2036        sky2->tx_stats.bytes += bytes_compl;
2037        u64_stats_update_end(&sky2->tx_stats.syncp);
2038}
2039
2040static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2041{
2042        /* Disable Force Sync bit and Enable Alloc bit */
2043        sky2_write8(hw, SK_REG(port, TXA_CTRL),
2044                    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2045
2046        /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2047        sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2048        sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2049
2050        /* Reset the PCI FIFO of the async Tx queue */
2051        sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2052                     BMU_RST_SET | BMU_FIFO_RST);
2053
2054        /* Reset the Tx prefetch units */
2055        sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2056                     PREF_UNIT_RST_SET);
2057
2058        sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2059        sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2060
2061        sky2_read32(hw, B0_CTST);
2062}
2063
2064static void sky2_hw_down(struct sky2_port *sky2)
2065{
2066        struct sky2_hw *hw = sky2->hw;
2067        unsigned port = sky2->port;
2068        u16 ctrl;
2069
2070        /* Force flow control off */
2071        sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2072
2073        /* Stop transmitter */
2074        sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2075        sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2076
2077        sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2078                     RB_RST_SET | RB_DIS_OP_MD);
2079
2080        ctrl = gma_read16(hw, port, GM_GP_CTRL);
2081        ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2082        gma_write16(hw, port, GM_GP_CTRL, ctrl);
2083
2084        sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2085
2086        /* Workaround shared GMAC reset */
2087        if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2088              port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2089                sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2090
2091        sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2092
2093        /* Force any delayed status interrupt and NAPI */
2094        sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2095        sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2096        sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2097        sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2098
2099        sky2_rx_stop(sky2);
2100
2101        spin_lock_bh(&sky2->phy_lock);
2102        sky2_phy_power_down(hw, port);
2103        spin_unlock_bh(&sky2->phy_lock);
2104
2105        sky2_tx_reset(hw, port);
2106
2107        /* Free any pending frames stuck in HW queue */
2108        sky2_tx_complete(sky2, sky2->tx_prod);
2109}
2110
2111/* Network shutdown */
2112static int sky2_close(struct net_device *dev)
2113{
2114        struct sky2_port *sky2 = netdev_priv(dev);
2115        struct sky2_hw *hw = sky2->hw;
2116
2117        /* Never really got started! */
2118        if (!sky2->tx_le)
2119                return 0;
2120
2121        netif_info(sky2, ifdown, dev, "disabling interface\n");
2122
2123        if (hw->ports == 1) {
2124                sky2_write32(hw, B0_IMSK, 0);
2125                sky2_read32(hw, B0_IMSK);
2126
2127                napi_disable(&hw->napi);
2128                free_irq(hw->pdev->irq, hw);
2129                hw->flags &= ~SKY2_HW_IRQ_SETUP;
2130        } else {
2131                u32 imask;
2132
2133                /* Disable port IRQ */
2134                imask  = sky2_read32(hw, B0_IMSK);
2135                imask &= ~portirq_msk[sky2->port];
2136                sky2_write32(hw, B0_IMSK, imask);
2137                sky2_read32(hw, B0_IMSK);
2138
2139                synchronize_irq(hw->pdev->irq);
2140                napi_synchronize(&hw->napi);
2141        }
2142
2143        sky2_hw_down(sky2);
2144
2145        sky2_free_buffers(sky2);
2146
2147        return 0;
2148}
2149
2150static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2151{
2152        if (hw->flags & SKY2_HW_FIBRE_PHY)
2153                return SPEED_1000;
2154
2155        if (!(hw->flags & SKY2_HW_GIGABIT)) {
2156                if (aux & PHY_M_PS_SPEED_100)
2157                        return SPEED_100;
2158                else
2159                        return SPEED_10;
2160        }
2161
2162        switch (aux & PHY_M_PS_SPEED_MSK) {
2163        case PHY_M_PS_SPEED_1000:
2164                return SPEED_1000;
2165        case PHY_M_PS_SPEED_100:
2166                return SPEED_100;
2167        default:
2168                return SPEED_10;
2169        }
2170}
2171
2172static void sky2_link_up(struct sky2_port *sky2)
2173{
2174        struct sky2_hw *hw = sky2->hw;
2175        unsigned port = sky2->port;
2176        static const char *fc_name[] = {
2177                [FC_NONE]       = "none",
2178                [FC_TX]         = "tx",
2179                [FC_RX]         = "rx",
2180                [FC_BOTH]       = "both",
2181        };
2182
2183        sky2_set_ipg(sky2);
2184
2185        sky2_enable_rx_tx(sky2);
2186
2187        gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2188
2189        netif_carrier_on(sky2->netdev);
2190
2191        mod_timer(&hw->watchdog_timer, jiffies + 1);
2192
2193        /* Turn on link LED */
2194        sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2195                    LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2196
2197        netif_info(sky2, link, sky2->netdev,
2198                   "Link is up at %d Mbps, %s duplex, flow control %s\n",
2199                   sky2->speed,
2200                   sky2->duplex == DUPLEX_FULL ? "full" : "half",
2201                   fc_name[sky2->flow_status]);
2202}
2203
2204static void sky2_link_down(struct sky2_port *sky2)
2205{
2206        struct sky2_hw *hw = sky2->hw;
2207        unsigned port = sky2->port;
2208        u16 reg;
2209
2210        gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2211
2212        reg = gma_read16(hw, port, GM_GP_CTRL);
2213        reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2214        gma_write16(hw, port, GM_GP_CTRL, reg);
2215
2216        netif_carrier_off(sky2->netdev);
2217
2218        /* Turn off link LED */
2219        sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2220
2221        netif_info(sky2, link, sky2->netdev, "Link is down\n");
2222
2223        sky2_phy_init(hw, port);
2224}
2225
2226static enum flow_control sky2_flow(int rx, int tx)
2227{
2228        if (rx)
2229                return tx ? FC_BOTH : FC_RX;
2230        else
2231                return tx ? FC_TX : FC_NONE;
2232}
2233
2234static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2235{
2236        struct sky2_hw *hw = sky2->hw;
2237        unsigned port = sky2->port;
2238        u16 advert, lpa;
2239
2240        advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2241        lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2242        if (lpa & PHY_M_AN_RF) {
2243                netdev_err(sky2->netdev, "remote fault\n");
2244                return -1;
2245        }
2246
2247        if (!(aux & PHY_M_PS_SPDUP_RES)) {
2248                netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2249                return -1;
2250        }
2251
2252        sky2->speed = sky2_phy_speed(hw, aux);
2253        sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2254
2255        /* Since the pause result bits seem to in different positions on
2256         * different chips. look at registers.
2257         */
2258        if (hw->flags & SKY2_HW_FIBRE_PHY) {
2259                /* Shift for bits in fiber PHY */
2260                advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2261                lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2262
2263                if (advert & ADVERTISE_1000XPAUSE)
2264                        advert |= ADVERTISE_PAUSE_CAP;
2265                if (advert & ADVERTISE_1000XPSE_ASYM)
2266                        advert |= ADVERTISE_PAUSE_ASYM;
2267                if (lpa & LPA_1000XPAUSE)
2268                        lpa |= LPA_PAUSE_CAP;
2269                if (lpa & LPA_1000XPAUSE_ASYM)
2270                        lpa |= LPA_PAUSE_ASYM;
2271        }
2272
2273        sky2->flow_status = FC_NONE;
2274        if (advert & ADVERTISE_PAUSE_CAP) {
2275                if (lpa & LPA_PAUSE_CAP)
2276                        sky2->flow_status = FC_BOTH;
2277                else if (advert & ADVERTISE_PAUSE_ASYM)
2278                        sky2->flow_status = FC_RX;
2279        } else if (advert & ADVERTISE_PAUSE_ASYM) {
2280                if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2281                        sky2->flow_status = FC_TX;
2282        }
2283
2284        if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2285            !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2286                sky2->flow_status = FC_NONE;
2287
2288        if (sky2->flow_status & FC_TX)
2289                sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2290        else
2291                sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2292
2293        return 0;
2294}
2295
2296/* Interrupt from PHY */
2297static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2298{
2299        struct net_device *dev = hw->dev[port];
2300        struct sky2_port *sky2 = netdev_priv(dev);
2301        u16 istatus, phystat;
2302
2303        if (!netif_running(dev))
2304                return;
2305
2306        spin_lock(&sky2->phy_lock);
2307        istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2308        phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2309
2310        netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2311                   istatus, phystat);
2312
2313        if (istatus & PHY_M_IS_AN_COMPL) {
2314                if (sky2_autoneg_done(sky2, phystat) == 0 &&
2315                    !netif_carrier_ok(dev))
2316                        sky2_link_up(sky2);
2317                goto out;
2318        }
2319
2320        if (istatus & PHY_M_IS_LSP_CHANGE)
2321                sky2->speed = sky2_phy_speed(hw, phystat);
2322
2323        if (istatus & PHY_M_IS_DUP_CHANGE)
2324                sky2->duplex =
2325                    (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2326
2327        if (istatus & PHY_M_IS_LST_CHANGE) {
2328                if (phystat & PHY_M_PS_LINK_UP)
2329                        sky2_link_up(sky2);
2330                else
2331                        sky2_link_down(sky2);
2332        }
2333out:
2334        spin_unlock(&sky2->phy_lock);
2335}
2336
2337/* Special quick link interrupt (Yukon-2 Optima only) */
2338static void sky2_qlink_intr(struct sky2_hw *hw)
2339{
2340        struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2341        u32 imask;
2342        u16 phy;
2343
2344        /* disable irq */
2345        imask = sky2_read32(hw, B0_IMSK);
2346        imask &= ~Y2_IS_PHY_QLNK;
2347        sky2_write32(hw, B0_IMSK, imask);
2348
2349        /* reset PHY Link Detect */
2350        phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2351        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2352        sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2353        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2354
2355        sky2_link_up(sky2);
2356}
2357
2358/* Transmit timeout is only called if we are running, carrier is up
2359 * and tx queue is full (stopped).
2360 */
2361static void sky2_tx_timeout(struct net_device *dev)
2362{
2363        struct sky2_port *sky2 = netdev_priv(dev);
2364        struct sky2_hw *hw = sky2->hw;
2365
2366        netif_err(sky2, timer, dev, "tx timeout\n");
2367
2368        netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2369                      sky2->tx_cons, sky2->tx_prod,
2370                      sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2371                      sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2372
2373        /* can't restart safely under softirq */
2374        schedule_work(&hw->restart_work);
2375}
2376
2377static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2378{
2379        struct sky2_port *sky2 = netdev_priv(dev);
2380        struct sky2_hw *hw = sky2->hw;
2381        unsigned port = sky2->port;
2382        int err;
2383        u16 ctl, mode;
2384        u32 imask;
2385
2386        if (!netif_running(dev)) {
2387                dev->mtu = new_mtu;
2388                netdev_update_features(dev);
2389                return 0;
2390        }
2391
2392        imask = sky2_read32(hw, B0_IMSK);
2393        sky2_write32(hw, B0_IMSK, 0);
2394        sky2_read32(hw, B0_IMSK);
2395
2396        netif_trans_update(dev);        /* prevent tx timeout */
2397        napi_disable(&hw->napi);
2398        netif_tx_disable(dev);
2399
2400        synchronize_irq(hw->pdev->irq);
2401
2402        if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2403                sky2_set_tx_stfwd(hw, port);
2404
2405        ctl = gma_read16(hw, port, GM_GP_CTRL);
2406        gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2407        sky2_rx_stop(sky2);
2408        sky2_rx_clean(sky2);
2409
2410        dev->mtu = new_mtu;
2411        netdev_update_features(dev);
2412
2413        mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2414        if (sky2->speed > SPEED_100)
2415                mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2416        else
2417                mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2418
2419        if (dev->mtu > ETH_DATA_LEN)
2420                mode |= GM_SMOD_JUMBO_ENA;
2421
2422        gma_write16(hw, port, GM_SERIAL_MODE, mode);
2423
2424        sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2425
2426        err = sky2_alloc_rx_skbs(sky2);
2427        if (!err)
2428                sky2_rx_start(sky2);
2429        else
2430                sky2_rx_clean(sky2);
2431        sky2_write32(hw, B0_IMSK, imask);
2432
2433        sky2_read32(hw, B0_Y2_SP_LISR);
2434        napi_enable(&hw->napi);
2435
2436        if (err)
2437                dev_close(dev);
2438        else {
2439                gma_write16(hw, port, GM_GP_CTRL, ctl);
2440
2441                netif_wake_queue(dev);
2442        }
2443
2444        return err;
2445}
2446
2447static inline bool needs_copy(const struct rx_ring_info *re,
2448                              unsigned length)
2449{
2450#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2451        /* Some architectures need the IP header to be aligned */
2452        if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2453                return true;
2454#endif
2455        return length < copybreak;
2456}
2457
2458/* For small just reuse existing skb for next receive */
2459static struct sk_buff *receive_copy(struct sky2_port *sky2,
2460                                    const struct rx_ring_info *re,
2461                                    unsigned length)
2462{
2463        struct sk_buff *skb;
2464
2465        skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2466        if (likely(skb)) {
2467                pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2468                                            length, PCI_DMA_FROMDEVICE);
2469                skb_copy_from_linear_data(re->skb, skb->data, length);
2470                skb->ip_summed = re->skb->ip_summed;
2471                skb->csum = re->skb->csum;
2472                skb_copy_hash(skb, re->skb);
2473                __vlan_hwaccel_copy_tag(skb, re->skb);
2474
2475                pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2476                                               length, PCI_DMA_FROMDEVICE);
2477                __vlan_hwaccel_clear_tag(re->skb);
2478                skb_clear_hash(re->skb);
2479                re->skb->ip_summed = CHECKSUM_NONE;
2480                skb_put(skb, length);
2481        }
2482        return skb;
2483}
2484
2485/* Adjust length of skb with fragments to match received data */
2486static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2487                          unsigned int length)
2488{
2489        int i, num_frags;
2490        unsigned int size;
2491
2492        /* put header into skb */
2493        size = min(length, hdr_space);
2494        skb->tail += size;
2495        skb->len += size;
2496        length -= size;
2497
2498        num_frags = skb_shinfo(skb)->nr_frags;
2499        for (i = 0; i < num_frags; i++) {
2500                skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2501
2502                if (length == 0) {
2503                        /* don't need this page */
2504                        __skb_frag_unref(frag);
2505                        --skb_shinfo(skb)->nr_frags;
2506                } else {
2507                        size = min(length, (unsigned) PAGE_SIZE);
2508
2509                        skb_frag_size_set(frag, size);
2510                        skb->data_len += size;
2511                        skb->truesize += PAGE_SIZE;
2512                        skb->len += size;
2513                        length -= size;
2514                }
2515        }
2516}
2517
2518/* Normal packet - take skb from ring element and put in a new one  */
2519static struct sk_buff *receive_new(struct sky2_port *sky2,
2520                                   struct rx_ring_info *re,
2521                                   unsigned int length)
2522{
2523        struct sk_buff *skb;
2524        struct rx_ring_info nre;
2525        unsigned hdr_space = sky2->rx_data_size;
2526
2527        nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2528        if (unlikely(!nre.skb))
2529                goto nobuf;
2530
2531        if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2532                goto nomap;
2533
2534        skb = re->skb;
2535        sky2_rx_unmap_skb(sky2->hw->pdev, re);
2536        prefetch(skb->data);
2537        *re = nre;
2538
2539        if (skb_shinfo(skb)->nr_frags)
2540                skb_put_frags(skb, hdr_space, length);
2541        else
2542                skb_put(skb, length);
2543        return skb;
2544
2545nomap:
2546        dev_kfree_skb(nre.skb);
2547nobuf:
2548        return NULL;
2549}
2550
2551/*
2552 * Receive one packet.
2553 * For larger packets, get new buffer.
2554 */
2555static struct sk_buff *sky2_receive(struct net_device *dev,
2556                                    u16 length, u32 status)
2557{
2558        struct sky2_port *sky2 = netdev_priv(dev);
2559        struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2560        struct sk_buff *skb = NULL;
2561        u16 count = (status & GMR_FS_LEN) >> 16;
2562
2563        netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2564                     "rx slot %u status 0x%x len %d\n",
2565                     sky2->rx_next, status, length);
2566
2567        sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2568        prefetch(sky2->rx_ring + sky2->rx_next);
2569
2570        if (skb_vlan_tag_present(re->skb))
2571                count -= VLAN_HLEN;     /* Account for vlan tag */
2572
2573        /* This chip has hardware problems that generates bogus status.
2574         * So do only marginal checking and expect higher level protocols
2575         * to handle crap frames.
2576         */
2577        if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2578            sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2579            length != count)
2580                goto okay;
2581
2582        if (status & GMR_FS_ANY_ERR)
2583                goto error;
2584
2585        if (!(status & GMR_FS_RX_OK))
2586                goto resubmit;
2587
2588        /* if length reported by DMA does not match PHY, packet was truncated */
2589        if (length != count)
2590                goto error;
2591
2592okay:
2593        if (needs_copy(re, length))
2594                skb = receive_copy(sky2, re, length);
2595        else
2596                skb = receive_new(sky2, re, length);
2597
2598        dev->stats.rx_dropped += (skb == NULL);
2599
2600resubmit:
2601        sky2_rx_submit(sky2, re);
2602
2603        return skb;
2604
2605error:
2606        ++dev->stats.rx_errors;
2607
2608        if (net_ratelimit())
2609                netif_info(sky2, rx_err, dev,
2610                           "rx error, status 0x%x length %d\n", status, length);
2611
2612        goto resubmit;
2613}
2614
2615/* Transmit complete */
2616static inline void sky2_tx_done(struct net_device *dev, u16 last)
2617{
2618        struct sky2_port *sky2 = netdev_priv(dev);
2619
2620        if (netif_running(dev)) {
2621                sky2_tx_complete(sky2, last);
2622
2623                /* Wake unless it's detached, and called e.g. from sky2_close() */
2624                if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2625                        netif_wake_queue(dev);
2626        }
2627}
2628
2629static inline void sky2_skb_rx(const struct sky2_port *sky2,
2630                               struct sk_buff *skb)
2631{
2632        if (skb->ip_summed == CHECKSUM_NONE)
2633                netif_receive_skb(skb);
2634        else
2635                napi_gro_receive(&sky2->hw->napi, skb);
2636}
2637
2638static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2639                                unsigned packets, unsigned bytes)
2640{
2641        struct net_device *dev = hw->dev[port];
2642        struct sky2_port *sky2 = netdev_priv(dev);
2643
2644        if (packets == 0)
2645                return;
2646
2647        u64_stats_update_begin(&sky2->rx_stats.syncp);
2648        sky2->rx_stats.packets += packets;
2649        sky2->rx_stats.bytes += bytes;
2650        u64_stats_update_end(&sky2->rx_stats.syncp);
2651
2652        sky2->last_rx = jiffies;
2653        sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2654}
2655
2656static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2657{
2658        /* If this happens then driver assuming wrong format for chip type */
2659        BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2660
2661        /* Both checksum counters are programmed to start at
2662         * the same offset, so unless there is a problem they
2663         * should match. This failure is an early indication that
2664         * hardware receive checksumming won't work.
2665         */
2666        if (likely((u16)(status >> 16) == (u16)status)) {
2667                struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2668                skb->ip_summed = CHECKSUM_COMPLETE;
2669                skb->csum = le16_to_cpu(status);
2670        } else {
2671                dev_notice(&sky2->hw->pdev->dev,
2672                           "%s: receive checksum problem (status = %#x)\n",
2673                           sky2->netdev->name, status);
2674
2675                /* Disable checksum offload
2676                 * It will be reenabled on next ndo_set_features, but if it's
2677                 * really broken, will get disabled again
2678                 */
2679                sky2->netdev->features &= ~NETIF_F_RXCSUM;
2680                sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2681                             BMU_DIS_RX_CHKSUM);
2682        }
2683}
2684
2685static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2686{
2687        struct sk_buff *skb;
2688
2689        skb = sky2->rx_ring[sky2->rx_next].skb;
2690        __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2691}
2692
2693static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2694{
2695        struct sk_buff *skb;
2696
2697        skb = sky2->rx_ring[sky2->rx_next].skb;
2698        skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3);
2699}
2700
2701/* Process status response ring */
2702static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2703{
2704        int work_done = 0;
2705        unsigned int total_bytes[2] = { 0 };
2706        unsigned int total_packets[2] = { 0 };
2707
2708        if (to_do <= 0)
2709                return work_done;
2710
2711        rmb();
2712        do {
2713                struct sky2_port *sky2;
2714                struct sky2_status_le *le  = hw->st_le + hw->st_idx;
2715                unsigned port;
2716                struct net_device *dev;
2717                struct sk_buff *skb;
2718                u32 status;
2719                u16 length;
2720                u8 opcode = le->opcode;
2721
2722                if (!(opcode & HW_OWNER))
2723                        break;
2724
2725                hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2726
2727                port = le->css & CSS_LINK_BIT;
2728                dev = hw->dev[port];
2729                sky2 = netdev_priv(dev);
2730                length = le16_to_cpu(le->length);
2731                status = le32_to_cpu(le->status);
2732
2733                le->opcode = 0;
2734                switch (opcode & ~HW_OWNER) {
2735                case OP_RXSTAT:
2736                        total_packets[port]++;
2737                        total_bytes[port] += length;
2738
2739                        skb = sky2_receive(dev, length, status);
2740                        if (!skb)
2741                                break;
2742
2743                        /* This chip reports checksum status differently */
2744                        if (hw->flags & SKY2_HW_NEW_LE) {
2745                                if ((dev->features & NETIF_F_RXCSUM) &&
2746                                    (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2747                                    (le->css & CSS_TCPUDPCSOK))
2748                                        skb->ip_summed = CHECKSUM_UNNECESSARY;
2749                                else
2750                                        skb->ip_summed = CHECKSUM_NONE;
2751                        }
2752
2753                        skb->protocol = eth_type_trans(skb, dev);
2754                        sky2_skb_rx(sky2, skb);
2755
2756                        /* Stop after net poll weight */
2757                        if (++work_done >= to_do)
2758                                goto exit_loop;
2759                        break;
2760
2761                case OP_RXVLAN:
2762                        sky2_rx_tag(sky2, length);
2763                        break;
2764
2765                case OP_RXCHKSVLAN:
2766                        sky2_rx_tag(sky2, length);
2767                        /* fall through */
2768                case OP_RXCHKS:
2769                        if (likely(dev->features & NETIF_F_RXCSUM))
2770                                sky2_rx_checksum(sky2, status);
2771                        break;
2772
2773                case OP_RSS_HASH:
2774                        sky2_rx_hash(sky2, status);
2775                        break;
2776
2777                case OP_TXINDEXLE:
2778                        /* TX index reports status for both ports */
2779                        sky2_tx_done(hw->dev[0], status & 0xfff);
2780                        if (hw->dev[1])
2781                                sky2_tx_done(hw->dev[1],
2782                                     ((status >> 24) & 0xff)
2783                                             | (u16)(length & 0xf) << 8);
2784                        break;
2785
2786                default:
2787                        if (net_ratelimit())
2788                                pr_warn("unknown status opcode 0x%x\n", opcode);
2789                }
2790        } while (hw->st_idx != idx);
2791
2792        /* Fully processed status ring so clear irq */
2793        sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2794
2795exit_loop:
2796        sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2797        sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2798
2799        return work_done;
2800}
2801
2802static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2803{
2804        struct net_device *dev = hw->dev[port];
2805
2806        if (net_ratelimit())
2807                netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2808
2809        if (status & Y2_IS_PAR_RD1) {
2810                if (net_ratelimit())
2811                        netdev_err(dev, "ram data read parity error\n");
2812                /* Clear IRQ */
2813                sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2814        }
2815
2816        if (status & Y2_IS_PAR_WR1) {
2817                if (net_ratelimit())
2818                        netdev_err(dev, "ram data write parity error\n");
2819
2820                sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2821        }
2822
2823        if (status & Y2_IS_PAR_MAC1) {
2824                if (net_ratelimit())
2825                        netdev_err(dev, "MAC parity error\n");
2826                sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2827        }
2828
2829        if (status & Y2_IS_PAR_RX1) {
2830                if (net_ratelimit())
2831                        netdev_err(dev, "RX parity error\n");
2832                sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2833        }
2834
2835        if (status & Y2_IS_TCP_TXA1) {
2836                if (net_ratelimit())
2837                        netdev_err(dev, "TCP segmentation error\n");
2838                sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2839        }
2840}
2841
2842static void sky2_hw_intr(struct sky2_hw *hw)
2843{
2844        struct pci_dev *pdev = hw->pdev;
2845        u32 status = sky2_read32(hw, B0_HWE_ISRC);
2846        u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2847
2848        status &= hwmsk;
2849
2850        if (status & Y2_IS_TIST_OV)
2851                sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2852
2853        if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2854                u16 pci_err;
2855
2856                sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2857                pci_err = sky2_pci_read16(hw, PCI_STATUS);
2858                if (net_ratelimit())
2859                        dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2860                                pci_err);
2861
2862                sky2_pci_write16(hw, PCI_STATUS,
2863                                      pci_err | PCI_STATUS_ERROR_BITS);
2864                sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2865        }
2866
2867        if (status & Y2_IS_PCI_EXP) {
2868                /* PCI-Express uncorrectable Error occurred */
2869                u32 err;
2870
2871                sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2872                err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2873                sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2874                             0xfffffffful);
2875                if (net_ratelimit())
2876                        dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2877
2878                sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2879                sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2880        }
2881
2882        if (status & Y2_HWE_L1_MASK)
2883                sky2_hw_error(hw, 0, status);
2884        status >>= 8;
2885        if (status & Y2_HWE_L1_MASK)
2886                sky2_hw_error(hw, 1, status);
2887}
2888
2889static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2890{
2891        struct net_device *dev = hw->dev[port];
2892        struct sky2_port *sky2 = netdev_priv(dev);
2893        u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2894
2895        netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2896
2897        if (status & GM_IS_RX_CO_OV)
2898                gma_read16(hw, port, GM_RX_IRQ_SRC);
2899
2900        if (status & GM_IS_TX_CO_OV)
2901                gma_read16(hw, port, GM_TX_IRQ_SRC);
2902
2903        if (status & GM_IS_RX_FF_OR) {
2904                ++dev->stats.rx_fifo_errors;
2905                sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2906        }
2907
2908        if (status & GM_IS_TX_FF_UR) {
2909                ++dev->stats.tx_fifo_errors;
2910                sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2911        }
2912}
2913
2914/* This should never happen it is a bug. */
2915static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2916{
2917        struct net_device *dev = hw->dev[port];
2918        u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2919
2920        dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2921                dev->name, (unsigned) q, (unsigned) idx,
2922                (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2923
2924        sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2925}
2926
2927static int sky2_rx_hung(struct net_device *dev)
2928{
2929        struct sky2_port *sky2 = netdev_priv(dev);
2930        struct sky2_hw *hw = sky2->hw;
2931        unsigned port = sky2->port;
2932        unsigned rxq = rxqaddr[port];
2933        u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2934        u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2935        u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2936        u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2937
2938        /* If idle and MAC or PCI is stuck */
2939        if (sky2->check.last == sky2->last_rx &&
2940            ((mac_rp == sky2->check.mac_rp &&
2941              mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2942             /* Check if the PCI RX hang */
2943             (fifo_rp == sky2->check.fifo_rp &&
2944              fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2945                netdev_printk(KERN_DEBUG, dev,
2946                              "hung mac %d:%d fifo %d (%d:%d)\n",
2947                              mac_lev, mac_rp, fifo_lev,
2948                              fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2949                return 1;
2950        } else {
2951                sky2->check.last = sky2->last_rx;
2952                sky2->check.mac_rp = mac_rp;
2953                sky2->check.mac_lev = mac_lev;
2954                sky2->check.fifo_rp = fifo_rp;
2955                sky2->check.fifo_lev = fifo_lev;
2956                return 0;
2957        }
2958}
2959
2960static void sky2_watchdog(struct timer_list *t)
2961{
2962        struct sky2_hw *hw = from_timer(hw, t, watchdog_timer);
2963
2964        /* Check for lost IRQ once a second */
2965        if (sky2_read32(hw, B0_ISRC)) {
2966                napi_schedule(&hw->napi);
2967        } else {
2968                int i, active = 0;
2969
2970                for (i = 0; i < hw->ports; i++) {
2971                        struct net_device *dev = hw->dev[i];
2972                        if (!netif_running(dev))
2973                                continue;
2974                        ++active;
2975
2976                        /* For chips with Rx FIFO, check if stuck */
2977                        if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2978                             sky2_rx_hung(dev)) {
2979                                netdev_info(dev, "receiver hang detected\n");
2980                                schedule_work(&hw->restart_work);
2981                                return;
2982                        }
2983                }
2984
2985                if (active == 0)
2986                        return;
2987        }
2988
2989        mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2990}
2991
2992/* Hardware/software error handling */
2993static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2994{
2995        if (net_ratelimit())
2996                dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2997
2998        if (status & Y2_IS_HW_ERR)
2999                sky2_hw_intr(hw);
3000
3001        if (status & Y2_IS_IRQ_MAC1)
3002                sky2_mac_intr(hw, 0);
3003
3004        if (status & Y2_IS_IRQ_MAC2)
3005                sky2_mac_intr(hw, 1);
3006
3007        if (status & Y2_IS_CHK_RX1)
3008                sky2_le_error(hw, 0, Q_R1);
3009
3010        if (status & Y2_IS_CHK_RX2)
3011                sky2_le_error(hw, 1, Q_R2);
3012
3013        if (status & Y2_IS_CHK_TXA1)
3014                sky2_le_error(hw, 0, Q_XA1);
3015
3016        if (status & Y2_IS_CHK_TXA2)
3017                sky2_le_error(hw, 1, Q_XA2);
3018}
3019
3020static int sky2_poll(struct napi_struct *napi, int work_limit)
3021{
3022        struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3023        u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3024        int work_done = 0;
3025        u16 idx;
3026
3027        if (unlikely(status & Y2_IS_ERROR))
3028                sky2_err_intr(hw, status);
3029
3030        if (status & Y2_IS_IRQ_PHY1)
3031                sky2_phy_intr(hw, 0);
3032
3033        if (status & Y2_IS_IRQ_PHY2)
3034                sky2_phy_intr(hw, 1);
3035
3036        if (status & Y2_IS_PHY_QLNK)
3037                sky2_qlink_intr(hw);
3038
3039        while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3040                work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3041
3042                if (work_done >= work_limit)
3043                        goto done;
3044        }
3045
3046        napi_complete_done(napi, work_done);
3047        sky2_read32(hw, B0_Y2_SP_LISR);
3048done:
3049
3050        return work_done;
3051}
3052
3053static irqreturn_t sky2_intr(int irq, void *dev_id)
3054{
3055        struct sky2_hw *hw = dev_id;
3056        u32 status;
3057
3058        /* Reading this mask interrupts as side effect */
3059        status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3060        if (status == 0 || status == ~0) {
3061                sky2_write32(hw, B0_Y2_SP_ICR, 2);
3062                return IRQ_NONE;
3063        }
3064
3065        prefetch(&hw->st_le[hw->st_idx]);
3066
3067        napi_schedule(&hw->napi);
3068
3069        return IRQ_HANDLED;
3070}
3071
3072#ifdef CONFIG_NET_POLL_CONTROLLER
3073static void sky2_netpoll(struct net_device *dev)
3074{
3075        struct sky2_port *sky2 = netdev_priv(dev);
3076
3077        napi_schedule(&sky2->hw->napi);
3078}
3079#endif
3080
3081/* Chip internal frequency for clock calculations */
3082static u32 sky2_mhz(const struct sky2_hw *hw)
3083{
3084        switch (hw->chip_id) {
3085        case CHIP_ID_YUKON_EC:
3086        case CHIP_ID_YUKON_EC_U:
3087        case CHIP_ID_YUKON_EX:
3088        case CHIP_ID_YUKON_SUPR:
3089        case CHIP_ID_YUKON_UL_2:
3090        case CHIP_ID_YUKON_OPT:
3091        case CHIP_ID_YUKON_PRM:
3092        case CHIP_ID_YUKON_OP_2:
3093                return 125;
3094
3095        case CHIP_ID_YUKON_FE:
3096                return 100;
3097
3098        case CHIP_ID_YUKON_FE_P:
3099                return 50;
3100
3101        case CHIP_ID_YUKON_XL:
3102                return 156;
3103
3104        default:
3105                BUG();
3106        }
3107}
3108
3109static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3110{
3111        return sky2_mhz(hw) * us;
3112}
3113
3114static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3115{
3116        return clk / sky2_mhz(hw);
3117}
3118
3119
3120static int sky2_init(struct sky2_hw *hw)
3121{
3122        u8 t8;
3123
3124        /* Enable all clocks and check for bad PCI access */
3125        sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3126
3127        sky2_write8(hw, B0_CTST, CS_RST_CLR);
3128
3129        hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3130        hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3131
3132        switch (hw->chip_id) {
3133        case CHIP_ID_YUKON_XL:
3134                hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3135                if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3136                        hw->flags |= SKY2_HW_RSS_BROKEN;
3137                break;
3138
3139        case CHIP_ID_YUKON_EC_U:
3140                hw->flags = SKY2_HW_GIGABIT
3141                        | SKY2_HW_NEWER_PHY
3142                        | SKY2_HW_ADV_POWER_CTL;
3143                break;
3144
3145        case CHIP_ID_YUKON_EX:
3146                hw->flags = SKY2_HW_GIGABIT
3147                        | SKY2_HW_NEWER_PHY
3148                        | SKY2_HW_NEW_LE
3149                        | SKY2_HW_ADV_POWER_CTL
3150                        | SKY2_HW_RSS_CHKSUM;
3151
3152                /* New transmit checksum */
3153                if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3154                        hw->flags |= SKY2_HW_AUTO_TX_SUM;
3155                break;
3156
3157        case CHIP_ID_YUKON_EC:
3158                /* This rev is really old, and requires untested workarounds */
3159                if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3160                        dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3161                        return -EOPNOTSUPP;
3162                }
3163                hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3164                break;
3165
3166        case CHIP_ID_YUKON_FE:
3167                hw->flags = SKY2_HW_RSS_BROKEN;
3168                break;
3169
3170        case CHIP_ID_YUKON_FE_P:
3171                hw->flags = SKY2_HW_NEWER_PHY
3172                        | SKY2_HW_NEW_LE
3173                        | SKY2_HW_AUTO_TX_SUM
3174                        | SKY2_HW_ADV_POWER_CTL;
3175
3176                /* The workaround for status conflicts VLAN tag detection. */
3177                if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3178                        hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3179                break;
3180
3181        case CHIP_ID_YUKON_SUPR:
3182                hw->flags = SKY2_HW_GIGABIT
3183                        | SKY2_HW_NEWER_PHY
3184                        | SKY2_HW_NEW_LE
3185                        | SKY2_HW_AUTO_TX_SUM
3186                        | SKY2_HW_ADV_POWER_CTL;
3187
3188                if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3189                        hw->flags |= SKY2_HW_RSS_CHKSUM;
3190                break;
3191
3192        case CHIP_ID_YUKON_UL_2:
3193                hw->flags = SKY2_HW_GIGABIT
3194                        | SKY2_HW_ADV_POWER_CTL;
3195                break;
3196
3197        case CHIP_ID_YUKON_OPT:
3198        case CHIP_ID_YUKON_PRM:
3199        case CHIP_ID_YUKON_OP_2:
3200                hw->flags = SKY2_HW_GIGABIT
3201                        | SKY2_HW_NEW_LE
3202                        | SKY2_HW_ADV_POWER_CTL;
3203                break;
3204
3205        default:
3206                dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3207                        hw->chip_id);
3208                return -EOPNOTSUPP;
3209        }
3210
3211        hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3212        if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3213                hw->flags |= SKY2_HW_FIBRE_PHY;
3214
3215        hw->ports = 1;
3216        t8 = sky2_read8(hw, B2_Y2_HW_RES);
3217        if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3218                if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3219                        ++hw->ports;
3220        }
3221
3222        if (sky2_read8(hw, B2_E_0))
3223                hw->flags |= SKY2_HW_RAM_BUFFER;
3224
3225        return 0;
3226}
3227
3228static void sky2_reset(struct sky2_hw *hw)
3229{
3230        struct pci_dev *pdev = hw->pdev;
3231        u16 status;
3232        int i;
3233        u32 hwe_mask = Y2_HWE_ALL_MASK;
3234
3235        /* disable ASF */
3236        if (hw->chip_id == CHIP_ID_YUKON_EX
3237            || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3238                sky2_write32(hw, CPU_WDOG, 0);
3239                status = sky2_read16(hw, HCU_CCSR);
3240                status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3241                            HCU_CCSR_UC_STATE_MSK);
3242                /*
3243                 * CPU clock divider shouldn't be used because
3244                 * - ASF firmware may malfunction
3245                 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3246                 */
3247                status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3248                sky2_write16(hw, HCU_CCSR, status);
3249                sky2_write32(hw, CPU_WDOG, 0);
3250        } else
3251                sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3252        sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3253
3254        /* do a SW reset */
3255        sky2_write8(hw, B0_CTST, CS_RST_SET);
3256        sky2_write8(hw, B0_CTST, CS_RST_CLR);
3257
3258        /* allow writes to PCI config */
3259        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3260
3261        /* clear PCI errors, if any */
3262        status = sky2_pci_read16(hw, PCI_STATUS);
3263        status |= PCI_STATUS_ERROR_BITS;
3264        sky2_pci_write16(hw, PCI_STATUS, status);
3265
3266        sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3267
3268        if (pci_is_pcie(pdev)) {
3269                sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3270                             0xfffffffful);
3271
3272                /* If error bit is stuck on ignore it */
3273                if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3274                        dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3275                else
3276                        hwe_mask |= Y2_IS_PCI_EXP;
3277        }
3278
3279        sky2_power_on(hw);
3280        sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3281
3282        for (i = 0; i < hw->ports; i++) {
3283                sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3284                sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3285
3286                if (hw->chip_id == CHIP_ID_YUKON_EX ||
3287                    hw->chip_id == CHIP_ID_YUKON_SUPR)
3288                        sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3289                                     GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3290                                     | GMC_BYP_RETR_ON);
3291
3292        }
3293
3294        if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3295                /* enable MACSec clock gating */
3296                sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3297        }
3298
3299        if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3300            hw->chip_id == CHIP_ID_YUKON_PRM ||
3301            hw->chip_id == CHIP_ID_YUKON_OP_2) {
3302                u16 reg;
3303
3304                if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3305                        /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3306                        sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3307
3308                        /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3309                        reg = 10;
3310
3311                        /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3312                        sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3313                } else {
3314                        /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3315                        reg = 3;
3316                }
3317
3318                reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3319                reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3320
3321                /* reset PHY Link Detect */
3322                sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3323                sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3324
3325                /* check if PSMv2 was running before */
3326                reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3327                if (reg & PCI_EXP_LNKCTL_ASPMC)
3328                        /* restore the PCIe Link Control register */
3329                        sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3330                                         reg);
3331
3332                if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3333                        hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3334                        /* change PHY Interrupt polarity to low active */
3335                        reg = sky2_read16(hw, GPHY_CTRL);
3336                        sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3337
3338                        /* adapt HW for low active PHY Interrupt */
3339                        reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3340                        sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3341                }
3342
3343                sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3344
3345                /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3346                sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3347        }
3348
3349        /* Clear I2C IRQ noise */
3350        sky2_write32(hw, B2_I2C_IRQ, 1);
3351
3352        /* turn off hardware timer (unused) */
3353        sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3354        sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3355
3356        /* Turn off descriptor polling */
3357        sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3358
3359        /* Turn off receive timestamp */
3360        sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3361        sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3362
3363        /* enable the Tx Arbiters */
3364        for (i = 0; i < hw->ports; i++)
3365                sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3366
3367        /* Initialize ram interface */
3368        for (i = 0; i < hw->ports; i++) {
3369                sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3370
3371                sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3372                sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3373                sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3374                sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3375                sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3376                sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3377                sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3378                sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3379                sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3380                sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3381                sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3382                sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3383        }
3384
3385        sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3386
3387        for (i = 0; i < hw->ports; i++)
3388                sky2_gmac_reset(hw, i);
3389
3390        memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3391        hw->st_idx = 0;
3392
3393        sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3394        sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3395
3396        sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3397        sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3398
3399        /* Set the list last index */
3400        sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3401
3402        sky2_write16(hw, STAT_TX_IDX_TH, 10);
3403        sky2_write8(hw, STAT_FIFO_WM, 16);
3404
3405        /* set Status-FIFO ISR watermark */
3406        if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3407                sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3408        else
3409                sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3410
3411        sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3412        sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3413        sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3414
3415        /* enable status unit */
3416        sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3417
3418        sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3419        sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3420        sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3421}
3422
3423/* Take device down (offline).
3424 * Equivalent to doing dev_stop() but this does not
3425 * inform upper layers of the transition.
3426 */
3427static void sky2_detach(struct net_device *dev)
3428{
3429        if (netif_running(dev)) {
3430                netif_tx_lock(dev);
3431                netif_device_detach(dev);       /* stop txq */
3432                netif_tx_unlock(dev);
3433                sky2_close(dev);
3434        }
3435}
3436
3437/* Bring device back after doing sky2_detach */
3438static int sky2_reattach(struct net_device *dev)
3439{
3440        int err = 0;
3441
3442        if (netif_running(dev)) {
3443                err = sky2_open(dev);
3444                if (err) {
3445                        netdev_info(dev, "could not restart %d\n", err);
3446                        dev_close(dev);
3447                } else {
3448                        netif_device_attach(dev);
3449                        sky2_set_multicast(dev);
3450                }
3451        }
3452
3453        return err;
3454}
3455
3456static void sky2_all_down(struct sky2_hw *hw)
3457{
3458        int i;
3459
3460        if (hw->flags & SKY2_HW_IRQ_SETUP) {
3461                sky2_write32(hw, B0_IMSK, 0);
3462                sky2_read32(hw, B0_IMSK);
3463
3464                synchronize_irq(hw->pdev->irq);
3465                napi_disable(&hw->napi);
3466        }
3467
3468        for (i = 0; i < hw->ports; i++) {
3469                struct net_device *dev = hw->dev[i];
3470                struct sky2_port *sky2 = netdev_priv(dev);
3471
3472                if (!netif_running(dev))
3473                        continue;
3474
3475                netif_carrier_off(dev);
3476                netif_tx_disable(dev);
3477                sky2_hw_down(sky2);
3478        }
3479}
3480
3481static void sky2_all_up(struct sky2_hw *hw)
3482{
3483        u32 imask = Y2_IS_BASE;
3484        int i;
3485
3486        for (i = 0; i < hw->ports; i++) {
3487                struct net_device *dev = hw->dev[i];
3488                struct sky2_port *sky2 = netdev_priv(dev);
3489
3490                if (!netif_running(dev))
3491                        continue;
3492
3493                sky2_hw_up(sky2);
3494                sky2_set_multicast(dev);
3495                imask |= portirq_msk[i];
3496                netif_wake_queue(dev);
3497        }
3498
3499        if (hw->flags & SKY2_HW_IRQ_SETUP) {
3500                sky2_write32(hw, B0_IMSK, imask);
3501                sky2_read32(hw, B0_IMSK);
3502                sky2_read32(hw, B0_Y2_SP_LISR);
3503                napi_enable(&hw->napi);
3504        }
3505}
3506
3507static void sky2_restart(struct work_struct *work)
3508{
3509        struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3510
3511        rtnl_lock();
3512
3513        sky2_all_down(hw);
3514        sky2_reset(hw);
3515        sky2_all_up(hw);
3516
3517        rtnl_unlock();
3518}
3519
3520static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3521{
3522        return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3523}
3524
3525static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3526{
3527        const struct sky2_port *sky2 = netdev_priv(dev);
3528
3529        wol->supported = sky2_wol_supported(sky2->hw);
3530        wol->wolopts = sky2->wol;
3531}
3532
3533static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3534{
3535        struct sky2_port *sky2 = netdev_priv(dev);
3536        struct sky2_hw *hw = sky2->hw;
3537        bool enable_wakeup = false;
3538        int i;
3539
3540        if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3541            !device_can_wakeup(&hw->pdev->dev))
3542                return -EOPNOTSUPP;
3543
3544        sky2->wol = wol->wolopts;
3545
3546        for (i = 0; i < hw->ports; i++) {
3547                struct net_device *dev = hw->dev[i];
3548                struct sky2_port *sky2 = netdev_priv(dev);
3549
3550                if (sky2->wol)
3551                        enable_wakeup = true;
3552        }
3553        device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3554
3555        return 0;
3556}
3557
3558static u32 sky2_supported_modes(const struct sky2_hw *hw)
3559{
3560        if (sky2_is_copper(hw)) {
3561                u32 modes = SUPPORTED_10baseT_Half
3562                        | SUPPORTED_10baseT_Full
3563                        | SUPPORTED_100baseT_Half
3564                        | SUPPORTED_100baseT_Full;
3565
3566                if (hw->flags & SKY2_HW_GIGABIT)
3567                        modes |= SUPPORTED_1000baseT_Half
3568                                | SUPPORTED_1000baseT_Full;
3569                return modes;
3570        } else
3571                return SUPPORTED_1000baseT_Half
3572                        | SUPPORTED_1000baseT_Full;
3573}
3574
3575static int sky2_get_link_ksettings(struct net_device *dev,
3576                                   struct ethtool_link_ksettings *cmd)
3577{
3578        struct sky2_port *sky2 = netdev_priv(dev);
3579        struct sky2_hw *hw = sky2->hw;
3580        u32 supported, advertising;
3581
3582        supported = sky2_supported_modes(hw);
3583        cmd->base.phy_address = PHY_ADDR_MARV;
3584        if (sky2_is_copper(hw)) {
3585                cmd->base.port = PORT_TP;
3586                cmd->base.speed = sky2->speed;
3587                supported |=  SUPPORTED_Autoneg | SUPPORTED_TP;
3588        } else {
3589                cmd->base.speed = SPEED_1000;
3590                cmd->base.port = PORT_FIBRE;
3591                supported |=  SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3592        }
3593
3594        advertising = sky2->advertising;
3595        cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3596                ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3597        cmd->base.duplex = sky2->duplex;
3598
3599        ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3600                                                supported);
3601        ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3602                                                advertising);
3603
3604        return 0;
3605}
3606
3607static int sky2_set_link_ksettings(struct net_device *dev,
3608                                   const struct ethtool_link_ksettings *cmd)
3609{
3610        struct sky2_port *sky2 = netdev_priv(dev);
3611        const struct sky2_hw *hw = sky2->hw;
3612        u32 supported = sky2_supported_modes(hw);
3613        u32 new_advertising;
3614
3615        ethtool_convert_link_mode_to_legacy_u32(&new_advertising,
3616                                                cmd->link_modes.advertising);
3617
3618        if (cmd->base.autoneg == AUTONEG_ENABLE) {
3619                if (new_advertising & ~supported)
3620                        return -EINVAL;
3621
3622                if (sky2_is_copper(hw))
3623                        sky2->advertising = new_advertising |
3624                                            ADVERTISED_TP |
3625                                            ADVERTISED_Autoneg;
3626                else
3627                        sky2->advertising = new_advertising |
3628                                            ADVERTISED_FIBRE |
3629                                            ADVERTISED_Autoneg;
3630
3631                sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3632                sky2->duplex = -1;
3633                sky2->speed = -1;
3634        } else {
3635                u32 setting;
3636                u32 speed = cmd->base.speed;
3637
3638                switch (speed) {
3639                case SPEED_1000:
3640                        if (cmd->base.duplex == DUPLEX_FULL)
3641                                setting = SUPPORTED_1000baseT_Full;
3642                        else if (cmd->base.duplex == DUPLEX_HALF)
3643                                setting = SUPPORTED_1000baseT_Half;
3644                        else
3645                                return -EINVAL;
3646                        break;
3647                case SPEED_100:
3648                        if (cmd->base.duplex == DUPLEX_FULL)
3649                                setting = SUPPORTED_100baseT_Full;
3650                        else if (cmd->base.duplex == DUPLEX_HALF)
3651                                setting = SUPPORTED_100baseT_Half;
3652                        else
3653                                return -EINVAL;
3654                        break;
3655
3656                case SPEED_10:
3657                        if (cmd->base.duplex == DUPLEX_FULL)
3658                                setting = SUPPORTED_10baseT_Full;
3659                        else if (cmd->base.duplex == DUPLEX_HALF)
3660                                setting = SUPPORTED_10baseT_Half;
3661                        else
3662                                return -EINVAL;
3663                        break;
3664                default:
3665                        return -EINVAL;
3666                }
3667
3668                if ((setting & supported) == 0)
3669                        return -EINVAL;
3670
3671                sky2->speed = speed;
3672                sky2->duplex = cmd->base.duplex;
3673                sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3674        }
3675
3676        if (netif_running(dev)) {
3677                sky2_phy_reinit(sky2);
3678                sky2_set_multicast(dev);
3679        }
3680
3681        return 0;
3682}
3683
3684static void sky2_get_drvinfo(struct net_device *dev,
3685                             struct ethtool_drvinfo *info)
3686{
3687        struct sky2_port *sky2 = netdev_priv(dev);
3688
3689        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3690        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3691        strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3692                sizeof(info->bus_info));
3693}
3694
3695static const struct sky2_stat {
3696        char name[ETH_GSTRING_LEN];
3697        u16 offset;
3698} sky2_stats[] = {
3699        { "tx_bytes",      GM_TXO_OK_HI },
3700        { "rx_bytes",      GM_RXO_OK_HI },
3701        { "tx_broadcast",  GM_TXF_BC_OK },
3702        { "rx_broadcast",  GM_RXF_BC_OK },
3703        { "tx_multicast",  GM_TXF_MC_OK },
3704        { "rx_multicast",  GM_RXF_MC_OK },
3705        { "tx_unicast",    GM_TXF_UC_OK },
3706        { "rx_unicast",    GM_RXF_UC_OK },
3707        { "tx_mac_pause",  GM_TXF_MPAUSE },
3708        { "rx_mac_pause",  GM_RXF_MPAUSE },
3709        { "collisions",    GM_TXF_COL },
3710        { "late_collision",GM_TXF_LAT_COL },
3711        { "aborted",       GM_TXF_ABO_COL },
3712        { "single_collisions", GM_TXF_SNG_COL },
3713        { "multi_collisions", GM_TXF_MUL_COL },
3714
3715        { "rx_short",      GM_RXF_SHT },
3716        { "rx_runt",       GM_RXE_FRAG },
3717        { "rx_64_byte_packets", GM_RXF_64B },
3718        { "rx_65_to_127_byte_packets", GM_RXF_127B },
3719        { "rx_128_to_255_byte_packets", GM_RXF_255B },
3720        { "rx_256_to_511_byte_packets", GM_RXF_511B },
3721        { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3722        { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3723        { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3724        { "rx_too_long",   GM_RXF_LNG_ERR },
3725        { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3726        { "rx_jabber",     GM_RXF_JAB_PKT },
3727        { "rx_fcs_error",   GM_RXF_FCS_ERR },
3728
3729        { "tx_64_byte_packets", GM_TXF_64B },
3730        { "tx_65_to_127_byte_packets", GM_TXF_127B },
3731        { "tx_128_to_255_byte_packets", GM_TXF_255B },
3732        { "tx_256_to_511_byte_packets", GM_TXF_511B },
3733        { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3734        { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3735        { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3736        { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3737};
3738
3739static u32 sky2_get_msglevel(struct net_device *netdev)
3740{
3741        struct sky2_port *sky2 = netdev_priv(netdev);
3742        return sky2->msg_enable;
3743}
3744
3745static int sky2_nway_reset(struct net_device *dev)
3746{
3747        struct sky2_port *sky2 = netdev_priv(dev);
3748
3749        if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3750                return -EINVAL;
3751
3752        sky2_phy_reinit(sky2);
3753        sky2_set_multicast(dev);
3754
3755        return 0;
3756}
3757
3758static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3759{
3760        struct sky2_hw *hw = sky2->hw;
3761        unsigned port = sky2->port;
3762        int i;
3763
3764        data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3765        data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3766
3767        for (i = 2; i < count; i++)
3768                data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3769}
3770
3771static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3772{
3773        struct sky2_port *sky2 = netdev_priv(netdev);
3774        sky2->msg_enable = value;
3775}
3776
3777static int sky2_get_sset_count(struct net_device *dev, int sset)
3778{
3779        switch (sset) {
3780        case ETH_SS_STATS:
3781                return ARRAY_SIZE(sky2_stats);
3782        default:
3783                return -EOPNOTSUPP;
3784        }
3785}
3786
3787static void sky2_get_ethtool_stats(struct net_device *dev,
3788                                   struct ethtool_stats *stats, u64 * data)
3789{
3790        struct sky2_port *sky2 = netdev_priv(dev);
3791
3792        sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3793}
3794
3795static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3796{
3797        int i;
3798
3799        switch (stringset) {
3800        case ETH_SS_STATS:
3801                for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3802                        memcpy(data + i * ETH_GSTRING_LEN,
3803                               sky2_stats[i].name, ETH_GSTRING_LEN);
3804                break;
3805        }
3806}
3807
3808static int sky2_set_mac_address(struct net_device *dev, void *p)
3809{
3810        struct sky2_port *sky2 = netdev_priv(dev);
3811        struct sky2_hw *hw = sky2->hw;
3812        unsigned port = sky2->port;
3813        const struct sockaddr *addr = p;
3814
3815        if (!is_valid_ether_addr(addr->sa_data))
3816                return -EADDRNOTAVAIL;
3817
3818        memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3819        memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3820                    dev->dev_addr, ETH_ALEN);
3821        memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3822                    dev->dev_addr, ETH_ALEN);
3823
3824        /* virtual address for data */
3825        gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3826
3827        /* physical address: used for pause frames */
3828        gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3829
3830        return 0;
3831}
3832
3833static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3834{
3835        u32 bit;
3836
3837        bit = ether_crc(ETH_ALEN, addr) & 63;
3838        filter[bit >> 3] |= 1 << (bit & 7);
3839}
3840
3841static void sky2_set_multicast(struct net_device *dev)
3842{
3843        struct sky2_port *sky2 = netdev_priv(dev);
3844        struct sky2_hw *hw = sky2->hw;
3845        unsigned port = sky2->port;
3846        struct netdev_hw_addr *ha;
3847        u16 reg;
3848        u8 filter[8];
3849        int rx_pause;
3850        static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3851
3852        rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3853        memset(filter, 0, sizeof(filter));
3854
3855        reg = gma_read16(hw, port, GM_RX_CTRL);
3856        reg |= GM_RXCR_UCF_ENA;
3857
3858        if (dev->flags & IFF_PROMISC)   /* promiscuous */
3859                reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3860        else if (dev->flags & IFF_ALLMULTI)
3861                memset(filter, 0xff, sizeof(filter));
3862        else if (netdev_mc_empty(dev) && !rx_pause)
3863                reg &= ~GM_RXCR_MCF_ENA;
3864        else {
3865                reg |= GM_RXCR_MCF_ENA;
3866
3867                if (rx_pause)
3868                        sky2_add_filter(filter, pause_mc_addr);
3869
3870                netdev_for_each_mc_addr(ha, dev)
3871                        sky2_add_filter(filter, ha->addr);
3872        }
3873
3874        gma_write16(hw, port, GM_MC_ADDR_H1,
3875                    (u16) filter[0] | ((u16) filter[1] << 8));
3876        gma_write16(hw, port, GM_MC_ADDR_H2,
3877                    (u16) filter[2] | ((u16) filter[3] << 8));
3878        gma_write16(hw, port, GM_MC_ADDR_H3,
3879                    (u16) filter[4] | ((u16) filter[5] << 8));
3880        gma_write16(hw, port, GM_MC_ADDR_H4,
3881                    (u16) filter[6] | ((u16) filter[7] << 8));
3882
3883        gma_write16(hw, port, GM_RX_CTRL, reg);
3884}
3885
3886static void sky2_get_stats(struct net_device *dev,
3887                           struct rtnl_link_stats64 *stats)
3888{
3889        struct sky2_port *sky2 = netdev_priv(dev);
3890        struct sky2_hw *hw = sky2->hw;
3891        unsigned port = sky2->port;
3892        unsigned int start;
3893        u64 _bytes, _packets;
3894
3895        do {
3896                start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp);
3897                _bytes = sky2->rx_stats.bytes;
3898                _packets = sky2->rx_stats.packets;
3899        } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start));
3900
3901        stats->rx_packets = _packets;
3902        stats->rx_bytes = _bytes;
3903
3904        do {
3905                start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp);
3906                _bytes = sky2->tx_stats.bytes;
3907                _packets = sky2->tx_stats.packets;
3908        } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start));
3909
3910        stats->tx_packets = _packets;
3911        stats->tx_bytes = _bytes;
3912
3913        stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3914                + get_stats32(hw, port, GM_RXF_BC_OK);
3915
3916        stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3917
3918        stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3919        stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3920        stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3921                + get_stats32(hw, port, GM_RXE_FRAG);
3922        stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3923
3924        stats->rx_dropped = dev->stats.rx_dropped;
3925        stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3926        stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3927}
3928
3929/* Can have one global because blinking is controlled by
3930 * ethtool and that is always under RTNL mutex
3931 */
3932static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3933{
3934        struct sky2_hw *hw = sky2->hw;
3935        unsigned port = sky2->port;
3936
3937        spin_lock_bh(&sky2->phy_lock);
3938        if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3939            hw->chip_id == CHIP_ID_YUKON_EX ||
3940            hw->chip_id == CHIP_ID_YUKON_SUPR) {
3941                u16 pg;
3942                pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3943                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3944
3945                switch (mode) {
3946                case MO_LED_OFF:
3947                        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3948                                     PHY_M_LEDC_LOS_CTRL(8) |
3949                                     PHY_M_LEDC_INIT_CTRL(8) |
3950                                     PHY_M_LEDC_STA1_CTRL(8) |
3951                                     PHY_M_LEDC_STA0_CTRL(8));
3952                        break;
3953                case MO_LED_ON:
3954                        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3955                                     PHY_M_LEDC_LOS_CTRL(9) |
3956                                     PHY_M_LEDC_INIT_CTRL(9) |
3957                                     PHY_M_LEDC_STA1_CTRL(9) |
3958                                     PHY_M_LEDC_STA0_CTRL(9));
3959                        break;
3960                case MO_LED_BLINK:
3961                        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3962                                     PHY_M_LEDC_LOS_CTRL(0xa) |
3963                                     PHY_M_LEDC_INIT_CTRL(0xa) |
3964                                     PHY_M_LEDC_STA1_CTRL(0xa) |
3965                                     PHY_M_LEDC_STA0_CTRL(0xa));
3966                        break;
3967                case MO_LED_NORM:
3968                        gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3969                                     PHY_M_LEDC_LOS_CTRL(1) |
3970                                     PHY_M_LEDC_INIT_CTRL(8) |
3971                                     PHY_M_LEDC_STA1_CTRL(7) |
3972                                     PHY_M_LEDC_STA0_CTRL(7));
3973                }
3974
3975                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3976        } else
3977                gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3978                                     PHY_M_LED_MO_DUP(mode) |
3979                                     PHY_M_LED_MO_10(mode) |
3980                                     PHY_M_LED_MO_100(mode) |
3981                                     PHY_M_LED_MO_1000(mode) |
3982                                     PHY_M_LED_MO_RX(mode) |
3983                                     PHY_M_LED_MO_TX(mode));
3984
3985        spin_unlock_bh(&sky2->phy_lock);
3986}
3987
3988/* blink LED's for finding board */
3989static int sky2_set_phys_id(struct net_device *dev,
3990                            enum ethtool_phys_id_state state)
3991{
3992        struct sky2_port *sky2 = netdev_priv(dev);
3993
3994        switch (state) {
3995        case ETHTOOL_ID_ACTIVE:
3996                return 1;       /* cycle on/off once per second */
3997        case ETHTOOL_ID_INACTIVE:
3998                sky2_led(sky2, MO_LED_NORM);
3999                break;
4000        case ETHTOOL_ID_ON:
4001                sky2_led(sky2, MO_LED_ON);
4002                break;
4003        case ETHTOOL_ID_OFF:
4004                sky2_led(sky2, MO_LED_OFF);
4005                break;
4006        }
4007
4008        return 0;
4009}
4010
4011static void sky2_get_pauseparam(struct net_device *dev,
4012                                struct ethtool_pauseparam *ecmd)
4013{
4014        struct sky2_port *sky2 = netdev_priv(dev);
4015
4016        switch (sky2->flow_mode) {
4017        case FC_NONE:
4018                ecmd->tx_pause = ecmd->rx_pause = 0;
4019                break;
4020        case FC_TX:
4021                ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4022                break;
4023        case FC_RX:
4024                ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4025                break;
4026        case FC_BOTH:
4027                ecmd->tx_pause = ecmd->rx_pause = 1;
4028        }
4029
4030        ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4031                ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4032}
4033
4034static int sky2_set_pauseparam(struct net_device *dev,
4035                               struct ethtool_pauseparam *ecmd)
4036{
4037        struct sky2_port *sky2 = netdev_priv(dev);
4038
4039        if (ecmd->autoneg == AUTONEG_ENABLE)
4040                sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4041        else
4042                sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4043
4044        sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4045
4046        if (netif_running(dev))
4047                sky2_phy_reinit(sky2);
4048
4049        return 0;
4050}
4051
4052static int sky2_get_coalesce(struct net_device *dev,
4053                             struct ethtool_coalesce *ecmd)
4054{
4055        struct sky2_port *sky2 = netdev_priv(dev);
4056        struct sky2_hw *hw = sky2->hw;
4057
4058        if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4059                ecmd->tx_coalesce_usecs = 0;
4060        else {
4061                u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4062                ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4063        }
4064        ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4065
4066        if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4067                ecmd->rx_coalesce_usecs = 0;
4068        else {
4069                u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4070                ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4071        }
4072        ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4073
4074        if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4075                ecmd->rx_coalesce_usecs_irq = 0;
4076        else {
4077                u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4078                ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4079        }
4080
4081        ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4082
4083        return 0;
4084}
4085
4086/* Note: this affect both ports */
4087static int sky2_set_coalesce(struct net_device *dev,
4088                             struct ethtool_coalesce *ecmd)
4089{
4090        struct sky2_port *sky2 = netdev_priv(dev);
4091        struct sky2_hw *hw = sky2->hw;
4092        const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4093
4094        if (ecmd->tx_coalesce_usecs > tmax ||
4095            ecmd->rx_coalesce_usecs > tmax ||
4096            ecmd->rx_coalesce_usecs_irq > tmax)
4097                return -EINVAL;
4098
4099        if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4100                return -EINVAL;
4101        if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4102                return -EINVAL;
4103        if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4104                return -EINVAL;
4105
4106        if (ecmd->tx_coalesce_usecs == 0)
4107                sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4108        else {
4109                sky2_write32(hw, STAT_TX_TIMER_INI,
4110                             sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4111                sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4112        }
4113        sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4114
4115        if (ecmd->rx_coalesce_usecs == 0)
4116                sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4117        else {
4118                sky2_write32(hw, STAT_LEV_TIMER_INI,
4119                             sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4120                sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4121        }
4122        sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4123
4124        if (ecmd->rx_coalesce_usecs_irq == 0)
4125                sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4126        else {
4127                sky2_write32(hw, STAT_ISR_TIMER_INI,
4128                             sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4129                sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4130        }
4131        sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4132        return 0;
4133}
4134
4135/*
4136 * Hardware is limited to min of 128 and max of 2048 for ring size
4137 * and  rounded up to next power of two
4138 * to avoid division in modulus calclation
4139 */
4140static unsigned long roundup_ring_size(unsigned long pending)
4141{
4142        return max(128ul, roundup_pow_of_two(pending+1));
4143}
4144
4145static void sky2_get_ringparam(struct net_device *dev,
4146                               struct ethtool_ringparam *ering)
4147{
4148        struct sky2_port *sky2 = netdev_priv(dev);
4149
4150        ering->rx_max_pending = RX_MAX_PENDING;
4151        ering->tx_max_pending = TX_MAX_PENDING;
4152
4153        ering->rx_pending = sky2->rx_pending;
4154        ering->tx_pending = sky2->tx_pending;
4155}
4156
4157static int sky2_set_ringparam(struct net_device *dev,
4158                              struct ethtool_ringparam *ering)
4159{
4160        struct sky2_port *sky2 = netdev_priv(dev);
4161
4162        if (ering->rx_pending > RX_MAX_PENDING ||
4163            ering->rx_pending < 8 ||
4164            ering->tx_pending < TX_MIN_PENDING ||
4165            ering->tx_pending > TX_MAX_PENDING)
4166                return -EINVAL;
4167
4168        sky2_detach(dev);
4169
4170        sky2->rx_pending = ering->rx_pending;
4171        sky2->tx_pending = ering->tx_pending;
4172        sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4173
4174        return sky2_reattach(dev);
4175}
4176
4177static int sky2_get_regs_len(struct net_device *dev)
4178{
4179        return 0x4000;
4180}
4181
4182static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4183{
4184        /* This complicated switch statement is to make sure and
4185         * only access regions that are unreserved.
4186         * Some blocks are only valid on dual port cards.
4187         */
4188        switch (b) {
4189        /* second port */
4190        case 5:         /* Tx Arbiter 2 */
4191        case 9:         /* RX2 */
4192        case 14 ... 15: /* TX2 */
4193        case 17: case 19: /* Ram Buffer 2 */
4194        case 22 ... 23: /* Tx Ram Buffer 2 */
4195        case 25:        /* Rx MAC Fifo 1 */
4196        case 27:        /* Tx MAC Fifo 2 */
4197        case 31:        /* GPHY 2 */
4198        case 40 ... 47: /* Pattern Ram 2 */
4199        case 52: case 54: /* TCP Segmentation 2 */
4200        case 112 ... 116: /* GMAC 2 */
4201                return hw->ports > 1;
4202
4203        case 0:         /* Control */
4204        case 2:         /* Mac address */
4205        case 4:         /* Tx Arbiter 1 */
4206        case 7:         /* PCI express reg */
4207        case 8:         /* RX1 */
4208        case 12 ... 13: /* TX1 */
4209        case 16: case 18:/* Rx Ram Buffer 1 */
4210        case 20 ... 21: /* Tx Ram Buffer 1 */
4211        case 24:        /* Rx MAC Fifo 1 */
4212        case 26:        /* Tx MAC Fifo 1 */
4213        case 28 ... 29: /* Descriptor and status unit */
4214        case 30:        /* GPHY 1*/
4215        case 32 ... 39: /* Pattern Ram 1 */
4216        case 48: case 50: /* TCP Segmentation 1 */
4217        case 56 ... 60: /* PCI space */
4218        case 80 ... 84: /* GMAC 1 */
4219                return 1;
4220
4221        default:
4222                return 0;
4223        }
4224}
4225
4226/*
4227 * Returns copy of control register region
4228 * Note: ethtool_get_regs always provides full size (16k) buffer
4229 */
4230static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4231                          void *p)
4232{
4233        const struct sky2_port *sky2 = netdev_priv(dev);
4234        const void __iomem *io = sky2->hw->regs;
4235        unsigned int b;
4236
4237        regs->version = 1;
4238
4239        for (b = 0; b < 128; b++) {
4240                /* skip poisonous diagnostic ram region in block 3 */
4241                if (b == 3)
4242                        memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4243                else if (sky2_reg_access_ok(sky2->hw, b))
4244                        memcpy_fromio(p, io, 128);
4245                else
4246                        memset(p, 0, 128);
4247
4248                p += 128;
4249                io += 128;
4250        }
4251}
4252
4253static int sky2_get_eeprom_len(struct net_device *dev)
4254{
4255        struct sky2_port *sky2 = netdev_priv(dev);
4256        struct sky2_hw *hw = sky2->hw;
4257        u16 reg2;
4258
4259        reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4260        return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4261}
4262
4263static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4264{
4265        unsigned long start = jiffies;
4266
4267        while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4268                /* Can take up to 10.6 ms for write */
4269                if (time_after(jiffies, start + HZ/4)) {
4270                        dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4271                        return -ETIMEDOUT;
4272                }
4273                msleep(1);
4274        }
4275
4276        return 0;
4277}
4278
4279static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4280                         u16 offset, size_t length)
4281{
4282        int rc = 0;
4283
4284        while (length > 0) {
4285                u32 val;
4286
4287                sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4288                rc = sky2_vpd_wait(hw, cap, 0);
4289                if (rc)
4290                        break;
4291
4292                val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4293
4294                memcpy(data, &val, min(sizeof(val), length));
4295                offset += sizeof(u32);
4296                data += sizeof(u32);
4297                length -= sizeof(u32);
4298        }
4299
4300        return rc;
4301}
4302
4303static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4304                          u16 offset, unsigned int length)
4305{
4306        unsigned int i;
4307        int rc = 0;
4308
4309        for (i = 0; i < length; i += sizeof(u32)) {
4310                u32 val = *(u32 *)(data + i);
4311
4312                sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4313                sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4314
4315                rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4316                if (rc)
4317                        break;
4318        }
4319        return rc;
4320}
4321
4322static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4323                           u8 *data)
4324{
4325        struct sky2_port *sky2 = netdev_priv(dev);
4326        int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4327
4328        if (!cap)
4329                return -EINVAL;
4330
4331        eeprom->magic = SKY2_EEPROM_MAGIC;
4332
4333        return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4334}
4335
4336static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4337                           u8 *data)
4338{
4339        struct sky2_port *sky2 = netdev_priv(dev);
4340        int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4341
4342        if (!cap)
4343                return -EINVAL;
4344
4345        if (eeprom->magic != SKY2_EEPROM_MAGIC)
4346                return -EINVAL;
4347
4348        /* Partial writes not supported */
4349        if ((eeprom->offset & 3) || (eeprom->len & 3))
4350                return -EINVAL;
4351
4352        return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4353}
4354
4355static netdev_features_t sky2_fix_features(struct net_device *dev,
4356        netdev_features_t features)
4357{
4358        const struct sky2_port *sky2 = netdev_priv(dev);
4359        const struct sky2_hw *hw = sky2->hw;
4360
4361        /* In order to do Jumbo packets on these chips, need to turn off the
4362         * transmit store/forward. Therefore checksum offload won't work.
4363         */
4364        if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4365                netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4366                features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK);
4367        }
4368
4369        /* Some hardware requires receive checksum for RSS to work. */
4370        if ( (features & NETIF_F_RXHASH) &&
4371             !(features & NETIF_F_RXCSUM) &&
4372             (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4373                netdev_info(dev, "receive hashing forces receive checksum\n");
4374                features |= NETIF_F_RXCSUM;
4375        }
4376
4377        return features;
4378}
4379
4380static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4381{
4382        struct sky2_port *sky2 = netdev_priv(dev);
4383        netdev_features_t changed = dev->features ^ features;
4384
4385        if ((changed & NETIF_F_RXCSUM) &&
4386            !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4387                sky2_write32(sky2->hw,
4388                             Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4389                             (features & NETIF_F_RXCSUM)
4390                             ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4391        }
4392
4393        if (changed & NETIF_F_RXHASH)
4394                rx_set_rss(dev, features);
4395
4396        if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4397                sky2_vlan_mode(dev, features);
4398
4399        return 0;
4400}
4401
4402static const struct ethtool_ops sky2_ethtool_ops = {
4403        .get_drvinfo    = sky2_get_drvinfo,
4404        .get_wol        = sky2_get_wol,
4405        .set_wol        = sky2_set_wol,
4406        .get_msglevel   = sky2_get_msglevel,
4407        .set_msglevel   = sky2_set_msglevel,
4408        .nway_reset     = sky2_nway_reset,
4409        .get_regs_len   = sky2_get_regs_len,
4410        .get_regs       = sky2_get_regs,
4411        .get_link       = ethtool_op_get_link,
4412        .get_eeprom_len = sky2_get_eeprom_len,
4413        .get_eeprom     = sky2_get_eeprom,
4414        .set_eeprom     = sky2_set_eeprom,
4415        .get_strings    = sky2_get_strings,
4416        .get_coalesce   = sky2_get_coalesce,
4417        .set_coalesce   = sky2_set_coalesce,
4418        .get_ringparam  = sky2_get_ringparam,
4419        .set_ringparam  = sky2_set_ringparam,
4420        .get_pauseparam = sky2_get_pauseparam,
4421        .set_pauseparam = sky2_set_pauseparam,
4422        .set_phys_id    = sky2_set_phys_id,
4423        .get_sset_count = sky2_get_sset_count,
4424        .get_ethtool_stats = sky2_get_ethtool_stats,
4425        .get_link_ksettings = sky2_get_link_ksettings,
4426        .set_link_ksettings = sky2_set_link_ksettings,
4427};
4428
4429#ifdef CONFIG_SKY2_DEBUG
4430
4431static struct dentry *sky2_debug;
4432
4433
4434/*
4435 * Read and parse the first part of Vital Product Data
4436 */
4437#define VPD_SIZE        128
4438#define VPD_MAGIC       0x82
4439
4440static const struct vpd_tag {
4441        char tag[2];
4442        char *label;
4443} vpd_tags[] = {
4444        { "PN", "Part Number" },
4445        { "EC", "Engineering Level" },
4446        { "MN", "Manufacturer" },
4447        { "SN", "Serial Number" },
4448        { "YA", "Asset Tag" },
4449        { "VL", "First Error Log Message" },
4450        { "VF", "Second Error Log Message" },
4451        { "VB", "Boot Agent ROM Configuration" },
4452        { "VE", "EFI UNDI Configuration" },
4453};
4454
4455static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4456{
4457        size_t vpd_size;
4458        loff_t offs;
4459        u8 len;
4460        unsigned char *buf;
4461        u16 reg2;
4462
4463        reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4464        vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4465
4466        seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4467        buf = kmalloc(vpd_size, GFP_KERNEL);
4468        if (!buf) {
4469                seq_puts(seq, "no memory!\n");
4470                return;
4471        }
4472
4473        if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4474                seq_puts(seq, "VPD read failed\n");
4475                goto out;
4476        }
4477
4478        if (buf[0] != VPD_MAGIC) {
4479                seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4480                goto out;
4481        }
4482        len = buf[1];
4483        if (len == 0 || len > vpd_size - 4) {
4484                seq_printf(seq, "Invalid id length: %d\n", len);
4485                goto out;
4486        }
4487
4488        seq_printf(seq, "%.*s\n", len, buf + 3);
4489        offs = len + 3;
4490
4491        while (offs < vpd_size - 4) {
4492                int i;
4493
4494                if (!memcmp("RW", buf + offs, 2))       /* end marker */
4495                        break;
4496                len = buf[offs + 2];
4497                if (offs + len + 3 >= vpd_size)
4498                        break;
4499
4500                for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4501                        if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4502                                seq_printf(seq, " %s: %.*s\n",
4503                                           vpd_tags[i].label, len, buf + offs + 3);
4504                                break;
4505                        }
4506                }
4507                offs += len + 3;
4508        }
4509out:
4510        kfree(buf);
4511}
4512
4513static int sky2_debug_show(struct seq_file *seq, void *v)
4514{
4515        struct net_device *dev = seq->private;
4516        const struct sky2_port *sky2 = netdev_priv(dev);
4517        struct sky2_hw *hw = sky2->hw;
4518        unsigned port = sky2->port;
4519        unsigned idx, last;
4520        int sop;
4521
4522        sky2_show_vpd(seq, hw);
4523
4524        seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4525                   sky2_read32(hw, B0_ISRC),
4526                   sky2_read32(hw, B0_IMSK),
4527                   sky2_read32(hw, B0_Y2_SP_ICR));
4528
4529        if (!netif_running(dev)) {
4530                seq_puts(seq, "network not running\n");
4531                return 0;
4532        }
4533
4534        napi_disable(&hw->napi);
4535        last = sky2_read16(hw, STAT_PUT_IDX);
4536
4537        seq_printf(seq, "Status ring %u\n", hw->st_size);
4538        if (hw->st_idx == last)
4539                seq_puts(seq, "Status ring (empty)\n");
4540        else {
4541                seq_puts(seq, "Status ring\n");
4542                for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4543                     idx = RING_NEXT(idx, hw->st_size)) {
4544                        const struct sky2_status_le *le = hw->st_le + idx;
4545                        seq_printf(seq, "[%d] %#x %d %#x\n",
4546                                   idx, le->opcode, le->length, le->status);
4547                }
4548                seq_puts(seq, "\n");
4549        }
4550
4551        seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4552                   sky2->tx_cons, sky2->tx_prod,
4553                   sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4554                   sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4555
4556        /* Dump contents of tx ring */
4557        sop = 1;
4558        for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4559             idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4560                const struct sky2_tx_le *le = sky2->tx_le + idx;
4561                u32 a = le32_to_cpu(le->addr);
4562
4563                if (sop)
4564                        seq_printf(seq, "%u:", idx);
4565                sop = 0;
4566
4567                switch (le->opcode & ~HW_OWNER) {
4568                case OP_ADDR64:
4569                        seq_printf(seq, " %#x:", a);
4570                        break;
4571                case OP_LRGLEN:
4572                        seq_printf(seq, " mtu=%d", a);
4573                        break;
4574                case OP_VLAN:
4575                        seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4576                        break;
4577                case OP_TCPLISW:
4578                        seq_printf(seq, " csum=%#x", a);
4579                        break;
4580                case OP_LARGESEND:
4581                        seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4582                        break;
4583                case OP_PACKET:
4584                        seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4585                        break;
4586                case OP_BUFFER:
4587                        seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4588                        break;
4589                default:
4590                        seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4591                                   a, le16_to_cpu(le->length));
4592                }
4593
4594                if (le->ctrl & EOP) {
4595                        seq_putc(seq, '\n');
4596                        sop = 1;
4597                }
4598        }
4599
4600        seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4601                   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4602                   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4603                   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4604
4605        sky2_read32(hw, B0_Y2_SP_LISR);
4606        napi_enable(&hw->napi);
4607        return 0;
4608}
4609DEFINE_SHOW_ATTRIBUTE(sky2_debug);
4610
4611/*
4612 * Use network device events to create/remove/rename
4613 * debugfs file entries
4614 */
4615static int sky2_device_event(struct notifier_block *unused,
4616                             unsigned long event, void *ptr)
4617{
4618        struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4619        struct sky2_port *sky2 = netdev_priv(dev);
4620
4621        if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4622                return NOTIFY_DONE;
4623
4624        switch (event) {
4625        case NETDEV_CHANGENAME:
4626                if (sky2->debugfs) {
4627                        sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4628                                                       sky2_debug, dev->name);
4629                }
4630                break;
4631
4632        case NETDEV_GOING_DOWN:
4633                if (sky2->debugfs) {
4634                        netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4635                        debugfs_remove(sky2->debugfs);
4636                        sky2->debugfs = NULL;
4637                }
4638                break;
4639
4640        case NETDEV_UP:
4641                sky2->debugfs = debugfs_create_file(dev->name, 0444,
4642                                                    sky2_debug, dev,
4643                                                    &sky2_debug_fops);
4644                if (IS_ERR(sky2->debugfs))
4645                        sky2->debugfs = NULL;
4646        }
4647
4648        return NOTIFY_DONE;
4649}
4650
4651static struct notifier_block sky2_notifier = {
4652        .notifier_call = sky2_device_event,
4653};
4654
4655
4656static __init void sky2_debug_init(void)
4657{
4658        struct dentry *ent;
4659
4660        ent = debugfs_create_dir("sky2", NULL);
4661        if (!ent || IS_ERR(ent))
4662                return;
4663
4664        sky2_debug = ent;
4665        register_netdevice_notifier(&sky2_notifier);
4666}
4667
4668static __exit void sky2_debug_cleanup(void)
4669{
4670        if (sky2_debug) {
4671                unregister_netdevice_notifier(&sky2_notifier);
4672                debugfs_remove(sky2_debug);
4673                sky2_debug = NULL;
4674        }
4675}
4676
4677#else
4678#define sky2_debug_init()
4679#define sky2_debug_cleanup()
4680#endif
4681
4682/* Two copies of network device operations to handle special case of
4683   not allowing netpoll on second port */
4684static const struct net_device_ops sky2_netdev_ops[2] = {
4685  {
4686        .ndo_open               = sky2_open,
4687        .ndo_stop               = sky2_close,
4688        .ndo_start_xmit         = sky2_xmit_frame,
4689        .ndo_do_ioctl           = sky2_ioctl,
4690        .ndo_validate_addr      = eth_validate_addr,
4691        .ndo_set_mac_address    = sky2_set_mac_address,
4692        .ndo_set_rx_mode        = sky2_set_multicast,
4693        .ndo_change_mtu         = sky2_change_mtu,
4694        .ndo_fix_features       = sky2_fix_features,
4695        .ndo_set_features       = sky2_set_features,
4696        .ndo_tx_timeout         = sky2_tx_timeout,
4697        .ndo_get_stats64        = sky2_get_stats,
4698#ifdef CONFIG_NET_POLL_CONTROLLER
4699        .ndo_poll_controller    = sky2_netpoll,
4700#endif
4701  },
4702  {
4703        .ndo_open               = sky2_open,
4704        .ndo_stop               = sky2_close,
4705        .ndo_start_xmit         = sky2_xmit_frame,
4706        .ndo_do_ioctl           = sky2_ioctl,
4707        .ndo_validate_addr      = eth_validate_addr,
4708        .ndo_set_mac_address    = sky2_set_mac_address,
4709        .ndo_set_rx_mode        = sky2_set_multicast,
4710        .ndo_change_mtu         = sky2_change_mtu,
4711        .ndo_fix_features       = sky2_fix_features,
4712        .ndo_set_features       = sky2_set_features,
4713        .ndo_tx_timeout         = sky2_tx_timeout,
4714        .ndo_get_stats64        = sky2_get_stats,
4715  },
4716};
4717
4718/* Initialize network device */
4719static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4720                                           int highmem, int wol)
4721{
4722        struct sky2_port *sky2;
4723        struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4724        const void *iap;
4725
4726        if (!dev)
4727                return NULL;
4728
4729        SET_NETDEV_DEV(dev, &hw->pdev->dev);
4730        dev->irq = hw->pdev->irq;
4731        dev->ethtool_ops = &sky2_ethtool_ops;
4732        dev->watchdog_timeo = TX_WATCHDOG;
4733        dev->netdev_ops = &sky2_netdev_ops[port];
4734
4735        sky2 = netdev_priv(dev);
4736        sky2->netdev = dev;
4737        sky2->hw = hw;
4738        sky2->msg_enable = netif_msg_init(debug, default_msg);
4739
4740        u64_stats_init(&sky2->tx_stats.syncp);
4741        u64_stats_init(&sky2->rx_stats.syncp);
4742
4743        /* Auto speed and flow control */
4744        sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4745        if (hw->chip_id != CHIP_ID_YUKON_XL)
4746                dev->hw_features |= NETIF_F_RXCSUM;
4747
4748        sky2->flow_mode = FC_BOTH;
4749
4750        sky2->duplex = -1;
4751        sky2->speed = -1;
4752        sky2->advertising = sky2_supported_modes(hw);
4753        sky2->wol = wol;
4754
4755        spin_lock_init(&sky2->phy_lock);
4756
4757        sky2->tx_pending = TX_DEF_PENDING;
4758        sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4759        sky2->rx_pending = RX_DEF_PENDING;
4760
4761        hw->dev[port] = dev;
4762
4763        sky2->port = port;
4764
4765        dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4766
4767        if (highmem)
4768                dev->features |= NETIF_F_HIGHDMA;
4769
4770        /* Enable receive hashing unless hardware is known broken */
4771        if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4772                dev->hw_features |= NETIF_F_RXHASH;
4773
4774        if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4775                dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4776                                    NETIF_F_HW_VLAN_CTAG_RX;
4777                dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4778        }
4779
4780        dev->features |= dev->hw_features;
4781
4782        /* MTU range: 60 - 1500 or 9000 */
4783        dev->min_mtu = ETH_ZLEN;
4784        if (hw->chip_id == CHIP_ID_YUKON_FE ||
4785            hw->chip_id == CHIP_ID_YUKON_FE_P)
4786                dev->max_mtu = ETH_DATA_LEN;
4787        else
4788                dev->max_mtu = ETH_JUMBO_MTU;
4789
4790        /* try to get mac address in the following order:
4791         * 1) from device tree data
4792         * 2) from internal registers set by bootloader
4793         */
4794        iap = of_get_mac_address(hw->pdev->dev.of_node);
4795        if (!IS_ERR(iap))
4796                ether_addr_copy(dev->dev_addr, iap);
4797        else
4798                memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
4799                              ETH_ALEN);
4800
4801        /* if the address is invalid, use a random value */
4802        if (!is_valid_ether_addr(dev->dev_addr)) {
4803                struct sockaddr sa = { AF_UNSPEC };
4804
4805                netdev_warn(dev,
4806                            "Invalid MAC address, defaulting to random\n");
4807                eth_hw_addr_random(dev);
4808                memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
4809                if (sky2_set_mac_address(dev, &sa))
4810                        netdev_warn(dev, "Failed to set MAC address.\n");
4811        }
4812
4813        return dev;
4814}
4815
4816static void sky2_show_addr(struct net_device *dev)
4817{
4818        const struct sky2_port *sky2 = netdev_priv(dev);
4819
4820        netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4821}
4822
4823/* Handle software interrupt used during MSI test */
4824static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4825{
4826        struct sky2_hw *hw = dev_id;
4827        u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4828
4829        if (status == 0)
4830                return IRQ_NONE;
4831
4832        if (status & Y2_IS_IRQ_SW) {
4833                hw->flags |= SKY2_HW_USE_MSI;
4834                wake_up(&hw->msi_wait);
4835                sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4836        }
4837        sky2_write32(hw, B0_Y2_SP_ICR, 2);
4838
4839        return IRQ_HANDLED;
4840}
4841
4842/* Test interrupt path by forcing a a software IRQ */
4843static int sky2_test_msi(struct sky2_hw *hw)
4844{
4845        struct pci_dev *pdev = hw->pdev;
4846        int err;
4847
4848        init_waitqueue_head(&hw->msi_wait);
4849
4850        err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4851        if (err) {
4852                dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4853                return err;
4854        }
4855
4856        sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4857
4858        sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4859        sky2_read8(hw, B0_CTST);
4860
4861        wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4862
4863        if (!(hw->flags & SKY2_HW_USE_MSI)) {
4864                /* MSI test failed, go back to INTx mode */
4865                dev_info(&pdev->dev, "No interrupt generated using MSI, "
4866                         "switching to INTx mode.\n");
4867
4868                err = -EOPNOTSUPP;
4869                sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4870        }
4871
4872        sky2_write32(hw, B0_IM