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37#ifndef MLX4_H
38#define MLX4_H
39
40#include <linux/mutex.h>
41#include <linux/radix-tree.h>
42#include <linux/rbtree.h>
43#include <linux/timer.h>
44#include <linux/semaphore.h>
45#include <linux/workqueue.h>
46#include <linux/interrupt.h>
47#include <linux/spinlock.h>
48#include <net/devlink.h>
49#include <linux/rwsem.h>
50
51#include <linux/mlx4/device.h>
52#include <linux/mlx4/driver.h>
53#include <linux/mlx4/doorbell.h>
54#include <linux/mlx4/cmd.h>
55#include "fw_qos.h"
56
57#define DRV_NAME "mlx4_core"
58#define DRV_VERSION "4.0-0"
59#define DRV_NAME_FOR_FW "Linux," DRV_NAME "," DRV_VERSION
60
61#define MLX4_FS_UDP_UC_EN (1 << 1)
62#define MLX4_FS_TCP_UC_EN (1 << 2)
63#define MLX4_FS_NUM_OF_L2_ADDR 8
64#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
65#define MLX4_FS_NUM_MCG (1 << 17)
66
67#define INIT_HCA_TPT_MW_ENABLE (1 << 7)
68
69#define MLX4_QUERY_IF_STAT_RESET BIT(31)
70
71enum {
72 MLX4_HCR_BASE = 0x80680,
73 MLX4_HCR_SIZE = 0x0001c,
74 MLX4_CLR_INT_SIZE = 0x00008,
75 MLX4_SLAVE_COMM_BASE = 0x0,
76 MLX4_COMM_PAGESIZE = 0x1000,
77 MLX4_CLOCK_SIZE = 0x00008,
78 MLX4_COMM_CHAN_CAPS = 0x8,
79 MLX4_COMM_CHAN_FLAGS = 0xc
80};
81
82enum {
83 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
84 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
85 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
86 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
87};
88
89enum {
90 MLX4_NUM_PDS = 1 << 15
91};
92
93enum {
94 MLX4_CMPT_TYPE_QP = 0,
95 MLX4_CMPT_TYPE_SRQ = 1,
96 MLX4_CMPT_TYPE_CQ = 2,
97 MLX4_CMPT_TYPE_EQ = 3,
98 MLX4_CMPT_NUM_TYPE
99};
100
101enum {
102 MLX4_CMPT_SHIFT = 24,
103 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
104};
105
106enum mlx4_mpt_state {
107 MLX4_MPT_DISABLED = 0,
108 MLX4_MPT_EN_HW,
109 MLX4_MPT_EN_SW
110};
111
112#define MLX4_COMM_TIME 10000
113#define MLX4_COMM_OFFLINE_TIME_OUT 30000
114#define MLX4_COMM_CMD_NA_OP 0x0
115
116
117enum {
118 MLX4_COMM_CMD_RESET,
119 MLX4_COMM_CMD_VHCR0,
120 MLX4_COMM_CMD_VHCR1,
121 MLX4_COMM_CMD_VHCR2,
122 MLX4_COMM_CMD_VHCR_EN,
123 MLX4_COMM_CMD_VHCR_POST,
124 MLX4_COMM_CMD_FLR = 254
125};
126
127enum {
128 MLX4_VF_SMI_DISABLED,
129 MLX4_VF_SMI_ENABLED
130};
131
132
133#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
134
135#define NUM_OF_RESET_RETRIES 10
136#define SLEEP_TIME_IN_RESET (2 * 1000)
137enum mlx4_resource {
138 RES_QP,
139 RES_CQ,
140 RES_SRQ,
141 RES_XRCD,
142 RES_MPT,
143 RES_MTT,
144 RES_MAC,
145 RES_VLAN,
146 RES_NPORT_ID,
147 RES_COUNTER,
148 RES_FS_RULE,
149 RES_EQ,
150 MLX4_NUM_OF_RESOURCE_TYPE
151};
152
153enum mlx4_alloc_mode {
154 RES_OP_RESERVE,
155 RES_OP_RESERVE_AND_MAP,
156 RES_OP_MAP_ICM,
157};
158
159enum mlx4_res_tracker_free_type {
160 RES_TR_FREE_ALL,
161 RES_TR_FREE_SLAVES_ONLY,
162 RES_TR_FREE_STRUCTS_ONLY,
163};
164
165
166
167
168
169
170
171
172
173
174struct mlx4_vhcr {
175 u64 in_param;
176 u64 out_param;
177 u32 in_modifier;
178 u32 errno;
179 u16 op;
180 u16 token;
181 u8 op_modifier;
182 u8 e_bit;
183};
184
185struct mlx4_vhcr_cmd {
186 __be64 in_param;
187 __be32 in_modifier;
188 u32 reserved1;
189 __be64 out_param;
190 __be16 token;
191 u16 reserved;
192 u8 status;
193 u8 flags;
194 __be16 opcode;
195};
196
197struct mlx4_cmd_info {
198 u16 opcode;
199 bool has_inbox;
200 bool has_outbox;
201 bool out_is_imm;
202 bool encode_slave_id;
203 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
204 struct mlx4_cmd_mailbox *inbox);
205 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox,
207 struct mlx4_cmd_mailbox *outbox,
208 struct mlx4_cmd_info *cmd);
209};
210
211#ifdef CONFIG_MLX4_DEBUG
212extern int mlx4_debug_level;
213#else
214#define mlx4_debug_level (0)
215#endif
216
217#define mlx4_dbg(mdev, format, ...) \
218do { \
219 if (mlx4_debug_level) \
220 dev_printk(KERN_DEBUG, \
221 &(mdev)->persist->pdev->dev, format, \
222 ##__VA_ARGS__); \
223} while (0)
224
225#define mlx4_err(mdev, format, ...) \
226 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
227#define mlx4_info(mdev, format, ...) \
228 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
229#define mlx4_warn(mdev, format, ...) \
230 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
231
232extern int log_mtts_per_seg;
233extern int mlx4_internal_err_reset;
234
235#define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \
236 MLX4_MFUNC_MAX))
237#define ALL_SLAVES 0xff
238
239struct mlx4_bitmap {
240 u32 last;
241 u32 top;
242 u32 max;
243 u32 reserved_top;
244 u32 mask;
245 u32 avail;
246 u32 effective_len;
247 spinlock_t lock;
248 unsigned long *table;
249};
250
251struct mlx4_buddy {
252 unsigned long **bits;
253 unsigned int *num_free;
254 u32 max_order;
255 spinlock_t lock;
256};
257
258struct mlx4_icm;
259
260struct mlx4_icm_table {
261 u64 virt;
262 int num_icm;
263 u32 num_obj;
264 int obj_size;
265 int lowmem;
266 int coherent;
267 struct mutex mutex;
268 struct mlx4_icm **icm;
269};
270
271#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
272#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
273#define MLX4_MPT_FLAG_MIO (1 << 17)
274#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
275#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
276#define MLX4_MPT_FLAG_REGION (1 << 8)
277
278#define MLX4_MPT_PD_MASK (0x1FFFFUL)
279#define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
280#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
281#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
282#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
283
284#define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
285
286#define MLX4_MPT_STATUS_SW 0xF0
287#define MLX4_MPT_STATUS_HW 0x00
288
289#define MLX4_CQE_SIZE_MASK_STRIDE 0x3
290#define MLX4_EQE_SIZE_MASK_STRIDE 0x30
291
292#define MLX4_EQ_ASYNC 0
293#define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \
294 !!((int)(vector) >= MLX4_EQ_ASYNC))
295#define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \
296 !!((int)(vector) >= MLX4_EQ_ASYNC))
297
298
299
300
301struct mlx4_mpt_entry {
302 __be32 flags;
303 __be32 qpn;
304 __be32 key;
305 __be32 pd_flags;
306 __be64 start;
307 __be64 length;
308 __be32 lkey;
309 __be32 win_cnt;
310 u8 reserved1[3];
311 u8 mtt_rep;
312 __be64 mtt_addr;
313 __be32 mtt_sz;
314 __be32 entity_size;
315 __be32 first_byte_offset;
316} __packed;
317
318
319
320
321struct mlx4_eq_context {
322 __be32 flags;
323 u16 reserved1[3];
324 __be16 page_offset;
325 u8 log_eq_size;
326 u8 reserved2[4];
327 u8 eq_period;
328 u8 reserved3;
329 u8 eq_max_count;
330 u8 reserved4[3];
331 u8 intr;
332 u8 log_page_size;
333 u8 reserved5[2];
334 u8 mtt_base_addr_h;
335 __be32 mtt_base_addr_l;
336 u32 reserved6[2];
337 __be32 consumer_index;
338 __be32 producer_index;
339 u32 reserved7[4];
340};
341
342struct mlx4_cq_context {
343 __be32 flags;
344 u16 reserved1[3];
345 __be16 page_offset;
346 __be32 logsize_usrpage;
347 __be16 cq_period;
348 __be16 cq_max_count;
349 u8 reserved2[3];
350 u8 comp_eqn;
351 u8 log_page_size;
352 u8 reserved3[2];
353 u8 mtt_base_addr_h;
354 __be32 mtt_base_addr_l;
355 __be32 last_notified_index;
356 __be32 solicit_producer_index;
357 __be32 consumer_index;
358 __be32 producer_index;
359 u32 reserved4[2];
360 __be64 db_rec_addr;
361};
362
363struct mlx4_srq_context {
364 __be32 state_logsize_srqn;
365 u8 logstride;
366 u8 reserved1;
367 __be16 xrcd;
368 __be32 pg_offset_cqn;
369 u32 reserved2;
370 u8 log_page_size;
371 u8 reserved3[2];
372 u8 mtt_base_addr_h;
373 __be32 mtt_base_addr_l;
374 __be32 pd;
375 __be16 limit_watermark;
376 __be16 wqe_cnt;
377 u16 reserved4;
378 __be16 wqe_counter;
379 u32 reserved5;
380 __be64 db_rec_addr;
381};
382
383struct mlx4_eq_tasklet {
384 struct list_head list;
385 struct list_head process_list;
386 struct tasklet_struct task;
387
388 spinlock_t lock;
389};
390
391struct mlx4_eq {
392 struct mlx4_dev *dev;
393 void __iomem *doorbell;
394 int eqn;
395 u32 cons_index;
396 u16 irq;
397 u16 have_irq;
398 int nent;
399 struct mlx4_buf_list *page_list;
400 struct mlx4_mtt mtt;
401 struct mlx4_eq_tasklet tasklet_ctx;
402 struct mlx4_active_ports actv_ports;
403 u32 ref_count;
404 cpumask_var_t affinity_mask;
405};
406
407struct mlx4_slave_eqe {
408 u8 type;
409 u8 port;
410 u32 param;
411};
412
413struct mlx4_slave_event_eq_info {
414 int eqn;
415 u16 token;
416};
417
418struct mlx4_profile {
419 int num_qp;
420 int rdmarc_per_qp;
421 int num_srq;
422 int num_cq;
423 int num_mcg;
424 int num_mpt;
425 unsigned num_mtt;
426};
427
428struct mlx4_fw {
429 u64 clr_int_base;
430 u64 catas_offset;
431 u64 comm_base;
432 u64 clock_offset;
433 struct mlx4_icm *fw_icm;
434 struct mlx4_icm *aux_icm;
435 u32 catas_size;
436 u16 fw_pages;
437 u8 clr_int_bar;
438 u8 catas_bar;
439 u8 comm_bar;
440 u8 clock_bar;
441};
442
443struct mlx4_comm {
444 u32 slave_write;
445 u32 slave_read;
446};
447
448enum {
449 MLX4_MCAST_CONFIG = 0,
450 MLX4_MCAST_DISABLE = 1,
451 MLX4_MCAST_ENABLE = 2,
452};
453
454#define VLAN_FLTR_SIZE 128
455
456struct mlx4_vlan_fltr {
457 __be32 entry[VLAN_FLTR_SIZE];
458};
459
460struct mlx4_mcast_entry {
461 struct list_head list;
462 u64 addr;
463};
464
465struct mlx4_promisc_qp {
466 struct list_head list;
467 u32 qpn;
468};
469
470struct mlx4_steer_index {
471 struct list_head list;
472 unsigned int index;
473 struct list_head duplicates;
474};
475
476#define MLX4_EVENT_TYPES_NUM 64
477
478struct mlx4_slave_state {
479 u8 comm_toggle;
480 u8 last_cmd;
481 u8 init_port_mask;
482 bool active;
483 bool old_vlan_api;
484 bool vst_qinq_supported;
485 u8 function;
486 dma_addr_t vhcr_dma;
487 u16 user_mtu[MLX4_MAX_PORTS + 1];
488 u16 mtu[MLX4_MAX_PORTS + 1];
489 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
490 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
491 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
492 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
493
494 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
495 u16 eq_pi;
496 u16 eq_ci;
497 spinlock_t lock;
498
499 u8 is_slave_going_down;
500 u32 cookie;
501 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
502};
503
504#define MLX4_VGT 4095
505#define NO_INDX (-1)
506
507struct mlx4_vport_state {
508 u64 mac;
509 u16 default_vlan;
510 u8 default_qos;
511 __be16 vlan_proto;
512 u32 tx_rate;
513 bool spoofchk;
514 u32 link_state;
515 u8 qos_vport;
516 __be64 guid;
517};
518
519struct mlx4_vf_admin_state {
520 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
521 u8 enable_smi[MLX4_MAX_PORTS + 1];
522};
523
524struct mlx4_vport_oper_state {
525 struct mlx4_vport_state state;
526 int mac_idx;
527 int vlan_idx;
528};
529
530struct mlx4_vf_oper_state {
531 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
532 u8 smi_enabled[MLX4_MAX_PORTS + 1];
533};
534
535struct slave_list {
536 struct mutex mutex;
537 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
538};
539
540struct resource_allocator {
541 spinlock_t alloc_lock;
542 union {
543 unsigned int res_reserved;
544 unsigned int res_port_rsvd[MLX4_MAX_PORTS];
545 };
546 union {
547 int res_free;
548 int res_port_free[MLX4_MAX_PORTS];
549 };
550 int *quota;
551 int *allocated;
552 int *guaranteed;
553};
554
555struct mlx4_resource_tracker {
556 spinlock_t lock;
557
558 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
559
560 struct slave_list *slave_list;
561 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
562};
563
564#define SLAVE_EVENT_EQ_SIZE 128
565struct mlx4_slave_event_eq {
566 u32 eqn;
567 u32 cons;
568 u32 prod;
569 spinlock_t event_lock;
570 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
571};
572
573struct mlx4_qos_manager {
574 int num_of_qos_vfs;
575 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP);
576};
577
578struct mlx4_master_qp0_state {
579 int proxy_qp0_active;
580 int qp0_active;
581 int port_active;
582};
583
584struct mlx4_mfunc_master_ctx {
585 struct mlx4_slave_state *slave_state;
586 struct mlx4_vf_admin_state *vf_admin;
587 struct mlx4_vf_oper_state *vf_oper;
588 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
589 int init_port_ref[MLX4_MAX_PORTS + 1];
590 u16 max_mtu[MLX4_MAX_PORTS + 1];
591 u16 max_user_mtu[MLX4_MAX_PORTS + 1];
592 u8 pptx;
593 u8 pprx;
594 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
595 struct mlx4_resource_tracker res_tracker;
596 struct workqueue_struct *comm_wq;
597 struct work_struct comm_work;
598 struct work_struct slave_event_work;
599 struct work_struct slave_flr_event_work;
600 spinlock_t slave_state_lock;
601 __be32 comm_arm_bit_vector[4];
602 struct mlx4_eqe cmd_eqe;
603 struct mlx4_slave_event_eq slave_eq;
604 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
605 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
606 u32 next_slave;
607};
608
609struct mlx4_mfunc {
610 struct mlx4_comm __iomem *comm;
611 struct mlx4_vhcr_cmd *vhcr;
612 dma_addr_t vhcr_dma;
613
614 struct mlx4_mfunc_master_ctx master;
615};
616
617#define MGM_QPN_MASK 0x00FFFFFF
618#define MGM_BLCK_LB_BIT 30
619
620struct mlx4_mgm {
621 __be32 next_gid_index;
622 __be32 members_count;
623 u32 reserved[2];
624 u8 gid[16];
625 __be32 qp[MLX4_MAX_QP_PER_MGM];
626};
627
628struct mlx4_cmd {
629 struct dma_pool *pool;
630 void __iomem *hcr;
631 struct mutex slave_cmd_mutex;
632 struct semaphore poll_sem;
633 struct semaphore event_sem;
634 struct rw_semaphore switch_sem;
635 int max_cmds;
636 spinlock_t context_lock;
637 int free_head;
638 struct mlx4_cmd_context *context;
639 u16 token_mask;
640 u8 use_events;
641 u8 toggle;
642 u8 comm_toggle;
643 u8 initialized;
644};
645
646enum {
647 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
648 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
649 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
650};
651struct mlx4_vf_immed_vlan_work {
652 struct work_struct work;
653 struct mlx4_priv *priv;
654 int flags;
655 int slave;
656 int vlan_ix;
657 int orig_vlan_ix;
658 u8 port;
659 u8 qos;
660 u8 qos_vport;
661 u16 vlan_id;
662 u16 orig_vlan_id;
663 __be16 vlan_proto;
664};
665
666
667struct mlx4_uar_table {
668 struct mlx4_bitmap bitmap;
669};
670
671struct mlx4_mr_table {
672 struct mlx4_bitmap mpt_bitmap;
673 struct mlx4_buddy mtt_buddy;
674 u64 mtt_base;
675 u64 mpt_base;
676 struct mlx4_icm_table mtt_table;
677 struct mlx4_icm_table dmpt_table;
678};
679
680struct mlx4_cq_table {
681 struct mlx4_bitmap bitmap;
682 spinlock_t lock;
683 struct radix_tree_root tree;
684 struct mlx4_icm_table table;
685 struct mlx4_icm_table cmpt_table;
686};
687
688struct mlx4_eq_table {
689 struct mlx4_bitmap bitmap;
690 char *irq_names;
691 void __iomem *clr_int;
692 void __iomem **uar_map;
693 u32 clr_mask;
694 struct mlx4_eq *eq;
695 struct mlx4_icm_table table;
696 struct mlx4_icm_table cmpt_table;
697 int have_irq;
698 u8 inta_pin;
699};
700
701struct mlx4_srq_table {
702 struct mlx4_bitmap bitmap;
703 spinlock_t lock;
704 struct radix_tree_root tree;
705 struct mlx4_icm_table table;
706 struct mlx4_icm_table cmpt_table;
707};
708
709enum mlx4_qp_table_zones {
710 MLX4_QP_TABLE_ZONE_GENERAL,
711 MLX4_QP_TABLE_ZONE_RSS,
712 MLX4_QP_TABLE_ZONE_RAW_ETH,
713 MLX4_QP_TABLE_ZONE_NUM
714};
715
716struct mlx4_qp_table {
717 struct mlx4_bitmap *bitmap_gen;
718 struct mlx4_zone_allocator *zones;
719 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM];
720 u32 rdmarc_base;
721 int rdmarc_shift;
722 spinlock_t lock;
723 struct mlx4_icm_table qp_table;
724 struct mlx4_icm_table auxc_table;
725 struct mlx4_icm_table altc_table;
726 struct mlx4_icm_table rdmarc_table;
727 struct mlx4_icm_table cmpt_table;
728};
729
730struct mlx4_mcg_table {
731 struct mutex mutex;
732 struct mlx4_bitmap bitmap;
733 struct mlx4_icm_table table;
734};
735
736struct mlx4_catas_err {
737 u32 __iomem *map;
738 struct timer_list timer;
739 struct list_head list;
740};
741
742#define MLX4_MAX_MAC_NUM 128
743#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
744
745struct mlx4_mac_table {
746 __be64 entries[MLX4_MAX_MAC_NUM];
747 int refs[MLX4_MAX_MAC_NUM];
748 bool is_dup[MLX4_MAX_MAC_NUM];
749 struct mutex mutex;
750 int total;
751 int max;
752};
753
754#define MLX4_ROCE_GID_ENTRY_SIZE 16
755
756struct mlx4_roce_gid_entry {
757 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
758};
759
760struct mlx4_roce_gid_table {
761 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
762 struct mutex mutex;
763};
764
765#define MLX4_MAX_VLAN_NUM 128
766#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
767
768struct mlx4_vlan_table {
769 __be32 entries[MLX4_MAX_VLAN_NUM];
770 int refs[MLX4_MAX_VLAN_NUM];
771 int is_dup[MLX4_MAX_VLAN_NUM];
772 struct mutex mutex;
773 int total;
774 int max;
775};
776
777#define SET_PORT_GEN_ALL_VALID (MLX4_FLAG_V_MTU_MASK | \
778 MLX4_FLAG_V_PPRX_MASK | \
779 MLX4_FLAG_V_PPTX_MASK)
780#define SET_PORT_PROMISC_SHIFT 31
781#define SET_PORT_MC_PROMISC_SHIFT 30
782
783enum {
784 MCAST_DIRECT_ONLY = 0,
785 MCAST_DIRECT = 1,
786 MCAST_DEFAULT = 2
787};
788
789
790struct mlx4_set_port_general_context {
791 u16 reserved1;
792 u8 flags2;
793 u8 flags;
794 union {
795 u8 ignore_fcs;
796 u8 roce_mode;
797 };
798 u8 reserved2;
799 __be16 mtu;
800 u8 pptx;
801 u8 pfctx;
802 u16 reserved3;
803 u8 pprx;
804 u8 pfcrx;
805 u16 reserved4;
806 u32 reserved5;
807 u8 phv_en;
808 u8 reserved6[5];
809 __be16 user_mtu;
810 u16 reserved7;
811 u8 user_mac[6];
812};
813
814struct mlx4_set_port_rqp_calc_context {
815 __be32 base_qpn;
816 u8 rererved;
817 u8 n_mac;
818 u8 n_vlan;
819 u8 n_prio;
820 u8 reserved2[3];
821 u8 mac_miss;
822 u8 intra_no_vlan;
823 u8 no_vlan;
824 u8 intra_vlan_miss;
825 u8 vlan_miss;
826 u8 reserved3[3];
827 u8 no_vlan_prio;
828 __be32 promisc;
829 __be32 mcast;
830};
831
832struct mlx4_port_info {
833 struct mlx4_dev *dev;
834 int port;
835 char dev_name[16];
836 struct device_attribute port_attr;
837 enum mlx4_port_type tmp_type;
838 char dev_mtu_name[16];
839 struct device_attribute port_mtu_attr;
840 struct mlx4_mac_table mac_table;
841 struct mlx4_vlan_table vlan_table;
842 struct mlx4_roce_gid_table gid_table;
843 int base_qpn;
844 struct cpu_rmap *rmap;
845 struct devlink_port devlink_port;
846};
847
848struct mlx4_sense {
849 struct mlx4_dev *dev;
850 u8 do_sense_port[MLX4_MAX_PORTS + 1];
851 u8 sense_allowed[MLX4_MAX_PORTS + 1];
852 struct delayed_work sense_poll;
853};
854
855struct mlx4_msix_ctl {
856 DECLARE_BITMAP(pool_bm, MAX_MSIX);
857 struct mutex pool_lock;
858};
859
860struct mlx4_steer {
861 struct list_head promisc_qps[MLX4_NUM_STEERS];
862 struct list_head steer_entries[MLX4_NUM_STEERS];
863};
864
865enum {
866 MLX4_PCI_DEV_IS_VF = 1 << 0,
867 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
868};
869
870enum {
871 MLX4_NO_RR = 0,
872 MLX4_USE_RR = 1,
873};
874
875struct mlx4_priv {
876 struct mlx4_dev dev;
877
878 struct list_head dev_list;
879 struct list_head ctx_list;
880 spinlock_t ctx_lock;
881
882 int pci_dev_data;
883 int removed;
884
885 struct list_head pgdir_list;
886 struct mutex pgdir_mutex;
887
888 struct mlx4_fw fw;
889 struct mlx4_cmd cmd;
890 struct mlx4_mfunc mfunc;
891
892 struct mlx4_bitmap pd_bitmap;
893 struct mlx4_bitmap xrcd_bitmap;
894 struct mlx4_uar_table uar_table;
895 struct mlx4_mr_table mr_table;
896 struct mlx4_cq_table cq_table;
897 struct mlx4_eq_table eq_table;
898 struct mlx4_srq_table srq_table;
899 struct mlx4_qp_table qp_table;
900 struct mlx4_mcg_table mcg_table;
901 struct mlx4_bitmap counters_bitmap;
902 int def_counter[MLX4_MAX_PORTS];
903
904 struct mlx4_catas_err catas_err;
905
906 void __iomem *clr_base;
907
908 struct mlx4_uar driver_uar;
909 void __iomem *kar;
910 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
911 struct mlx4_sense sense;
912 struct mutex port_mutex;
913 struct mlx4_msix_ctl msix_ctl;
914 struct mlx4_steer *steer;
915 struct list_head bf_list;
916 struct mutex bf_mutex;
917 struct io_mapping *bf_mapping;
918 void __iomem *clock_mapping;
919 int reserved_mtts;
920 int fs_hash_mode;
921 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
922 struct mlx4_port_map v2p;
923 struct mutex bond_mutex;
924 __be64 slave_node_guids[MLX4_MFUNC_MAX];
925
926 atomic_t opreq_count;
927 struct work_struct opreq_task;
928};
929
930static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
931{
932 return container_of(dev, struct mlx4_priv, dev);
933}
934
935#define MLX4_SENSE_RANGE (HZ * 3)
936
937extern struct workqueue_struct *mlx4_wq;
938
939u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
940void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
941u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
942 int align, u32 skip_mask);
943void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
944 int use_rr);
945u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
946int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
947 u32 reserved_bot, u32 resetrved_top);
948void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
949
950int mlx4_reset(struct mlx4_dev *dev);
951
952int mlx4_alloc_eq_table(struct mlx4_dev *dev);
953void mlx4_free_eq_table(struct mlx4_dev *dev);
954
955int mlx4_init_pd_table(struct mlx4_dev *dev);
956int mlx4_init_xrcd_table(struct mlx4_dev *dev);
957int mlx4_init_uar_table(struct mlx4_dev *dev);
958int mlx4_init_mr_table(struct mlx4_dev *dev);
959int mlx4_init_eq_table(struct mlx4_dev *dev);
960int mlx4_init_cq_table(struct mlx4_dev *dev);
961int mlx4_init_qp_table(struct mlx4_dev *dev);
962int mlx4_init_srq_table(struct mlx4_dev *dev);
963int mlx4_init_mcg_table(struct mlx4_dev *dev);
964
965void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
966void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
967void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
968void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
969void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
970void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
971void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
972void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
973void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
974int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
975void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
976int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
977void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
978int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
979void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
980int __mlx4_mpt_reserve(struct mlx4_dev *dev);
981void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
982int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
983void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
984u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
985void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
986
987int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
992int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
993 struct mlx4_vhcr *vhcr,
994 struct mlx4_cmd_mailbox *inbox,
995 struct mlx4_cmd_mailbox *outbox,
996 struct mlx4_cmd_info *cmd);
997int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
998 struct mlx4_vhcr *vhcr,
999 struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd);
1002int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd);
1007int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
1008 struct mlx4_vhcr *vhcr,
1009 struct mlx4_cmd_mailbox *inbox,
1010 struct mlx4_cmd_mailbox *outbox,
1011 struct mlx4_cmd_info *cmd);
1012int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1013 struct mlx4_vhcr *vhcr,
1014 struct mlx4_cmd_mailbox *inbox,
1015 struct mlx4_cmd_mailbox *outbox,
1016 struct mlx4_cmd_info *cmd);
1017int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
1018 struct mlx4_vhcr *vhcr,
1019 struct mlx4_cmd_mailbox *inbox,
1020 struct mlx4_cmd_mailbox *outbox,
1021 struct mlx4_cmd_info *cmd);
1022int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1023 struct mlx4_vhcr *vhcr,
1024 struct mlx4_cmd_mailbox *inbox,
1025 struct mlx4_cmd_mailbox *outbox,
1026 struct mlx4_cmd_info *cmd);
1027int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1028 int *base, u8 flags);
1029void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1030int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1031void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1032int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1033 int start_index, int npages, u64 *page_list);
1034int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1035void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1036int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1037 struct mlx4_counter *data);
1038int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1039void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1040
1041void mlx4_start_catas_poll(struct mlx4_dev *dev);
1042void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1043int mlx4_catas_init(struct mlx4_dev *dev);
1044void mlx4_catas_end(struct mlx4_dev *dev);
1045int mlx4_crdump_init(struct mlx4_dev *dev);
1046void mlx4_crdump_end(struct mlx4_dev *dev);
1047int mlx4_restart_one(struct pci_dev *pdev);
1048int mlx4_register_device(struct mlx4_dev *dev);
1049void mlx4_unregister_device(struct mlx4_dev *dev);
1050void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1051 unsigned long param);
1052
1053struct mlx4_dev_cap;
1054struct mlx4_init_hca_param;
1055
1056u64 mlx4_make_profile(struct mlx4_dev *dev,
1057 struct mlx4_profile *request,
1058 struct mlx4_dev_cap *dev_cap,
1059 struct mlx4_init_hca_param *init_hca);
1060void mlx4_master_comm_channel(struct work_struct *work);
1061void mlx4_gen_slave_eqe(struct work_struct *work);
1062void mlx4_master_handle_slave_flr(struct work_struct *work);
1063
1064int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1065 struct mlx4_vhcr *vhcr,
1066 struct mlx4_cmd_mailbox *inbox,
1067 struct mlx4_cmd_mailbox *outbox,
1068 struct mlx4_cmd_info *cmd);
1069int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1070 struct mlx4_vhcr *vhcr,
1071 struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd);
1074int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1075 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1076 struct mlx4_cmd_mailbox *outbox,
1077 struct mlx4_cmd_info *cmd);
1078int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1079 struct mlx4_vhcr *vhcr,
1080 struct mlx4_cmd_mailbox *inbox,
1081 struct mlx4_cmd_mailbox *outbox,
1082 struct mlx4_cmd_info *cmd);
1083int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1084 struct mlx4_vhcr *vhcr,
1085 struct mlx4_cmd_mailbox *inbox,
1086 struct mlx4_cmd_mailbox *outbox,
1087 struct mlx4_cmd_info *cmd);
1088int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1089 struct mlx4_vhcr *vhcr,
1090 struct mlx4_cmd_mailbox *inbox,
1091 struct mlx4_cmd_mailbox *outbox,
1092 struct mlx4_cmd_info *cmd);
1093int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1094 struct mlx4_vhcr *vhcr,
1095 struct mlx4_cmd_mailbox *inbox,
1096 struct mlx4_cmd_mailbox *outbox,
1097 struct mlx4_cmd_info *cmd);
1098int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1099 struct mlx4_vhcr *vhcr,
1100 struct mlx4_cmd_mailbox *inbox,
1101 struct mlx4_cmd_mailbox *outbox,
1102 struct mlx4_cmd_info *cmd);
1103int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1104 struct mlx4_vhcr *vhcr,
1105 struct mlx4_cmd_mailbox *inbox,
1106 struct mlx4_cmd_mailbox *outbox,
1107 struct mlx4_cmd_info *cmd);
1108int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1109 struct mlx4_vhcr *vhcr,
1110 struct mlx4_cmd_mailbox *inbox,
1111 struct mlx4_cmd_mailbox *outbox,
1112 struct mlx4_cmd_info *cmd);
1113int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1114 struct mlx4_vhcr *vhcr,
1115 struct mlx4_cmd_mailbox *inbox,
1116 struct mlx4_cmd_mailbox *outbox,
1117 struct mlx4_cmd_info *cmd);
1118int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1119 struct mlx4_vhcr *vhcr,
1120 struct mlx4_cmd_mailbox *inbox,
1121 struct mlx4_cmd_mailbox *outbox,
1122 struct mlx4_cmd_info *cmd);
1123int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1124 struct mlx4_vhcr *vhcr,
1125 struct mlx4_cmd_mailbox *inbox,
1126 struct mlx4_cmd_mailbox *outbox,
1127 struct mlx4_cmd_info *cmd);
1128int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1129 struct mlx4_vhcr *vhcr,
1130 struct mlx4_cmd_mailbox *inbox,
1131 struct mlx4_cmd_mailbox *outbox,
1132 struct mlx4_cmd_info *cmd);
1133int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1134 struct mlx4_vhcr *vhcr,
1135 struct mlx4_cmd_mailbox *inbox,
1136 struct mlx4_cmd_mailbox *outbox,
1137 struct mlx4_cmd_info *cmd);
1138int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1139 struct mlx4_vhcr *vhcr,
1140 struct mlx4_cmd_mailbox *inbox,
1141 struct mlx4_cmd_mailbox *outbox,
1142 struct mlx4_cmd_info *cmd);
1143int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1144 struct mlx4_vhcr *vhcr,
1145 struct mlx4_cmd_mailbox *inbox,
1146 struct mlx4_cmd_mailbox *outbox,
1147 struct mlx4_cmd_info *cmd);
1148int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1149 struct mlx4_vhcr *vhcr,
1150 struct mlx4_cmd_mailbox *inbox,
1151 struct mlx4_cmd_mailbox *outbox,
1152 struct mlx4_cmd_info *cmd);
1153int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1154 struct mlx4_vhcr *vhcr,
1155 struct mlx4_cmd_mailbox *inbox,
1156 struct mlx4_cmd_mailbox *outbox,
1157 struct mlx4_cmd_info *cmd);
1158int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1159 struct mlx4_vhcr *vhcr,
1160 struct mlx4_cmd_mailbox *inbox,
1161 struct mlx4_cmd_mailbox *outbox,
1162 struct mlx4_cmd_info *cmd);
1163int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1164 struct mlx4_vhcr *vhcr,
1165 struct mlx4_cmd_mailbox *inbox,
1166 struct mlx4_cmd_mailbox *outbox,
1167 struct mlx4_cmd_info *cmd);
1168int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1169 struct mlx4_vhcr *vhcr,
1170 struct mlx4_cmd_mailbox *inbox,
1171 struct mlx4_cmd_mailbox *outbox,
1172 struct mlx4_cmd_info *cmd);
1173int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1174 struct mlx4_vhcr *vhcr,
1175 struct mlx4_cmd_mailbox *inbox,
1176 struct mlx4_cmd_mailbox *outbox,
1177 struct mlx4_cmd_info *cmd);
1178int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1179 struct mlx4_vhcr *vhcr,
1180 struct mlx4_cmd_mailbox *inbox,
1181 struct mlx4_cmd_mailbox *outbox,
1182 struct mlx4_cmd_info *cmd);
1183int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1184 struct mlx4_vhcr *vhcr,
1185 struct mlx4_cmd_mailbox *inbox,
1186 struct mlx4_cmd_mailbox *outbox,
1187 struct mlx4_cmd_info *cmd);
1188int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1189 struct mlx4_vhcr *vhcr,
1190 struct mlx4_cmd_mailbox *inbox,
1191 struct mlx4_cmd_mailbox *outbox,
1192 struct mlx4_cmd_info *cmd);
1193int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1194 struct mlx4_vhcr *vhcr,
1195 struct mlx4_cmd_mailbox *inbox,
1196 struct mlx4_cmd_mailbox *outbox,
1197 struct mlx4_cmd_info *cmd);
1198
1199int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1200
1201enum {
1202 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1203 MLX4_CMD_CLEANUP_POOL = 1UL << 1,
1204 MLX4_CMD_CLEANUP_HCR = 1UL << 2,
1205 MLX4_CMD_CLEANUP_VHCR = 1UL << 3,
1206 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1207};
1208
1209int mlx4_cmd_init(struct mlx4_dev *dev);
1210void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1211int mlx4_multi_func_init(struct mlx4_dev *dev);
1212int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1213void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1214void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1215int mlx4_cmd_use_events(struct mlx4_dev *dev);
1216void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1217
1218int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1219 u16 op, unsigned long timeout);
1220
1221void mlx4_cq_tasklet_cb(struct tasklet_struct *t);
1222void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1223void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1224
1225void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1226
1227void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1228
1229void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1230int mlx4_comm_internal_err(u32 slave_read);
1231
1232int mlx4_crdump_collect(struct mlx4_dev *dev);
1233
1234int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1235 enum mlx4_port_type *type);
1236void mlx4_do_sense_ports(struct mlx4_dev *dev,
1237 enum mlx4_port_type *stype,
1238 enum mlx4_port_type *defaults);
1239void mlx4_start_sense(struct mlx4_dev *dev);
1240void mlx4_stop_sense(struct mlx4_dev *dev);
1241void mlx4_sense_init(struct mlx4_dev *dev);
1242int mlx4_check_port_params(struct mlx4_dev *dev,
1243 enum mlx4_port_type *port_type);
1244int mlx4_change_port_types(struct mlx4_dev *dev,
1245 enum mlx4_port_type *port_types);
1246
1247void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1248void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1249void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1250 struct mlx4_roce_gid_table *table);
1251void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1252int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1253int mlx4_bond_vlan_table(struct mlx4_dev *dev);
1254int mlx4_unbond_vlan_table(struct mlx4_dev *dev);
1255int mlx4_bond_mac_table(struct mlx4_dev *dev);
1256int mlx4_unbond_mac_table(struct mlx4_dev *dev);
1257
1258int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1259
1260int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1261 enum mlx4_resource resource_type,
1262 u64 resource_id, int *slave);
1263void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1264void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1265int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1266
1267void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1268 enum mlx4_res_tracker_free_type type);
1269
1270int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1271 struct mlx4_vhcr *vhcr,
1272 struct mlx4_cmd_mailbox *inbox,
1273 struct mlx4_cmd_mailbox *outbox,
1274 struct mlx4_cmd_info *cmd);
1275int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1276 struct mlx4_vhcr *vhcr,
1277 struct mlx4_cmd_mailbox *inbox,
1278 struct mlx4_cmd_mailbox *outbox,
1279 struct mlx4_cmd_info *cmd);
1280int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1281 struct mlx4_vhcr *vhcr,
1282 struct mlx4_cmd_mailbox *inbox,
1283 struct mlx4_cmd_mailbox *outbox,
1284 struct mlx4_cmd_info *cmd);
1285int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1286 struct mlx4_vhcr *vhcr,
1287 struct mlx4_cmd_mailbox *inbox,
1288 struct mlx4_cmd_mailbox *outbox,
1289 struct mlx4_cmd_info *cmd);
1290int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1291 struct mlx4_vhcr *vhcr,
1292 struct mlx4_cmd_mailbox *inbox,
1293 struct mlx4_cmd_mailbox *outbox,
1294 struct mlx4_cmd_info *cmd);
1295int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1296 struct mlx4_vhcr *vhcr,
1297 struct mlx4_cmd_mailbox *inbox,
1298 struct mlx4_cmd_mailbox *outbox,
1299 struct mlx4_cmd_info *cmd);
1300int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1301
1302int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1303 int *gid_tbl_len, int *pkey_tbl_len);
1304
1305int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1306 struct mlx4_vhcr *vhcr,
1307 struct mlx4_cmd_mailbox *inbox,
1308 struct mlx4_cmd_mailbox *outbox,
1309 struct mlx4_cmd_info *cmd);
1310
1311int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1312 struct mlx4_vhcr *vhcr,
1313 struct mlx4_cmd_mailbox *inbox,
1314 struct mlx4_cmd_mailbox *outbox,
1315 struct mlx4_cmd_info *cmd);
1316
1317int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1318 struct mlx4_vhcr *vhcr,
1319 struct mlx4_cmd_mailbox *inbox,
1320 struct mlx4_cmd_mailbox *outbox,
1321 struct mlx4_cmd_info *cmd);
1322int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1323 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1324int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1325 int block_mcast_loopback, enum mlx4_protocol prot,
1326 enum mlx4_steer_type steer);
1327int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1328 u8 gid[16], u8 port,
1329 int block_mcast_loopback,
1330 enum mlx4_protocol prot, u64 *reg_id);
1331int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1332 struct mlx4_vhcr *vhcr,
1333 struct mlx4_cmd_mailbox *inbox,
1334 struct mlx4_cmd_mailbox *outbox,
1335 struct mlx4_cmd_info *cmd);
1336int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1337 struct mlx4_vhcr *vhcr,
1338 struct mlx4_cmd_mailbox *inbox,
1339 struct mlx4_cmd_mailbox *outbox,
1340 struct mlx4_cmd_info *cmd);
1341int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1342 int port, void *buf);
1343int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1344 struct mlx4_vhcr *vhcr,
1345 struct mlx4_cmd_mailbox *inbox,
1346 struct mlx4_cmd_mailbox *outbox,
1347 struct mlx4_cmd_info *cmd);
1348int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1349 struct mlx4_vhcr *vhcr,
1350 struct mlx4_cmd_mailbox *inbox,
1351 struct mlx4_cmd_mailbox *outbox,
1352 struct mlx4_cmd_info *cmd);
1353int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1354 struct mlx4_vhcr *vhcr,
1355 struct mlx4_cmd_mailbox *inbox,
1356 struct mlx4_cmd_mailbox *outbox,
1357 struct mlx4_cmd_info *cmd);
1358int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1359 struct mlx4_vhcr *vhcr,
1360 struct mlx4_cmd_mailbox *inbox,
1361 struct mlx4_cmd_mailbox *outbox,
1362 struct mlx4_cmd_info *cmd);
1363int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1364 struct mlx4_vhcr *vhcr,
1365 struct mlx4_cmd_mailbox *inbox,
1366 struct mlx4_cmd_mailbox *outbox,
1367 struct mlx4_cmd_info *cmd);
1368int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1369 struct mlx4_vhcr *vhcr,
1370 struct mlx4_cmd_mailbox *inbox,
1371 struct mlx4_cmd_mailbox *outbox,
1372 struct mlx4_cmd_info *cmd);
1373
1374int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1375int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1376
1377static inline void set_param_l(u64 *arg, u32 val)
1378{
1379 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1380}
1381
1382static inline void set_param_h(u64 *arg, u32 val)
1383{
1384 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1385}
1386
1387static inline u32 get_param_l(u64 *arg)
1388{
1389 return (u32) (*arg & 0xffffffff);
1390}
1391
1392static inline u32 get_param_h(u64 *arg)
1393{
1394 return (u32)(*arg >> 32);
1395}
1396
1397static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1398{
1399 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1400}
1401
1402#define NOT_MASKED_PD_BITS 17
1403
1404void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1405
1406void mlx4_init_quotas(struct mlx4_dev *dev);
1407
1408
1409void mlx4_replace_zero_macs(struct mlx4_dev *dev);
1410int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1411
1412int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1413int mlx4_config_mad_demux(struct mlx4_dev *dev);
1414int mlx4_do_bond(struct mlx4_dev *dev, bool enable);
1415int mlx4_bond_fs_rules(struct mlx4_dev *dev);
1416int mlx4_unbond_fs_rules(struct mlx4_dev *dev);
1417
1418enum mlx4_zone_flags {
1419 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0,
1420 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1,
1421 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2,
1422 MLX4_ZONE_USE_RR = 1UL << 3,
1423};
1424
1425enum mlx4_zone_alloc_flags {
1426
1427
1428
1429
1430
1431 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0,
1432};
1433
1434struct mlx4_zone_allocator;
1435
1436
1437struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1449 struct mlx4_bitmap *bitmap,
1450 u32 flags,
1451 int priority,
1452 int offset,
1453 u32 *puid);
1454
1455
1456int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1457
1458
1459
1460
1461void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1462
1463
1464
1465
1466
1467
1468u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1469 int align, u32 skip_mask, u32 *puid);
1470
1471
1472
1473
1474u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1475 u32 uid, u32 obj, u32 count);
1476
1477
1478
1479
1480
1481u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1482
1483
1484struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);
1485
1486#endif
1487