LXR linux/drivers/net/ethernet/mellanox/mlx5/core/en

   1/*
   2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#ifndef __MLX5_EN_TC_H__
  34#define __MLX5_EN_TC_H__
  35
  36#include <net/pkt_cls.h>
  37#include "en.h"
  38#include "eswitch.h"
  39#include "en/tc_ct.h"
  40#include "en/tc_tun.h"
  41#include "en_rep.h"
  42
  43#define MLX5E_TC_FLOW_ID_MASK 0x0000ffff
  44
  45#ifdef CONFIG_MLX5_ESWITCH
  46
  47#define NIC_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
  48                          sizeof(struct mlx5_nic_flow_attr))
  49#define ESW_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
  50                          sizeof(struct mlx5_esw_flow_attr))
  51#define ns_to_attr_sz(ns) (((ns) == MLX5_FLOW_NAMESPACE_FDB) ?\
  52                            ESW_FLOW_ATTR_SZ :\
  53                            NIC_FLOW_ATTR_SZ)
  54
  55
  56int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags);
  57
  58struct mlx5e_tc_update_priv {
  59        struct net_device *tun_dev;
  60};
  61
  62struct mlx5_nic_flow_attr {
  63        u32 flow_tag;
  64        u32 hairpin_tirn;
  65        struct mlx5_flow_table *hairpin_ft;
  66};
  67
  68struct mlx5_flow_attr {
  69        u32 action;
  70        struct mlx5_fc *counter;
  71        struct mlx5_modify_hdr *modify_hdr;
  72        struct mlx5_ct_attr ct_attr;
  73        struct mlx5e_sample_attr *sample_attr;
  74        struct mlx5e_tc_flow_parse_attr *parse_attr;
  75        u32 chain;
  76        u16 prio;
  77        u32 dest_chain;
  78        struct mlx5_flow_table *ft;
  79        struct mlx5_flow_table *dest_ft;
  80        u8 inner_match_level;
  81        u8 outer_match_level;
  82        u8 ip_version;
  83        u8 tun_ip_version;
  84        u32 flags;
  85        union {
  86                struct mlx5_esw_flow_attr esw_attr[0];
  87                struct mlx5_nic_flow_attr nic_attr[0];
  88        };
  89};
  90
  91struct mlx5_rx_tun_attr {
  92        u16 decap_vport;
  93        union {
  94                __be32 v4;
  95                struct in6_addr v6;
  96        } src_ip; /* Valid if decap_vport is not zero */
  97        union {
  98                __be32 v4;
  99                struct in6_addr v6;
 100        } dst_ip; /* Valid if decap_vport is not zero */
 101        u32 vni;
 102};
 103
 104#define MLX5E_TC_TABLE_CHAIN_TAG_BITS 16
 105#define MLX5E_TC_TABLE_CHAIN_TAG_MASK GENMASK(MLX5E_TC_TABLE_CHAIN_TAG_BITS - 1, 0)
 106
 107#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
 108
 109struct tunnel_match_key {
 110        struct flow_dissector_key_control enc_control;
 111        struct flow_dissector_key_keyid enc_key_id;
 112        struct flow_dissector_key_ports enc_tp;
 113        struct flow_dissector_key_ip enc_ip;
 114        union {
 115                struct flow_dissector_key_ipv4_addrs enc_ipv4;
 116                struct flow_dissector_key_ipv6_addrs enc_ipv6;
 117        };
 118
 119        int filter_ifindex;
 120};
 121
 122struct tunnel_match_enc_opts {
 123        struct flow_dissector_key_enc_opts key;
 124        struct flow_dissector_key_enc_opts mask;
 125};
 126
 127/* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
 128 * Upper TUNNEL_INFO_BITS for general tunnel info.
 129 * Lower ENC_OPTS_BITS bits for enc_opts.
 130 */
 131#define TUNNEL_INFO_BITS 12
 132#define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
 133#define ENC_OPTS_BITS 11
 134#define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
 135#define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
 136#define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
 137
 138enum {
 139        MLX5E_TC_FLAG_INGRESS_BIT,
 140        MLX5E_TC_FLAG_EGRESS_BIT,
 141        MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
 142        MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
 143        MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
 144        MLX5E_TC_FLAG_LAST_EXPORTED_BIT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
 145};
 146
 147#define MLX5_TC_FLAG(flag) BIT(MLX5E_TC_FLAG_##flag##_BIT)
 148
 149int mlx5e_tc_esw_init(struct rhashtable *tc_ht);
 150void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht);
 151bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow);
 152
 153int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
 154                           struct flow_cls_offload *f, unsigned long flags);
 155int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
 156                        struct flow_cls_offload *f, unsigned long flags);
 157
 158int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
 159                       struct flow_cls_offload *f, unsigned long flags);
 160
 161int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
 162                                struct tc_cls_matchall_offload *f);
 163int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
 164                             struct tc_cls_matchall_offload *f);
 165void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
 166                             struct tc_cls_matchall_offload *ma);
 167
 168struct mlx5e_encap_entry;
 169void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
 170                              struct mlx5e_encap_entry *e,
 171                              struct list_head *flow_list);
 172void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
 173                              struct mlx5e_encap_entry *e,
 174                              struct list_head *flow_list);
 175bool mlx5e_encap_take(struct mlx5e_encap_entry *e);
 176void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e);
 177
 178void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list);
 179void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list);
 180
 181struct mlx5e_neigh_hash_entry;
 182struct mlx5e_encap_entry *
 183mlx5e_get_next_init_encap(struct mlx5e_neigh_hash_entry *nhe,
 184                          struct mlx5e_encap_entry *e);
 185void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe);
 186
 187void mlx5e_tc_reoffload_flows_work(struct work_struct *work);
 188
 189enum mlx5e_tc_attr_to_reg {
 190        CHAIN_TO_REG,
 191        VPORT_TO_REG,
 192        TUNNEL_TO_REG,
 193        CTSTATE_TO_REG,
 194        ZONE_TO_REG,
 195        ZONE_RESTORE_TO_REG,
 196        MARK_TO_REG,
 197        LABELS_TO_REG,
 198        FTEID_TO_REG,
 199        NIC_CHAIN_TO_REG,
 200        NIC_ZONE_RESTORE_TO_REG,
 201};
 202
 203struct mlx5e_tc_attr_to_reg_mapping {
 204        int mfield; /* rewrite field */
 205        int moffset; /* bit offset of mfield */
 206        int mlen; /* bits to rewrite/match */
 207
 208        int soffset; /* byte offset of spec for match */
 209};
 210
 211extern struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[];
 212
 213bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
 214                                    struct net_device *out_dev);
 215
 216int mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
 217                              struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 218                              enum mlx5_flow_namespace_type ns,
 219                              enum mlx5e_tc_attr_to_reg type,
 220                              u32 data);
 221
 222void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
 223                                          struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 224                                          enum mlx5e_tc_attr_to_reg type,
 225                                          int act_id, u32 data);
 226
 227void mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
 228                                 enum mlx5e_tc_attr_to_reg type,
 229                                 u32 data,
 230                                 u32 mask);
 231
 232void mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
 233                                     enum mlx5e_tc_attr_to_reg type,
 234                                     u32 *data,
 235                                     u32 *mask);
 236
 237int mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
 238                                         struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
 239                                         enum mlx5_flow_namespace_type ns,
 240                                         enum mlx5e_tc_attr_to_reg type,
 241                                         u32 data);
 242
 243int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
 244                              struct mlx5e_tc_flow_parse_attr *parse_attr,
 245                              struct mlx5e_tc_flow *flow);
 246
 247int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
 248                          int namespace,
 249                          struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts);
 250void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts);
 251
 252struct mlx5e_tc_flow;
 253u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow);
 254
 255void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
 256                            struct flow_match_basic *match, bool outer,
 257                            void *headers_c, void *headers_v);
 258
 259int mlx5e_tc_nic_init(struct mlx5e_priv *priv);
 260void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv);
 261
 262int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
 263                            void *cb_priv);
 264
 265struct mlx5_flow_handle *
 266mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
 267                             struct mlx5_flow_spec *spec,
 268                             struct mlx5_flow_attr *attr);
 269void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
 270                                  struct mlx5_flow_handle *rule,
 271                                  struct mlx5_flow_attr *attr);
 272
 273struct mlx5_flow_handle *
 274mlx5_tc_rule_insert(struct mlx5e_priv *priv,
 275                    struct mlx5_flow_spec *spec,
 276                    struct mlx5_flow_attr *attr);
 277void
 278mlx5_tc_rule_delete(struct mlx5e_priv *priv,
 279                    struct mlx5_flow_handle *rule,
 280                    struct mlx5_flow_attr *attr);
 281
 282bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev);
 283int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev,
 284                               u16 *vport);
 285
 286#else /* CONFIG_MLX5_CLS_ACT */
 287static inline int  mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
 288static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
 289static inline int
 290mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
 291{ return -EOPNOTSUPP; }
 292
 293#endif /* CONFIG_MLX5_CLS_ACT */
 294
 295struct mlx5_flow_attr *mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type);
 296
 297struct mlx5_flow_handle *
 298mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
 299                             struct mlx5_flow_spec *spec,
 300                             struct mlx5_flow_attr *attr);
 301void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
 302                                  struct mlx5_flow_handle *rule,
 303                                  struct mlx5_flow_attr *attr);
 304
 305#else /* CONFIG_MLX5_ESWITCH */
 306static inline int  mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
 307static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
 308static inline int  mlx5e_tc_num_filters(struct mlx5e_priv *priv,
 309                                        unsigned long flags)
 310{
 311        return 0;
 312}
 313
 314static inline int
 315mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
 316{ return -EOPNOTSUPP; }
 317#endif
 318
 319#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
 320static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
 321{
 322#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
 323        u32 chain, reg_b;
 324
 325        reg_b = be32_to_cpu(cqe->ft_metadata);
 326
 327        if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))
 328                return false;
 329
 330        chain = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
 331        if (chain)
 332                return true;
 333#endif
 334
 335        return false;
 336}
 337
 338bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb);
 339#else /* CONFIG_MLX5_CLS_ACT */
 340static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
 341{ return false; }
 342static inline bool
 343mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
 344{ return true; }
 345#endif
 346
 347#endif /* __MLX5_EN_TC_H__ */
 348