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33#include <linux/etherdevice.h>
34#include <linux/idr.h>
35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
41#include "esw/indir_table.h"
42#include "esw/acl/ofld.h"
43#include "rdma.h"
44#include "en.h"
45#include "fs_core.h"
46#include "lib/devcom.h"
47#include "lib/eq.h"
48#include "lib/fs_chains.h"
49#include "en_tc.h"
50#include "en/mapping.h"
51#include "devlink.h"
52
53#define mlx5_esw_for_each_rep(esw, i, rep) \
54 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
55
56#define mlx5_esw_for_each_sf_rep(esw, i, rep) \
57 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
58
59#define mlx5_esw_for_each_vf_rep(esw, index, rep) \
60 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
61 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
62
63
64
65
66#define MLX5_ESW_MISS_FLOWS (2)
67#define UPLINK_REP_INDEX 0
68
69#define MLX5_ESW_VPORT_TBL_SIZE 128
70#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
71
72static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
73 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
74 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
75 .flags = 0,
76};
77
78static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
79 u16 vport_num)
80{
81 return xa_load(&esw->offloads.vport_reps, vport_num);
82}
83
84static void
85mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
86 struct mlx5_flow_spec *spec,
87 struct mlx5_esw_flow_attr *attr)
88{
89 if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) &&
90 attr && attr->in_rep)
91 spec->flow_context.flow_source =
92 attr->in_rep->vport == MLX5_VPORT_UPLINK ?
93 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
94 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
95}
96
97
98
99
100void
101mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
102{
103 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
104 void *misc2;
105
106 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
107 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
108
109 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
110 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
111
112 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
113 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
114 }
115}
116
117static void
118mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
119 struct mlx5_flow_spec *spec,
120 struct mlx5_flow_attr *attr,
121 struct mlx5_eswitch *src_esw,
122 u16 vport)
123{
124 void *misc2;
125 void *misc;
126
127
128
129
130 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
131 if (mlx5_esw_indir_table_decap_vport(attr))
132 vport = mlx5_esw_indir_table_decap_vport(attr);
133 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
134 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
135 mlx5_eswitch_get_vport_metadata_for_match(src_esw,
136 vport));
137
138 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
139 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
140 mlx5_eswitch_get_vport_metadata_mask());
141
142 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
143 } else {
144 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
145 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
146
147 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
148 MLX5_SET(fte_match_set_misc, misc,
149 source_eswitch_owner_vhca_id,
150 MLX5_CAP_GEN(src_esw->dev, vhca_id));
151
152 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
153 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
154 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
155 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
156 source_eswitch_owner_vhca_id);
157
158 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
159 }
160}
161
162static int
163esw_setup_decap_indir(struct mlx5_eswitch *esw,
164 struct mlx5_flow_attr *attr,
165 struct mlx5_flow_spec *spec)
166{
167 struct mlx5_flow_table *ft;
168
169 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
170 return -EOPNOTSUPP;
171
172 ft = mlx5_esw_indir_table_get(esw, attr, spec,
173 mlx5_esw_indir_table_decap_vport(attr), true);
174 return PTR_ERR_OR_ZERO(ft);
175}
176
177static void
178esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
179 struct mlx5_flow_attr *attr)
180{
181 if (mlx5_esw_indir_table_decap_vport(attr))
182 mlx5_esw_indir_table_put(esw, attr,
183 mlx5_esw_indir_table_decap_vport(attr),
184 true);
185}
186
187static int
188esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
189 struct mlx5_flow_act *flow_act,
190 struct mlx5_flow_attr *attr,
191 int i)
192{
193 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
194 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
195 dest[i].sampler_id = attr->sample_attr->sampler_id;
196
197 return 0;
198}
199
200static int
201esw_setup_ft_dest(struct mlx5_flow_destination *dest,
202 struct mlx5_flow_act *flow_act,
203 struct mlx5_eswitch *esw,
204 struct mlx5_flow_attr *attr,
205 struct mlx5_flow_spec *spec,
206 int i)
207{
208 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
209 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
210 dest[i].ft = attr->dest_ft;
211
212 if (mlx5_esw_indir_table_decap_vport(attr))
213 return esw_setup_decap_indir(esw, attr, spec);
214 return 0;
215}
216
217static void
218esw_setup_slow_path_dest(struct mlx5_flow_destination *dest,
219 struct mlx5_flow_act *flow_act,
220 struct mlx5_fs_chains *chains,
221 int i)
222{
223 if (mlx5_chains_ignore_flow_level_supported(chains))
224 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
225 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
226 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
227}
228
229static int
230esw_setup_chain_dest(struct mlx5_flow_destination *dest,
231 struct mlx5_flow_act *flow_act,
232 struct mlx5_fs_chains *chains,
233 u32 chain, u32 prio, u32 level,
234 int i)
235{
236 struct mlx5_flow_table *ft;
237
238 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
239 ft = mlx5_chains_get_table(chains, chain, prio, level);
240 if (IS_ERR(ft))
241 return PTR_ERR(ft);
242
243 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
244 dest[i].ft = ft;
245 return 0;
246}
247
248static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
249 int from, int to)
250{
251 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
252 struct mlx5_fs_chains *chains = esw_chains(esw);
253 int i;
254
255 for (i = from; i < to; i++)
256 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
257 mlx5_chains_put_table(chains, 0, 1, 0);
258 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
259 esw_attr->dests[i].mdev))
260 mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport,
261 false);
262}
263
264static bool
265esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
266{
267 int i;
268
269 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
270 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
271 return true;
272 return false;
273}
274
275static int
276esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
277 struct mlx5_flow_act *flow_act,
278 struct mlx5_eswitch *esw,
279 struct mlx5_fs_chains *chains,
280 struct mlx5_flow_attr *attr,
281 int *i)
282{
283 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
284 int j, err;
285
286 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
287 return -EOPNOTSUPP;
288
289 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
290 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
291 if (err)
292 goto err_setup_chain;
293 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
294 flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat;
295 }
296 return 0;
297
298err_setup_chain:
299 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
300 return err;
301}
302
303static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
304 struct mlx5_flow_attr *attr)
305{
306 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
307
308 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
309}
310
311static bool
312esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
313{
314 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
315 int i;
316
317 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
318 if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
319 esw_attr->dests[i].mdev))
320 return true;
321 return false;
322}
323
324static int
325esw_setup_indir_table(struct mlx5_flow_destination *dest,
326 struct mlx5_flow_act *flow_act,
327 struct mlx5_eswitch *esw,
328 struct mlx5_flow_attr *attr,
329 struct mlx5_flow_spec *spec,
330 bool ignore_flow_lvl,
331 int *i)
332{
333 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
334 int j, err;
335
336 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE))
337 return -EOPNOTSUPP;
338
339 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
340 if (ignore_flow_lvl)
341 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
342 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
343
344 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec,
345 esw_attr->dests[j].rep->vport, false);
346 if (IS_ERR(dest[*i].ft)) {
347 err = PTR_ERR(dest[*i].ft);
348 goto err_indir_tbl_get;
349 }
350 }
351
352 if (mlx5_esw_indir_table_decap_vport(attr)) {
353 err = esw_setup_decap_indir(esw, attr, spec);
354 if (err)
355 goto err_indir_tbl_get;
356 }
357
358 return 0;
359
360err_indir_tbl_get:
361 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
362 return err;
363}
364
365static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
366{
367 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
368
369 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
370 esw_cleanup_decap_indir(esw, attr);
371}
372
373static void
374esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
375{
376 mlx5_chains_put_table(chains, chain, prio, level);
377}
378
379static void
380esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
381 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
382 int attr_idx, int dest_idx, bool pkt_reformat)
383{
384 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
385 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
386 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
387 dest[dest_idx].vport.vhca_id =
388 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
389 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
390 }
391 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) {
392 if (pkt_reformat) {
393 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
394 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
395 }
396 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
397 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
398 }
399}
400
401static int
402esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
403 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
404 int i)
405{
406 int j;
407
408 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
409 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
410 return i;
411}
412
413static bool
414esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
415{
416 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
417 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
418 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
419}
420
421static int
422esw_setup_dests(struct mlx5_flow_destination *dest,
423 struct mlx5_flow_act *flow_act,
424 struct mlx5_eswitch *esw,
425 struct mlx5_flow_attr *attr,
426 struct mlx5_flow_spec *spec,
427 int *i)
428{
429 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
430 struct mlx5_fs_chains *chains = esw_chains(esw);
431 int err = 0;
432
433 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
434 esw_src_port_rewrite_supported(esw))
435 attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE;
436
437 if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) {
438 esw_setup_sampler_dest(dest, flow_act, attr, *i);
439 (*i)++;
440 } else if (attr->dest_ft) {
441 esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i);
442 (*i)++;
443 } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) {
444 esw_setup_slow_path_dest(dest, flow_act, chains, *i);
445 (*i)++;
446 } else if (attr->dest_chain) {
447 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
448 1, 0, *i);
449 (*i)++;
450 } else if (esw_is_indir_table(esw, attr)) {
451 err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i);
452 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
453 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
454 } else {
455 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
456 }
457
458 return err;
459}
460
461static void
462esw_cleanup_dests(struct mlx5_eswitch *esw,
463 struct mlx5_flow_attr *attr)
464{
465 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
466 struct mlx5_fs_chains *chains = esw_chains(esw);
467
468 if (attr->dest_ft) {
469 esw_cleanup_decap_indir(esw, attr);
470 } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
471 if (attr->dest_chain)
472 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
473 else if (esw_is_indir_table(esw, attr))
474 esw_cleanup_indir_table(esw, attr);
475 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
476 esw_cleanup_chain_src_port_rewrite(esw, attr);
477 }
478}
479
480struct mlx5_flow_handle *
481mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
482 struct mlx5_flow_spec *spec,
483 struct mlx5_flow_attr *attr)
484{
485 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
486 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
487 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
488 struct mlx5_fs_chains *chains = esw_chains(esw);
489 bool split = !!(esw_attr->split_count);
490 struct mlx5_vport_tbl_attr fwd_attr;
491 struct mlx5_flow_handle *rule;
492 struct mlx5_flow_table *fdb;
493 int i = 0;
494
495 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
496 return ERR_PTR(-EOPNOTSUPP);
497
498 flow_act.action = attr->action;
499
500 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
501 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
502 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
503 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
504 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
505 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
506 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
507 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
508 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
509 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
510 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
511 }
512 }
513
514 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
515
516 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
517 int err;
518
519 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
520 if (err) {
521 rule = ERR_PTR(err);
522 goto err_create_goto_table;
523 }
524 }
525
526 if (esw_attr->decap_pkt_reformat)
527 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
528
529 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
530 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
531 dest[i].counter_id = mlx5_fc_id(attr->counter);
532 i++;
533 }
534
535 if (attr->outer_match_level != MLX5_MATCH_NONE)
536 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
537 if (attr->inner_match_level != MLX5_MATCH_NONE)
538 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
539
540 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
541 flow_act.modify_hdr = attr->modify_hdr;
542
543 if (split) {
544 fwd_attr.chain = attr->chain;
545 fwd_attr.prio = attr->prio;
546 fwd_attr.vport = esw_attr->in_rep->vport;
547 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
548
549 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
550 } else {
551 if (attr->chain || attr->prio)
552 fdb = mlx5_chains_get_table(chains, attr->chain,
553 attr->prio, 0);
554 else
555 fdb = attr->ft;
556
557 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT))
558 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
559 esw_attr->in_mdev->priv.eswitch,
560 esw_attr->in_rep->vport);
561 }
562 if (IS_ERR(fdb)) {
563 rule = ERR_CAST(fdb);
564 goto err_esw_get;
565 }
566
567 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
568 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
569 &flow_act, dest, i);
570 else
571 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
572 if (IS_ERR(rule))
573 goto err_add_rule;
574 else
575 atomic64_inc(&esw->offloads.num_flows);
576
577 return rule;
578
579err_add_rule:
580 if (split)
581 mlx5_esw_vporttbl_put(esw, &fwd_attr);
582 else if (attr->chain || attr->prio)
583 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
584err_esw_get:
585 esw_cleanup_dests(esw, attr);
586err_create_goto_table:
587 return rule;
588}
589
590struct mlx5_flow_handle *
591mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
592 struct mlx5_flow_spec *spec,
593 struct mlx5_flow_attr *attr)
594{
595 struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {};
596 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
597 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
598 struct mlx5_fs_chains *chains = esw_chains(esw);
599 struct mlx5_vport_tbl_attr fwd_attr;
600 struct mlx5_flow_table *fast_fdb;
601 struct mlx5_flow_table *fwd_fdb;
602 struct mlx5_flow_handle *rule;
603 int i, err = 0;
604
605 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
606 if (IS_ERR(fast_fdb)) {
607 rule = ERR_CAST(fast_fdb);
608 goto err_get_fast;
609 }
610
611 fwd_attr.chain = attr->chain;
612 fwd_attr.prio = attr->prio;
613 fwd_attr.vport = esw_attr->in_rep->vport;
614 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
615 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
616 if (IS_ERR(fwd_fdb)) {
617 rule = ERR_CAST(fwd_fdb);
618 goto err_get_fwd;
619 }
620
621 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
622 for (i = 0; i < esw_attr->split_count; i++) {
623 if (esw_is_indir_table(esw, attr))
624 err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i);
625 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
626 err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr,
627 &i);
628 else
629 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
630
631 if (err) {
632 rule = ERR_PTR(err);
633 goto err_chain_src_rewrite;
634 }
635 }
636 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
637 dest[i].ft = fwd_fdb;
638 i++;
639
640 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
641 esw_attr->in_mdev->priv.eswitch,
642 esw_attr->in_rep->vport);
643
644 if (attr->outer_match_level != MLX5_MATCH_NONE)
645 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
646
647 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
648 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
649
650 if (IS_ERR(rule)) {
651 i = esw_attr->split_count;
652 goto err_chain_src_rewrite;
653 }
654
655 atomic64_inc(&esw->offloads.num_flows);
656
657 return rule;
658err_chain_src_rewrite:
659 esw_put_dest_tables_loop(esw, attr, 0, i);
660 mlx5_esw_vporttbl_put(esw, &fwd_attr);
661err_get_fwd:
662 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
663err_get_fast:
664 return rule;
665}
666
667static void
668__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
669 struct mlx5_flow_handle *rule,
670 struct mlx5_flow_attr *attr,
671 bool fwd_rule)
672{
673 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
674 struct mlx5_fs_chains *chains = esw_chains(esw);
675 bool split = (esw_attr->split_count > 0);
676 struct mlx5_vport_tbl_attr fwd_attr;
677 int i;
678
679 mlx5_del_flow_rules(rule);
680
681 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) {
682
683 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
684 if (esw_attr->dests[i].termtbl)
685 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
686 }
687 }
688
689 atomic64_dec(&esw->offloads.num_flows);
690
691 if (fwd_rule || split) {
692 fwd_attr.chain = attr->chain;
693 fwd_attr.prio = attr->prio;
694 fwd_attr.vport = esw_attr->in_rep->vport;
695 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
696 }
697
698 if (fwd_rule) {
699 mlx5_esw_vporttbl_put(esw, &fwd_attr);
700 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
701 esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count);
702 } else {
703 if (split)
704 mlx5_esw_vporttbl_put(esw, &fwd_attr);
705 else if (attr->chain || attr->prio)
706 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
707 esw_cleanup_dests(esw, attr);
708 }
709}
710
711void
712mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
713 struct mlx5_flow_handle *rule,
714 struct mlx5_flow_attr *attr)
715{
716 __mlx5_eswitch_del_rule(esw, rule, attr, false);
717}
718
719void
720mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
721 struct mlx5_flow_handle *rule,
722 struct mlx5_flow_attr *attr)
723{
724 __mlx5_eswitch_del_rule(esw, rule, attr, true);
725}
726
727static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
728{
729 struct mlx5_eswitch_rep *rep;
730 unsigned long i;
731 int err = 0;
732
733 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
734 mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) {
735 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
736 continue;
737
738 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
739 if (err)
740 goto out;
741 }
742
743out:
744 return err;
745}
746
747static struct mlx5_eswitch_rep *
748esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
749{
750 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
751
752 in_rep = attr->in_rep;
753 out_rep = attr->dests[0].rep;
754
755 if (push)
756 vport = in_rep;
757 else if (pop)
758 vport = out_rep;
759 else
760 vport = in_rep;
761
762 return vport;
763}
764
765static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
766 bool push, bool pop, bool fwd)
767{
768 struct mlx5_eswitch_rep *in_rep, *out_rep;
769
770 if ((push || pop) && !fwd)
771 goto out_notsupp;
772
773 in_rep = attr->in_rep;
774 out_rep = attr->dests[0].rep;
775
776 if (push && in_rep->vport == MLX5_VPORT_UPLINK)
777 goto out_notsupp;
778
779 if (pop && out_rep->vport == MLX5_VPORT_UPLINK)
780 goto out_notsupp;
781
782
783 if (!push && !pop && fwd)
784 if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK)
785 goto out_notsupp;
786
787
788
789
790 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0]))
791 goto out_notsupp;
792
793 return 0;
794
795out_notsupp:
796 return -EOPNOTSUPP;
797}
798
799int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
800 struct mlx5_flow_attr *attr)
801{
802 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
803 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
804 struct mlx5_eswitch_rep *vport = NULL;
805 bool push, pop, fwd;
806 int err = 0;
807
808
809 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
810 return 0;
811
812 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
813 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
814 fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) &&
815 !attr->dest_chain);
816
817 mutex_lock(&esw->state_lock);
818
819 err = esw_add_vlan_action_check(esw_attr, push, pop, fwd);
820 if (err)
821 goto unlock;
822
823 attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
824
825 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
826
827 if (!push && !pop && fwd) {
828
829 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) {
830 vport->vlan_refcount++;
831 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
832 }
833
834 goto unlock;
835 }
836
837 if (!push && !pop)
838 goto unlock;
839
840 if (!(offloads->vlan_push_pop_refcount)) {
841
842 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
843 if (err)
844 goto out;
845 }
846 offloads->vlan_push_pop_refcount++;
847
848 if (push) {
849 if (vport->vlan_refcount)
850 goto skip_set_push;
851
852 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0],
853 0, SET_VLAN_INSERT | SET_VLAN_STRIP);
854 if (err)
855 goto out;
856 vport->vlan = esw_attr->vlan_vid[0];
857skip_set_push:
858 vport->vlan_refcount++;
859 }
860out:
861 if (!err)
862 attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED;
863unlock:
864 mutex_unlock(&esw->state_lock);
865 return err;
866}
867
868int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
869 struct mlx5_flow_attr *attr)
870{
871 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
872 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
873 struct mlx5_eswitch_rep *vport = NULL;
874 bool push, pop, fwd;
875 int err = 0;
876
877
878 if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
879 return 0;
880
881 if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED))
882 return 0;
883
884 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
885 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
886 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
887
888 mutex_lock(&esw->state_lock);
889
890 vport = esw_vlan_action_get_vport(esw_attr, push, pop);
891
892 if (!push && !pop && fwd) {
893
894 if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK)
895 vport->vlan_refcount--;
896
897 goto out;
898 }
899
900 if (push) {
901 vport->vlan_refcount--;
902 if (vport->vlan_refcount)
903 goto skip_unset_push;
904
905 vport->vlan = 0;
906 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
907 0, 0, SET_VLAN_STRIP);
908 if (err)
909 goto out;
910 }
911
912skip_unset_push:
913 offloads->vlan_push_pop_refcount--;
914 if (offloads->vlan_push_pop_refcount)
915 goto out;
916
917
918 err = esw_set_global_vlan_pop(esw, 0);
919
920out:
921 mutex_unlock(&esw->state_lock);
922 return err;
923}
924
925struct mlx5_flow_handle *
926mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
927 struct mlx5_eswitch *from_esw,
928 struct mlx5_eswitch_rep *rep,
929 u32 sqn)
930{
931 struct mlx5_flow_act flow_act = {0};
932 struct mlx5_flow_destination dest = {};
933 struct mlx5_flow_handle *flow_rule;
934 struct mlx5_flow_spec *spec;
935 void *misc;
936
937 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
938 if (!spec) {
939 flow_rule = ERR_PTR(-ENOMEM);
940 goto out;
941 }
942
943 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
944 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
945
946 MLX5_SET(fte_match_set_misc, misc, source_port, from_esw->manager_vport);
947 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
948 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
949 MLX5_CAP_GEN(from_esw->dev, vhca_id));
950
951 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
952 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
953 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
954 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
955 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
956 source_eswitch_owner_vhca_id);
957
958 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
959 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
960 dest.vport.num = rep->vport;
961 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
962 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
963 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
964
965 if (rep->vport == MLX5_VPORT_UPLINK)
966 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
967
968 flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb,
969 spec, &flow_act, &dest, 1);
970 if (IS_ERR(flow_rule))
971 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
972 PTR_ERR(flow_rule));
973out:
974 kvfree(spec);
975 return flow_rule;
976}
977EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
978
979void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
980{
981 mlx5_del_flow_rules(rule);
982}
983
984static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
985{
986 struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules;
987 int i = 0, num_vfs = esw->esw_funcs.num_vfs;
988
989 if (!num_vfs || !flows)
990 return;
991
992 for (i = 0; i < num_vfs; i++)
993 mlx5_del_flow_rules(flows[i]);
994
995 kvfree(flows);
996}
997
998static int
999mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw)
1000{
1001 struct mlx5_flow_destination dest = {};
1002 struct mlx5_flow_act flow_act = {0};
1003 int num_vfs, rule_idx = 0, err = 0;
1004 struct mlx5_flow_handle *flow_rule;
1005 struct mlx5_flow_handle **flows;
1006 struct mlx5_flow_spec *spec;
1007 struct mlx5_vport *vport;
1008 unsigned long i;
1009 u16 vport_num;
1010
1011 num_vfs = esw->esw_funcs.num_vfs;
1012 flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL);
1013 if (!flows)
1014 return -ENOMEM;
1015
1016 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1017 if (!spec) {
1018 err = -ENOMEM;
1019 goto alloc_err;
1020 }
1021
1022 MLX5_SET(fte_match_param, spec->match_criteria,
1023 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1024 MLX5_SET(fte_match_param, spec->match_criteria,
1025 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1026 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1027 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1028
1029 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1030 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1031 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1032
1033 mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) {
1034 vport_num = vport->vport;
1035 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1036 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1037 dest.vport.num = vport_num;
1038
1039 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1040 spec, &flow_act, &dest, 1);
1041 if (IS_ERR(flow_rule)) {
1042 err = PTR_ERR(flow_rule);
1043 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n",
1044 rule_idx, PTR_ERR(flow_rule));
1045 goto rule_err;
1046 }
1047 flows[rule_idx++] = flow_rule;
1048 }
1049
1050 esw->fdb_table.offloads.send_to_vport_meta_rules = flows;
1051 kvfree(spec);
1052 return 0;
1053
1054rule_err:
1055 while (--rule_idx >= 0)
1056 mlx5_del_flow_rules(flows[rule_idx]);
1057 kvfree(spec);
1058alloc_err:
1059 kvfree(flows);
1060 return err;
1061}
1062
1063static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1064{
1065 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1066 MLX5_FDB_TO_VPORT_REG_C_1;
1067}
1068
1069static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
1070{
1071 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
1072 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1073 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
1074 u8 curr, wanted;
1075 int err;
1076
1077 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1078 !mlx5_eswitch_vport_match_metadata_enabled(esw))
1079 return 0;
1080
1081 MLX5_SET(query_esw_vport_context_in, in, opcode,
1082 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1083 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
1084 if (err)
1085 return err;
1086
1087 curr = MLX5_GET(query_esw_vport_context_out, out,
1088 esw_vport_context.fdb_to_vport_reg_c_id);
1089 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1090 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1091 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
1092
1093 if (enable)
1094 curr |= wanted;
1095 else
1096 curr &= ~wanted;
1097
1098 MLX5_SET(modify_esw_vport_context_in, min,
1099 esw_vport_context.fdb_to_vport_reg_c_id, curr);
1100 MLX5_SET(modify_esw_vport_context_in, min,
1101 field_select.fdb_to_vport_reg_c_id, 1);
1102
1103 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
1104 if (!err) {
1105 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1106 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1107 else
1108 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1109 }
1110
1111 return err;
1112}
1113
1114static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1115 struct mlx5_core_dev *peer_dev,
1116 struct mlx5_flow_spec *spec,
1117 struct mlx5_flow_destination *dest)
1118{
1119 void *misc;
1120
1121 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1122 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1123 misc_parameters_2);
1124 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1125 mlx5_eswitch_get_vport_metadata_mask());
1126
1127 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1128 } else {
1129 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1130 misc_parameters);
1131
1132 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1133 MLX5_CAP_GEN(peer_dev, vhca_id));
1134
1135 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1136
1137 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1138 misc_parameters);
1139 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1140 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1141 source_eswitch_owner_vhca_id);
1142 }
1143
1144 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1145 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
1146 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
1147 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
1148}
1149
1150static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1151 struct mlx5_eswitch *peer_esw,
1152 struct mlx5_flow_spec *spec,
1153 u16 vport)
1154{
1155 void *misc;
1156
1157 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1158 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1159 misc_parameters_2);
1160 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1161 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1162 vport));
1163 } else {
1164 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1165 misc_parameters);
1166 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1167 }
1168}
1169
1170static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1171 struct mlx5_core_dev *peer_dev)
1172{
1173 struct mlx5_flow_destination dest = {};
1174 struct mlx5_flow_act flow_act = {0};
1175 struct mlx5_flow_handle **flows;
1176
1177 int nvports = esw->total_vports;
1178 struct mlx5_flow_handle *flow;
1179 struct mlx5_flow_spec *spec;
1180 struct mlx5_vport *vport;
1181 unsigned long i;
1182 void *misc;
1183 int err;
1184
1185 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1186 if (!spec)
1187 return -ENOMEM;
1188
1189 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
1190
1191 flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL);
1192 if (!flows) {
1193 err = -ENOMEM;
1194 goto alloc_flows_err;
1195 }
1196
1197 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1198 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1199 misc_parameters);
1200
1201 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1202 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1203 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1204 spec, MLX5_VPORT_PF);
1205
1206 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1207 spec, &flow_act, &dest, 1);
1208 if (IS_ERR(flow)) {
1209 err = PTR_ERR(flow);
1210 goto add_pf_flow_err;
1211 }
1212 flows[vport->index] = flow;
1213 }
1214
1215 if (mlx5_ecpf_vport_exists(esw->dev)) {
1216 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1217 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
1218 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1219 spec, &flow_act, &dest, 1);
1220 if (IS_ERR(flow)) {
1221 err = PTR_ERR(flow);
1222 goto add_ecpf_flow_err;
1223 }
1224 flows[vport->index] = flow;
1225 }
1226
1227 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1228 esw_set_peer_miss_rule_source_port(esw,
1229 peer_dev->priv.eswitch,
1230 spec, vport->vport);
1231
1232 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1233 spec, &flow_act, &dest, 1);
1234 if (IS_ERR(flow)) {
1235 err = PTR_ERR(flow);
1236 goto add_vf_flow_err;
1237 }
1238 flows[vport->index] = flow;
1239 }
1240
1241 esw->fdb_table.offloads.peer_miss_rules = flows;
1242
1243 kvfree(spec);
1244 return 0;
1245
1246add_vf_flow_err:
1247 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1248 if (!flows[vport->index])
1249 continue;
1250 mlx5_del_flow_rules(flows[vport->index]);
1251 }
1252 if (mlx5_ecpf_vport_exists(esw->dev)) {
1253 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1254 mlx5_del_flow_rules(flows[vport->index]);
1255 }
1256add_ecpf_flow_err:
1257 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1258 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1259 mlx5_del_flow_rules(flows[vport->index]);
1260 }
1261add_pf_flow_err:
1262 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
1263 kvfree(flows);
1264alloc_flows_err:
1265 kvfree(spec);
1266 return err;
1267}
1268
1269static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1270{
1271 struct mlx5_flow_handle **flows;
1272 struct mlx5_vport *vport;
1273 unsigned long i;
1274
1275 flows = esw->fdb_table.offloads.peer_miss_rules;
1276
1277 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1278 mlx5_del_flow_rules(flows[vport->index]);
1279
1280 if (mlx5_ecpf_vport_exists(esw->dev)) {
1281 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1282 mlx5_del_flow_rules(flows[vport->index]);
1283 }
1284
1285 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1286 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1287 mlx5_del_flow_rules(flows[vport->index]);
1288 }
1289 kvfree(flows);
1290}
1291
1292static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1293{
1294 struct mlx5_flow_act flow_act = {0};
1295 struct mlx5_flow_destination dest = {};
1296 struct mlx5_flow_handle *flow_rule = NULL;
1297 struct mlx5_flow_spec *spec;
1298 void *headers_c;
1299 void *headers_v;
1300 int err = 0;
1301 u8 *dmac_c;
1302 u8 *dmac_v;
1303
1304 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1305 if (!spec) {
1306 err = -ENOMEM;
1307 goto out;
1308 }
1309
1310 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1311 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1312 outer_headers);
1313 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1314 outer_headers.dmac_47_16);
1315 dmac_c[0] = 0x01;
1316
1317 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1318 dest.vport.num = esw->manager_vport;
1319 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1320
1321 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1322 spec, &flow_act, &dest, 1);
1323 if (IS_ERR(flow_rule)) {
1324 err = PTR_ERR(flow_rule);
1325 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
1326 goto out;
1327 }
1328
1329 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1330
1331 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1332 outer_headers);
1333 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1334 outer_headers.dmac_47_16);
1335 dmac_v[0] = 0x01;
1336 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1337 spec, &flow_act, &dest, 1);
1338 if (IS_ERR(flow_rule)) {
1339 err = PTR_ERR(flow_rule);
1340 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1341 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1342 goto out;
1343 }
1344
1345 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1346
1347out:
1348 kvfree(spec);
1349 return err;
1350}
1351
1352struct mlx5_flow_handle *
1353esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1354{
1355 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1356 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1357 struct mlx5_flow_context *flow_context;
1358 struct mlx5_flow_handle *flow_rule;
1359 struct mlx5_flow_destination dest;
1360 struct mlx5_flow_spec *spec;
1361 void *misc;
1362
1363 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1364 return ERR_PTR(-EOPNOTSUPP);
1365
1366 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1367 if (!spec)
1368 return ERR_PTR(-ENOMEM);
1369
1370 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1371 misc_parameters_2);
1372 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1373 ESW_REG_C0_USER_DATA_METADATA_MASK);
1374 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1375 misc_parameters_2);
1376 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1377 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1378 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1379 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1380 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
1381
1382 flow_context = &spec->flow_context;
1383 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1384 flow_context->flow_tag = tag;
1385 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1386 dest.ft = esw->offloads.ft_offloads;
1387
1388 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
1389 kvfree(spec);
1390
1391 if (IS_ERR(flow_rule))
1392 esw_warn(esw->dev,
1393 "Failed to create restore rule for tag: %d, err(%d)\n",
1394 tag, (int)PTR_ERR(flow_rule));
1395
1396 return flow_rule;
1397}
1398
1399#define MAX_PF_SQ 256
1400#define MAX_SQ_NVPORTS 32
1401
1402static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1403 u32 *flow_group_in)
1404{
1405 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1406 flow_group_in,
1407 match_criteria);
1408
1409 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1410 MLX5_SET(create_flow_group_in, flow_group_in,
1411 match_criteria_enable,
1412 MLX5_MATCH_MISC_PARAMETERS_2);
1413
1414 MLX5_SET(fte_match_param, match_criteria,
1415 misc_parameters_2.metadata_reg_c_0,
1416 mlx5_eswitch_get_vport_metadata_mask());
1417 } else {
1418 MLX5_SET(create_flow_group_in, flow_group_in,
1419 match_criteria_enable,
1420 MLX5_MATCH_MISC_PARAMETERS);
1421
1422 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1423 misc_parameters.source_port);
1424 }
1425}
1426
1427#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
1428static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
1429{
1430 struct mlx5_vport_tbl_attr attr;
1431 struct mlx5_vport *vport;
1432 unsigned long i;
1433
1434 attr.chain = 0;
1435 attr.prio = 1;
1436 mlx5_esw_for_each_vport(esw, i, vport) {
1437 attr.vport = vport->vport;
1438 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1439 mlx5_esw_vporttbl_put(esw, &attr);
1440 }
1441}
1442
1443static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
1444{
1445 struct mlx5_vport_tbl_attr attr;
1446 struct mlx5_flow_table *fdb;
1447 struct mlx5_vport *vport;
1448 unsigned long i;
1449
1450 attr.chain = 0;
1451 attr.prio = 1;
1452 mlx5_esw_for_each_vport(esw, i, vport) {
1453 attr.vport = vport->vport;
1454 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
1455 fdb = mlx5_esw_vporttbl_get(esw, &attr);
1456 if (IS_ERR(fdb))
1457 goto out;
1458 }
1459 return 0;
1460
1461out:
1462 esw_vport_tbl_put(esw);
1463 return PTR_ERR(fdb);
1464}
1465
1466#define fdb_modify_header_fwd_to_table_supported(esw) \
1467 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1468static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1469{
1470 struct mlx5_core_dev *dev = esw->dev;
1471
1472 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1473 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1474
1475 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1476 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1477 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1478 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1479 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1480 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1481 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1482 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1483
1484
1485
1486 esw_warn(dev,
1487 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1488 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1489 } else {
1490 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1491 esw_info(dev, "Supported tc chains and prios offload\n");
1492 }
1493
1494 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1495 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1496}
1497
1498static int
1499esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1500{
1501 struct mlx5_core_dev *dev = esw->dev;
1502 struct mlx5_flow_table *nf_ft, *ft;
1503 struct mlx5_chains_attr attr = {};
1504 struct mlx5_fs_chains *chains;
1505 u32 fdb_max;
1506 int err;
1507
1508 fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size);
1509
1510 esw_init_chains_offload_flags(esw, &attr.flags);
1511 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
1512 attr.max_ft_sz = fdb_max;
1513 attr.max_grp_num = esw->params.large_group_num;
1514 attr.default_ft = miss_fdb;
1515 attr.mapping = esw->offloads.reg_c0_obj_pool;
1516
1517 chains = mlx5_chains_create(dev, &attr);
1518 if (IS_ERR(chains)) {
1519 err = PTR_ERR(chains);
1520 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1521 return err;
1522 }
1523
1524 esw->fdb_table.offloads.esw_chains_priv = chains;
1525
1526
1527 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1528 1, 0);
1529 if (IS_ERR(nf_ft)) {
1530 err = PTR_ERR(nf_ft);
1531 goto nf_ft_err;
1532 }
1533
1534
1535 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1536 if (IS_ERR(ft)) {
1537 err = PTR_ERR(ft);
1538 goto level_0_err;
1539 }
1540
1541
1542 if (!mlx5_chains_prios_supported(chains)) {
1543 err = esw_vport_tbl_get(esw);
1544 if (err)
1545 goto level_1_err;
1546 }
1547
1548 mlx5_chains_set_end_ft(chains, nf_ft);
1549
1550 return 0;
1551
1552level_1_err:
1553 mlx5_chains_put_table(chains, 0, 1, 0);
1554level_0_err:
1555 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1556nf_ft_err:
1557 mlx5_chains_destroy(chains);
1558 esw->fdb_table.offloads.esw_chains_priv = NULL;
1559
1560 return err;
1561}
1562
1563static void
1564esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1565{
1566 if (!mlx5_chains_prios_supported(chains))
1567 esw_vport_tbl_put(esw);
1568 mlx5_chains_put_table(chains, 0, 1, 0);
1569 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1570 mlx5_chains_destroy(chains);
1571}
1572
1573#else
1574
1575static int
1576esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1577{ return 0; }
1578
1579static void
1580esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1581{}
1582
1583#endif
1584
1585static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1586{
1587 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1588 struct mlx5_flow_table_attr ft_attr = {};
1589 int num_vfs, table_size, ix, err = 0;
1590 struct mlx5_core_dev *dev = esw->dev;
1591 struct mlx5_flow_namespace *root_ns;
1592 struct mlx5_flow_table *fdb = NULL;
1593 u32 flags = 0, *flow_group_in;
1594 struct mlx5_flow_group *g;
1595 void *match_criteria;
1596 u8 *dmac;
1597
1598 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1599
1600 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1601 if (!flow_group_in)
1602 return -ENOMEM;
1603
1604 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1605 if (!root_ns) {
1606 esw_warn(dev, "Failed to get FDB flow namespace\n");
1607 err = -EOPNOTSUPP;
1608 goto ns_err;
1609 }
1610 esw->fdb_table.offloads.ns = root_ns;
1611 err = mlx5_flow_namespace_set_mode(root_ns,
1612 esw->dev->priv.steering->mode);
1613 if (err) {
1614 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1615 goto ns_err;
1616 }
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
1630 MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs;
1631
1632
1633
1634
1635 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1636 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1637 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1638
1639 ft_attr.flags = flags;
1640 ft_attr.max_fte = table_size;
1641 ft_attr.prio = FDB_SLOW_PATH;
1642
1643 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1644 if (IS_ERR(fdb)) {
1645 err = PTR_ERR(fdb);
1646 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1647 goto slow_fdb_err;
1648 }
1649 esw->fdb_table.offloads.slow_fdb = fdb;
1650
1651
1652
1653
1654
1655
1656 memset(&ft_attr, 0, sizeof(ft_attr));
1657 ft_attr.prio = FDB_TC_MISS;
1658 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1659 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1660 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1661 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1662 goto tc_miss_table_err;
1663 }
1664
1665 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
1666 if (err) {
1667 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
1668 goto fdb_chains_err;
1669 }
1670
1671
1672 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1673 MLX5_MATCH_MISC_PARAMETERS);
1674
1675 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1676
1677 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
1678 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
1679 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1680 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1681 misc_parameters.source_eswitch_owner_vhca_id);
1682 MLX5_SET(create_flow_group_in, flow_group_in,
1683 source_eswitch_owner_vhca_id_valid, 1);
1684 }
1685
1686
1687 ix = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1688 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1689 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
1690
1691 g = mlx5_create_flow_group(fdb, flow_group_in);
1692 if (IS_ERR(g)) {
1693 err = PTR_ERR(g);
1694 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1695 goto send_vport_err;
1696 }
1697 esw->fdb_table.offloads.send_to_vport_grp = g;
1698
1699 if (esw_src_port_rewrite_supported(esw)) {
1700
1701 memset(flow_group_in, 0, inlen);
1702 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1703 MLX5_MATCH_MISC_PARAMETERS_2);
1704
1705 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1706
1707 MLX5_SET(fte_match_param, match_criteria,
1708 misc_parameters_2.metadata_reg_c_0,
1709 mlx5_eswitch_get_vport_metadata_mask());
1710 MLX5_SET(fte_match_param, match_criteria,
1711 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1712
1713 num_vfs = esw->esw_funcs.num_vfs;
1714 if (num_vfs) {
1715 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1716 MLX5_SET(create_flow_group_in, flow_group_in,
1717 end_flow_index, ix + num_vfs - 1);
1718 ix += num_vfs;
1719
1720 g = mlx5_create_flow_group(fdb, flow_group_in);
1721 if (IS_ERR(g)) {
1722 err = PTR_ERR(g);
1723 esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n",
1724 err);
1725 goto send_vport_meta_err;
1726 }
1727 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
1728
1729 err = mlx5_eswitch_add_send_to_vport_meta_rules(esw);
1730 if (err)
1731 goto meta_rule_err;
1732 }
1733 }
1734
1735 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
1736
1737 memset(flow_group_in, 0, inlen);
1738
1739 esw_set_flow_group_source_port(esw, flow_group_in);
1740
1741 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1742 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1743 flow_group_in,
1744 match_criteria);
1745
1746 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1747 misc_parameters.source_eswitch_owner_vhca_id);
1748
1749 MLX5_SET(create_flow_group_in, flow_group_in,
1750 source_eswitch_owner_vhca_id_valid, 1);
1751 }
1752
1753 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1754 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1755 ix + esw->total_vports - 1);
1756 ix += esw->total_vports;
1757
1758 g = mlx5_create_flow_group(fdb, flow_group_in);
1759 if (IS_ERR(g)) {
1760 err = PTR_ERR(g);
1761 esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err);
1762 goto peer_miss_err;
1763 }
1764 esw->fdb_table.offloads.peer_miss_grp = g;
1765 }
1766
1767
1768 memset(flow_group_in, 0, inlen);
1769 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1770 MLX5_MATCH_OUTER_HEADERS);
1771 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1772 match_criteria);
1773 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1774 outer_headers.dmac_47_16);
1775 dmac[0] = 0x01;
1776
1777 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
1778 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1779 ix + MLX5_ESW_MISS_FLOWS);
1780
1781 g = mlx5_create_flow_group(fdb, flow_group_in);
1782 if (IS_ERR(g)) {
1783 err = PTR_ERR(g);
1784 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
1785 goto miss_err;
1786 }
1787 esw->fdb_table.offloads.miss_grp = g;
1788
1789 err = esw_add_fdb_miss_rule(esw);
1790 if (err)
1791 goto miss_rule_err;
1792
1793 kvfree(flow_group_in);
1794 return 0;
1795
1796miss_rule_err:
1797 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1798miss_err:
1799 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1800 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1801peer_miss_err:
1802 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1803meta_rule_err:
1804 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1805 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1806send_vport_meta_err:
1807 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1808send_vport_err:
1809 esw_chains_destroy(esw, esw_chains(esw));
1810fdb_chains_err:
1811 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1812tc_miss_table_err:
1813 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1814slow_fdb_err:
1815
1816 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
1817ns_err:
1818 kvfree(flow_group_in);
1819 return err;
1820}
1821
1822static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
1823{
1824 if (!esw->fdb_table.offloads.slow_fdb)
1825 return;
1826
1827 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
1828 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1829 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1830 mlx5_eswitch_del_send_to_vport_meta_rules(esw);
1831 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1832 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1833 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1834 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1835 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
1836 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1837
1838 esw_chains_destroy(esw, esw_chains(esw));
1839
1840 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1841 mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb);
1842
1843 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1844 MLX5_FLOW_STEERING_MODE_DMFS);
1845 atomic64_set(&esw->user_count, 0);
1846}
1847
1848static int esw_create_offloads_table(struct mlx5_eswitch *esw)
1849{
1850 struct mlx5_flow_table_attr ft_attr = {};
1851 struct mlx5_core_dev *dev = esw->dev;
1852 struct mlx5_flow_table *ft_offloads;
1853 struct mlx5_flow_namespace *ns;
1854 int err = 0;
1855
1856 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1857 if (!ns) {
1858 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
1859 return -EOPNOTSUPP;
1860 }
1861
1862 ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1863 ft_attr.prio = 1;
1864
1865 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
1866 if (IS_ERR(ft_offloads)) {
1867 err = PTR_ERR(ft_offloads);
1868 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1869 return err;
1870 }
1871
1872 esw->offloads.ft_offloads = ft_offloads;
1873 return 0;
1874}
1875
1876static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1877{
1878 struct mlx5_esw_offload *offloads = &esw->offloads;
1879
1880 mlx5_destroy_flow_table(offloads->ft_offloads);
1881}
1882
1883static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
1884{
1885 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1886 struct mlx5_flow_group *g;
1887 u32 *flow_group_in;
1888 int nvports;
1889 int err = 0;
1890
1891 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1892 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1893 if (!flow_group_in)
1894 return -ENOMEM;
1895
1896
1897 esw_set_flow_group_source_port(esw, flow_group_in);
1898
1899 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1900 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1901
1902 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1903
1904 if (IS_ERR(g)) {
1905 err = PTR_ERR(g);
1906 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1907 goto out;
1908 }
1909
1910 esw->offloads.vport_rx_group = g;
1911out:
1912 kvfree(flow_group_in);
1913 return err;
1914}
1915
1916static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1917{
1918 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1919}
1920
1921struct mlx5_flow_handle *
1922mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1923 struct mlx5_flow_destination *dest)
1924{
1925 struct mlx5_flow_act flow_act = {0};
1926 struct mlx5_flow_handle *flow_rule;
1927 struct mlx5_flow_spec *spec;
1928 void *misc;
1929
1930 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1931 if (!spec) {
1932 flow_rule = ERR_PTR(-ENOMEM);
1933 goto out;
1934 }
1935
1936 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1937 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1938 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1939 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
1940
1941 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
1942 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1943 mlx5_eswitch_get_vport_metadata_mask());
1944
1945 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1946 } else {
1947 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1948 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1949
1950 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1951 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1952
1953 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1954 }
1955
1956 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1957 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
1958 &flow_act, dest, 1);
1959 if (IS_ERR(flow_rule)) {
1960 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1961 goto out;
1962 }
1963
1964out:
1965 kvfree(spec);
1966 return flow_rule;
1967}
1968
1969static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
1970{
1971 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
1972 struct mlx5_core_dev *dev = esw->dev;
1973 struct mlx5_vport *vport;
1974 unsigned long i;
1975
1976 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1977 return -EOPNOTSUPP;
1978
1979 if (esw->mode == MLX5_ESWITCH_NONE)
1980 return -EOPNOTSUPP;
1981
1982 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1983 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1984 mlx5_mode = MLX5_INLINE_MODE_NONE;
1985 goto out;
1986 case MLX5_CAP_INLINE_MODE_L2:
1987 mlx5_mode = MLX5_INLINE_MODE_L2;
1988 goto out;
1989 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1990 goto query_vports;
1991 }
1992
1993query_vports:
1994 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
1995 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
1996 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
1997 if (prev_mlx5_mode != mlx5_mode)
1998 return -EINVAL;
1999 prev_mlx5_mode = mlx5_mode;
2000 }
2001
2002out:
2003 *mode = mlx5_mode;
2004 return 0;
2005}
2006
2007static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2008{
2009 struct mlx5_esw_offload *offloads = &esw->offloads;
2010
2011 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2012 return;
2013
2014 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
2015 mlx5_destroy_flow_group(offloads->restore_group);
2016 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2017}
2018
2019static int esw_create_restore_table(struct mlx5_eswitch *esw)
2020{
2021 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
2022 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2023 struct mlx5_flow_table_attr ft_attr = {};
2024 struct mlx5_core_dev *dev = esw->dev;
2025 struct mlx5_flow_namespace *ns;
2026 struct mlx5_modify_hdr *mod_hdr;
2027 void *match_criteria, *misc;
2028 struct mlx5_flow_table *ft;
2029 struct mlx5_flow_group *g;
2030 u32 *flow_group_in;
2031 int err = 0;
2032
2033 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2034 return 0;
2035
2036 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2037 if (!ns) {
2038 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2039 return -EOPNOTSUPP;
2040 }
2041
2042 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2043 if (!flow_group_in) {
2044 err = -ENOMEM;
2045 goto out_free;
2046 }
2047
2048 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
2049 ft = mlx5_create_flow_table(ns, &ft_attr);
2050 if (IS_ERR(ft)) {
2051 err = PTR_ERR(ft);
2052 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2053 err);
2054 goto out_free;
2055 }
2056
2057 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2058 match_criteria);
2059 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2060 misc_parameters_2);
2061
2062 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2063 ESW_REG_C0_USER_DATA_METADATA_MASK);
2064 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2065 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2066 ft_attr.max_fte - 1);
2067 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2068 MLX5_MATCH_MISC_PARAMETERS_2);
2069 g = mlx5_create_flow_group(ft, flow_group_in);
2070 if (IS_ERR(g)) {
2071 err = PTR_ERR(g);
2072 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2073 err);
2074 goto err_group;
2075 }
2076
2077 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2078 MLX5_SET(copy_action_in, modact, src_field,
2079 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2080 MLX5_SET(copy_action_in, modact, dst_field,
2081 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2082 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2083 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2084 modact);
2085 if (IS_ERR(mod_hdr)) {
2086 err = PTR_ERR(mod_hdr);
2087 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2088 err);
2089 goto err_mod_hdr;
2090 }
2091
2092 esw->offloads.ft_offloads_restore = ft;
2093 esw->offloads.restore_group = g;
2094 esw->offloads.restore_copy_hdr_id = mod_hdr;
2095
2096 kvfree(flow_group_in);
2097
2098 return 0;
2099
2100err_mod_hdr:
2101 mlx5_destroy_flow_group(g);
2102err_group:
2103 mlx5_destroy_flow_table(ft);
2104out_free:
2105 kvfree(flow_group_in);
2106
2107 return err;
2108}
2109
2110static int esw_offloads_start(struct mlx5_eswitch *esw,
2111 struct netlink_ext_ack *extack)
2112{
2113 int err, err1;
2114
2115 mlx5_eswitch_disable_locked(esw, false);
2116 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
2117 esw->dev->priv.sriov.num_vfs);
2118 if (err) {
2119 NL_SET_ERR_MSG_MOD(extack,
2120 "Failed setting eswitch to offloads");
2121 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
2122 MLX5_ESWITCH_IGNORE_NUM_VFS);
2123 if (err1) {
2124 NL_SET_ERR_MSG_MOD(extack,
2125 "Failed setting eswitch back to legacy");
2126 }
2127 }
2128 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2129 if (mlx5_eswitch_inline_mode_get(esw,
2130 &esw->offloads.inline_mode)) {
2131 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
2132 NL_SET_ERR_MSG_MOD(extack,
2133 "Inline mode is different between vports");
2134 }
2135 }
2136 return err;
2137}
2138
2139static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2140 struct mlx5_eswitch_rep *rep,
2141 xa_mark_t mark)
2142{
2143 bool mark_set;
2144
2145
2146 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2147 if (mark_set)
2148 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
2149}
2150
2151static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
2152{
2153 struct mlx5_eswitch_rep *rep;
2154 int rep_type;
2155 int err;
2156
2157 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2158 if (!rep)
2159 return -ENOMEM;
2160
2161 rep->vport = vport->vport;
2162 rep->vport_index = vport->index;
2163 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2164 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
2165
2166 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2167 if (err)
2168 goto insert_err;
2169
2170 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2171 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2172 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2173 return 0;
2174
2175insert_err:
2176 kfree(rep);
2177 return err;
2178}
2179
2180static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2181 struct mlx5_eswitch_rep *rep)
2182{
2183 xa_erase(&esw->offloads.vport_reps, rep->vport);
2184 kfree(rep);
2185}
2186
2187void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
2188{
2189 struct mlx5_eswitch_rep *rep;
2190 unsigned long i;
2191
2192 mlx5_esw_for_each_rep(esw, i, rep)
2193 mlx5_esw_offloads_rep_cleanup(esw, rep);
2194 xa_destroy(&esw->offloads.vport_reps);
2195}
2196
2197int esw_offloads_init_reps(struct mlx5_eswitch *esw)
2198{
2199 struct mlx5_vport *vport;
2200 unsigned long i;
2201 int err;
2202
2203 xa_init(&esw->offloads.vport_reps);
2204
2205 mlx5_esw_for_each_vport(esw, i, vport) {
2206 err = mlx5_esw_offloads_rep_init(esw, vport);
2207 if (err)
2208 goto err;
2209 }
2210 return 0;
2211
2212err:
2213 esw_offloads_cleanup_reps(esw);
2214 return err;
2215}
2216
2217static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2218 struct mlx5_eswitch_rep *rep, u8 rep_type)
2219{
2220 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2221 REP_LOADED, REP_REGISTERED) == REP_LOADED)
2222 esw->offloads.rep_ops[rep_type]->unload(rep);
2223}
2224
2225static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2226{
2227 struct mlx5_eswitch_rep *rep;
2228 unsigned long i;
2229
2230 mlx5_esw_for_each_sf_rep(esw, i, rep)
2231 __esw_offloads_unload_rep(esw, rep, rep_type);
2232}
2233
2234static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
2235{
2236 struct mlx5_eswitch_rep *rep;
2237 unsigned long i;
2238
2239 __unload_reps_sf_vport(esw, rep_type);
2240
2241 mlx5_esw_for_each_vf_rep(esw, i, rep)
2242 __esw_offloads_unload_rep(esw, rep, rep_type);
2243
2244 if (mlx5_ecpf_vport_exists(esw->dev)) {
2245 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2246 __esw_offloads_unload_rep(esw, rep, rep_type);
2247 }
2248
2249 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2250 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2251 __esw_offloads_unload_rep(esw, rep, rep_type);
2252 }
2253
2254 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2255 __esw_offloads_unload_rep(esw, rep, rep_type);
2256}
2257
2258int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
2259{
2260 struct mlx5_eswitch_rep *rep;
2261 int rep_type;
2262 int err;
2263
2264 rep = mlx5_eswitch_get_rep(esw, vport_num);
2265 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2266 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2267 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2268 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2269 if (err)
2270 goto err_reps;
2271 }
2272
2273 return 0;
2274
2275err_reps:
2276 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2277 for (--rep_type; rep_type >= 0; rep_type--)
2278 __esw_offloads_unload_rep(esw, rep, rep_type);
2279 return err;
2280}
2281
2282void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
2283{
2284 struct mlx5_eswitch_rep *rep;
2285 int rep_type;
2286
2287 rep = mlx5_eswitch_get_rep(esw, vport_num);
2288 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2289 __esw_offloads_unload_rep(esw, rep, rep_type);
2290}
2291
2292int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2293{
2294 int err;
2295
2296 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2297 return 0;
2298
2299 if (vport_num != MLX5_VPORT_UPLINK) {
2300 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2301 if (err)
2302 return err;
2303 }
2304
2305 err = mlx5_esw_offloads_rep_load(esw, vport_num);
2306 if (err)
2307 goto load_err;
2308 return err;
2309
2310load_err:
2311 if (vport_num != MLX5_VPORT_UPLINK)
2312 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
2313 return err;
2314}
2315
2316void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2317{
2318 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2319 return;
2320
2321 mlx5_esw_offloads_rep_unload(esw, vport_num);
2322
2323 if (vport_num != MLX5_VPORT_UPLINK)
2324 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
2325}
2326
2327static int esw_set_uplink_slave_ingress_root(struct mlx5_core_dev *master,
2328 struct mlx5_core_dev *slave)
2329{
2330 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2331 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2332 struct mlx5_eswitch *esw;
2333 struct mlx5_flow_root_namespace *root;
2334 struct mlx5_flow_namespace *ns;
2335 struct mlx5_vport *vport;
2336 int err;
2337
2338 MLX5_SET(set_flow_table_root_in, in, opcode,
2339 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2340 MLX5_SET(set_flow_table_root_in, in, table_type, FS_FT_ESW_INGRESS_ACL);
2341 MLX5_SET(set_flow_table_root_in, in, other_vport, 1);
2342 MLX5_SET(set_flow_table_root_in, in, vport_number, MLX5_VPORT_UPLINK);
2343
2344 if (master) {
2345 esw = master->priv.eswitch;
2346 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2347 MLX5_SET(set_flow_table_root_in, in, table_of_other_vport, 1);
2348 MLX5_SET(set_flow_table_root_in, in, table_vport_number,
2349 MLX5_VPORT_UPLINK);
2350
2351 ns = mlx5_get_flow_vport_acl_namespace(master,
2352 MLX5_FLOW_NAMESPACE_ESW_INGRESS,
2353 vport->index);
2354 root = find_root(&ns->node);
2355 mutex_lock(&root->chain_lock);
2356
2357 MLX5_SET(set_flow_table_root_in, in,
2358 table_eswitch_owner_vhca_id_valid, 1);
2359 MLX5_SET(set_flow_table_root_in, in,
2360 table_eswitch_owner_vhca_id,
2361 MLX5_CAP_GEN(master, vhca_id));
2362 MLX5_SET(set_flow_table_root_in, in, table_id,
2363 root->root_ft->id);
2364 } else {
2365 esw = slave->priv.eswitch;
2366 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2367 ns = mlx5_get_flow_vport_acl_namespace(slave,
2368 MLX5_FLOW_NAMESPACE_ESW_INGRESS,
2369 vport->index);
2370 root = find_root(&ns->node);
2371 mutex_lock(&root->chain_lock);
2372 MLX5_SET(set_flow_table_root_in, in, table_id, root->root_ft->id);
2373 }
2374
2375 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2376 mutex_unlock(&root->chain_lock);
2377
2378 return err;
2379}
2380
2381static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2382 struct mlx5_core_dev *slave)
2383{
2384 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2385 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2386 struct mlx5_flow_root_namespace *root;
2387 struct mlx5_flow_namespace *ns;
2388 int err;
2389
2390 MLX5_SET(set_flow_table_root_in, in, opcode,
2391 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2392 MLX5_SET(set_flow_table_root_in, in, table_type,
2393 FS_FT_FDB);
2394
2395 if (master) {
2396 ns = mlx5_get_flow_namespace(master,
2397 MLX5_FLOW_NAMESPACE_FDB);
2398 root = find_root(&ns->node);
2399 mutex_lock(&root->chain_lock);
2400 MLX5_SET(set_flow_table_root_in, in,
2401 table_eswitch_owner_vhca_id_valid, 1);
2402 MLX5_SET(set_flow_table_root_in, in,
2403 table_eswitch_owner_vhca_id,
2404 MLX5_CAP_GEN(master, vhca_id));
2405 MLX5_SET(set_flow_table_root_in, in, table_id,
2406 root->root_ft->id);
2407 } else {
2408 ns = mlx5_get_flow_namespace(slave,
2409 MLX5_FLOW_NAMESPACE_FDB);
2410 root = find_root(&ns->node);
2411 mutex_lock(&root->chain_lock);
2412 MLX5_SET(set_flow_table_root_in, in, table_id,
2413 root->root_ft->id);
2414 }
2415
2416 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2417 mutex_unlock(&root->chain_lock);
2418
2419 return err;
2420}
2421
2422static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2423 struct mlx5_core_dev *slave,
2424 struct mlx5_vport *vport,
2425 struct mlx5_flow_table *acl)
2426{
2427 struct mlx5_flow_handle *flow_rule = NULL;
2428 struct mlx5_flow_destination dest = {};
2429 struct mlx5_flow_act flow_act = {};
2430 struct mlx5_flow_spec *spec;
2431 int err = 0;
2432 void *misc;
2433
2434 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2435 if (!spec)
2436 return -ENOMEM;
2437
2438 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2439 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2440 misc_parameters);
2441 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2442 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
2443 MLX5_CAP_GEN(slave, vhca_id));
2444
2445 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2446 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2447 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2448 source_eswitch_owner_vhca_id);
2449
2450 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2451 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2452 dest.vport.num = slave->priv.eswitch->manager_vport;
2453 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2454 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2455
2456 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2457 &dest, 1);
2458 if (IS_ERR(flow_rule))
2459 err = PTR_ERR(flow_rule);
2460 else
2461 vport->egress.offloads.bounce_rule = flow_rule;
2462
2463 kvfree(spec);
2464 return err;
2465}
2466
2467static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2468 struct mlx5_core_dev *slave)
2469{
2470 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2471 struct mlx5_eswitch *esw = master->priv.eswitch;
2472 struct mlx5_flow_table_attr ft_attr = {
2473 .max_fte = 1, .prio = 0, .level = 0,
2474 };
2475 struct mlx5_flow_namespace *egress_ns;
2476 struct mlx5_flow_table *acl;
2477 struct mlx5_flow_group *g;
2478 struct mlx5_vport *vport;
2479 void *match_criteria;
2480 u32 *flow_group_in;
2481 int err;
2482
2483 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2484 if (IS_ERR(vport))
2485 return PTR_ERR(vport);
2486
2487 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2488 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2489 vport->index);
2490 if (!egress_ns)
2491 return -EINVAL;
2492
2493 if (vport->egress.acl)
2494 return -EINVAL;
2495
2496 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2497 if (!flow_group_in)
2498 return -ENOMEM;
2499
2500 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2501 if (IS_ERR(acl)) {
2502 err = PTR_ERR(acl);
2503 goto out;
2504 }
2505
2506 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2507 match_criteria);
2508 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2509 misc_parameters.source_port);
2510 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2511 misc_parameters.source_eswitch_owner_vhca_id);
2512 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2513 MLX5_MATCH_MISC_PARAMETERS);
2514
2515 MLX5_SET(create_flow_group_in, flow_group_in,
2516 source_eswitch_owner_vhca_id_valid, 1);
2517 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2518 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
2519
2520 g = mlx5_create_flow_group(acl, flow_group_in);
2521 if (IS_ERR(g)) {
2522 err = PTR_ERR(g);
2523 goto err_group;
2524 }
2525
2526 err = __esw_set_master_egress_rule(master, slave, vport, acl);
2527 if (err)
2528 goto err_rule;
2529
2530 vport->egress.acl = acl;
2531 vport->egress.offloads.bounce_grp = g;
2532
2533 kvfree(flow_group_in);
2534
2535 return 0;
2536
2537err_rule:
2538 mlx5_destroy_flow_group(g);
2539err_group:
2540 mlx5_destroy_flow_table(acl);
2541out:
2542 kvfree(flow_group_in);
2543 return err;
2544}
2545
2546static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev)
2547{
2548 struct mlx5_vport *vport;
2549
2550 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2551 dev->priv.eswitch->manager_vport);
2552
2553 esw_acl_egress_ofld_cleanup(vport);
2554}
2555
2556int mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw,
2557 struct mlx5_eswitch *slave_esw)
2558{
2559 int err;
2560
2561 err = esw_set_uplink_slave_ingress_root(master_esw->dev,
2562 slave_esw->dev);
2563 if (err)
2564 return -EINVAL;
2565
2566 err = esw_set_slave_root_fdb(master_esw->dev,
2567 slave_esw->dev);
2568 if (err)
2569 goto err_fdb;
2570
2571 err = esw_set_master_egress_rule(master_esw->dev,
2572 slave_esw->dev);
2573 if (err)
2574 goto err_acl;
2575
2576 return err;
2577
2578err_acl:
2579 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2580
2581err_fdb:
2582 esw_set_uplink_slave_ingress_root(NULL, slave_esw->dev);
2583
2584 return err;
2585}
2586
2587void mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw,
2588 struct mlx5_eswitch *slave_esw)
2589{
2590 esw_unset_master_egress_rule(master_esw->dev);
2591 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2592 esw_set_uplink_slave_ingress_root(NULL, slave_esw->dev);
2593}
2594
2595#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2596#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2597
2598static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw)
2599{
2600 const struct mlx5_eswitch_rep_ops *ops;
2601 struct mlx5_eswitch_rep *rep;
2602 unsigned long i;
2603 u8 rep_type;
2604
2605 mlx5_esw_for_each_rep(esw, i, rep) {
2606 rep_type = NUM_REP_TYPES;
2607 while (rep_type--) {
2608 ops = esw->offloads.rep_ops[rep_type];
2609 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2610 ops->event)
2611 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, NULL);
2612 }
2613 }
2614}
2615
2616static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw)
2617{
2618#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
2619 mlx5e_tc_clean_fdb_peer_flows(esw);
2620#endif
2621 mlx5_esw_offloads_rep_event_unpair(esw);
2622 esw_del_fdb_peer_miss_rules(esw);
2623}
2624
2625static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2626 struct mlx5_eswitch *peer_esw)
2627{
2628 const struct mlx5_eswitch_rep_ops *ops;
2629 struct mlx5_eswitch_rep *rep;
2630 unsigned long i;
2631 u8 rep_type;
2632 int err;
2633
2634 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2635 if (err)
2636 return err;
2637
2638 mlx5_esw_for_each_rep(esw, i, rep) {
2639 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2640 ops = esw->offloads.rep_ops[rep_type];
2641 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2642 ops->event) {
2643 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2644 if (err)
2645 goto err_out;
2646 }
2647 }
2648 }
2649
2650 return 0;
2651
2652err_out:
2653 mlx5_esw_offloads_unpair(esw);
2654 return err;
2655}
2656
2657static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2658 struct mlx5_eswitch *peer_esw,
2659 bool pair)
2660{
2661 struct mlx5_flow_root_namespace *peer_ns;
2662 struct mlx5_flow_root_namespace *ns;
2663 int err;
2664
2665 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2666 ns = esw->dev->priv.steering->fdb_root_ns;
2667
2668 if (pair) {
2669 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2670 if (err)
2671 return err;
2672
2673 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
2674 if (err) {
2675 mlx5_flow_namespace_set_peer(ns, NULL);
2676 return err;
2677 }
2678 } else {
2679 mlx5_flow_namespace_set_peer(ns, NULL);
2680 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2681 }
2682
2683 return 0;
2684}
2685
2686static int mlx5_esw_offloads_devcom_event(int event,
2687 void *my_data,
2688 void *event_data)
2689{
2690 struct mlx5_eswitch *esw = my_data;
2691 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2692 struct mlx5_eswitch *peer_esw = event_data;
2693 int err;
2694
2695 switch (event) {
2696 case ESW_OFFLOADS_DEVCOM_PAIR:
2697 if (mlx5_get_next_phys_dev(esw->dev) != peer_esw->dev)
2698 break;
2699
2700 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2701 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2702 break;
2703
2704 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
2705 if (err)
2706 goto err_out;
2707 err = mlx5_esw_offloads_pair(esw, peer_esw);
2708 if (err)
2709 goto err_peer;
2710
2711 err = mlx5_esw_offloads_pair(peer_esw, esw);
2712 if (err)
2713 goto err_pair;
2714
2715 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2716 break;
2717
2718 case ESW_OFFLOADS_DEVCOM_UNPAIR:
2719 if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS))
2720 break;
2721
2722 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
2723 mlx5_esw_offloads_unpair(peer_esw);
2724 mlx5_esw_offloads_unpair(esw);
2725 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
2726 break;
2727 }
2728
2729 return 0;
2730
2731err_pair:
2732 mlx5_esw_offloads_unpair(esw);
2733err_peer:
2734 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
2735err_out:
2736 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2737 event, err);
2738 return err;
2739}
2740
2741static void esw_offloads_devcom_init(struct mlx5_eswitch *esw)
2742{
2743 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2744
2745 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2746 mutex_init(&esw->offloads.peer_mutex);
2747
2748 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2749 return;
2750
2751 mlx5_devcom_register_component(devcom,
2752 MLX5_DEVCOM_ESW_OFFLOADS,
2753 mlx5_esw_offloads_devcom_event,
2754 esw);
2755
2756 mlx5_devcom_send_event(devcom,
2757 MLX5_DEVCOM_ESW_OFFLOADS,
2758 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2759}
2760
2761static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
2762{
2763 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2764
2765 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2766 return;
2767
2768 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2769 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2770
2771 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2772}
2773
2774bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
2775{
2776 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2777 return false;
2778
2779 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2780 MLX5_FDB_TO_VPORT_REG_C_0))
2781 return false;
2782
2783 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source))
2784 return false;
2785
2786 if (mlx5_core_is_ecpf_esw_manager(esw->dev) ||
2787 mlx5_ecpf_vport_exists(esw->dev))
2788 return false;
2789
2790 return true;
2791}
2792
2793u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2794{
2795 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
2796 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1;
2797 u32 pf_num;
2798 int id;
2799
2800
2801 pf_num = PCI_FUNC(esw->dev->pdev->devfn);
2802 if (pf_num > max_pf_num)
2803 return 0;
2804
2805
2806
2807 id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL);
2808 if (id < 0)
2809 return 0;
2810 id = (pf_num << ESW_VPORT_BITS) | id;
2811 return id;
2812}
2813
2814void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2815{
2816 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2817
2818
2819 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
2820}
2821
2822static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2823 struct mlx5_vport *vport)
2824{
2825 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2826 vport->metadata = vport->default_metadata;
2827 return vport->metadata ? 0 : -ENOSPC;
2828}
2829
2830static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2831 struct mlx5_vport *vport)
2832{
2833 if (!vport->default_metadata)
2834 return;
2835
2836 WARN_ON(vport->metadata != vport->default_metadata);
2837 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2838}
2839
2840static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2841{
2842 struct mlx5_vport *vport;
2843 unsigned long i;
2844
2845 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2846 return;
2847
2848 mlx5_esw_for_each_vport(esw, i, vport)
2849 esw_offloads_vport_metadata_cleanup(esw, vport);
2850}
2851
2852static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2853{
2854 struct mlx5_vport *vport;
2855 unsigned long i;
2856 int err;
2857
2858 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2859 return 0;
2860
2861 mlx5_esw_for_each_vport(esw, i, vport) {
2862 err = esw_offloads_vport_metadata_setup(esw, vport);
2863 if (err)
2864 goto metadata_err;
2865 }
2866
2867 return 0;
2868
2869metadata_err:
2870 esw_offloads_metadata_uninit(esw);
2871 return err;
2872}
2873
2874int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable)
2875{
2876 int err = 0;
2877
2878 down_write(&esw->mode_lock);
2879 if (esw->mode != MLX5_ESWITCH_NONE) {
2880 err = -EBUSY;
2881 goto done;
2882 }
2883 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2884 err = -EOPNOTSUPP;
2885 goto done;
2886 }
2887 if (enable)
2888 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2889 else
2890 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2891done:
2892 up_write(&esw->mode_lock);
2893 return err;
2894}
2895
2896int
2897esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2898 struct mlx5_vport *vport)
2899{
2900 int err;
2901
2902 err = esw_acl_ingress_ofld_setup(esw, vport);
2903 if (err)
2904 return err;
2905
2906 err = esw_acl_egress_ofld_setup(esw, vport);
2907 if (err)
2908 goto egress_err;
2909
2910 return 0;
2911
2912egress_err:
2913 esw_acl_ingress_ofld_cleanup(esw, vport);
2914 return err;
2915}
2916
2917void
2918esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
2919 struct mlx5_vport *vport)
2920{
2921 esw_acl_egress_ofld_cleanup(vport);
2922 esw_acl_ingress_ofld_cleanup(esw, vport);
2923}
2924
2925static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
2926{
2927 struct mlx5_vport *vport;
2928
2929 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2930 if (IS_ERR(vport))
2931 return PTR_ERR(vport);
2932
2933 return esw_vport_create_offloads_acl_tables(esw, vport);
2934}
2935
2936static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
2937{
2938 struct mlx5_vport *vport;
2939
2940 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
2941 if (IS_ERR(vport))
2942 return;
2943
2944 esw_vport_destroy_offloads_acl_tables(esw, vport);
2945}
2946
2947int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw)
2948{
2949 struct mlx5_eswitch_rep *rep;
2950 unsigned long i;
2951 int ret;
2952
2953 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
2954 return 0;
2955
2956 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
2957 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
2958 return 0;
2959
2960 ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
2961 if (ret)
2962 return ret;
2963
2964 mlx5_esw_for_each_rep(esw, i, rep) {
2965 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
2966 mlx5_esw_offloads_rep_load(esw, rep->vport);
2967 }
2968
2969 return 0;
2970}
2971
2972static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
2973{
2974 struct mlx5_esw_indir_table *indir;
2975 int err;
2976
2977 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
2978 mutex_init(&esw->fdb_table.offloads.vports.lock);
2979 hash_init(esw->fdb_table.offloads.vports.table);
2980 atomic64_set(&esw->user_count, 0);
2981
2982 indir = mlx5_esw_indir_table_init();
2983 if (IS_ERR(indir)) {
2984 err = PTR_ERR(indir);
2985 goto create_indir_err;
2986 }
2987 esw->fdb_table.offloads.indir = indir;
2988
2989 err = esw_create_uplink_offloads_acl_tables(esw);
2990 if (err)
2991 goto create_acl_err;
2992
2993 err = esw_create_offloads_table(esw);
2994 if (err)
2995 goto create_offloads_err;
2996
2997 err = esw_create_restore_table(esw);
2998 if (err)
2999 goto create_restore_err;
3000
3001 err = esw_create_offloads_fdb_tables(esw);
3002 if (err)
3003 goto create_fdb_err;
3004
3005 err = esw_create_vport_rx_group(esw);
3006 if (err)
3007 goto create_fg_err;
3008
3009 return 0;
3010
3011create_fg_err:
3012 esw_destroy_offloads_fdb_tables(esw);
3013create_fdb_err:
3014 esw_destroy_restore_table(esw);
3015create_restore_err:
3016 esw_destroy_offloads_table(esw);
3017create_offloads_err:
3018 esw_destroy_uplink_offloads_acl_tables(esw);
3019create_acl_err:
3020 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3021create_indir_err:
3022 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3023 return err;
3024}
3025
3026static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3027{
3028 esw_destroy_vport_rx_group(esw);
3029 esw_destroy_offloads_fdb_tables(esw);
3030 esw_destroy_restore_table(esw);
3031 esw_destroy_offloads_table(esw);
3032 esw_destroy_uplink_offloads_acl_tables(esw);
3033 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3034 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
3035}
3036
3037static void
3038esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
3039{
3040 bool host_pf_disabled;
3041 u16 new_num_vfs;
3042
3043 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3044 host_params_context.host_num_of_vfs);
3045 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3046 host_params_context.host_pf_disabled);
3047
3048 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3049 return;
3050
3051
3052 if (esw->esw_funcs.num_vfs > 0) {
3053 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
3054 } else {
3055 int err;
3056
3057 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3058 MLX5_VPORT_UC_ADDR_CHANGE);
3059 if (err)
3060 return;
3061 }
3062 esw->esw_funcs.num_vfs = new_num_vfs;
3063}
3064
3065static void esw_functions_changed_event_handler(struct work_struct *work)
3066{
3067 struct mlx5_host_work *host_work;
3068 struct mlx5_eswitch *esw;
3069 const u32 *out;
3070
3071 host_work = container_of(work, struct mlx5_host_work, work);
3072 esw = host_work->esw;
3073
3074 out = mlx5_esw_query_functions(esw->dev);
3075 if (IS_ERR(out))
3076 goto out;
3077
3078 esw_vfs_changed_event_handler(esw, out);
3079 kvfree(out);
3080out:
3081 kfree(host_work);
3082}
3083
3084int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
3085{
3086 struct mlx5_esw_functions *esw_funcs;
3087 struct mlx5_host_work *host_work;
3088 struct mlx5_eswitch *esw;
3089
3090 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3091 if (!host_work)
3092 return NOTIFY_DONE;
3093
3094 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3095 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
3096
3097 host_work->esw = esw;
3098
3099 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
3100 queue_work(esw->work_queue, &host_work->work);
3101
3102 return NOTIFY_OK;
3103}
3104
3105static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3106{
3107 const u32 *query_host_out;
3108
3109 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3110 return 0;
3111
3112 query_host_out = mlx5_esw_query_functions(esw->dev);
3113 if (IS_ERR(query_host_out))
3114 return PTR_ERR(query_host_out);
3115
3116
3117 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3118 host_params_context.host_number);
3119 kvfree(query_host_out);
3120 return 0;
3121}
3122
3123bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3124{
3125
3126 if (controller == 0)
3127 return true;
3128
3129 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3130 return false;
3131
3132
3133 return (controller == esw->offloads.host_number + 1);
3134}
3135
3136int esw_offloads_enable(struct mlx5_eswitch *esw)
3137{
3138 struct mapping_ctx *reg_c0_obj_pool;
3139 struct mlx5_vport *vport;
3140 unsigned long i;
3141 u64 mapping_id;
3142 int err;
3143
3144 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) &&
3145 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap))
3146 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC;
3147 else
3148 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3149
3150 mutex_init(&esw->offloads.termtbl_mutex);
3151 mlx5_rdma_enable_roce(esw->dev);
3152
3153 err = mlx5_esw_host_number_init(esw);
3154 if (err)
3155 goto err_metadata;
3156
3157 err = esw_offloads_metadata_init(esw);
3158 if (err)
3159 goto err_metadata;
3160
3161 err = esw_set_passing_vport_metadata(esw, true);
3162 if (err)
3163 goto err_vport_metadata;
3164
3165 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3166
3167 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3168 sizeof(struct mlx5_mapped_obj),
3169 ESW_REG_C0_USER_DATA_METADATA_MASK,
3170 true);
3171
3172 if (IS_ERR(reg_c0_obj_pool)) {
3173 err = PTR_ERR(reg_c0_obj_pool);
3174 goto err_pool;
3175 }
3176 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3177
3178 err = esw_offloads_steering_init(esw);
3179 if (err)
3180 goto err_steering_init;
3181
3182
3183 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3184 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3185
3186
3187 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
3188 if (err)
3189 goto err_uplink;
3190
3191 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
3192 if (err)
3193 goto err_vports;
3194
3195 esw_offloads_devcom_init(esw);
3196
3197 return 0;
3198
3199err_vports:
3200 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
3201err_uplink:
3202 esw_offloads_steering_cleanup(esw);
3203err_steering_init:
3204 mapping_destroy(reg_c0_obj_pool);
3205err_pool:
3206 esw_set_passing_vport_metadata(esw, false);
3207err_vport_metadata:
3208 esw_offloads_metadata_uninit(esw);
3209err_metadata:
3210 mlx5_rdma_disable_roce(esw->dev);
3211 mutex_destroy(&esw->offloads.termtbl_mutex);
3212 return err;
3213}
3214
3215static int esw_offloads_stop(struct mlx5_eswitch *esw,
3216 struct netlink_ext_ack *extack)
3217{
3218 int err, err1;
3219
3220 mlx5_eswitch_disable_locked(esw, false);
3221 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY,
3222 MLX5_ESWITCH_IGNORE_NUM_VFS);
3223 if (err) {
3224 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
3225 err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS,
3226 MLX5_ESWITCH_IGNORE_NUM_VFS);
3227 if (err1) {
3228 NL_SET_ERR_MSG_MOD(extack,
3229 "Failed setting eswitch back to offloads");
3230 }
3231 }
3232
3233 return err;
3234}
3235
3236void esw_offloads_disable(struct mlx5_eswitch *esw)
3237{
3238 esw_offloads_devcom_cleanup(esw);
3239 mlx5_eswitch_disable_pf_vf_vports(esw);
3240 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
3241 esw_set_passing_vport_metadata(esw, false);
3242 esw_offloads_steering_cleanup(esw);
3243 mapping_destroy(esw->offloads.reg_c0_obj_pool);
3244 esw_offloads_metadata_uninit(esw);
3245 mlx5_rdma_disable_roce(esw->dev);
3246 mutex_destroy(&esw->offloads.termtbl_mutex);
3247 esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE;
3248}
3249
3250static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
3251{
3252 switch (mode) {
3253 case DEVLINK_ESWITCH_MODE_LEGACY:
3254 *mlx5_mode = MLX5_ESWITCH_LEGACY;
3255 break;
3256 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
3257 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
3258 break;
3259 default:
3260 return -EINVAL;
3261 }
3262
3263 return 0;
3264}
3265
3266static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3267{
3268 switch (mlx5_mode) {
3269 case MLX5_ESWITCH_LEGACY:
3270 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3271 break;
3272 case MLX5_ESWITCH_OFFLOADS:
3273 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3274 break;
3275 default:
3276 return -EINVAL;
3277 }
3278
3279 return 0;
3280}
3281
3282static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3283{
3284 switch (mode) {
3285 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3286 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3287 break;
3288 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3289 *mlx5_mode = MLX5_INLINE_MODE_L2;
3290 break;
3291 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3292 *mlx5_mode = MLX5_INLINE_MODE_IP;
3293 break;
3294 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3295 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3296 break;
3297 default:
3298 return -EINVAL;
3299 }
3300
3301 return 0;
3302}
3303
3304static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3305{
3306 switch (mlx5_mode) {
3307 case MLX5_INLINE_MODE_NONE:
3308 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3309 break;
3310 case MLX5_INLINE_MODE_L2:
3311 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3312 break;
3313 case MLX5_INLINE_MODE_IP:
3314 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3315 break;
3316 case MLX5_INLINE_MODE_TCP_UDP:
3317 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3318 break;
3319 default:
3320 return -EINVAL;
3321 }
3322
3323 return 0;
3324}
3325
3326static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw)
3327{
3328
3329
3330
3331 return (esw->mode == MLX5_ESWITCH_NONE &&
3332 !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0;
3333}
3334
3335int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3336 struct netlink_ext_ack *extack)
3337{
3338 u16 cur_mlx5_mode, mlx5_mode = 0;
3339 struct mlx5_eswitch *esw;
3340 int err = 0;
3341
3342 esw = mlx5_devlink_eswitch_get(devlink);
3343 if (IS_ERR(esw))
3344 return PTR_ERR(esw);
3345
3346 if (esw_mode_from_devlink(mode, &mlx5_mode))
3347 return -EINVAL;
3348
3349 mlx5_lag_disable_change(esw->dev);
3350 err = mlx5_esw_try_lock(esw);
3351 if (err < 0) {
3352 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
3353 goto enable_lag;
3354 }
3355 cur_mlx5_mode = err;
3356 err = 0;
3357
3358 if (cur_mlx5_mode == mlx5_mode)
3359 goto unlock;
3360
3361 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3362 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3363 NL_SET_ERR_MSG_MOD(extack,
3364 "Can't change mode while devlink traps are active");
3365 err = -EOPNOTSUPP;
3366 goto unlock;
3367 }
3368 err = esw_offloads_start(esw, extack);
3369 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
3370 err = esw_offloads_stop(esw, extack);
3371 } else {
3372 err = -EINVAL;
3373 }
3374
3375unlock:
3376 mlx5_esw_unlock(esw);
3377enable_lag:
3378 mlx5_lag_enable_change(esw->dev);
3379 return err;
3380}
3381
3382int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3383{
3384 struct mlx5_eswitch *esw;
3385 int err;
3386
3387 esw = mlx5_devlink_eswitch_get(devlink);
3388 if (IS_ERR(esw))
3389 return PTR_ERR(esw);
3390
3391 down_write(&esw->mode_lock);
3392 err = eswitch_devlink_esw_mode_check(esw);
3393 if (err)
3394 goto unlock;
3395
3396 err = esw_mode_to_devlink(esw->mode, mode);
3397unlock:
3398 up_write(&esw->mode_lock);
3399 return err;
3400}
3401
3402static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3403 struct netlink_ext_ack *extack)
3404{
3405 struct mlx5_core_dev *dev = esw->dev;
3406 struct mlx5_vport *vport;
3407 u16 err_vport_num = 0;
3408 unsigned long i;
3409 int err = 0;
3410
3411 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3412 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3413 if (err) {
3414 err_vport_num = vport->vport;
3415 NL_SET_ERR_MSG_MOD(extack,
3416 "Failed to set min inline on vport");
3417 goto revert_inline_mode;
3418 }
3419 }
3420 return 0;
3421
3422revert_inline_mode:
3423 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3424 if (vport->vport == err_vport_num)
3425 break;
3426 mlx5_modify_nic_vport_min_inline(dev,
3427 vport->vport,
3428 esw->offloads.inline_mode);
3429 }
3430 return err;
3431}
3432
3433int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3434 struct netlink_ext_ack *extack)
3435{
3436 struct mlx5_core_dev *dev = devlink_priv(devlink);
3437 struct mlx5_eswitch *esw;
3438 u8 mlx5_mode;
3439 int err;
3440
3441 esw = mlx5_devlink_eswitch_get(devlink);
3442 if (IS_ERR(esw))
3443 return PTR_ERR(esw);
3444
3445 down_write(&esw->mode_lock);
3446 err = eswitch_devlink_esw_mode_check(esw);
3447 if (err)
3448 goto out;
3449
3450 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3451 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
3452 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3453 err = 0;
3454 goto out;
3455 }
3456
3457 fallthrough;
3458 case MLX5_CAP_INLINE_MODE_L2:
3459 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
3460 err = -EOPNOTSUPP;
3461 goto out;
3462 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3463 break;
3464 }
3465
3466 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3467 NL_SET_ERR_MSG_MOD(extack,
3468 "Can't set inline mode when flows are configured");
3469 err = -EOPNOTSUPP;
3470 goto out;
3471 }
3472
3473 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3474 if (err)
3475 goto out;
3476
3477 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3478 if (err)
3479 goto out;
3480
3481 esw->offloads.inline_mode = mlx5_mode;
3482 up_write(&esw->mode_lock);
3483 return 0;
3484
3485out:
3486 up_write(&esw->mode_lock);
3487 return err;
3488}
3489
3490int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3491{
3492 struct mlx5_eswitch *esw;
3493 int err;
3494
3495 esw = mlx5_devlink_eswitch_get(devlink);
3496 if (IS_ERR(esw))
3497 return PTR_ERR(esw);
3498
3499 down_write(&esw->mode_lock);
3500 err = eswitch_devlink_esw_mode_check(esw);
3501 if (err)
3502 goto unlock;
3503
3504 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
3505unlock:
3506 up_write(&esw->mode_lock);
3507 return err;
3508}
3509
3510int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3511 enum devlink_eswitch_encap_mode encap,
3512 struct netlink_ext_ack *extack)
3513{
3514 struct mlx5_core_dev *dev = devlink_priv(devlink);
3515 struct mlx5_eswitch *esw;
3516 int err;
3517
3518 esw = mlx5_devlink_eswitch_get(devlink);
3519 if (IS_ERR(esw))
3520 return PTR_ERR(esw);
3521
3522 down_write(&esw->mode_lock);
3523 err = eswitch_devlink_esw_mode_check(esw);
3524 if (err)
3525 goto unlock;
3526
3527 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
3528 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
3529 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3530 err = -EOPNOTSUPP;
3531 goto unlock;
3532 }
3533
3534 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3535 err = -EOPNOTSUPP;
3536 goto unlock;
3537 }
3538
3539 if (esw->mode == MLX5_ESWITCH_LEGACY) {
3540 esw->offloads.encap = encap;
3541 goto unlock;
3542 }
3543
3544 if (esw->offloads.encap == encap)
3545 goto unlock;
3546
3547 if (atomic64_read(&esw->offloads.num_flows) > 0) {
3548 NL_SET_ERR_MSG_MOD(extack,
3549 "Can't set encapsulation when flows are configured");
3550 err = -EOPNOTSUPP;
3551 goto unlock;
3552 }
3553
3554 esw_destroy_offloads_fdb_tables(esw);
3555
3556 esw->offloads.encap = encap;
3557
3558 err = esw_create_offloads_fdb_tables(esw);
3559
3560 if (err) {
3561 NL_SET_ERR_MSG_MOD(extack,
3562 "Failed re-creating fast FDB table");
3563 esw->offloads.encap = !encap;
3564 (void)esw_create_offloads_fdb_tables(esw);
3565 }
3566
3567unlock:
3568 up_write(&esw->mode_lock);
3569 return err;
3570}
3571
3572int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3573 enum devlink_eswitch_encap_mode *encap)
3574{
3575 struct mlx5_eswitch *esw;
3576 int err;
3577
3578 esw = mlx5_devlink_eswitch_get(devlink);
3579 if (IS_ERR(esw))
3580 return PTR_ERR(esw);
3581
3582
3583 down_write(&esw->mode_lock);
3584 err = eswitch_devlink_esw_mode_check(esw);
3585 if (err)
3586 goto unlock;
3587
3588 *encap = esw->offloads.encap;
3589unlock:
3590 up_write(&esw->mode_lock);
3591 return 0;
3592}
3593
3594static bool
3595mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3596{
3597
3598 if (vport_num == MLX5_VPORT_PF &&
3599 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3600 return false;
3601
3602 if (vport_num == MLX5_VPORT_ECPF &&
3603 !mlx5_ecpf_vport_exists(esw->dev))
3604 return false;
3605
3606 return true;
3607}
3608
3609void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
3610 const struct mlx5_eswitch_rep_ops *ops,
3611 u8 rep_type)
3612{
3613 struct mlx5_eswitch_rep_data *rep_data;
3614 struct mlx5_eswitch_rep *rep;
3615 unsigned long i;
3616
3617 esw->offloads.rep_ops[rep_type] = ops;
3618 mlx5_esw_for_each_rep(esw, i, rep) {
3619 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
3620 rep->esw = esw;
3621 rep_data = &rep->rep_data[rep_type];
3622 atomic_set(&rep_data->state, REP_REGISTERED);
3623 }
3624 }
3625}
3626EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
3627
3628void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
3629{
3630 struct mlx5_eswitch_rep *rep;
3631 unsigned long i;
3632
3633 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
3634 __unload_reps_all_vport(esw, rep_type);
3635
3636 mlx5_esw_for_each_rep(esw, i, rep)
3637 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
3638}
3639EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
3640
3641void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
3642{
3643 struct mlx5_eswitch_rep *rep;
3644
3645 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3646 return rep->rep_data[rep_type].priv;
3647}
3648
3649void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
3650 u16 vport,
3651 u8 rep_type)
3652{
3653 struct mlx5_eswitch_rep *rep;
3654
3655 rep = mlx5_eswitch_get_rep(esw, vport);
3656
3657 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3658 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3659 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
3660 return NULL;
3661}
3662EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
3663
3664void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3665{
3666 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
3667}
3668EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3669
3670struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
3671 u16 vport)
3672{
3673 return mlx5_eswitch_get_rep(esw, vport);
3674}
3675EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
3676
3677bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3678{
3679 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3680}
3681EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3682
3683bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3684{
3685 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3686}
3687EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3688
3689u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
3690 u16 vport_num)
3691{
3692 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3693
3694 if (WARN_ON_ONCE(IS_ERR(vport)))
3695 return 0;
3696
3697 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
3698}
3699EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
3700
3701int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
3702 u16 vport_num, u32 controller, u32 sfnum)
3703{
3704 int err;
3705
3706 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3707 if (err)
3708 return err;
3709
3710 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
3711 if (err)
3712 goto devlink_err;
3713
3714 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3715 if (err)
3716 goto rep_err;
3717 return 0;
3718
3719rep_err:
3720 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3721devlink_err:
3722 mlx5_esw_vport_disable(esw, vport_num);
3723 return err;
3724}
3725
3726void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3727{
3728 mlx5_esw_offloads_rep_unload(esw, vport_num);
3729 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3730 mlx5_esw_vport_disable(esw, vport_num);
3731}
3732
3733static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3734{
3735 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3736 void *query_ctx;
3737 void *hca_caps;
3738 int err;
3739
3740 *vhca_id = 0;
3741 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3742 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3743 return -EPERM;
3744
3745 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3746 if (!query_ctx)
3747 return -ENOMEM;
3748
3749 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx);
3750 if (err)
3751 goto out_free;
3752
3753 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3754 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3755
3756out_free:
3757 kfree(query_ctx);
3758 return err;
3759}
3760
3761int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3762{
3763 u16 *old_entry, *vhca_map_entry, vhca_id;
3764 int err;
3765
3766 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3767 if (err) {
3768 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3769 vport_num, err);
3770 return err;
3771 }
3772
3773 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3774 if (!vhca_map_entry)
3775 return -ENOMEM;
3776
3777 *vhca_map_entry = vport_num;
3778 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3779 if (xa_is_err(old_entry)) {
3780 kfree(vhca_map_entry);
3781 return xa_err(old_entry);
3782 }
3783 kfree(old_entry);
3784 return 0;
3785}
3786
3787void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3788{
3789 u16 *vhca_map_entry, vhca_id;
3790 int err;
3791
3792 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3793 if (err)
3794 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3795 vport_num, err);
3796
3797 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3798 kfree(vhca_map_entry);
3799}
3800
3801int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3802{
3803 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3804
3805 if (!res)
3806 return -ENOENT;
3807
3808 *vport_num = *res;
3809 return 0;
3810}
3811
3812u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3813 u16 vport_num)
3814{
3815 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3816
3817 if (WARN_ON_ONCE(IS_ERR(vport)))
3818 return 0;
3819
3820 return vport->metadata;
3821}
3822EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
3823
