LXR linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.h

   1/*
   2 * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 *
  32 */
  33
  34#ifndef __MLX5_FPGA_CONN_H__
  35#define __MLX5_FPGA_CONN_H__
  36
  37#include <linux/mlx5/cq.h>
  38#include <linux/mlx5/qp.h>
  39
  40#include "fpga/core.h"
  41#include "fpga/sdk.h"
  42#include "wq.h"
  43
  44struct mlx5_fpga_conn {
  45        struct mlx5_fpga_device *fdev;
  46
  47        void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf);
  48        void *cb_arg;
  49
  50        /* FPGA QP */
  51        u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
  52        u32 fpga_qpn;
  53
  54        /* CQ */
  55        struct {
  56                struct mlx5_cqwq wq;
  57                struct mlx5_wq_ctrl wq_ctrl;
  58                struct mlx5_core_cq mcq;
  59                struct tasklet_struct tasklet;
  60        } cq;
  61
  62        /* QP */
  63        struct {
  64                bool active;
  65                int sgid_index;
  66                struct mlx5_wq_qp wq;
  67                struct mlx5_wq_ctrl wq_ctrl;
  68                u32 qpn;
  69                struct {
  70                        spinlock_t lock; /* Protects all SQ state */
  71                        unsigned int pc;
  72                        unsigned int cc;
  73                        unsigned int size;
  74                        struct mlx5_fpga_dma_buf **bufs;
  75                        struct list_head backlog;
  76                } sq;
  77                struct {
  78                        unsigned int pc;
  79                        unsigned int cc;
  80                        unsigned int size;
  81                        struct mlx5_fpga_dma_buf **bufs;
  82                } rq;
  83        } qp;
  84};
  85
  86int mlx5_fpga_conn_device_init(struct mlx5_fpga_device *fdev);
  87void mlx5_fpga_conn_device_cleanup(struct mlx5_fpga_device *fdev);
  88struct mlx5_fpga_conn *
  89mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev,
  90                      struct mlx5_fpga_conn_attr *attr,
  91                      enum mlx5_ifc_fpga_qp_type qp_type);
  92void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn);
  93int mlx5_fpga_conn_send(struct mlx5_fpga_conn *conn,
  94                        struct mlx5_fpga_dma_buf *buf);
  95
  96#endif /* __MLX5_FPGA_CONN_H__ */
  97