1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2/* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. */ 3 4#ifndef MLX5_IFC_DR_STE_V1_H 5#define MLX5_IFC_DR_STE_V1_H 6 7enum mlx5_ifc_ste_v1_modify_hdr_offset { 8 MLX5_MODIFY_HEADER_V1_QW_OFFSET = 0x20, 9}; 10 11struct mlx5_ifc_ste_single_action_flow_tag_v1_bits { 12 u8 action_id[0x8]; 13 u8 flow_tag[0x18]; 14}; 15 16struct mlx5_ifc_ste_single_action_modify_list_v1_bits { 17 u8 action_id[0x8]; 18 u8 num_of_modify_actions[0x8]; 19 u8 modify_actions_ptr[0x10]; 20}; 21 22struct mlx5_ifc_ste_single_action_remove_header_v1_bits { 23 u8 action_id[0x8]; 24 u8 reserved_at_8[0x2]; 25 u8 start_anchor[0x6]; 26 u8 reserved_at_10[0x2]; 27 u8 end_anchor[0x6]; 28 u8 reserved_at_18[0x4]; 29 u8 decap[0x1]; 30 u8 vni_to_cqe[0x1]; 31 u8 qos_profile[0x2]; 32}; 33 34struct mlx5_ifc_ste_single_action_remove_header_size_v1_bits { 35 u8 action_id[0x8]; 36 u8 reserved_at_8[0x2]; 37 u8 start_anchor[0x6]; 38 u8 outer_l4_remove[0x1]; 39 u8 reserved_at_11[0x1]; 40 u8 start_offset[0x7]; 41 u8 reserved_at_18[0x1]; 42 u8 remove_size[0x6]; 43}; 44 45struct mlx5_ifc_ste_double_action_copy_v1_bits { 46 u8 action_id[0x8]; 47 u8 destination_dw_offset[0x8]; 48 u8 reserved_at_10[0x2]; 49 u8 destination_left_shifter[0x6]; 50 u8 reserved_at_17[0x2]; 51 u8 destination_length[0x6]; 52 53 u8 reserved_at_20[0x8]; 54 u8 source_dw_offset[0x8]; 55 u8 reserved_at_30[0x2]; 56 u8 source_right_shifter[0x6]; 57 u8 reserved_at_38[0x8]; 58}; 59 60struct mlx5_ifc_ste_double_action_set_v1_bits { 61 u8 action_id[0x8]; 62 u8 destination_dw_offset[0x8]; 63 u8 reserved_at_10[0x2]; 64 u8 destination_left_shifter[0x6]; 65 u8 reserved_at_18[0x2]; 66 u8 destination_length[0x6]; 67 68 u8 inline_data[0x20]; 69}; 70 71struct mlx5_ifc_ste_double_action_add_v1_bits { 72 u8 action_id[0x8]; 73 u8 destination_dw_offset[0x8]; 74 u8 reserved_at_10[0x2]; 75 u8 destination_left_shifter[0x6]; 76 u8 reserved_at_18[0x2]; 77 u8 destination_length[0x6]; 78 79 u8 add_value[0x20]; 80}; 81 82struct mlx5_ifc_ste_double_action_insert_with_inline_v1_bits { 83 u8 action_id[0x8]; 84 u8 reserved_at_8[0x2]; 85 u8 start_anchor[0x6]; 86 u8 start_offset[0x7]; 87 u8 reserved_at_17[0x9]; 88 89 u8 inline_data[0x20]; 90}; 91 92struct mlx5_ifc_ste_double_action_insert_with_ptr_v1_bits { 93 u8 action_id[0x8]; 94 u8 reserved_at_8[0x2]; 95 u8 start_anchor[0x6]; 96 u8 start_offset[0x7]; 97 u8 size[0x6]; 98 u8 attributes[0x3]; 99 100 u8 pointer[0x20]; 101}; 102 103struct mlx5_ifc_ste_double_action_modify_action_list_v1_bits { 104 u8 action_id[0x8]; 105 u8 modify_actions_pattern_pointer[0x18]; 106 107 u8 number_of_modify_actions[0x8]; 108 u8 modify_actions_argument_pointer[0x18]; 109}; 110 111struct mlx5_ifc_ste_match_bwc_v1_bits { 112 u8 entry_format[0x8]; 113 u8 counter_id[0x18]; 114 115 u8 miss_address_63_48[0x10]; 116 u8 match_definer_ctx_idx[0x8]; 117 u8 miss_address_39_32[0x8]; 118 119 u8 miss_address_31_6[0x1a]; 120 u8 reserved_at_5a[0x1]; 121 u8 match_polarity[0x1]; 122 u8 reparse[0x1]; 123 u8 reserved_at_5d[0x3]; 124 125 u8 next_table_base_63_48[0x10]; 126 u8 hash_definer_ctx_idx[0x8]; 127 u8 next_table_base_39_32_size[0x8]; 128 129 u8 next_table_base_31_5_size[0x1b]; 130 u8 hash_type[0x2]; 131 u8 hash_after_actions[0x1]; 132 u8 reserved_at_9e[0x2]; 133 134 u8 byte_mask[0x10]; 135 u8 next_entry_format[0x1]; 136 u8 mask_mode[0x1]; 137 u8 gvmi[0xe]; 138 139 u8 action[0x40]; 140}; 141 142struct mlx5_ifc_ste_mask_and_match_v1_bits { 143 u8 entry_format[0x8]; 144 u8 counter_id[0x18]; 145 146 u8 miss_address_63_48[0x10]; 147 u8 match_definer_ctx_idx[0x8]; 148 u8 miss_address_39_32[0x8]; 149 150 u8 miss_address_31_6[0x1a]; 151 u8 reserved_at_5a[0x1]; 152 u8 match_polarity[0x1]; 153 u8 reparse[0x1]; 154 u8 reserved_at_5d[0x3]; 155 156 u8 next_table_base_63_48[0x10]; 157 u8 hash_definer_ctx_idx[0x8]; 158 u8 next_table_base_39_32_size[0x8]; 159 160 u8 next_table_base_31_5_size[0x1b]; 161 u8 hash_type[0x2]; 162 u8 hash_after_actions[0x1]; 163 u8 reserved_at_9e[0x2]; 164 165 u8 action[0x60]; 166}; 167 168struct mlx5_ifc_ste_eth_l2_src_v1_bits { 169 u8 reserved_at_0[0x1]; 170 u8 sx_sniffer[0x1]; 171 u8 functional_loopback[0x1]; 172 u8 ip_fragmented[0x1]; 173 u8 qp_type[0x2]; 174 u8 encapsulation_type[0x2]; 175 u8 port[0x2]; 176 u8 l3_type[0x2]; 177 u8 l4_type[0x2]; 178 u8 first_vlan_qualifier[0x2]; 179 u8 first_priority[0x3]; 180 u8 first_cfi[0x1]; 181 u8 first_vlan_id[0xc]; 182 183 u8 smac_47_16[0x20]; 184 185 u8 smac_15_0[0x10]; 186 u8 l3_ethertype[0x10]; 187 188 u8 reserved_at_60[0x6]; 189 u8 tcp_syn[0x1]; 190 u8 reserved_at_67[0x3]; 191 u8 force_loopback[0x1]; 192 u8 l2_ok[0x1]; 193 u8 l3_ok[0x1]; 194 u8 l4_ok[0x1]; 195 u8 second_vlan_qualifier[0x2]; 196 197 u8 second_priority[0x3]; 198 u8 second_cfi[0x1]; 199 u8 second_vlan_id[0xc]; 200}; 201 202struct mlx5_ifc_ste_eth_l2_dst_v1_bits { 203 u8 reserved_at_0[0x1]; 204 u8 sx_sniffer[0x1]; 205 u8 functional_lb[0x1]; 206 u8 ip_fragmented[0x1]; 207 u8 qp_type[0x2]; 208 u8 encapsulation_type[0x2]; 209 u8 port[0x2]; 210 u8 l3_type[0x2]; 211 u8 l4_type[0x2]; 212 u8 first_vlan_qualifier[0x2]; 213 u8 first_priority[0x3]; 214 u8 first_cfi[0x1]; 215 u8 first_vlan_id[0xc]; 216 217 u8 dmac_47_16[0x20]; 218 219 u8 dmac_15_0[0x10]; 220 u8 l3_ethertype[0x10]; 221 222 u8 reserved_at_60[0x6]; 223 u8 tcp_syn[0x1]; 224 u8 reserved_at_67[0x3]; 225 u8 force_lb[0x1]; 226 u8 l2_ok[0x1]; 227 u8 l3_ok[0x1]; 228 u8 l4_ok[0x1]; 229 u8 second_vlan_qualifier[0x2]; 230 u8 second_priority[0x3]; 231 u8 second_cfi[0x1]; 232 u8 second_vlan_id[0xc]; 233}; 234 235struct mlx5_ifc_ste_eth_l2_src_dst_v1_bits { 236 u8 dmac_47_16[0x20]; 237 238 u8 smac_47_16[0x20]; 239 240 u8 dmac_15_0[0x10]; 241 u8 reserved_at_50[0x2]; 242 u8 functional_lb[0x1]; 243 u8 reserved_at_53[0x5]; 244 u8 port[0x2]; 245 u8 l3_type[0x2]; 246 u8 reserved_at_5c[0x2]; 247 u8 first_vlan_qualifier[0x2]; 248 249 u8 first_priority[0x3]; 250 u8 first_cfi[0x1]; 251 u8 first_vlan_id[0xc]; 252 u8 smac_15_0[0x10]; 253}; 254 255struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_v1_bits { 256 u8 source_address[0x20]; 257 258 u8 destination_address[0x20]; 259 260 u8 source_port[0x10]; 261 u8 destination_port[0x10]; 262 263 u8 reserved_at_60[0x4]; 264 u8 l4_ok[0x1]; 265 u8 l3_ok[0x1]; 266 u8 fragmented[0x1]; 267 u8 tcp_ns[0x1]; 268 u8 tcp_cwr[0x1]; 269 u8 tcp_ece[0x1]; 270 u8 tcp_urg[0x1]; 271 u8 tcp_ack[0x1]; 272 u8 tcp_psh[0x1]; 273 u8 tcp_rst[0x1]; 274 u8 tcp_syn[0x1]; 275 u8 tcp_fin[0x1]; 276 u8 dscp[0x6]; 277 u8 ecn[0x2]; 278 u8 protocol[0x8]; 279}; 280 281struct mlx5_ifc_ste_eth_l2_tnl_v1_bits { 282 u8 l2_tunneling_network_id[0x20]; 283 284 u8 dmac_47_16[0x20]; 285 286 u8 dmac_15_0[0x10]; 287 u8 l3_ethertype[0x10]; 288 289 u8 reserved_at_60[0x3]; 290 u8 ip_fragmented[0x1]; 291 u8 reserved_at_64[0x2]; 292 u8 encp_type[0x2]; 293 u8 reserved_at_68[0x2]; 294 u8 l3_type[0x2]; 295 u8 l4_type[0x2]; 296 u8 first_vlan_qualifier[0x2]; 297 u8 first_priority[0x3]; 298 u8 first_cfi[0x1]; 299 u8 first_vlan_id[0xc]; 300}; 301 302struct mlx5_ifc_ste_eth_l3_ipv4_misc_v1_bits { 303 u8 identification[0x10]; 304 u8 flags[0x3]; 305 u8 fragment_offset[0xd]; 306 307 u8 total_length[0x10]; 308 u8 checksum[0x10]; 309 310 u8 version[0x4]; 311 u8 ihl[0x4]; 312 u8 time_to_live[0x8]; 313 u8 reserved_at_50[0x10]; 314 315 u8 reserved_at_60[0x1c]; 316 u8 voq_internal_prio[0x4]; 317}; 318 319struct mlx5_ifc_ste_eth_l4_v1_bits { 320 u8 ipv6_version[0x4]; 321 u8 reserved_at_4[0x4]; 322 u8 dscp[0x6]; 323 u8 ecn[0x2]; 324 u8 ipv6_hop_limit[0x8]; 325 u8 protocol[0x8]; 326 327 u8 src_port[0x10]; 328 u8 dst_port[0x10]; 329 330 u8 first_fragment[0x1]; 331 u8 reserved_at_41[0xb]; 332 u8 flow_label[0x14]; 333 334 u8 tcp_data_offset[0x4]; 335 u8 l4_ok[0x1]; 336 u8 l3_ok[0x1]; 337 u8 fragmented[0x1]; 338 u8 tcp_ns[0x1]; 339 u8 tcp_cwr[0x1]; 340 u8 tcp_ece[0x1]; 341 u8 tcp_urg[0x1]; 342 u8 tcp_ack[0x1]; 343 u8 tcp_psh[0x1]; 344 u8 tcp_rst[0x1]; 345 u8 tcp_syn[0x1]; 346 u8 tcp_fin[0x1]; 347 u8 ipv6_paylen[0x10]; 348}; 349 350struct mlx5_ifc_ste_eth_l4_misc_v1_bits { 351 u8 window_size[0x10]; 352 u8 urgent_pointer[0x10]; 353 354 u8 ack_num[0x20]; 355 356 u8 seq_num[0x20]; 357 358 u8 length[0x10]; 359 u8 checksum[0x10]; 360}; 361 362struct mlx5_ifc_ste_mpls_v1_bits { 363 u8 reserved_at_0[0x15]; 364 u8 mpls_ok[0x1]; 365 u8 mpls4_s_bit[0x1]; 366 u8 mpls4_qualifier[0x1]; 367 u8 mpls3_s_bit[0x1]; 368 u8 mpls3_qualifier[0x1]; 369 u8 mpls2_s_bit[0x1]; 370 u8 mpls2_qualifier[0x1]; 371 u8 mpls1_s_bit[0x1]; 372 u8 mpls1_qualifier[0x1]; 373 u8 mpls0_s_bit[0x1]; 374 u8 mpls0_qualifier[0x1]; 375 376 u8 mpls0_label[0x14]; 377 u8 mpls0_exp[0x3]; 378 u8 mpls0_s_bos[0x1]; 379 u8 mpls0_ttl[0x8]; 380 381 u8 mpls1_label[0x20]; 382 383 u8 mpls2_label[0x20]; 384}; 385 386struct mlx5_ifc_ste_gre_v1_bits { 387 u8 gre_c_present[0x1]; 388 u8 reserved_at_1[0x1]; 389 u8 gre_k_present[0x1]; 390 u8 gre_s_present[0x1]; 391 u8 strict_src_route[0x1]; 392 u8 recur[0x3]; 393 u8 flags[0x5]; 394 u8 version[0x3]; 395 u8 gre_protocol[0x10]; 396 397 u8 reserved_at_20[0x20]; 398 399 u8 gre_key_h[0x18]; 400 u8 gre_key_l[0x8]; 401 402 u8 reserved_at_60[0x20]; 403}; 404 405struct mlx5_ifc_ste_src_gvmi_qp_v1_bits { 406 u8 loopback_synd[0x8]; 407 u8 reserved_at_8[0x7]; 408 u8 functional_lb[0x1]; 409 u8 source_gvmi[0x10]; 410 411 u8 force_lb[0x1]; 412 u8 reserved_at_21[0x1]; 413 u8 source_is_requestor[0x1]; 414 u8 reserved_at_23[0x5]; 415 u8 source_qp[0x18]; 416 417 u8 reserved_at_40[0x20]; 418 419 u8 reserved_at_60[0x20]; 420}; 421 422struct mlx5_ifc_ste_icmp_v1_bits { 423 u8 icmp_payload_data[0x20]; 424 425 u8 icmp_header_data[0x20]; 426 427 u8 icmp_type[0x8]; 428 u8 icmp_code[0x8]; 429 u8 reserved_at_50[0x10]; 430 431 u8 reserved_at_60[0x20]; 432}; 433 434#endif /* MLX5_IFC_DR_STE_V1_H */ 435