1
2
3
4#ifndef _MLXSW_REG_H
5#define _MLXSW_REG_H
6
7#include <linux/kernel.h>
8#include <linux/string.h>
9#include <linux/bitops.h>
10#include <linux/if_vlan.h>
11
12#include "item.h"
13#include "port.h"
14
15struct mlxsw_reg_info {
16 u16 id;
17 u16 len;
18 const char *name;
19};
20
21#define MLXSW_REG_DEFINE(_name, _id, _len) \
22static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
23 .id = _id, \
24 .len = _len, \
25 .name = #_name, \
26}
27
28#define MLXSW_REG(type) (&mlxsw_reg_##type)
29#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
31
32
33
34
35
36#define MLXSW_REG_SGCR_ID 0x2000
37#define MLXSW_REG_SGCR_LEN 0x10
38
39MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
40
41
42
43
44
45
46
47MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
48
49static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
50{
51 MLXSW_REG_ZERO(sgcr, payload);
52 mlxsw_reg_sgcr_llb_set(payload, !!llb);
53}
54
55
56
57
58
59#define MLXSW_REG_SPAD_ID 0x2002
60#define MLXSW_REG_SPAD_LEN 0x10
61
62MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
63
64
65
66
67
68
69
70MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
71
72
73
74
75
76
77
78#define MLXSW_REG_SMID_ID 0x2007
79#define MLXSW_REG_SMID_LEN 0x240
80
81MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
82
83
84
85
86
87MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
88
89
90
91
92
93
94MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
95
96
97
98
99
100MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
101
102
103
104
105
106MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
107
108static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
109 u8 port, bool set)
110{
111 MLXSW_REG_ZERO(smid, payload);
112 mlxsw_reg_smid_swid_set(payload, 0);
113 mlxsw_reg_smid_mid_set(payload, mid);
114 mlxsw_reg_smid_port_set(payload, port, set);
115 mlxsw_reg_smid_port_mask_set(payload, port, 1);
116}
117
118
119
120
121
122#define MLXSW_REG_SSPR_ID 0x2008
123#define MLXSW_REG_SSPR_LEN 0x8
124
125MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
126
127
128
129
130
131
132
133
134
135
136
137MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
138
139
140
141
142
143
144MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
145
146
147
148
149
150
151
152MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
153
154
155
156
157
158
159
160
161
162MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
163
164static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
165{
166 MLXSW_REG_ZERO(sspr, payload);
167 mlxsw_reg_sspr_m_set(payload, 1);
168 mlxsw_reg_sspr_local_port_set(payload, local_port);
169 mlxsw_reg_sspr_sub_port_set(payload, 0);
170 mlxsw_reg_sspr_system_port_set(payload, local_port);
171}
172
173
174
175
176
177
178#define MLXSW_REG_SFDAT_ID 0x2009
179#define MLXSW_REG_SFDAT_LEN 0x8
180
181MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
182
183
184
185
186
187MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
188
189
190
191
192
193
194
195
196MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
197
198static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
199{
200 MLXSW_REG_ZERO(sfdat, payload);
201 mlxsw_reg_sfdat_swid_set(payload, 0);
202 mlxsw_reg_sfdat_age_time_set(payload, age_time);
203}
204
205
206
207
208
209
210
211
212#define MLXSW_REG_SFD_ID 0x200A
213#define MLXSW_REG_SFD_BASE_LEN 0x10
214#define MLXSW_REG_SFD_REC_LEN 0x10
215#define MLXSW_REG_SFD_REC_MAX_COUNT 64
216#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
218
219MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
220
221
222
223
224
225MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
226
227enum mlxsw_reg_sfd_op {
228
229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
230
231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
232
233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
234
235
236
237 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
238
239
240
241
242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
243
244
245
246
247
248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
249
250
251
252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
253};
254
255
256
257
258
259MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
260
261
262
263
264
265
266
267
268MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
269
270
271
272
273
274
275
276
277MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
278
279static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
280 u32 record_locator)
281{
282 MLXSW_REG_ZERO(sfd, payload);
283 mlxsw_reg_sfd_op_set(payload, op);
284 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
285}
286
287
288
289
290
291MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
292 MLXSW_REG_SFD_REC_LEN, 0x00, false);
293
294enum mlxsw_reg_sfd_rec_type {
295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
299};
300
301
302
303
304
305MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
306 MLXSW_REG_SFD_REC_LEN, 0x00, false);
307
308enum mlxsw_reg_sfd_rec_policy {
309
310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
311
312
313
314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
315
316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
317};
318
319
320
321
322
323MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
324 MLXSW_REG_SFD_REC_LEN, 0x00, false);
325
326
327
328
329
330
331
332MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
333 MLXSW_REG_SFD_REC_LEN, 0x00, false);
334
335
336
337
338
339MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
340 MLXSW_REG_SFD_REC_LEN, 0x02);
341
342enum mlxsw_reg_sfd_rec_action {
343
344 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
345
346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
347
348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
349
350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
352};
353
354
355
356
357
358
359MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
360 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
361
362
363
364
365
366
367
368MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
369 MLXSW_REG_SFD_REC_LEN, 0x08, false);
370
371
372
373
374
375
376
377
378
379
380
381MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
382 MLXSW_REG_SFD_REC_LEN, 0x08, false);
383
384
385
386
387
388MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
389 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
390
391static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
392 enum mlxsw_reg_sfd_rec_type rec_type,
393 const char *mac,
394 enum mlxsw_reg_sfd_rec_action action)
395{
396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
397
398 if (rec_index >= num_rec)
399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
404}
405
406static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
407 enum mlxsw_reg_sfd_rec_policy policy,
408 const char *mac, u16 fid_vid,
409 enum mlxsw_reg_sfd_rec_action action,
410 u8 local_port)
411{
412 mlxsw_reg_sfd_rec_pack(payload, rec_index,
413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
418}
419
420static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
421 char *mac, u16 *p_fid_vid,
422 u8 *p_local_port)
423{
424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
427}
428
429
430
431
432
433
434MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
435 MLXSW_REG_SFD_REC_LEN, 0x08, false);
436
437
438
439
440
441
442
443
444
445
446
447MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
448 MLXSW_REG_SFD_REC_LEN, 0x08, false);
449
450
451
452
453
454MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
455 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
456
457
458
459
460
461MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
462 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
463
464static inline void
465mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
466 enum mlxsw_reg_sfd_rec_policy policy,
467 const char *mac, u16 fid_vid,
468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
469 u16 lag_id)
470{
471 mlxsw_reg_sfd_rec_pack(payload, rec_index,
472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
473 mac, action);
474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
479}
480
481static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
482 char *mac, u16 *p_vid,
483 u16 *p_lag_id)
484{
485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
488}
489
490
491
492
493
494
495
496
497MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
498 MLXSW_REG_SFD_REC_LEN, 0x08, false);
499
500
501
502
503
504
505MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
506 MLXSW_REG_SFD_REC_LEN, 0x08, false);
507
508
509
510
511
512
513
514MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
515 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
516
517static inline void
518mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
519 const char *mac, u16 fid_vid,
520 enum mlxsw_reg_sfd_rec_action action, u16 mid)
521{
522 mlxsw_reg_sfd_rec_pack(payload, rec_index,
523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
527}
528
529
530
531
532
533
534
535MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
537
538
539
540
541
542MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
543 MLXSW_REG_SFD_REC_LEN, 0x08, false);
544
545enum mlxsw_reg_sfd_uc_tunnel_protocol {
546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
548};
549
550
551
552
553
554MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
556
557
558
559
560
561
562
563
564MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
566
567static inline void
568mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
569 enum mlxsw_reg_sfd_rec_policy policy,
570 const char *mac, u16 fid,
571 enum mlxsw_reg_sfd_rec_action action, u32 uip,
572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
573{
574 mlxsw_reg_sfd_rec_pack(payload, rec_index,
575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
576 action);
577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
582}
583
584enum mlxsw_reg_tunnel_port {
585 MLXSW_REG_TUNNEL_PORT_NVE,
586 MLXSW_REG_TUNNEL_PORT_VPLS,
587 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL0,
588 MLXSW_REG_TUNNEL_PORT_FLEX_TUNNEL1,
589};
590
591
592
593
594
595
596#define MLXSW_REG_SFN_ID 0x200B
597#define MLXSW_REG_SFN_BASE_LEN 0x10
598#define MLXSW_REG_SFN_REC_LEN 0x10
599#define MLXSW_REG_SFN_REC_MAX_COUNT 64
600#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
601 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
602
603MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
604
605
606
607
608
609MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
610
611
612
613
614
615MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
616
617
618
619
620
621
622
623
624
625MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
626
627static inline void mlxsw_reg_sfn_pack(char *payload)
628{
629 MLXSW_REG_ZERO(sfn, payload);
630 mlxsw_reg_sfn_swid_set(payload, 0);
631 mlxsw_reg_sfn_end_set(payload, 0);
632 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
633}
634
635
636
637
638
639MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
640 MLXSW_REG_SFN_REC_LEN, 0x00, false);
641
642enum mlxsw_reg_sfn_rec_type {
643
644 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
645
646 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
647
648 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
649
650 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
651
652 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
653
654 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
655};
656
657
658
659
660
661MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
662 MLXSW_REG_SFN_REC_LEN, 0x00, false);
663
664
665
666
667
668MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
669 MLXSW_REG_SFN_REC_LEN, 0x02);
670
671
672
673
674
675
676MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
677 MLXSW_REG_SFN_REC_LEN, 0x08, false);
678
679
680
681
682
683MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
684 MLXSW_REG_SFN_REC_LEN, 0x08, false);
685
686
687
688
689
690MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
691 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
692
693static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
694 char *mac, u16 *p_vid,
695 u8 *p_local_port)
696{
697 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
698 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
699 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
700}
701
702
703
704
705
706MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
707 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
708
709static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
710 char *mac, u16 *p_vid,
711 u16 *p_lag_id)
712{
713 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
714 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
715 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
716}
717
718
719
720
721
722
723
724MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
725 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
726
727enum mlxsw_reg_sfn_uc_tunnel_protocol {
728 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
729 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
730};
731
732
733
734
735
736MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
737 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
738
739
740
741
742
743
744
745MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
746 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
747
748
749
750
751
752
753MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
754 MLXSW_REG_SFN_REC_LEN, 0x10, false);
755
756static inline void
757mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac,
758 u16 *p_fid, u32 *p_uip,
759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
760{
761 u32 uip_msb, uip_lsb;
762
763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
767 *p_uip = uip_msb << 24 | uip_lsb;
768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
769}
770
771
772
773
774
775#define MLXSW_REG_SPMS_ID 0x200D
776#define MLXSW_REG_SPMS_LEN 0x404
777
778MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
779
780
781
782
783
784MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
785
786enum mlxsw_reg_spms_state {
787 MLXSW_REG_SPMS_STATE_NO_CHANGE,
788 MLXSW_REG_SPMS_STATE_DISCARDING,
789 MLXSW_REG_SPMS_STATE_LEARNING,
790 MLXSW_REG_SPMS_STATE_FORWARDING,
791};
792
793
794
795
796
797
798
799
800
801MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
802
803static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
804{
805 MLXSW_REG_ZERO(spms, payload);
806 mlxsw_reg_spms_local_port_set(payload, local_port);
807}
808
809static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
810 enum mlxsw_reg_spms_state state)
811{
812 mlxsw_reg_spms_state_set(payload, vid, state);
813}
814
815
816
817
818
819#define MLXSW_REG_SPVID_ID 0x200E
820#define MLXSW_REG_SPVID_LEN 0x08
821
822MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
823
824
825
826
827
828
829MLXSW_ITEM32(reg, spvid, tport, 0x00, 24, 1);
830
831
832
833
834
835
836MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
837
838
839
840
841
842
843MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
844
845
846
847
848
849
850
851MLXSW_ITEM32(reg, spvid, egr_et_set, 0x04, 24, 1);
852
853
854
855
856
857
858
859
860
861
862
863MLXSW_ITEM32(reg, spvid, et_vlan, 0x04, 16, 2);
864
865
866
867
868
869MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
870
871static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid,
872 u8 et_vlan)
873{
874 MLXSW_REG_ZERO(spvid, payload);
875 mlxsw_reg_spvid_local_port_set(payload, local_port);
876 mlxsw_reg_spvid_pvid_set(payload, pvid);
877 mlxsw_reg_spvid_et_vlan_set(payload, et_vlan);
878}
879
880
881
882
883
884
885
886#define MLXSW_REG_SPVM_ID 0x200F
887#define MLXSW_REG_SPVM_BASE_LEN 0x04
888#define MLXSW_REG_SPVM_REC_LEN 0x04
889#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
890#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
891 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
892
893MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
894
895
896
897
898
899
900
901MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
902
903
904
905
906
907
908MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
909
910
911
912
913
914MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
915
916
917
918
919
920
921MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
922
923
924
925
926
927MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
928
929
930
931
932
933MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
934 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
935 MLXSW_REG_SPVM_REC_LEN, 0, false);
936
937
938
939
940
941MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
942 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
943 MLXSW_REG_SPVM_REC_LEN, 0, false);
944
945
946
947
948
949
950MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
951 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
952 MLXSW_REG_SPVM_REC_LEN, 0, false);
953
954
955
956
957
958MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
959 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
960 MLXSW_REG_SPVM_REC_LEN, 0, false);
961
962static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
963 u16 vid_begin, u16 vid_end,
964 bool is_member, bool untagged)
965{
966 int size = vid_end - vid_begin + 1;
967 int i;
968
969 MLXSW_REG_ZERO(spvm, payload);
970 mlxsw_reg_spvm_local_port_set(payload, local_port);
971 mlxsw_reg_spvm_num_rec_set(payload, size);
972
973 for (i = 0; i < size; i++) {
974 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
975 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
976 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
977 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
978 }
979}
980
981
982
983
984
985
986#define MLXSW_REG_SPAFT_ID 0x2010
987#define MLXSW_REG_SPAFT_LEN 0x08
988
989MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
990
991
992
993
994
995
996
997MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
998
999
1000
1001
1002
1003
1004MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
1005
1006
1007
1008
1009
1010MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
1011
1012
1013
1014
1015
1016MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
1017
1018
1019
1020
1021
1022MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
1023
1024static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
1025 bool allow_untagged)
1026{
1027 MLXSW_REG_ZERO(spaft, payload);
1028 mlxsw_reg_spaft_local_port_set(payload, local_port);
1029 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
1030 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged);
1031 mlxsw_reg_spaft_allow_tagged_set(payload, true);
1032}
1033
1034
1035
1036
1037
1038
1039#define MLXSW_REG_SFGC_ID 0x2011
1040#define MLXSW_REG_SFGC_LEN 0x10
1041
1042MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
1043
1044enum mlxsw_reg_sfgc_type {
1045 MLXSW_REG_SFGC_TYPE_BROADCAST,
1046 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1047 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1048 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1049 MLXSW_REG_SFGC_TYPE_RESERVED,
1050 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1051 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
1052 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
1053 MLXSW_REG_SFGC_TYPE_MAX,
1054};
1055
1056
1057
1058
1059
1060MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
1061
1062enum mlxsw_reg_sfgc_bridge_type {
1063 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
1064 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
1065};
1066
1067
1068
1069
1070
1071
1072MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
1073
1074enum mlxsw_flood_table_type {
1075 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
1076 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
1077 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
1078 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
1079 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
1080};
1081
1082
1083
1084
1085
1086
1087
1088MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1089
1090
1091
1092
1093
1094
1095MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1096
1097
1098
1099
1100
1101MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1102
1103
1104
1105
1106
1107MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1108
1109
1110
1111
1112
1113MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1114
1115static inline void
1116mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1117 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1118 enum mlxsw_flood_table_type table_type,
1119 unsigned int flood_table)
1120{
1121 MLXSW_REG_ZERO(sfgc, payload);
1122 mlxsw_reg_sfgc_type_set(payload, type);
1123 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1124 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1125 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1126 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1127}
1128
1129
1130
1131
1132
1133
1134#define MLXSW_REG_SFTR_ID 0x2012
1135#define MLXSW_REG_SFTR_LEN 0x420
1136
1137MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1138
1139
1140
1141
1142
1143MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1144
1145
1146
1147
1148
1149
1150MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1151
1152
1153
1154
1155
1156
1157MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1158
1159
1160
1161
1162
1163MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1164
1165
1166
1167
1168
1169MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1170
1171
1172
1173
1174
1175MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1176
1177
1178
1179
1180
1181MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1182
1183static inline void mlxsw_reg_sftr_pack(char *payload,
1184 unsigned int flood_table,
1185 unsigned int index,
1186 enum mlxsw_flood_table_type table_type,
1187 unsigned int range, u8 port, bool set)
1188{
1189 MLXSW_REG_ZERO(sftr, payload);
1190 mlxsw_reg_sftr_swid_set(payload, 0);
1191 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1192 mlxsw_reg_sftr_index_set(payload, index);
1193 mlxsw_reg_sftr_table_type_set(payload, table_type);
1194 mlxsw_reg_sftr_range_set(payload, range);
1195 mlxsw_reg_sftr_port_set(payload, port, set);
1196 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1197}
1198
1199
1200
1201
1202
1203
1204#define MLXSW_REG_SFDF_ID 0x2013
1205#define MLXSW_REG_SFDF_LEN 0x14
1206
1207MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1208
1209
1210
1211
1212
1213MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1214
1215enum mlxsw_reg_sfdf_flush_type {
1216 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1217 MLXSW_REG_SFDF_FLUSH_PER_FID,
1218 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1219 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1220 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1221 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1222 MLXSW_REG_SFDF_FLUSH_PER_NVE,
1223 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1224};
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1241
1242
1243
1244
1245
1246
1247
1248MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1249
1250static inline void mlxsw_reg_sfdf_pack(char *payload,
1251 enum mlxsw_reg_sfdf_flush_type type)
1252{
1253 MLXSW_REG_ZERO(sfdf, payload);
1254 mlxsw_reg_sfdf_flush_type_set(payload, type);
1255 mlxsw_reg_sfdf_flush_static_set(payload, true);
1256}
1257
1258
1259
1260
1261
1262MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1263
1264
1265
1266
1267
1268MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1269
1270
1271
1272
1273
1274MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1275
1276
1277
1278
1279
1280MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1281
1282
1283
1284
1285
1286MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1287
1288
1289
1290
1291
1292
1293
1294#define MLXSW_REG_SLDR_ID 0x2014
1295#define MLXSW_REG_SLDR_LEN 0x0C
1296
1297MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1298
1299enum mlxsw_reg_sldr_op {
1300
1301 MLXSW_REG_SLDR_OP_LAG_CREATE,
1302 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1303
1304 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1305
1306 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1307};
1308
1309
1310
1311
1312
1313MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1314
1315
1316
1317
1318
1319MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1320
1321static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1322{
1323 MLXSW_REG_ZERO(sldr, payload);
1324 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1325 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1326}
1327
1328static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1329{
1330 MLXSW_REG_ZERO(sldr, payload);
1331 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1332 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1333}
1334
1335
1336
1337
1338
1339
1340
1341MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1342
1343
1344
1345
1346
1347MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1348
1349static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1350 u8 local_port)
1351{
1352 MLXSW_REG_ZERO(sldr, payload);
1353 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1354 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1355 mlxsw_reg_sldr_num_ports_set(payload, 1);
1356 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1357}
1358
1359static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1360 u8 local_port)
1361{
1362 MLXSW_REG_ZERO(sldr, payload);
1363 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1364 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1365 mlxsw_reg_sldr_num_ports_set(payload, 1);
1366 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1367}
1368
1369
1370
1371
1372
1373
1374#define MLXSW_REG_SLCR_ID 0x2015
1375#define MLXSW_REG_SLCR_LEN 0x10
1376
1377MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1378
1379enum mlxsw_reg_slcr_pp {
1380
1381 MLXSW_REG_SLCR_PP_GLOBAL,
1382
1383 MLXSW_REG_SLCR_PP_PER_PORT,
1384};
1385
1386
1387
1388
1389
1390
1391MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1392
1393
1394
1395
1396
1397
1398
1399
1400MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1401
1402enum mlxsw_reg_slcr_type {
1403 MLXSW_REG_SLCR_TYPE_CRC,
1404 MLXSW_REG_SLCR_TYPE_XOR,
1405 MLXSW_REG_SLCR_TYPE_RANDOM,
1406};
1407
1408
1409
1410
1411
1412MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1413
1414
1415#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1416
1417#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1418
1419#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1420#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1421 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1422 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1423
1424#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1425
1426#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1427#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1428 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1429 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1430
1431#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1432
1433#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1434#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1435 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1436 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1437
1438#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1439
1440#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1441#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1442 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1443 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1444
1445#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1446
1447#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1448
1449#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1450
1451#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1452
1453#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1454
1455#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1456
1457#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1458
1459#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1460
1461#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1462
1463#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1464
1465
1466
1467
1468
1469
1470
1471
1472MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1473
1474
1475
1476
1477
1478MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1479
1480static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1481{
1482 MLXSW_REG_ZERO(slcr, payload);
1483 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1484 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1485 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1486 mlxsw_reg_slcr_seed_set(payload, seed);
1487}
1488
1489
1490
1491
1492
1493
1494#define MLXSW_REG_SLCOR_ID 0x2016
1495#define MLXSW_REG_SLCOR_LEN 0x10
1496
1497MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1498
1499enum mlxsw_reg_slcor_col {
1500
1501 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1502 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1503 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1504 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1505};
1506
1507
1508
1509
1510
1511MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1512
1513
1514
1515
1516
1517
1518MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1519
1520
1521
1522
1523
1524MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1525
1526
1527
1528
1529
1530
1531MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1532
1533static inline void mlxsw_reg_slcor_pack(char *payload,
1534 u8 local_port, u16 lag_id,
1535 enum mlxsw_reg_slcor_col col)
1536{
1537 MLXSW_REG_ZERO(slcor, payload);
1538 mlxsw_reg_slcor_col_set(payload, col);
1539 mlxsw_reg_slcor_local_port_set(payload, local_port);
1540 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1541}
1542
1543static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1544 u8 local_port, u16 lag_id,
1545 u8 port_index)
1546{
1547 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1548 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1549 mlxsw_reg_slcor_port_index_set(payload, port_index);
1550}
1551
1552static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1553 u8 local_port, u16 lag_id)
1554{
1555 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1556 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1557}
1558
1559static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1560 u8 local_port, u16 lag_id)
1561{
1562 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1563 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1564}
1565
1566static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1567 u8 local_port, u16 lag_id)
1568{
1569 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1570 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1571}
1572
1573
1574
1575
1576
1577#define MLXSW_REG_SPMLR_ID 0x2018
1578#define MLXSW_REG_SPMLR_LEN 0x8
1579
1580MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1581
1582
1583
1584
1585
1586MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1587
1588
1589
1590
1591
1592
1593MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1594
1595enum mlxsw_reg_spmlr_learn_mode {
1596 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1597 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1598 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1599};
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1613
1614static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1615 enum mlxsw_reg_spmlr_learn_mode mode)
1616{
1617 MLXSW_REG_ZERO(spmlr, payload);
1618 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1619 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1620 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1621}
1622
1623
1624
1625
1626
1627
1628#define MLXSW_REG_SVFA_ID 0x201C
1629#define MLXSW_REG_SVFA_LEN 0x10
1630
1631MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1632
1633
1634
1635
1636
1637MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1638
1639
1640
1641
1642
1643
1644
1645MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1646
1647enum mlxsw_reg_svfa_mt {
1648 MLXSW_REG_SVFA_MT_VID_TO_FID,
1649 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1650};
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1661
1662
1663
1664
1665
1666
1667
1668
1669MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1670
1671
1672
1673
1674
1675MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1676
1677
1678
1679
1680
1681MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1682
1683
1684
1685
1686
1687
1688
1689MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1690
1691
1692
1693
1694
1695
1696
1697MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1698
1699static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1700 enum mlxsw_reg_svfa_mt mt, bool valid,
1701 u16 fid, u16 vid)
1702{
1703 MLXSW_REG_ZERO(svfa, payload);
1704 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1705 mlxsw_reg_svfa_swid_set(payload, 0);
1706 mlxsw_reg_svfa_local_port_set(payload, local_port);
1707 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1708 mlxsw_reg_svfa_v_set(payload, valid);
1709 mlxsw_reg_svfa_fid_set(payload, fid);
1710 mlxsw_reg_svfa_vid_set(payload, vid);
1711}
1712
1713
1714
1715
1716
1717
1718#define MLXSW_REG_SPVTR_ID 0x201D
1719#define MLXSW_REG_SPVTR_LEN 0x10
1720
1721MLXSW_REG_DEFINE(spvtr, MLXSW_REG_SPVTR_ID, MLXSW_REG_SPVTR_LEN);
1722
1723
1724
1725
1726
1727
1728
1729MLXSW_ITEM32(reg, spvtr, tport, 0x00, 24, 1);
1730
1731
1732
1733
1734
1735
1736MLXSW_ITEM32(reg, spvtr, local_port, 0x00, 16, 8);
1737
1738
1739
1740
1741
1742
1743
1744MLXSW_ITEM32(reg, spvtr, ippe, 0x04, 31, 1);
1745
1746
1747
1748
1749
1750
1751
1752
1753MLXSW_ITEM32(reg, spvtr, ipve, 0x04, 30, 1);
1754
1755
1756
1757
1758
1759
1760
1761MLXSW_ITEM32(reg, spvtr, epve, 0x04, 29, 1);
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773MLXSW_ITEM32(reg, spvtr, ipprio_mode, 0x04, 20, 4);
1774
1775enum mlxsw_reg_spvtr_ipvid_mode {
1776
1777 MLXSW_REG_SPVTR_IPVID_MODE_IEEE_COMPLIANT_PVID,
1778
1779 MLXSW_REG_SPVTR_IPVID_MODE_PUSH_VLAN_FOR_UNTAGGED_PACKET,
1780
1781 MLXSW_REG_SPVTR_IPVID_MODE_ALWAYS_PUSH_VLAN,
1782};
1783
1784
1785
1786
1787
1788
1789MLXSW_ITEM32(reg, spvtr, ipvid_mode, 0x04, 16, 4);
1790
1791enum mlxsw_reg_spvtr_epvid_mode {
1792
1793 MLXSW_REG_SPVTR_EPVID_MODE_IEEE_COMPLIANT_VLAN_MEMBERSHIP,
1794
1795 MLXSW_REG_SPVTR_EPVID_MODE_POP_VLAN,
1796};
1797
1798
1799
1800
1801
1802
1803MLXSW_ITEM32(reg, spvtr, epvid_mode, 0x04, 0, 4);
1804
1805static inline void mlxsw_reg_spvtr_pack(char *payload, bool tport,
1806 u8 local_port,
1807 enum mlxsw_reg_spvtr_ipvid_mode ipvid_mode)
1808{
1809 MLXSW_REG_ZERO(spvtr, payload);
1810 mlxsw_reg_spvtr_tport_set(payload, tport);
1811 mlxsw_reg_spvtr_local_port_set(payload, local_port);
1812 mlxsw_reg_spvtr_ipvid_mode_set(payload, ipvid_mode);
1813 mlxsw_reg_spvtr_ipve_set(payload, true);
1814}
1815
1816
1817
1818
1819
1820#define MLXSW_REG_SVPE_ID 0x201E
1821#define MLXSW_REG_SVPE_LEN 0x4
1822
1823MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1824
1825
1826
1827
1828
1829
1830
1831MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1832
1833
1834
1835
1836
1837
1838
1839MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1840
1841static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1842 bool enable)
1843{
1844 MLXSW_REG_ZERO(svpe, payload);
1845 mlxsw_reg_svpe_local_port_set(payload, local_port);
1846 mlxsw_reg_svpe_vp_en_set(payload, enable);
1847}
1848
1849
1850
1851
1852
1853#define MLXSW_REG_SFMR_ID 0x201F
1854#define MLXSW_REG_SFMR_LEN 0x18
1855
1856MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1857
1858enum mlxsw_reg_sfmr_op {
1859 MLXSW_REG_SFMR_OP_CREATE_FID,
1860 MLXSW_REG_SFMR_OP_DESTROY_FID,
1861};
1862
1863
1864
1865
1866
1867
1868
1869MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1870
1871
1872
1873
1874
1875MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1876
1877
1878
1879
1880
1881
1882
1883MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1884
1885
1886
1887
1888
1889
1890
1891
1892MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1893
1894
1895
1896
1897
1898
1899
1900MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1901
1902
1903
1904
1905
1906
1907
1908
1909MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1910
1911
1912
1913
1914
1915
1916
1917MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1918
1919static inline void mlxsw_reg_sfmr_pack(char *payload,
1920 enum mlxsw_reg_sfmr_op op, u16 fid,
1921 u16 fid_offset)
1922{
1923 MLXSW_REG_ZERO(sfmr, payload);
1924 mlxsw_reg_sfmr_op_set(payload, op);
1925 mlxsw_reg_sfmr_fid_set(payload, fid);
1926 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1927 mlxsw_reg_sfmr_vtfp_set(payload, false);
1928 mlxsw_reg_sfmr_vv_set(payload, false);
1929}
1930
1931
1932
1933
1934
1935#define MLXSW_REG_SPVMLR_ID 0x2020
1936#define MLXSW_REG_SPVMLR_BASE_LEN 0x04
1937#define MLXSW_REG_SPVMLR_REC_LEN 0x04
1938#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1939#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1940 MLXSW_REG_SPVMLR_REC_LEN * \
1941 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1942
1943MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1944
1945
1946
1947
1948
1949
1950
1951MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1952
1953
1954
1955
1956
1957MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1958
1959
1960
1961
1962
1963
1964MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1965 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1966
1967
1968
1969
1970
1971MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1972 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1973
1974static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1975 u16 vid_begin, u16 vid_end,
1976 bool learn_enable)
1977{
1978 int num_rec = vid_end - vid_begin + 1;
1979 int i;
1980
1981 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1982
1983 MLXSW_REG_ZERO(spvmlr, payload);
1984 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1985 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1986
1987 for (i = 0; i < num_rec; i++) {
1988 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1989 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1990 }
1991}
1992
1993
1994
1995
1996
1997
1998
1999#define MLXSW_REG_SPVC_ID 0x2026
2000#define MLXSW_REG_SPVC_LEN 0x0C
2001
2002MLXSW_REG_DEFINE(spvc, MLXSW_REG_SPVC_ID, MLXSW_REG_SPVC_LEN);
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012MLXSW_ITEM32(reg, spvc, local_port, 0x00, 16, 8);
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023MLXSW_ITEM32(reg, spvc, inner_et2, 0x08, 17, 1);
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033MLXSW_ITEM32(reg, spvc, et2, 0x08, 16, 1);
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044MLXSW_ITEM32(reg, spvc, inner_et1, 0x08, 9, 1);
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054MLXSW_ITEM32(reg, spvc, et1, 0x08, 8, 1);
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065MLXSW_ITEM32(reg, spvc, inner_et0, 0x08, 1, 1);
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075MLXSW_ITEM32(reg, spvc, et0, 0x08, 0, 1);
2076
2077static inline void mlxsw_reg_spvc_pack(char *payload, u8 local_port, bool et1,
2078 bool et0)
2079{
2080 MLXSW_REG_ZERO(spvc, payload);
2081 mlxsw_reg_spvc_local_port_set(payload, local_port);
2082
2083
2084
2085 mlxsw_reg_spvc_inner_et1_set(payload, 1);
2086 mlxsw_reg_spvc_inner_et0_set(payload, 1);
2087 mlxsw_reg_spvc_et1_set(payload, et1);
2088 mlxsw_reg_spvc_et0_set(payload, et0);
2089}
2090
2091
2092
2093
2094
2095
2096
2097#define MLXSW_REG_SPEVET_ID 0x202A
2098#define MLXSW_REG_SPEVET_LEN 0x08
2099
2100MLXSW_REG_DEFINE(spevet, MLXSW_REG_SPEVET_ID, MLXSW_REG_SPEVET_LEN);
2101
2102
2103
2104
2105
2106
2107MLXSW_ITEM32(reg, spevet, local_port, 0x00, 16, 8);
2108
2109
2110
2111
2112
2113
2114
2115
2116MLXSW_ITEM32(reg, spevet, et_vlan, 0x04, 16, 2);
2117
2118static inline void mlxsw_reg_spevet_pack(char *payload, u8 local_port,
2119 u8 et_vlan)
2120{
2121 MLXSW_REG_ZERO(spevet, payload);
2122 mlxsw_reg_spevet_local_port_set(payload, local_port);
2123 mlxsw_reg_spevet_et_vlan_set(payload, et_vlan);
2124}
2125
2126
2127
2128
2129
2130#define MLXSW_REG_CWTP_ID 0x2802
2131#define MLXSW_REG_CWTP_BASE_LEN 0x28
2132#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
2133#define MLXSW_REG_CWTP_LEN 0x40
2134
2135MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
2136
2137
2138
2139
2140
2141
2142MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
2143
2144
2145
2146
2147
2148MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
2149
2150
2151
2152
2153
2154MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
2155 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
2156
2157
2158
2159
2160
2161
2162MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
2163 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2164
2165
2166
2167
2168
2169MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
2170 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
2171
2172#define MLXSW_REG_CWTP_MIN_VALUE 64
2173#define MLXSW_REG_CWTP_MAX_PROFILE 2
2174#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
2175
2176static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
2177 u8 traffic_class)
2178{
2179 int i;
2180
2181 MLXSW_REG_ZERO(cwtp, payload);
2182 mlxsw_reg_cwtp_local_port_set(payload, local_port);
2183 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
2184
2185 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
2186 mlxsw_reg_cwtp_profile_min_set(payload, i,
2187 MLXSW_REG_CWTP_MIN_VALUE);
2188 mlxsw_reg_cwtp_profile_max_set(payload, i,
2189 MLXSW_REG_CWTP_MIN_VALUE);
2190 }
2191}
2192
2193#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
2194
2195static inline void
2196mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
2197 u32 probability)
2198{
2199 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
2200
2201 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
2202 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
2203 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
2204}
2205
2206
2207
2208
2209
2210#define MLXSW_REG_CWTPM_ID 0x2803
2211#define MLXSW_REG_CWTPM_LEN 0x44
2212
2213MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
2214
2215
2216
2217
2218
2219
2220MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
2221
2222
2223
2224
2225
2226MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
2227
2228
2229
2230
2231
2232
2233
2234MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
2235
2236
2237
2238
2239
2240
2241
2242MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
2243
2244
2245
2246
2247
2248
2249
2250MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
2251
2252
2253
2254
2255
2256
2257
2258MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
2259
2260
2261
2262
2263
2264
2265
2266MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
2267
2268
2269
2270
2271
2272
2273
2274MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
2275
2276
2277
2278
2279
2280
2281
2282MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
2283
2284
2285
2286
2287
2288
2289
2290MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
2291
2292#define MLXSW_REG_CWTPM_RESET_PROFILE 0
2293
2294static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
2295 u8 traffic_class, u8 profile,
2296 bool wred, bool ecn)
2297{
2298 MLXSW_REG_ZERO(cwtpm, payload);
2299 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
2300 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
2301 mlxsw_reg_cwtpm_ew_set(payload, wred);
2302 mlxsw_reg_cwtpm_ee_set(payload, ecn);
2303 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
2304 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
2305 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
2306 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
2307 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
2308 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
2309}
2310
2311
2312
2313
2314
2315#define MLXSW_REG_PGCR_ID 0x3001
2316#define MLXSW_REG_PGCR_LEN 0x20
2317
2318MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN);
2319
2320
2321
2322
2323
2324
2325MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24);
2326
2327static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base)
2328{
2329 MLXSW_REG_ZERO(pgcr, payload);
2330 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base);
2331}
2332
2333
2334
2335
2336
2337#define MLXSW_REG_PPBT_ID 0x3002
2338#define MLXSW_REG_PPBT_LEN 0x14
2339
2340MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
2341
2342enum mlxsw_reg_pxbt_e {
2343 MLXSW_REG_PXBT_E_IACL,
2344 MLXSW_REG_PXBT_E_EACL,
2345};
2346
2347
2348
2349
2350MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
2351
2352enum mlxsw_reg_pxbt_op {
2353 MLXSW_REG_PXBT_OP_BIND,
2354 MLXSW_REG_PXBT_OP_UNBIND,
2355};
2356
2357
2358
2359
2360MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
2361
2362
2363
2364
2365
2366MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
2367
2368
2369
2370
2371
2372
2373
2374MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
2375
2376
2377
2378
2379
2380
2381MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
2382
2383static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
2384 enum mlxsw_reg_pxbt_op op,
2385 u8 local_port, u16 acl_info)
2386{
2387 MLXSW_REG_ZERO(ppbt, payload);
2388 mlxsw_reg_ppbt_e_set(payload, e);
2389 mlxsw_reg_ppbt_op_set(payload, op);
2390 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2391 mlxsw_reg_ppbt_g_set(payload, true);
2392 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2393}
2394
2395
2396
2397
2398
2399#define MLXSW_REG_PACL_ID 0x3004
2400#define MLXSW_REG_PACL_LEN 0x70
2401
2402MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2403
2404
2405
2406
2407
2408
2409MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2410
2411
2412
2413
2414
2415
2416MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2417
2418#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2419
2420
2421
2422
2423
2424
2425MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2426 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2427
2428static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2429 bool valid, const char *tcam_region_info)
2430{
2431 MLXSW_REG_ZERO(pacl, payload);
2432 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2433 mlxsw_reg_pacl_v_set(payload, valid);
2434 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2435}
2436
2437
2438
2439
2440
2441#define MLXSW_REG_PAGT_ID 0x3005
2442#define MLXSW_REG_PAGT_BASE_LEN 0x30
2443#define MLXSW_REG_PAGT_ACL_LEN 4
2444#define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2445#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2446 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2447
2448MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2460
2461
2462
2463
2464
2465
2466MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2467
2468
2469
2470
2471
2472
2473
2474MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
2475
2476
2477
2478
2479
2480MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2481
2482static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2483{
2484 MLXSW_REG_ZERO(pagt, payload);
2485 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2486}
2487
2488static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2489 u16 acl_id, bool multi)
2490{
2491 u8 size = mlxsw_reg_pagt_size_get(payload);
2492
2493 if (index >= size)
2494 mlxsw_reg_pagt_size_set(payload, index + 1);
2495 mlxsw_reg_pagt_multi_set(payload, index, multi);
2496 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2497}
2498
2499
2500
2501
2502
2503
2504#define MLXSW_REG_PTAR_ID 0x3006
2505#define MLXSW_REG_PTAR_BASE_LEN 0x20
2506#define MLXSW_REG_PTAR_KEY_ID_LEN 1
2507#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2508#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2509 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2510
2511MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2512
2513enum mlxsw_reg_ptar_op {
2514
2515 MLXSW_REG_PTAR_OP_ALLOC,
2516
2517 MLXSW_REG_PTAR_OP_RESIZE,
2518
2519 MLXSW_REG_PTAR_OP_FREE,
2520
2521 MLXSW_REG_PTAR_OP_TEST,
2522};
2523
2524
2525
2526
2527MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2528
2529
2530
2531
2532
2533
2534MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2535
2536enum mlxsw_reg_ptar_key_type {
2537 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50,
2538 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51,
2539};
2540
2541
2542
2543
2544
2545MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2556
2557
2558
2559
2560
2561
2562MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2563
2564
2565
2566
2567
2568
2569
2570MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2571 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2582 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2583
2584static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2585 enum mlxsw_reg_ptar_key_type key_type,
2586 u16 region_size, u16 region_id,
2587 const char *tcam_region_info)
2588{
2589 MLXSW_REG_ZERO(ptar, payload);
2590 mlxsw_reg_ptar_op_set(payload, op);
2591 mlxsw_reg_ptar_action_set_type_set(payload, 2);
2592 mlxsw_reg_ptar_key_type_set(payload, key_type);
2593 mlxsw_reg_ptar_region_size_set(payload, region_size);
2594 mlxsw_reg_ptar_region_id_set(payload, region_id);
2595 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2596}
2597
2598static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2599 u16 key_id)
2600{
2601 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2602}
2603
2604static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2605{
2606 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2607}
2608
2609
2610
2611
2612
2613#define MLXSW_REG_PPBS_ID 0x300C
2614#define MLXSW_REG_PPBS_LEN 0x14
2615
2616MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2617
2618
2619
2620
2621
2622
2623MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2624
2625
2626
2627
2628
2629MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2630
2631static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2632 u16 system_port)
2633{
2634 MLXSW_REG_ZERO(ppbs, payload);
2635 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2636 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2637}
2638
2639
2640
2641
2642
2643#define MLXSW_REG_PRCR_ID 0x300D
2644#define MLXSW_REG_PRCR_LEN 0x40
2645
2646MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2647
2648enum mlxsw_reg_prcr_op {
2649
2650
2651
2652
2653 MLXSW_REG_PRCR_OP_MOVE,
2654
2655
2656
2657
2658 MLXSW_REG_PRCR_OP_COPY,
2659};
2660
2661
2662
2663
2664MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2665
2666
2667
2668
2669
2670MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2671
2672
2673
2674
2675
2676MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2677
2678
2679
2680
2681
2682MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2683 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2684
2685
2686
2687
2688
2689MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2690
2691
2692
2693
2694
2695MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2696 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2697
2698static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2699 const char *src_tcam_region_info,
2700 u16 src_offset,
2701 const char *dest_tcam_region_info,
2702 u16 dest_offset, u16 size)
2703{
2704 MLXSW_REG_ZERO(prcr, payload);
2705 mlxsw_reg_prcr_op_set(payload, op);
2706 mlxsw_reg_prcr_offset_set(payload, src_offset);
2707 mlxsw_reg_prcr_size_set(payload, size);
2708 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2709 src_tcam_region_info);
2710 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2711 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2712 dest_tcam_region_info);
2713}
2714
2715
2716
2717
2718
2719
2720#define MLXSW_REG_PEFA_ID 0x300F
2721#define MLXSW_REG_PEFA_LEN 0xB0
2722
2723MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2724
2725
2726
2727
2728
2729MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2730
2731
2732
2733
2734
2735
2736
2737
2738MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1);
2739
2740
2741
2742
2743
2744
2745
2746MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1);
2747
2748#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2749
2750
2751
2752
2753
2754
2755MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2756
2757static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca,
2758 const char *flex_action_set)
2759{
2760 MLXSW_REG_ZERO(pefa, payload);
2761 mlxsw_reg_pefa_index_set(payload, index);
2762 mlxsw_reg_pefa_ca_set(payload, ca);
2763 if (flex_action_set)
2764 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload,
2765 flex_action_set);
2766}
2767
2768static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a)
2769{
2770 *p_a = mlxsw_reg_pefa_a_get(payload);
2771}
2772
2773
2774
2775
2776
2777
2778
2779#define MLXSW_REG_PEMRBT_ID 0x3014
2780#define MLXSW_REG_PEMRBT_LEN 0x14
2781
2782MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
2783
2784enum mlxsw_reg_pemrbt_protocol {
2785 MLXSW_REG_PEMRBT_PROTO_IPV4,
2786 MLXSW_REG_PEMRBT_PROTO_IPV6,
2787};
2788
2789
2790
2791
2792MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
2793
2794
2795
2796
2797
2798
2799MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
2800
2801static inline void
2802mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
2803 u16 group_id)
2804{
2805 MLXSW_REG_ZERO(pemrbt, payload);
2806 mlxsw_reg_pemrbt_protocol_set(payload, protocol);
2807 mlxsw_reg_pemrbt_group_id_set(payload, group_id);
2808}
2809
2810
2811
2812
2813
2814
2815
2816
2817#define MLXSW_REG_PTCE2_ID 0x3017
2818#define MLXSW_REG_PTCE2_LEN 0x1D8
2819
2820MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2821
2822
2823
2824
2825
2826MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2827
2828
2829
2830
2831
2832
2833MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2834
2835enum mlxsw_reg_ptce2_op {
2836
2837 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2838
2839
2840
2841 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2842
2843
2844
2845
2846 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2847
2848 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2849
2850 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2851};
2852
2853
2854
2855
2856MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2857
2858
2859
2860
2861MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2862
2863
2864
2865
2866
2867
2868
2869
2870MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24);
2871
2872
2873
2874
2875
2876MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2877 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2878
2879#define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96
2880
2881
2882
2883
2884
2885MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2886 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2887
2888
2889
2890
2891
2892
2893
2894MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2895 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
2896
2897
2898
2899
2900
2901MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2902 MLXSW_REG_FLEX_ACTION_SET_LEN);
2903
2904static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2905 enum mlxsw_reg_ptce2_op op,
2906 const char *tcam_region_info,
2907 u16 offset, u32 priority)
2908{
2909 MLXSW_REG_ZERO(ptce2, payload);
2910 mlxsw_reg_ptce2_v_set(payload, valid);
2911 mlxsw_reg_ptce2_op_set(payload, op);
2912 mlxsw_reg_ptce2_offset_set(payload, offset);
2913 mlxsw_reg_ptce2_priority_set(payload, priority);
2914 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2915}
2916
2917
2918
2919
2920
2921#define MLXSW_REG_PERPT_ID 0x3021
2922#define MLXSW_REG_PERPT_LEN 0x80
2923
2924MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN);
2925
2926
2927
2928
2929
2930
2931MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4);
2932
2933
2934
2935
2936
2937
2938MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8);
2939
2940enum mlxsw_reg_perpt_key_size {
2941 MLXSW_REG_PERPT_KEY_SIZE_2KB,
2942 MLXSW_REG_PERPT_KEY_SIZE_4KB,
2943 MLXSW_REG_PERPT_KEY_SIZE_8KB,
2944 MLXSW_REG_PERPT_KEY_SIZE_12KB,
2945};
2946
2947
2948
2949
2950MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4);
2951
2952
2953
2954
2955
2956
2957
2958
2959MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1);
2960
2961
2962
2963
2964
2965MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4);
2966
2967
2968
2969
2970
2971
2972MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4);
2973
2974
2975
2976
2977
2978
2979MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8);
2980
2981
2982
2983
2984
2985MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4);
2986
2987
2988
2989
2990
2991MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1);
2992
2993
2994
2995
2996
2997
2998
2999MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3000
3001static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload,
3002 unsigned long *erp_vector,
3003 unsigned long size)
3004{
3005 unsigned long bit;
3006
3007 for_each_set_bit(bit, erp_vector, size)
3008 mlxsw_reg_perpt_erp_vector_set(payload, bit, true);
3009}
3010
3011static inline void
3012mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index,
3013 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id,
3014 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index,
3015 char *mask)
3016{
3017 MLXSW_REG_ZERO(perpt, payload);
3018 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
3019 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
3020 mlxsw_reg_perpt_key_size_set(payload, key_size);
3021 mlxsw_reg_perpt_bf_bypass_set(payload, false);
3022 mlxsw_reg_perpt_erp_id_set(payload, erp_id);
3023 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
3024 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
3025 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index);
3026 mlxsw_reg_perpt_mask_memcpy_to(payload, mask);
3027}
3028
3029
3030
3031
3032
3033
3034#define MLXSW_REG_PERAR_ID 0x3026
3035#define MLXSW_REG_PERAR_LEN 0x08
3036
3037MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN);
3038
3039
3040
3041
3042
3043
3044MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16);
3045
3046static inline unsigned int
3047mlxsw_reg_perar_hw_regions_needed(unsigned int block_num)
3048{
3049 return DIV_ROUND_UP(block_num, 4);
3050}
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16);
3061
3062static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id,
3063 u16 hw_region)
3064{
3065 MLXSW_REG_ZERO(perar, payload);
3066 mlxsw_reg_perar_region_id_set(payload, region_id);
3067 mlxsw_reg_perar_hw_region_set(payload, hw_region);
3068}
3069
3070
3071
3072
3073
3074
3075#define MLXSW_REG_PTCE3_ID 0x3027
3076#define MLXSW_REG_PTCE3_LEN 0xF0
3077
3078MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN);
3079
3080
3081
3082
3083
3084MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1);
3085
3086enum mlxsw_reg_ptce3_op {
3087
3088
3089
3090
3091
3092 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0,
3093
3094 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1,
3095
3096 MLXSW_REG_PTCE3_OP_QUERY_READ = 0,
3097};
3098
3099
3100
3101
3102MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3);
3103
3104
3105
3106
3107
3108
3109
3110MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24);
3111
3112
3113
3114
3115
3116MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10,
3117 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
3118
3119
3120
3121
3122
3123
3124MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20,
3125 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN);
3126
3127
3128
3129
3130
3131MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4);
3132
3133
3134
3135
3136
3137
3138MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10);
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8);
3150
3151
3152
3153
3154
3155
3156MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8);
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1);
3169
3170
3171
3172
3173
3174
3175
3176MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1);
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1);
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24);
3200
3201
3202
3203
3204
3205
3206MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24);
3207
3208static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid,
3209 enum mlxsw_reg_ptce3_op op,
3210 u32 priority,
3211 const char *tcam_region_info,
3212 const char *key, u8 erp_id,
3213 u16 delta_start, u8 delta_mask,
3214 u8 delta_value, bool large_exists,
3215 u32 lkey_id, u32 action_pointer)
3216{
3217 MLXSW_REG_ZERO(ptce3, payload);
3218 mlxsw_reg_ptce3_v_set(payload, valid);
3219 mlxsw_reg_ptce3_op_set(payload, op);
3220 mlxsw_reg_ptce3_priority_set(payload, priority);
3221 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
3222 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
3223 mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
3224 mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
3225 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
3226 mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
3227 mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
3228 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
3229 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
3230}
3231
3232
3233
3234
3235
3236
3237#define MLXSW_REG_PERCR_ID 0x302A
3238#define MLXSW_REG_PERCR_LEN 0x80
3239
3240MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN);
3241
3242
3243
3244
3245
3246
3247MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16);
3248
3249
3250
3251
3252
3253MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1);
3254
3255
3256
3257
3258
3259MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1);
3260
3261
3262
3263
3264
3265
3266
3267
3268MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1);
3269
3270
3271
3272
3273
3274
3275
3276MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96);
3277
3278static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id)
3279{
3280 MLXSW_REG_ZERO(percr, payload);
3281 mlxsw_reg_percr_region_id_set(payload, region_id);
3282 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
3283 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
3284 mlxsw_reg_percr_bf_bypass_set(payload, false);
3285}
3286
3287
3288
3289
3290
3291
3292#define MLXSW_REG_PERERP_ID 0x302B
3293#define MLXSW_REG_PERERP_LEN 0x1C
3294
3295MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN);
3296
3297
3298
3299
3300
3301
3302MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16);
3303
3304
3305
3306
3307
3308MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1);
3309
3310
3311
3312
3313
3314MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1);
3315
3316
3317
3318
3319
3320
3321MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4);
3322
3323
3324
3325
3326
3327
3328
3329
3330MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8);
3331
3332
3333
3334
3335
3336
3337
3338
3339MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1);
3340
3341
3342
3343
3344
3345
3346
3347MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4);
3348
3349static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload,
3350 unsigned long *erp_vector,
3351 unsigned long size)
3352{
3353 unsigned long bit;
3354
3355 for_each_set_bit(bit, erp_vector, size)
3356 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true);
3357}
3358
3359static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id,
3360 bool ctcam_le, bool erpt_pointer_valid,
3361 u8 erpt_bank_pointer, u8 erpt_pointer,
3362 u8 master_rp_id)
3363{
3364 MLXSW_REG_ZERO(pererp, payload);
3365 mlxsw_reg_pererp_region_id_set(payload, region_id);
3366 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le);
3367 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid);
3368 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer);
3369 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer);
3370 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
3371}
3372
3373
3374
3375
3376
3377#define MLXSW_REG_PEABFE_ID 0x3022
3378#define MLXSW_REG_PEABFE_BASE_LEN 0x10
3379#define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
3380#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
3381#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
3382 MLXSW_REG_PEABFE_BF_REC_LEN * \
3383 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
3384
3385MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
3386
3387
3388
3389
3390
3391
3392MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
3393
3394
3395
3396
3397
3398
3399
3400MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
3401 MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
3402 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3403
3404
3405
3406
3407
3408
3409MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
3410 MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
3411 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3412
3413
3414
3415
3416
3417
3418MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
3419 MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
3420 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
3421
3422static inline void mlxsw_reg_peabfe_pack(char *payload)
3423{
3424 MLXSW_REG_ZERO(peabfe, payload);
3425}
3426
3427static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
3428 u8 state, u8 bank, u32 bf_index)
3429{
3430 u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
3431
3432 if (rec_index >= num_rec)
3433 mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
3434 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
3435 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
3436 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
3437}
3438
3439
3440
3441
3442
3443
3444
3445#define MLXSW_REG_IEDR_ID 0x3804
3446#define MLXSW_REG_IEDR_BASE_LEN 0x10
3447#define MLXSW_REG_IEDR_REC_LEN 0x8
3448#define MLXSW_REG_IEDR_REC_MAX_COUNT 64
3449#define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \
3450 MLXSW_REG_IEDR_REC_LEN * \
3451 MLXSW_REG_IEDR_REC_MAX_COUNT)
3452
3453MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN);
3454
3455
3456
3457
3458
3459MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8);
3460
3461
3462
3463
3464
3465MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8,
3466 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3467
3468
3469
3470
3471
3472MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
3473 MLXSW_REG_IEDR_REC_LEN, 0x00, false);
3474
3475
3476
3477
3478
3479MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24,
3480 MLXSW_REG_IEDR_REC_LEN, 0x04, false);
3481
3482static inline void mlxsw_reg_iedr_pack(char *payload)
3483{
3484 MLXSW_REG_ZERO(iedr, payload);
3485}
3486
3487static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index,
3488 u8 rec_type, u16 rec_size,
3489 u32 rec_index_start)
3490{
3491 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload);
3492
3493 if (rec_index >= num_rec)
3494 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1);
3495 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type);
3496 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size);
3497 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start);
3498}
3499
3500
3501
3502
3503
3504
3505#define MLXSW_REG_QPTS_ID 0x4002
3506#define MLXSW_REG_QPTS_LEN 0x8
3507
3508MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN);
3509
3510
3511
3512
3513
3514
3515
3516MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8);
3517
3518enum mlxsw_reg_qpts_trust_state {
3519 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1,
3520 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2,
3521};
3522
3523
3524
3525
3526
3527MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3);
3528
3529static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port,
3530 enum mlxsw_reg_qpts_trust_state ts)
3531{
3532 MLXSW_REG_ZERO(qpts, payload);
3533
3534 mlxsw_reg_qpts_local_port_set(payload, local_port);
3535 mlxsw_reg_qpts_trust_state_set(payload, ts);
3536}
3537
3538
3539
3540
3541
3542
3543#define MLXSW_REG_QPCR_ID 0x4004
3544#define MLXSW_REG_QPCR_LEN 0x28
3545
3546MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
3547
3548enum mlxsw_reg_qpcr_g {
3549 MLXSW_REG_QPCR_G_GLOBAL = 2,
3550 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
3551};
3552
3553
3554
3555
3556
3557MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
3558
3559
3560
3561
3562
3563MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
3564
3565
3566
3567
3568
3569MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3570
3571
3572
3573
3574
3575
3576MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
3577
3578
3579
3580
3581
3582
3583
3584MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
3585
3586enum mlxsw_reg_qpcr_ir_units {
3587 MLXSW_REG_QPCR_IR_UNITS_M,
3588 MLXSW_REG_QPCR_IR_UNITS_K,
3589};
3590
3591
3592
3593
3594
3595
3596
3597MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
3598
3599enum mlxsw_reg_qpcr_rate_type {
3600 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
3601 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
3602};
3603
3604
3605
3606
3607
3608
3609
3610MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
3624
3625
3626
3627
3628
3629
3630
3631
3632MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
3643
3644#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
3645
3646
3647
3648
3649
3650MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
3651
3652enum mlxsw_reg_qpcr_action {
3653
3654 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
3655
3656
3657
3658 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
3659};
3660
3661
3662
3663
3664
3665
3666MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3667
3668
3669
3670
3671
3672MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
3673
3674
3675#define MLXSW_REG_QPCR_LOWEST_CIR 1
3676#define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000)
3677#define MLXSW_REG_QPCR_LOWEST_CBS 4
3678#define MLXSW_REG_QPCR_HIGHEST_CBS 24
3679
3680
3681#define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024
3682#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL
3683#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4
3684#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4
3685#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25
3686#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31
3687
3688static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3689 enum mlxsw_reg_qpcr_ir_units ir_units,
3690 bool bytes, u32 cir, u16 cbs)
3691{
3692 MLXSW_REG_ZERO(qpcr, payload);
3693 mlxsw_reg_qpcr_pid_set(payload, pid);
3694 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
3695 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
3696 mlxsw_reg_qpcr_violate_action_set(payload,
3697 MLXSW_REG_QPCR_ACTION_DISCARD);
3698 mlxsw_reg_qpcr_cir_set(payload, cir);
3699 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
3700 mlxsw_reg_qpcr_bytes_set(payload, bytes);
3701 mlxsw_reg_qpcr_cbs_set(payload, cbs);
3702}
3703
3704
3705
3706
3707
3708
3709#define MLXSW_REG_QTCT_ID 0x400A
3710#define MLXSW_REG_QTCT_LEN 0x08
3711
3712MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
3713
3714
3715
3716
3717
3718
3719
3720MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
3721
3722
3723
3724
3725
3726
3727MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
3728
3729
3730
3731
3732
3733MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
3744
3745static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
3746 u8 switch_prio, u8 tclass)
3747{
3748 MLXSW_REG_ZERO(qtct, payload);
3749 mlxsw_reg_qtct_local_port_set(payload, local_port);
3750 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
3751 mlxsw_reg_qtct_tclass_set(payload, tclass);
3752}
3753
3754
3755
3756
3757
3758#define MLXSW_REG_QEEC_ID 0x400D
3759#define MLXSW_REG_QEEC_LEN 0x20
3760
3761MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
3762
3763
3764
3765
3766
3767
3768
3769MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3770
3771enum mlxsw_reg_qeec_hr {
3772 MLXSW_REG_QEEC_HR_PORT,
3773 MLXSW_REG_QEEC_HR_GROUP,
3774 MLXSW_REG_QEEC_HR_SUBGROUP,
3775 MLXSW_REG_QEEC_HR_TC,
3776};
3777
3778
3779
3780
3781
3782
3783
3784
3785MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
3786
3787
3788
3789
3790
3791MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
3792
3793
3794
3795
3796
3797
3798
3799MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
3800
3801
3802
3803
3804
3805
3806
3807
3808MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3821
3822enum {
3823 MLXSW_REG_QEEC_BYTES_MODE,
3824 MLXSW_REG_QEEC_PACKETS_MODE,
3825};
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
3837
3838
3839#define MLXSW_REG_QEEC_MIS_MIN 200000
3840
3841
3842
3843
3844
3845
3846
3847MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28);
3848
3849
3850
3851
3852
3853
3854
3855
3856MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3857
3858
3859#define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1)
3860
3861
3862
3863
3864
3865
3866
3867MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
3868
3869
3870
3871
3872
3873
3874
3875
3876MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
3877
3878
3879
3880
3881
3882
3883
3884
3885MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
3906
3907#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25
3908#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5
3909#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11
3910#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11
3911
3912static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3913 enum mlxsw_reg_qeec_hr hr, u8 index,
3914 u8 next_index)
3915{
3916 MLXSW_REG_ZERO(qeec, payload);
3917 mlxsw_reg_qeec_local_port_set(payload, local_port);
3918 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3919 mlxsw_reg_qeec_element_index_set(payload, index);
3920 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
3921}
3922
3923static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
3924 bool ptps)
3925{
3926 MLXSW_REG_ZERO(qeec, payload);
3927 mlxsw_reg_qeec_local_port_set(payload, local_port);
3928 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
3929 mlxsw_reg_qeec_ptps_set(payload, ptps);
3930}
3931
3932
3933
3934
3935
3936#define MLXSW_REG_QRWE_ID 0x400F
3937#define MLXSW_REG_QRWE_LEN 0x08
3938
3939MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN);
3940
3941
3942
3943
3944
3945
3946
3947MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8);
3948
3949
3950
3951
3952
3953MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1);
3954
3955
3956
3957
3958
3959MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1);
3960
3961static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port,
3962 bool rewrite_pcp, bool rewrite_dscp)
3963{
3964 MLXSW_REG_ZERO(qrwe, payload);
3965 mlxsw_reg_qrwe_local_port_set(payload, local_port);
3966 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp);
3967 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp);
3968}
3969
3970
3971
3972
3973
3974#define MLXSW_REG_QPDSM_ID 0x4011
3975#define MLXSW_REG_QPDSM_BASE_LEN 0x04
3976#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4
3977#define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16
3978#define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \
3979 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \
3980 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT)
3981
3982MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN);
3983
3984
3985
3986
3987
3988MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8);
3989
3990
3991
3992
3993
3994MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e,
3995 MLXSW_REG_QPDSM_BASE_LEN, 31, 1,
3996 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
3997
3998
3999
4000
4001
4002
4003MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp,
4004 MLXSW_REG_QPDSM_BASE_LEN, 24, 6,
4005 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4006
4007
4008
4009
4010
4011MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e,
4012 MLXSW_REG_QPDSM_BASE_LEN, 23, 1,
4013 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4014
4015
4016
4017
4018
4019
4020MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp,
4021 MLXSW_REG_QPDSM_BASE_LEN, 16, 6,
4022 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4023
4024
4025
4026
4027
4028MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e,
4029 MLXSW_REG_QPDSM_BASE_LEN, 15, 1,
4030 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4031
4032
4033
4034
4035
4036
4037MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp,
4038 MLXSW_REG_QPDSM_BASE_LEN, 8, 6,
4039 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false);
4040
4041static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port)
4042{
4043 MLXSW_REG_ZERO(qpdsm, payload);
4044 mlxsw_reg_qpdsm_local_port_set(payload, local_port);
4045}
4046
4047static inline void
4048mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp)
4049{
4050 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1);
4051 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp);
4052 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1);
4053 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp);
4054 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1);
4055 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
4056}
4057
4058
4059
4060
4061
4062
4063
4064
4065#define MLXSW_REG_QPDP_ID 0x4007
4066#define MLXSW_REG_QPDP_LEN 0x8
4067
4068MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
4069
4070
4071
4072
4073
4074MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8);
4075
4076
4077
4078
4079
4080MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
4081
4082static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port,
4083 u8 switch_prio)
4084{
4085 MLXSW_REG_ZERO(qpdp, payload);
4086 mlxsw_reg_qpdp_local_port_set(payload, local_port);
4087 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
4088}
4089
4090
4091
4092
4093
4094
4095#define MLXSW_REG_QPDPM_ID 0x4013
4096#define MLXSW_REG_QPDPM_BASE_LEN 0x4
4097#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2
4098#define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64
4099#define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \
4100 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \
4101 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT)
4102
4103MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN);
4104
4105
4106
4107
4108
4109MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8);
4110
4111
4112
4113
4114
4115
4116
4117MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1,
4118 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4119
4120
4121
4122
4123
4124MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio,
4125 MLXSW_REG_QPDPM_BASE_LEN, 0, 4,
4126 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4127
4128static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port)
4129{
4130 MLXSW_REG_ZERO(qpdpm, payload);
4131 mlxsw_reg_qpdpm_local_port_set(payload, local_port);
4132}
4133
4134static inline void
4135mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio)
4136{
4137 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1);
4138 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio);
4139}
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150#define MLXSW_REG_QTCTM_ID 0x401A
4151#define MLXSW_REG_QTCTM_LEN 0x08
4152
4153MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN);
4154
4155
4156
4157
4158
4159
4160MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8);
4161
4162
4163
4164
4165
4166
4167MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1);
4168
4169static inline void
4170mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc)
4171{
4172 MLXSW_REG_ZERO(qtctm, payload);
4173 mlxsw_reg_qtctm_local_port_set(payload, local_port);
4174 mlxsw_reg_qtctm_mc_set(payload, mc);
4175}
4176
4177
4178
4179
4180
4181
4182#define MLXSW_REG_QPSC_ID 0x401B
4183#define MLXSW_REG_QPSC_LEN 0x28
4184
4185MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
4186
4187enum mlxsw_reg_qpsc_port_speed {
4188 MLXSW_REG_QPSC_PORT_SPEED_100M,
4189 MLXSW_REG_QPSC_PORT_SPEED_1G,
4190 MLXSW_REG_QPSC_PORT_SPEED_10G,
4191 MLXSW_REG_QPSC_PORT_SPEED_25G,
4192};
4193
4194
4195
4196
4197
4198MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
4199
4200
4201
4202
4203
4204
4205
4206MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
4207
4208
4209
4210
4211
4212
4213
4214MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
4215
4216
4217
4218
4219
4220
4221MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
4222
4223
4224
4225
4226
4227
4228
4229MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
4230
4231
4232
4233
4234
4235MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
4236
4237
4238
4239
4240
4241
4242
4243MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
4264
4265static inline void
4266mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
4267 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
4268 u8 shaper_bs, u8 port_to_shaper_credits,
4269 int ing_timestamp_inc, int egr_timestamp_inc)
4270{
4271 MLXSW_REG_ZERO(qpsc, payload);
4272 mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
4273 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
4274 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
4275 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
4276 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
4277 mlxsw_reg_qpsc_ptsc_we_set(payload, true);
4278 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
4279 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
4280 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
4281}
4282
4283
4284
4285
4286
4287#define MLXSW_REG_PMLP_ID 0x5002
4288#define MLXSW_REG_PMLP_LEN 0x40
4289
4290MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
4291
4292
4293
4294
4295
4296
4297MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
4298
4299
4300
4301
4302
4303MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
4314
4315
4316
4317
4318
4319MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
4320
4321
4322
4323
4324
4325MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
4326
4327
4328
4329
4330
4331
4332MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
4333
4334static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
4335{
4336 MLXSW_REG_ZERO(pmlp, payload);
4337 mlxsw_reg_pmlp_local_port_set(payload, local_port);
4338}
4339
4340
4341
4342
4343
4344#define MLXSW_REG_PMTU_ID 0x5003
4345#define MLXSW_REG_PMTU_LEN 0x10
4346
4347MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
4348
4349
4350
4351
4352
4353MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
4354
4355
4356
4357
4358
4359
4360
4361
4362MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
4363
4364
4365
4366
4367
4368
4369
4370MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
4371
4372
4373
4374
4375
4376
4377
4378
4379MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
4380
4381static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
4382 u16 new_mtu)
4383{
4384 MLXSW_REG_ZERO(pmtu, payload);
4385 mlxsw_reg_pmtu_local_port_set(payload, local_port);
4386 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
4387 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
4388 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
4389}
4390
4391
4392
4393
4394
4395
4396
4397
4398#define MLXSW_REG_PTYS_ID 0x5004
4399#define MLXSW_REG_PTYS_LEN 0x40
4400
4401MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
4402
4403
4404
4405
4406
4407
4408
4409MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
4410
4411
4412
4413
4414
4415MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
4416
4417#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
4418#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
4419
4420
4421
4422
4423
4424
4425
4426
4427MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
4428
4429enum {
4430 MLXSW_REG_PTYS_AN_STATUS_NA,
4431 MLXSW_REG_PTYS_AN_STATUS_OK,
4432 MLXSW_REG_PTYS_AN_STATUS_FAIL,
4433};
4434
4435
4436
4437
4438
4439MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
4440
4441#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
4442#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
4443#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
4444#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
4445#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
4446#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
4447#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
4448#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
4449#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
4450#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
4451#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
4452#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15)
4453
4454
4455
4456
4457
4458MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
4459
4460#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
4461#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
4462#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
4463#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
4464#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
4465#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
4466#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
4467#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
4468#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
4469#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
4470#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
4471#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
4472#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
4473#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
4474#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
4475#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
4476#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
4477#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
4478#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
4479#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
4480#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
4481#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
4482#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
4483
4484
4485
4486
4487
4488MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
4489
4490
4491
4492
4493
4494MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
4495
4496#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
4497#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
4498#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
4499#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
4500#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
4501#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
4502
4503
4504
4505
4506
4507MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
4508
4509
4510
4511
4512
4513MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
4514
4515
4516
4517
4518
4519MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
4520
4521
4522
4523
4524
4525MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
4526
4527
4528
4529
4530
4531MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
4532
4533
4534
4535
4536
4537MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
4538
4539
4540
4541
4542
4543MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
4544
4545
4546
4547
4548
4549MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
4550
4551
4552
4553
4554
4555MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
4556
4557enum mlxsw_reg_ptys_connector_type {
4558 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
4559 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
4560 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
4561 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
4562 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
4563 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
4564 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
4565 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
4566 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
4567};
4568
4569
4570
4571
4572
4573MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
4574
4575static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
4576 u32 proto_admin, bool autoneg)
4577{
4578 MLXSW_REG_ZERO(ptys, payload);
4579 mlxsw_reg_ptys_local_port_set(payload, local_port);
4580 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4581 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
4582 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4583}
4584
4585static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
4586 u32 proto_admin, bool autoneg)
4587{
4588 MLXSW_REG_ZERO(ptys, payload);
4589 mlxsw_reg_ptys_local_port_set(payload, local_port);
4590 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
4591 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
4592 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
4593}
4594
4595static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
4596 u32 *p_eth_proto_cap,
4597 u32 *p_eth_proto_admin,
4598 u32 *p_eth_proto_oper)
4599{
4600 if (p_eth_proto_cap)
4601 *p_eth_proto_cap =
4602 mlxsw_reg_ptys_eth_proto_cap_get(payload);
4603 if (p_eth_proto_admin)
4604 *p_eth_proto_admin =
4605 mlxsw_reg_ptys_eth_proto_admin_get(payload);
4606 if (p_eth_proto_oper)
4607 *p_eth_proto_oper =
4608 mlxsw_reg_ptys_eth_proto_oper_get(payload);
4609}
4610
4611static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
4612 u32 *p_eth_proto_cap,
4613 u32 *p_eth_proto_admin,
4614 u32 *p_eth_proto_oper)
4615{
4616 if (p_eth_proto_cap)
4617 *p_eth_proto_cap =
4618 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
4619 if (p_eth_proto_admin)
4620 *p_eth_proto_admin =
4621 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
4622 if (p_eth_proto_oper)
4623 *p_eth_proto_oper =
4624 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
4625}
4626
4627static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
4628 u16 proto_admin, u16 link_width)
4629{
4630 MLXSW_REG_ZERO(ptys, payload);
4631 mlxsw_reg_ptys_local_port_set(payload, local_port);
4632 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
4633 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
4634 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
4635}
4636
4637static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
4638 u16 *p_ib_link_width_cap,
4639 u16 *p_ib_proto_oper,
4640 u16 *p_ib_link_width_oper)
4641{
4642 if (p_ib_proto_cap)
4643 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
4644 if (p_ib_link_width_cap)
4645 *p_ib_link_width_cap =
4646 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
4647 if (p_ib_proto_oper)
4648 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
4649 if (p_ib_link_width_oper)
4650 *p_ib_link_width_oper =
4651 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
4652}
4653
4654
4655
4656
4657
4658#define MLXSW_REG_PPAD_ID 0x5005
4659#define MLXSW_REG_PPAD_LEN 0x10
4660
4661MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
4662
4663
4664
4665
4666
4667
4668
4669MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
4670
4671
4672
4673
4674
4675MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
4676
4677
4678
4679
4680
4681
4682MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
4683
4684static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
4685 u8 local_port)
4686{
4687 MLXSW_REG_ZERO(ppad, payload);
4688 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
4689 mlxsw_reg_ppad_local_port_set(payload, local_port);
4690}
4691
4692
4693
4694
4695
4696#define MLXSW_REG_PAOS_ID 0x5006
4697#define MLXSW_REG_PAOS_LEN 0x10
4698
4699MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
4700
4701
4702
4703
4704
4705
4706
4707
4708MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
4709
4710
4711
4712
4713
4714MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
4736
4737
4738
4739
4740
4741MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
4742
4743
4744
4745
4746
4747
4748MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
4749
4750
4751
4752
4753
4754
4755
4756
4757MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
4758
4759static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
4760 enum mlxsw_port_admin_status status)
4761{
4762 MLXSW_REG_ZERO(paos, payload);
4763 mlxsw_reg_paos_swid_set(payload, 0);
4764 mlxsw_reg_paos_local_port_set(payload, local_port);
4765 mlxsw_reg_paos_admin_status_set(payload, status);
4766 mlxsw_reg_paos_oper_status_set(payload, 0);
4767 mlxsw_reg_paos_ase_set(payload, 1);
4768 mlxsw_reg_paos_ee_set(payload, 1);
4769 mlxsw_reg_paos_e_set(payload, 1);
4770}
4771
4772
4773
4774
4775
4776#define MLXSW_REG_PFCC_ID 0x5007
4777#define MLXSW_REG_PFCC_LEN 0x20
4778
4779MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
4780
4781
4782
4783
4784
4785MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
4786
4787
4788
4789
4790
4791
4792
4793MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
4794
4795
4796
4797
4798
4799
4800
4801
4802MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
4803
4804
4805
4806
4807
4808
4809
4810
4811MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
4824
4825
4826
4827
4828
4829
4830MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
4831
4832
4833
4834
4835
4836
4837MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
4838
4839
4840
4841
4842
4843
4844
4845MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
4846
4847
4848
4849
4850
4851
4852
4853MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
4866
4867
4868
4869
4870
4871
4872
4873MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
4874
4875
4876
4877
4878
4879
4880
4881MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
4882
4883
4884
4885
4886
4887
4888
4889
4890MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
4891
4892#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
4893
4894static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
4895{
4896 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4897 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
4898 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
4899 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
4900}
4901
4902static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
4903{
4904 MLXSW_REG_ZERO(pfcc, payload);
4905 mlxsw_reg_pfcc_local_port_set(payload, local_port);
4906}
4907
4908
4909
4910
4911
4912#define MLXSW_REG_PPCNT_ID 0x5008
4913#define MLXSW_REG_PPCNT_LEN 0x100
4914#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
4915
4916MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
4928
4929
4930
4931
4932
4933
4934
4935MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
4936
4937
4938
4939
4940
4941
4942
4943MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
4944
4945enum mlxsw_reg_ppcnt_grp {
4946 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
4947 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4948 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
4949 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4950 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
4951 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4952 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4953 MLXSW_REG_PPCNT_TC_CNT = 0x11,
4954 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
4955};
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
4973
4974MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
4975
4976
4977
4978
4979
4980
4981
4982MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
4983
4984
4985
4986
4987
4988
4989
4990
4991
4992MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
4993
4994
4995
4996
4997
4998
4999MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
5000 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5001
5002
5003
5004
5005MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
5006 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5007
5008
5009
5010
5011MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
5012 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5013
5014
5015
5016
5017MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
5018 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5019
5020
5021
5022
5023MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
5024 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5025
5026
5027
5028
5029MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
5030 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5031
5032
5033
5034
5035MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
5036 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5037
5038
5039
5040
5041MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
5042 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5043
5044
5045
5046
5047MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
5048 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5049
5050
5051
5052
5053MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
5054 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5055
5056
5057
5058
5059MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
5060 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5061
5062
5063
5064
5065MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
5066 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5067
5068
5069
5070
5071MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
5072 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5073
5074
5075
5076
5077MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
5078 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5079
5080
5081
5082
5083MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
5084 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5085
5086
5087
5088
5089MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
5090 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5091
5092
5093
5094
5095MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
5096 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5097
5098
5099
5100
5101MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
5102 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5103
5104
5105
5106
5107MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
5108 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5109
5110
5111
5112
5113
5114
5115MLXSW_ITEM64(reg, ppcnt, if_in_discards,
5116 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5117
5118
5119
5120
5121MLXSW_ITEM64(reg, ppcnt, if_out_discards,
5122 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5123
5124
5125
5126
5127MLXSW_ITEM64(reg, ppcnt, if_out_errors,
5128 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5129
5130
5131
5132
5133
5134
5135MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
5136 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5137
5138
5139
5140
5141MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
5142 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
5143
5144
5145
5146
5147MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
5148 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5149
5150
5151
5152
5153MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets,
5154 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5155
5156
5157
5158
5159MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets,
5160 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5161
5162
5163
5164
5165MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets,
5166 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5167
5168
5169
5170
5171MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets,
5172 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5173
5174
5175
5176
5177MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets,
5178 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
5179
5180
5181
5182
5183MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets,
5184 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
5185
5186
5187
5188
5189MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets,
5190 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
5191
5192
5193
5194
5195MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets,
5196 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
5197
5198
5199
5200
5201MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets,
5202 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64);
5203
5204
5205
5206
5207MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
5208 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
5209
5210
5211
5212
5213
5214
5215MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
5216 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5217
5218
5219
5220
5221MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
5222 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5223
5224
5225
5226
5227MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
5228 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5229
5230
5231
5232
5233MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
5234 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5235
5236
5237
5238
5239
5240
5241MLXSW_ITEM64(reg, ppcnt, ecn_marked,
5242 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5243
5244
5245
5246
5247
5248
5249MLXSW_ITEM64(reg, ppcnt, ingress_general,
5250 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5251
5252
5253
5254
5255MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
5256 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5257
5258
5259
5260
5261MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
5262 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
5263
5264
5265
5266
5267MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
5268 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
5269
5270
5271
5272
5273MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
5274 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5275
5276
5277
5278
5279MLXSW_ITEM64(reg, ppcnt, loopback_filter,
5280 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5281
5282
5283
5284
5285MLXSW_ITEM64(reg, ppcnt, egress_general,
5286 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
5287
5288
5289
5290
5291MLXSW_ITEM64(reg, ppcnt, egress_hoq,
5292 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
5293
5294
5295
5296
5297MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
5298 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5299
5300
5301
5302
5303MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
5304 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5305
5306
5307
5308
5309MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
5310 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5311
5312
5313
5314
5315MLXSW_ITEM64(reg, ppcnt, egress_sll,
5316 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5317
5318
5319
5320
5321
5322
5323MLXSW_ITEM64(reg, ppcnt, rx_octets,
5324 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5325
5326
5327
5328
5329MLXSW_ITEM64(reg, ppcnt, rx_frames,
5330 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
5331
5332
5333
5334
5335MLXSW_ITEM64(reg, ppcnt, tx_octets,
5336 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
5337
5338
5339
5340
5341MLXSW_ITEM64(reg, ppcnt, tx_frames,
5342 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
5343
5344
5345
5346
5347MLXSW_ITEM64(reg, ppcnt, rx_pause,
5348 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
5349
5350
5351
5352
5353MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
5354 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
5355
5356
5357
5358
5359MLXSW_ITEM64(reg, ppcnt, tx_pause,
5360 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
5361
5362
5363
5364
5365MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
5366 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
5367
5368
5369
5370
5371MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
5372 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
5373
5374
5375
5376
5377
5378
5379
5380
5381
5382MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
5383 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5384
5385
5386
5387
5388
5389
5390MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
5391 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
5392
5393
5394
5395
5396
5397
5398MLXSW_ITEM64(reg, ppcnt, wred_discard,
5399 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
5400
5401static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
5402 enum mlxsw_reg_ppcnt_grp grp,
5403 u8 prio_tc)
5404{
5405 MLXSW_REG_ZERO(ppcnt, payload);
5406 mlxsw_reg_ppcnt_swid_set(payload, 0);
5407 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
5408 mlxsw_reg_ppcnt_pnat_set(payload, 0);
5409 mlxsw_reg_ppcnt_grp_set(payload, grp);
5410 mlxsw_reg_ppcnt_clr_set(payload, 0);
5411 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
5412}
5413
5414
5415
5416
5417
5418#define MLXSW_REG_PLIB_ID 0x500A
5419#define MLXSW_REG_PLIB_LEN 0x10
5420
5421MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
5422
5423
5424
5425
5426
5427MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
5428
5429
5430
5431
5432
5433MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
5434
5435
5436
5437
5438
5439#define MLXSW_REG_PPTB_ID 0x500B
5440#define MLXSW_REG_PPTB_LEN 0x10
5441
5442MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
5443
5444enum {
5445 MLXSW_REG_PPTB_MM_UM,
5446 MLXSW_REG_PPTB_MM_UNICAST,
5447 MLXSW_REG_PPTB_MM_MULTICAST,
5448};
5449
5450
5451
5452
5453
5454
5455
5456
5457
5458
5459MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
5460
5461
5462
5463
5464
5465MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
5466
5467
5468
5469
5470
5471MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
5472
5473
5474
5475
5476
5477
5478MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
5479
5480
5481
5482
5483
5484
5485MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
5486
5487
5488
5489
5490
5491
5492MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
5493
5494
5495
5496
5497
5498
5499
5500
5501MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
5502
5503
5504
5505
5506
5507
5508MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
5509
5510#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
5511
5512static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
5513{
5514 MLXSW_REG_ZERO(pptb, payload);
5515 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
5516 mlxsw_reg_pptb_local_port_set(payload, local_port);
5517 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5518 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
5519}
5520
5521static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
5522 u8 buff)
5523{
5524 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
5525 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
5526}
5527
5528
5529
5530
5531
5532
5533#define MLXSW_REG_PBMC_ID 0x500C
5534#define MLXSW_REG_PBMC_LEN 0x6C
5535
5536MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
5537
5538
5539
5540
5541
5542MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
5543
5544
5545
5546
5547
5548
5549MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
5550
5551
5552
5553
5554
5555
5556
5557MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
5558
5559#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
5560
5561
5562
5563
5564
5565
5566
5567MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
5568
5569
5570
5571
5572
5573
5574
5575
5576MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
5577
5578
5579
5580
5581
5582
5583MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
5595 0x08, 0x04, false);
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605
5606MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
5607 0x08, 0x04, false);
5608
5609static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
5610 u16 xoff_timer_value, u16 xoff_refresh)
5611{
5612 MLXSW_REG_ZERO(pbmc, payload);
5613 mlxsw_reg_pbmc_local_port_set(payload, local_port);
5614 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
5615 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
5616}
5617
5618static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
5619 int buf_index,
5620 u16 size)
5621{
5622 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
5623 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5624 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5625}
5626
5627static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
5628 int buf_index, u16 size,
5629 u16 threshold)
5630{
5631 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
5632 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
5633 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
5634 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
5635 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
5636}
5637
5638
5639
5640
5641
5642
5643#define MLXSW_REG_PSPA_ID 0x500D
5644#define MLXSW_REG_PSPA_LEN 0x8
5645
5646MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
5647
5648
5649
5650
5651
5652MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
5653
5654
5655
5656
5657
5658MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
5659
5660
5661
5662
5663
5664
5665MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
5666
5667static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
5668{
5669 MLXSW_REG_ZERO(pspa, payload);
5670 mlxsw_reg_pspa_swid_set(payload, swid);
5671 mlxsw_reg_pspa_local_port_set(payload, local_port);
5672 mlxsw_reg_pspa_sub_port_set(payload, 0);
5673}
5674
5675
5676
5677
5678
5679#define MLXSW_REG_PMAOS_ID 0x5012
5680#define MLXSW_REG_PMAOS_LEN 0x10
5681
5682MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN);
5683
5684
5685
5686
5687
5688MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);
5689
5690
5691
5692
5693
5694MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);
5695
5696
5697
5698
5699
5700
5701
5702MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
5703
5704
5705
5706
5707
5708
5709
5710MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
5711
5712enum mlxsw_reg_pmaos_e {
5713 MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT,
5714 MLXSW_REG_PMAOS_E_GENERATE_EVENT,
5715 MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT,
5716};
5717
5718
5719
5720
5721
5722MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);
5723
5724static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module,
5725 enum mlxsw_reg_pmaos_e e)
5726{
5727 MLXSW_REG_ZERO(pmaos, payload);
5728 mlxsw_reg_pmaos_module_set(payload, module);
5729 mlxsw_reg_pmaos_e_set(payload, e);
5730 mlxsw_reg_pmaos_ee_set(payload, true);
5731}
5732
5733
5734
5735
5736
5737#define MLXSW_REG_PPLR_ID 0x5018
5738#define MLXSW_REG_PPLR_LEN 0x8
5739
5740MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
5741
5742
5743
5744
5745
5746MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
5747
5748
5749
5750
5751#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
5752
5753
5754
5755
5756
5757MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
5758
5759static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
5760 bool phy_local)
5761{
5762 MLXSW_REG_ZERO(pplr, payload);
5763 mlxsw_reg_pplr_local_port_set(payload, local_port);
5764 mlxsw_reg_pplr_lb_en_set(payload,
5765 phy_local ?
5766 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
5767}
5768
5769
5770
5771
5772
5773
5774
5775
5776
5777#define MLXSW_REG_PMPE_ID 0x5024
5778#define MLXSW_REG_PMPE_LEN 0x10
5779
5780MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN);
5781
5782
5783
5784
5785
5786MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);
5787
5788
5789
5790
5791
5792MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);
5793
5794enum mlxsw_reg_pmpe_module_status {
5795 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1,
5796 MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED,
5797 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR,
5798 MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED,
5799};
5800
5801
5802
5803
5804
5805MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);
5806
5807
5808
5809
5810
5811MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);
5812
5813
5814
5815
5816
5817#define MLXSW_REG_PDDR_ID 0x5031
5818#define MLXSW_REG_PDDR_LEN 0x100
5819
5820MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN);
5821
5822
5823
5824
5825
5826MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8);
5827
5828enum mlxsw_reg_pddr_page_select {
5829 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1,
5830};
5831
5832
5833
5834
5835
5836MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);
5837
5838enum mlxsw_reg_pddr_trblsh_group_opcode {
5839
5840 MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR,
5841};
5842
5843
5844
5845
5846
5847MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
5848
5849
5850
5851
5852
5853MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
5854
5855static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port,
5856 u8 page_select)
5857{
5858 MLXSW_REG_ZERO(pddr, payload);
5859 mlxsw_reg_pddr_local_port_set(payload, local_port);
5860 mlxsw_reg_pddr_page_select_set(payload, page_select);
5861}
5862
5863
5864
5865
5866
5867#define MLXSW_REG_PMTM_ID 0x5067
5868#define MLXSW_REG_PMTM_LEN 0x10
5869
5870MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);
5871
5872
5873
5874
5875
5876MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
5877
5878enum mlxsw_reg_pmtm_module_type {
5879
5880 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X,
5881
5882 MLXSW_REG_PMTM_MODULE_TYPE_QSFP,
5883
5884 MLXSW_REG_PMTM_MODULE_TYPE_SFP,
5885
5886 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4,
5887
5888 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8,
5889
5890 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10,
5891
5892 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X,
5893
5894 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X,
5895
5896 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,
5897
5898 MLXSW_REG_PMTM_MODULE_TYPE_OSFP,
5899
5900 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD,
5901
5902 MLXSW_REG_PMTM_MODULE_TYPE_DSFP,
5903
5904 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X,
5905};
5906
5907
5908
5909
5910
5911MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4);
5912
5913static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module)
5914{
5915 MLXSW_REG_ZERO(pmtm, payload);
5916 mlxsw_reg_pmtm_module_set(payload, module);
5917}
5918
5919static inline void
5920mlxsw_reg_pmtm_unpack(char *payload,
5921 enum mlxsw_reg_pmtm_module_type *module_type)
5922{
5923 *module_type = mlxsw_reg_pmtm_module_type_get(payload);
5924}
5925
5926
5927
5928
5929
5930#define MLXSW_REG_HTGT_ID 0x7002
5931#define MLXSW_REG_HTGT_LEN 0x20
5932
5933MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
5934
5935
5936
5937
5938
5939MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
5940
5941#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0
5942
5943
5944
5945
5946
5947MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
5948
5949enum mlxsw_reg_htgt_trap_group {
5950 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
5951 MLXSW_REG_HTGT_TRAP_GROUP_MFDE,
5952 MLXSW_REG_HTGT_TRAP_GROUP_MTWE,
5953 MLXSW_REG_HTGT_TRAP_GROUP_PMPE,
5954 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
5955 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
5956 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
5957 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING,
5958 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
5959 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
5960 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
5961 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
5962 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY,
5963 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
5964 MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE,
5965 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
5966 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
5967 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
5968 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,
5969 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
5970 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
5971 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
5972 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
5973 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,
5974 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,
5975 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,
5976 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,
5977 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,
5978 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
5979 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,
5980 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS,
5981 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,
5982 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,
5983 MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS,
5984
5985 __MLXSW_REG_HTGT_TRAP_GROUP_MAX,
5986 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
5987};
5988
5989
5990
5991
5992
5993
5994
5995MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
5996
5997enum {
5998 MLXSW_REG_HTGT_POLICER_DISABLE,
5999 MLXSW_REG_HTGT_POLICER_ENABLE,
6000};
6001
6002
6003
6004
6005
6006MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
6007
6008#define MLXSW_REG_HTGT_INVALID_POLICER 0xff
6009
6010
6011
6012
6013
6014MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
6015
6016#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
6017
6018
6019
6020
6021
6022
6023
6024
6025
6026
6027MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
6028
6029
6030
6031
6032
6033MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
6034
6035#define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
6036
6037
6038
6039
6040
6041
6042
6043
6044
6045
6046
6047
6048MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
6049
6050#define MLXSW_REG_HTGT_DEFAULT_TC 7
6051
6052
6053
6054
6055
6056MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
6057
6058enum mlxsw_reg_htgt_local_path_rdq {
6059 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
6060 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
6061 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
6062 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
6063};
6064
6065
6066
6067
6068MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
6069
6070static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
6071 u8 priority, u8 tc)
6072{
6073 MLXSW_REG_ZERO(htgt, payload);
6074
6075 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
6076 mlxsw_reg_htgt_pide_set(payload,
6077 MLXSW_REG_HTGT_POLICER_DISABLE);
6078 } else {
6079 mlxsw_reg_htgt_pide_set(payload,
6080 MLXSW_REG_HTGT_POLICER_ENABLE);
6081 mlxsw_reg_htgt_pid_set(payload, policer_id);
6082 }
6083
6084 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
6085 mlxsw_reg_htgt_trap_group_set(payload, group);
6086 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
6087 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
6088 mlxsw_reg_htgt_priority_set(payload, priority);
6089 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
6090 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
6091}
6092
6093
6094
6095
6096
6097#define MLXSW_REG_HPKT_ID 0x7003
6098#define MLXSW_REG_HPKT_LEN 0x10
6099
6100MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
6101
6102enum {
6103 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
6104 MLXSW_REG_HPKT_ACK_REQUIRED,
6105};
6106
6107
6108
6109
6110
6111
6112
6113
6114
6115MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
6116
6117enum mlxsw_reg_hpkt_action {
6118 MLXSW_REG_HPKT_ACTION_FORWARD,
6119 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
6120 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
6121 MLXSW_REG_HPKT_ACTION_DISCARD,
6122 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
6123 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
6124 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
6125 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
6126};
6127
6128
6129
6130
6131
6132
6133
6134
6135
6136
6137
6138
6139
6140
6141
6142
6143MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
6144
6145
6146
6147
6148
6149MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
6150
6151
6152
6153
6154
6155
6156
6157
6158MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
6159
6160enum {
6161 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
6162 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
6163 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
6164};
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
6175
6176static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
6177 enum mlxsw_reg_htgt_trap_group trap_group,
6178 bool is_ctrl)
6179{
6180 MLXSW_REG_ZERO(hpkt, payload);
6181 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
6182 mlxsw_reg_hpkt_action_set(payload, action);
6183 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
6184 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
6185 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
6186 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
6187 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
6188}
6189
6190
6191
6192
6193
6194#define MLXSW_REG_RGCR_ID 0x8001
6195#define MLXSW_REG_RGCR_LEN 0x28
6196
6197MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
6198
6199
6200
6201
6202
6203MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
6204
6205
6206
6207
6208
6209MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
6210
6211
6212
6213
6214
6215
6216MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
6227
6228
6229
6230
6231
6232
6233
6234
6235
6236
6237MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
6254
6255static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
6256 bool ipv6_en)
6257{
6258 MLXSW_REG_ZERO(rgcr, payload);
6259 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
6260 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
6261}
6262
6263
6264
6265
6266
6267#define MLXSW_REG_RITR_ID 0x8002
6268#define MLXSW_REG_RITR_LEN 0x40
6269
6270MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
6271
6272
6273
6274
6275
6276MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
6277
6278
6279
6280
6281
6282
6283MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
6284
6285
6286
6287
6288
6289
6290MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
6291
6292
6293
6294
6295
6296MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
6297
6298
6299
6300
6301
6302MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
6303
6304enum mlxsw_reg_ritr_if_type {
6305
6306 MLXSW_REG_RITR_VLAN_IF,
6307
6308 MLXSW_REG_RITR_FID_IF,
6309
6310 MLXSW_REG_RITR_SP_IF,
6311
6312 MLXSW_REG_RITR_LOOPBACK_IF,
6313};
6314
6315
6316
6317
6318
6319MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
6320
6321enum {
6322 MLXSW_REG_RITR_RIF_CREATE,
6323 MLXSW_REG_RITR_RIF_DEL,
6324};
6325
6326
6327
6328
6329
6330
6331
6332
6333
6334
6335MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
6336
6337
6338
6339
6340
6341MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
6342
6343
6344
6345
6346
6347
6348
6349
6350MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
6351
6352
6353
6354
6355
6356
6357
6358
6359MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
6360
6361
6362
6363
6364
6365
6366
6367MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
6368
6369
6370
6371
6372
6373
6374
6375MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
6376
6377
6378
6379
6380
6381
6382
6383
6384MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
6385
6386
6387
6388
6389
6390MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
6391
6392
6393
6394
6395
6396MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
6397
6398
6399
6400
6401
6402MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
6403
6404
6405
6406
6407
6408
6409MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
6410
6411
6412
6413
6414
6415
6416MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8);
6417
6418
6419
6420
6421
6422
6423MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8);
6424
6425
6426
6427
6428
6429
6430
6431MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
6432
6433
6434
6435
6436
6437
6438
6439
6440MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
6441
6442static inline void mlxsw_reg_ritr_fid_set(char *payload,
6443 enum mlxsw_reg_ritr_if_type rif_type,
6444 u16 fid)
6445{
6446 if (rif_type == MLXSW_REG_RITR_FID_IF)
6447 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
6448 else
6449 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
6450}
6451
6452
6453
6454
6455
6456
6457
6458
6459MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
6460
6461
6462
6463
6464
6465
6466MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
6467
6468
6469
6470
6471
6472MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
6473
6474
6475
6476enum mlxsw_reg_ritr_loopback_protocol {
6477
6478 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
6479
6480 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
6481
6482 MLXSW_REG_RITR_LOOPBACK_GENERIC,
6483};
6484
6485
6486
6487
6488MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
6489
6490enum mlxsw_reg_ritr_loopback_ipip_type {
6491
6492 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
6493
6494 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
6495
6496 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
6497};
6498
6499
6500
6501
6502
6503MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
6504
6505enum mlxsw_reg_ritr_loopback_ipip_options {
6506
6507 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
6508};
6509
6510
6511
6512
6513MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
6514
6515
6516
6517
6518
6519
6520
6521MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
6522
6523
6524
6525
6526
6527
6528MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
6529
6530
6531
6532
6533
6534MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
6535MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
6536
6537
6538
6539
6540
6541
6542MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
6543
6544
6545enum mlxsw_reg_ritr_counter_set_type {
6546
6547 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
6548
6549
6550
6551
6552
6553
6554 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
6555};
6556
6557
6558
6559
6560
6561MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
6562
6563
6564
6565
6566
6567MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
6568
6569
6570
6571
6572
6573MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
6574
6575
6576
6577
6578
6579MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
6580
6581static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
6582 bool enable, bool egress)
6583{
6584 enum mlxsw_reg_ritr_counter_set_type set_type;
6585
6586 if (enable)
6587 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
6588 else
6589 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
6590 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
6591
6592 if (egress)
6593 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
6594 else
6595 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
6596}
6597
6598static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
6599{
6600 MLXSW_REG_ZERO(ritr, payload);
6601 mlxsw_reg_ritr_rif_set(payload, rif);
6602}
6603
6604static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
6605 u16 system_port, u16 vid)
6606{
6607 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
6608 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
6609 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
6610}
6611
6612static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
6613 enum mlxsw_reg_ritr_if_type type,
6614 u16 rif, u16 vr_id, u16 mtu)
6615{
6616 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
6617
6618 MLXSW_REG_ZERO(ritr, payload);
6619 mlxsw_reg_ritr_enable_set(payload, enable);
6620 mlxsw_reg_ritr_ipv4_set(payload, 1);
6621 mlxsw_reg_ritr_ipv6_set(payload, 1);
6622 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
6623 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
6624 mlxsw_reg_ritr_type_set(payload, type);
6625 mlxsw_reg_ritr_op_set(payload, op);
6626 mlxsw_reg_ritr_rif_set(payload, rif);
6627 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
6628 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
6629 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
6630 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
6631 mlxsw_reg_ritr_lb_en_set(payload, 1);
6632 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
6633 mlxsw_reg_ritr_mtu_set(payload, mtu);
6634}
6635
6636static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
6637{
6638 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
6639}
6640
6641static inline void
6642mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
6643 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6644 enum mlxsw_reg_ritr_loopback_ipip_options options,
6645 u16 uvr_id, u16 underlay_rif, u32 gre_key)
6646{
6647 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
6648 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
6649 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
6650 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
6651 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
6652}
6653
6654static inline void
6655mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
6656 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
6657 enum mlxsw_reg_ritr_loopback_ipip_options options,
6658 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
6659{
6660 mlxsw_reg_ritr_loopback_protocol_set(payload,
6661 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
6662 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
6663 uvr_id, underlay_rif, gre_key);
6664 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
6665}
6666
6667
6668
6669
6670
6671#define MLXSW_REG_RTAR_ID 0x8004
6672#define MLXSW_REG_RTAR_LEN 0x20
6673
6674MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
6675
6676enum mlxsw_reg_rtar_op {
6677 MLXSW_REG_RTAR_OP_ALLOCATE,
6678 MLXSW_REG_RTAR_OP_RESIZE,
6679 MLXSW_REG_RTAR_OP_DEALLOCATE,
6680};
6681
6682
6683
6684
6685MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
6686
6687enum mlxsw_reg_rtar_key_type {
6688 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
6689 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
6690};
6691
6692
6693
6694
6695
6696MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
6697
6698
6699
6700
6701
6702
6703
6704
6705MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
6706
6707static inline void mlxsw_reg_rtar_pack(char *payload,
6708 enum mlxsw_reg_rtar_op op,
6709 enum mlxsw_reg_rtar_key_type key_type,
6710 u16 region_size)
6711{
6712 MLXSW_REG_ZERO(rtar, payload);
6713 mlxsw_reg_rtar_op_set(payload, op);
6714 mlxsw_reg_rtar_key_type_set(payload, key_type);
6715 mlxsw_reg_rtar_region_size_set(payload, region_size);
6716}
6717
6718
6719
6720
6721
6722
6723#define MLXSW_REG_RATR_ID 0x8008
6724#define MLXSW_REG_RATR_LEN 0x2C
6725
6726MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
6727
6728enum mlxsw_reg_ratr_op {
6729
6730 MLXSW_REG_RATR_OP_QUERY_READ = 0,
6731
6732 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
6733
6734 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
6735
6736
6737
6738
6739
6740
6741 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
6742};
6743
6744
6745
6746
6747
6748
6749
6750MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
6751
6752
6753
6754
6755
6756
6757
6758
6759
6760
6761
6762
6763
6764MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
6765
6766
6767
6768
6769
6770
6771MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
6772
6773enum mlxsw_reg_ratr_type {
6774
6775 MLXSW_REG_RATR_TYPE_ETHERNET,
6776
6777
6778
6779 MLXSW_REG_RATR_TYPE_IPOIB_UC,
6780
6781
6782
6783
6784 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
6785
6786
6787
6788 MLXSW_REG_RATR_TYPE_IPOIB_MC,
6789
6790
6791
6792 MLXSW_REG_RATR_TYPE_MPLS,
6793
6794
6795
6796 MLXSW_REG_RATR_TYPE_IPIP,
6797};
6798
6799
6800
6801
6802
6803MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
6804
6805
6806
6807
6808
6809
6810
6811
6812MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
6813
6814
6815
6816
6817
6818MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
6819
6820enum mlxsw_reg_ratr_trap_action {
6821 MLXSW_REG_RATR_TRAP_ACTION_NOP,
6822 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
6823 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
6824 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
6825 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
6826};
6827
6828
6829
6830
6831
6832MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
6833
6834
6835
6836
6837
6838MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
6839
6840enum mlxsw_reg_ratr_trap_id {
6841 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
6842 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
6843};
6844
6845
6846
6847
6848
6849
6850
6851MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
6852
6853
6854
6855
6856
6857MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
6858
6859enum mlxsw_reg_ratr_ipip_type {
6860
6861 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
6862
6863 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
6864};
6865
6866
6867
6868
6869
6870
6871MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
6872
6873
6874
6875
6876
6877
6878MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
6879
6880
6881
6882
6883
6884
6885MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
6886
6887enum mlxsw_reg_flow_counter_set_type {
6888
6889 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
6890
6891 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
6892
6893 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
6894};
6895
6896
6897
6898
6899
6900MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
6901
6902
6903
6904
6905
6906MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
6907
6908static inline void
6909mlxsw_reg_ratr_pack(char *payload,
6910 enum mlxsw_reg_ratr_op op, bool valid,
6911 enum mlxsw_reg_ratr_type type,
6912 u32 adjacency_index, u16 egress_rif)
6913{
6914 MLXSW_REG_ZERO(ratr, payload);
6915 mlxsw_reg_ratr_op_set(payload, op);
6916 mlxsw_reg_ratr_v_set(payload, valid);
6917 mlxsw_reg_ratr_type_set(payload, type);
6918 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
6919 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
6920 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
6921}
6922
6923static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
6924 const char *dest_mac)
6925{
6926 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
6927}
6928
6929static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
6930{
6931 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
6932 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
6933}
6934
6935static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
6936 bool counter_enable)
6937{
6938 enum mlxsw_reg_flow_counter_set_type set_type;
6939
6940 if (counter_enable)
6941 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
6942 else
6943 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
6944
6945 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
6946 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
6947}
6948
6949
6950
6951
6952
6953#define MLXSW_REG_RDPM_ID 0x8009
6954#define MLXSW_REG_RDPM_BASE_LEN 0x00
6955#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
6956#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
6957#define MLXSW_REG_RDPM_LEN 0x40
6958#define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
6959 MLXSW_REG_RDPM_LEN - \
6960 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
6961
6962MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
6963
6964
6965
6966
6967
6968MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
6969 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6970
6971
6972
6973
6974
6975MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
6976 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
6977
6978static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
6979 u8 prio)
6980{
6981 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
6982 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
6983}
6984
6985
6986
6987
6988
6989#define MLXSW_REG_RICNT_ID 0x800B
6990#define MLXSW_REG_RICNT_LEN 0x100
6991
6992MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
6993
6994
6995
6996
6997
6998MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
6999
7000enum mlxsw_reg_ricnt_counter_set_type {
7001
7002 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
7003
7004
7005
7006
7007
7008
7009 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
7010};
7011
7012
7013
7014
7015
7016MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
7017
7018enum mlxsw_reg_ricnt_opcode {
7019
7020 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
7021
7022
7023
7024 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
7025};
7026
7027
7028
7029
7030
7031MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
7032
7033
7034
7035
7036
7037MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
7038
7039
7040
7041
7042
7043MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
7044
7045
7046
7047
7048
7049MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
7050
7051
7052
7053
7054
7055
7056MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
7057
7058
7059
7060
7061
7062
7063MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
7064
7065
7066
7067
7068
7069
7070MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
7071
7072
7073
7074
7075
7076MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
7077
7078
7079
7080
7081
7082MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
7083
7084
7085
7086
7087
7088
7089MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
7090
7091
7092
7093
7094
7095
7096MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
7097
7098static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
7099 enum mlxsw_reg_ricnt_opcode op)
7100{
7101 MLXSW_REG_ZERO(ricnt, payload);
7102 mlxsw_reg_ricnt_op_set(payload, op);
7103 mlxsw_reg_ricnt_counter_index_set(payload, index);
7104 mlxsw_reg_ricnt_counter_set_type_set(payload,
7105 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
7106}
7107
7108
7109
7110
7111
7112#define MLXSW_REG_RRCR_ID 0x800F
7113#define MLXSW_REG_RRCR_LEN 0x24
7114
7115MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
7116
7117enum mlxsw_reg_rrcr_op {
7118
7119 MLXSW_REG_RRCR_OP_MOVE,
7120
7121 MLXSW_REG_RRCR_OP_COPY,
7122};
7123
7124
7125
7126
7127MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
7128
7129
7130
7131
7132
7133MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
7134
7135
7136
7137
7138
7139MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
7140
7141
7142
7143
7144
7145
7146MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
7147
7148
7149
7150
7151
7152MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
7153
7154static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
7155 u16 offset, u16 size,
7156 enum mlxsw_reg_rtar_key_type table_id,
7157 u16 dest_offset)
7158{
7159 MLXSW_REG_ZERO(rrcr, payload);
7160 mlxsw_reg_rrcr_op_set(payload, op);
7161 mlxsw_reg_rrcr_offset_set(payload, offset);
7162 mlxsw_reg_rrcr_size_set(payload, size);
7163 mlxsw_reg_rrcr_table_id_set(payload, table_id);
7164 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
7165}
7166
7167
7168
7169
7170
7171#define MLXSW_REG_RALTA_ID 0x8010
7172#define MLXSW_REG_RALTA_LEN 0x04
7173
7174MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
7175
7176
7177
7178
7179
7180
7181
7182MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
7183
7184enum mlxsw_reg_ralxx_protocol {
7185 MLXSW_REG_RALXX_PROTOCOL_IPV4,
7186 MLXSW_REG_RALXX_PROTOCOL_IPV6,
7187};
7188
7189
7190
7191
7192
7193
7194MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
7195
7196
7197
7198
7199
7200
7201
7202MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
7203
7204static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
7205 enum mlxsw_reg_ralxx_protocol protocol,
7206 u8 tree_id)
7207{
7208 MLXSW_REG_ZERO(ralta, payload);
7209 mlxsw_reg_ralta_op_set(payload, !alloc);
7210 mlxsw_reg_ralta_protocol_set(payload, protocol);
7211 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
7212}
7213
7214
7215
7216
7217
7218
7219
7220
7221
7222
7223#define MLXSW_REG_RALST_ID 0x8011
7224#define MLXSW_REG_RALST_LEN 0x104
7225
7226MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
7227
7228
7229
7230
7231
7232
7233
7234MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
7235
7236
7237
7238
7239
7240MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
7241
7242#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
7243#define MLXSW_REG_RALST_BIN_OFFSET 0x04
7244#define MLXSW_REG_RALST_BIN_COUNT 128
7245
7246
7247
7248
7249
7250
7251
7252MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
7253
7254
7255
7256
7257
7258
7259
7260MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
7261 false);
7262
7263static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
7264{
7265 MLXSW_REG_ZERO(ralst, payload);
7266
7267
7268 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
7269 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
7270
7271 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
7272 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
7273}
7274
7275static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
7276 u8 left_child_bin,
7277 u8 right_child_bin)
7278{
7279 int bin_index = bin_number - 1;
7280
7281 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
7282 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
7283 right_child_bin);
7284}
7285
7286
7287
7288
7289
7290#define MLXSW_REG_RALTB_ID 0x8012
7291#define MLXSW_REG_RALTB_LEN 0x04
7292
7293MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
7294
7295
7296
7297
7298
7299
7300MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
7301
7302
7303
7304
7305
7306MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
7307
7308
7309
7310
7311
7312
7313
7314MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
7315
7316static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
7317 enum mlxsw_reg_ralxx_protocol protocol,
7318 u8 tree_id)
7319{
7320 MLXSW_REG_ZERO(raltb, payload);
7321 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
7322 mlxsw_reg_raltb_protocol_set(payload, protocol);
7323 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
7324}
7325
7326
7327
7328
7329
7330
7331#define MLXSW_REG_RALUE_ID 0x8013
7332#define MLXSW_REG_RALUE_LEN 0x38
7333
7334MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
7335
7336
7337
7338
7339
7340MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
7341
7342enum mlxsw_reg_ralue_op {
7343
7344 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
7345
7346
7347
7348 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
7349
7350
7351
7352
7353 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
7354
7355
7356
7357
7358 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
7359
7360
7361
7362 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
7363
7364
7365
7366 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
7367};
7368
7369
7370
7371
7372
7373MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
7374
7375
7376
7377
7378
7379
7380
7381
7382MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
7383
7384
7385
7386
7387
7388
7389MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
7390
7391#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
7392#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
7393#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
7394
7395
7396
7397
7398
7399
7400
7401
7402MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
7403
7404
7405
7406
7407
7408
7409
7410MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
7411
7412
7413
7414
7415
7416
7417
7418
7419
7420MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
7421MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
7422
7423enum mlxsw_reg_ralue_entry_type {
7424 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
7425 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
7426 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
7427};
7428
7429
7430
7431
7432
7433
7434MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
7435
7436
7437
7438
7439
7440
7441
7442
7443
7444MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
7445
7446enum mlxsw_reg_ralue_action_type {
7447 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
7448 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
7449 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
7450};
7451
7452
7453
7454
7455
7456
7457
7458
7459
7460
7461MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
7462
7463enum mlxsw_reg_ralue_trap_action {
7464 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
7465 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
7466 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
7467 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
7468 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
7469};
7470
7471
7472
7473
7474
7475
7476MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
7477
7478
7479
7480
7481
7482
7483
7484MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
7485
7486
7487
7488
7489
7490
7491MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
7492
7493
7494
7495
7496
7497
7498
7499
7500
7501MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
7502
7503
7504
7505
7506
7507
7508MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
7509
7510
7511
7512
7513
7514
7515
7516
7517
7518
7519
7520MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
7521
7522
7523
7524
7525
7526
7527
7528MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
7529
7530static inline void mlxsw_reg_ralue_pack(char *payload,
7531 enum mlxsw_reg_ralxx_protocol protocol,
7532 enum mlxsw_reg_ralue_op op,
7533 u16 virtual_router, u8 prefix_len)
7534{
7535 MLXSW_REG_ZERO(ralue, payload);
7536 mlxsw_reg_ralue_protocol_set(payload, protocol);
7537 mlxsw_reg_ralue_op_set(payload, op);
7538 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
7539 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
7540 mlxsw_reg_ralue_entry_type_set(payload,
7541 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
7542 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
7543}
7544
7545static inline void mlxsw_reg_ralue_pack4(char *payload,
7546 enum mlxsw_reg_ralxx_protocol protocol,
7547 enum mlxsw_reg_ralue_op op,
7548 u16 virtual_router, u8 prefix_len,
7549 u32 *dip)
7550{
7551 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7552 if (dip)
7553 mlxsw_reg_ralue_dip4_set(payload, *dip);
7554}
7555
7556static inline void mlxsw_reg_ralue_pack6(char *payload,
7557 enum mlxsw_reg_ralxx_protocol protocol,
7558 enum mlxsw_reg_ralue_op op,
7559 u16 virtual_router, u8 prefix_len,
7560 const void *dip)
7561{
7562 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
7563 if (dip)
7564 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
7565}
7566
7567static inline void
7568mlxsw_reg_ralue_act_remote_pack(char *payload,
7569 enum mlxsw_reg_ralue_trap_action trap_action,
7570 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
7571{
7572 mlxsw_reg_ralue_action_type_set(payload,
7573 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
7574 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7575 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7576 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
7577 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
7578}
7579
7580static inline void
7581mlxsw_reg_ralue_act_local_pack(char *payload,
7582 enum mlxsw_reg_ralue_trap_action trap_action,
7583 u16 trap_id, u16 local_erif)
7584{
7585 mlxsw_reg_ralue_action_type_set(payload,
7586 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
7587 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
7588 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
7589 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
7590}
7591
7592static inline void
7593mlxsw_reg_ralue_act_ip2me_pack(char *payload)
7594{
7595 mlxsw_reg_ralue_action_type_set(payload,
7596 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7597}
7598
7599static inline void
7600mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
7601{
7602 mlxsw_reg_ralue_action_type_set(payload,
7603 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
7604 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
7605 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
7606}
7607
7608
7609
7610
7611
7612
7613#define MLXSW_REG_RAUHT_ID 0x8014
7614#define MLXSW_REG_RAUHT_LEN 0x74
7615
7616MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
7617
7618enum mlxsw_reg_rauht_type {
7619 MLXSW_REG_RAUHT_TYPE_IPV4,
7620 MLXSW_REG_RAUHT_TYPE_IPV6,
7621};
7622
7623
7624
7625
7626MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
7627
7628enum mlxsw_reg_rauht_op {
7629 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
7630
7631 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
7632
7633
7634
7635 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
7636
7637
7638
7639 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
7640
7641
7642
7643
7644 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
7645
7646 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
7647
7648 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
7649
7650
7651
7652};
7653
7654
7655
7656
7657MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
7658
7659
7660
7661
7662
7663
7664
7665
7666MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
7667
7668
7669
7670
7671
7672MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
7673
7674
7675
7676
7677
7678MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
7679MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
7680
7681enum mlxsw_reg_rauht_trap_action {
7682 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
7683 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
7684 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
7685 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
7686 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
7687};
7688
7689
7690
7691
7692MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
7693
7694enum mlxsw_reg_rauht_trap_id {
7695 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
7696 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
7697};
7698
7699
7700
7701
7702
7703
7704
7705
7706MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
7707
7708
7709
7710
7711
7712MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
7713
7714
7715
7716
7717
7718MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
7719
7720
7721
7722
7723
7724MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
7725
7726static inline void mlxsw_reg_rauht_pack(char *payload,
7727 enum mlxsw_reg_rauht_op op, u16 rif,
7728 const char *mac)
7729{
7730 MLXSW_REG_ZERO(rauht, payload);
7731 mlxsw_reg_rauht_op_set(payload, op);
7732 mlxsw_reg_rauht_rif_set(payload, rif);
7733 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
7734}
7735
7736static inline void mlxsw_reg_rauht_pack4(char *payload,
7737 enum mlxsw_reg_rauht_op op, u16 rif,
7738 const char *mac, u32 dip)
7739{
7740 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7741 mlxsw_reg_rauht_dip4_set(payload, dip);
7742}
7743
7744static inline void mlxsw_reg_rauht_pack6(char *payload,
7745 enum mlxsw_reg_rauht_op op, u16 rif,
7746 const char *mac, const char *dip)
7747{
7748 mlxsw_reg_rauht_pack(payload, op, rif, mac);
7749 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
7750 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
7751}
7752
7753static inline void mlxsw_reg_rauht_pack_counter(char *payload,
7754 u64 counter_index)
7755{
7756 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
7757 mlxsw_reg_rauht_counter_set_type_set(payload,
7758 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
7759}
7760
7761
7762
7763
7764
7765
7766
7767#define MLXSW_REG_RALEU_ID 0x8015
7768#define MLXSW_REG_RALEU_LEN 0x28
7769
7770MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
7771
7772
7773
7774
7775
7776MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
7777
7778
7779
7780
7781
7782
7783MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
7784
7785
7786
7787
7788
7789MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
7790
7791
7792
7793
7794
7795MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
7796
7797
7798
7799
7800
7801MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
7802
7803
7804
7805
7806
7807MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
7808
7809static inline void mlxsw_reg_raleu_pack(char *payload,
7810 enum mlxsw_reg_ralxx_protocol protocol,
7811 u16 virtual_router,
7812 u32 adjacency_index, u16 ecmp_size,
7813 u32 new_adjacency_index,
7814 u16 new_ecmp_size)
7815{
7816 MLXSW_REG_ZERO(raleu, payload);
7817 mlxsw_reg_raleu_protocol_set(payload, protocol);
7818 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
7819 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
7820 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
7821 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
7822 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
7823}
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833
7834#define MLXSW_REG_RAUHTD_ID 0x8018
7835#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
7836#define MLXSW_REG_RAUHTD_REC_LEN 0x20
7837#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
7838#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
7839 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
7840#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
7841
7842MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
7843
7844#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
7845#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
7846
7847
7848
7849
7850
7851
7852
7853
7854MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
7855
7856enum mlxsw_reg_rauhtd_op {
7857 MLXSW_REG_RAUHTD_OP_DUMP,
7858 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
7859};
7860
7861
7862
7863
7864MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
7865
7866
7867
7868
7869
7870
7871
7872
7873
7874MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
7875
7876
7877
7878
7879
7880
7881MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
7882
7883enum mlxsw_reg_rauhtd_type {
7884 MLXSW_REG_RAUHTD_TYPE_IPV4,
7885 MLXSW_REG_RAUHTD_TYPE_IPV6,
7886};
7887
7888
7889
7890
7891
7892
7893
7894MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
7895
7896
7897
7898
7899
7900
7901MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
7902
7903static inline void mlxsw_reg_rauhtd_pack(char *payload,
7904 enum mlxsw_reg_rauhtd_type type)
7905{
7906 MLXSW_REG_ZERO(rauhtd, payload);
7907 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
7908 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
7909 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
7910 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
7911 mlxsw_reg_rauhtd_type_set(payload, type);
7912}
7913
7914
7915
7916
7917
7918
7919
7920
7921
7922MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
7923 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
7924 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7925
7926
7927
7928
7929
7930
7931
7932MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
7933 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
7934
7935#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
7936
7937
7938
7939
7940
7941
7942MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7943 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7944
7945
7946
7947
7948
7949MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7950 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
7951
7952
7953
7954
7955
7956MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7957 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
7958
7959#define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
7960
7961
7962
7963
7964
7965
7966MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
7967 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7968
7969
7970
7971
7972
7973MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
7974 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
7975
7976
7977
7978
7979
7980MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
7981 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
7982
7983static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
7984 int ent_index, u16 *p_rif,
7985 u32 *p_dip)
7986{
7987 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
7988 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
7989}
7990
7991static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
7992 int rec_index, u16 *p_rif,
7993 char *p_dip)
7994{
7995 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
7996 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
7997}
7998
7999
8000
8001
8002
8003
8004#define MLXSW_REG_RTDP_ID 0x8020
8005#define MLXSW_REG_RTDP_LEN 0x44
8006
8007MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
8008
8009enum mlxsw_reg_rtdp_type {
8010 MLXSW_REG_RTDP_TYPE_NVE,
8011 MLXSW_REG_RTDP_TYPE_IPIP,
8012};
8013
8014
8015
8016
8017
8018MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
8019
8020
8021
8022
8023
8024
8025MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
8026
8027
8028
8029
8030
8031
8032MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
8033
8034
8035
8036
8037
8038
8039
8040MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
8041
8042enum mlxsw_reg_rtdp_ipip_sip_check {
8043
8044 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
8045
8046
8047
8048 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
8049
8050
8051
8052 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
8053};
8054
8055
8056
8057
8058
8059
8060MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
8061
8062
8063#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
8064
8065#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
8066
8067#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
8068
8069
8070
8071
8072
8073
8074MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
8075
8076
8077
8078
8079
8080
8081
8082
8083
8084
8085MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
8086
8087
8088
8089
8090
8091
8092MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
8093
8094
8095
8096
8097
8098
8099
8100
8101MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
8102
8103
8104
8105
8106
8107
8108MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
8109
8110static inline void mlxsw_reg_rtdp_pack(char *payload,
8111 enum mlxsw_reg_rtdp_type type,
8112 u32 tunnel_index)
8113{
8114 MLXSW_REG_ZERO(rtdp, payload);
8115 mlxsw_reg_rtdp_type_set(payload, type);
8116 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
8117}
8118
8119static inline void
8120mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
8121 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
8122 unsigned int type_check, bool gre_key_check,
8123 u32 ipv4_usip, u32 expected_gre_key)
8124{
8125 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
8126 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
8127 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
8128 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
8129 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
8130 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
8131}
8132
8133
8134
8135
8136
8137
8138#define MLXSW_REG_RATRAD_ID 0x8022
8139#define MLXSW_REG_RATRAD_LEN 0x210
8140
8141MLXSW_REG_DEFINE(ratrad, MLXSW_REG_RATRAD_ID, MLXSW_REG_RATRAD_LEN);
8142
8143enum {
8144
8145 MLXSW_REG_RATRAD_OP_READ_ACTIVITY,
8146
8147 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY,
8148};
8149
8150
8151
8152
8153MLXSW_ITEM32(reg, ratrad, op, 0x00, 30, 2);
8154
8155
8156
8157
8158
8159
8160
8161
8162MLXSW_ITEM32(reg, ratrad, ecmp_size, 0x00, 0, 13);
8163
8164
8165
8166
8167
8168MLXSW_ITEM32(reg, ratrad, adjacency_index, 0x04, 0, 24);
8169
8170
8171
8172
8173
8174
8175MLXSW_ITEM_BIT_ARRAY(reg, ratrad, activity_vector, 0x10, 0x200, 1);
8176
8177static inline void mlxsw_reg_ratrad_pack(char *payload, u32 adjacency_index,
8178 u16 ecmp_size)
8179{
8180 MLXSW_REG_ZERO(ratrad, payload);
8181 mlxsw_reg_ratrad_op_set(payload,
8182 MLXSW_REG_RATRAD_OP_READ_CLEAR_ACTIVITY);
8183 mlxsw_reg_ratrad_ecmp_size_set(payload, ecmp_size);
8184 mlxsw_reg_ratrad_adjacency_index_set(payload, adjacency_index);
8185}
8186
8187
8188
8189
8190
8191
8192#define MLXSW_REG_RIGR2_ID 0x8023
8193#define MLXSW_REG_RIGR2_LEN 0xB0
8194
8195#define MLXSW_REG_RIGR2_MAX_ERIFS 32
8196
8197MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
8198
8199
8200
8201
8202
8203MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
8204
8205
8206
8207
8208
8209MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
8210
8211
8212
8213
8214
8215
8216MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
8217
8218
8219
8220
8221
8222MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
8223
8224
8225
8226
8227
8228
8229
8230
8231MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
8232
8233
8234
8235
8236
8237
8238
8239
8240
8241MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
8242
8243
8244
8245
8246
8247
8248
8249MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
8250
8251static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
8252 bool vnext, u32 next_rigr_index)
8253{
8254 MLXSW_REG_ZERO(rigr2, payload);
8255 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
8256 mlxsw_reg_rigr2_vnext_set(payload, vnext);
8257 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
8258 mlxsw_reg_rigr2_vrmid_set(payload, 0);
8259 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
8260}
8261
8262static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
8263 bool v, u16 erif)
8264{
8265 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
8266 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
8267}
8268
8269
8270
8271
8272#define MLXSW_REG_RECR2_ID 0x8025
8273#define MLXSW_REG_RECR2_LEN 0x38
8274
8275MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
8276
8277
8278
8279
8280
8281MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
8282
8283
8284
8285
8286
8287MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
8288
8289
8290
8291
8292
8293MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
8294
8295enum {
8296
8297 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
8298
8299 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
8300
8301 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
8302
8303 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
8304
8305 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
8306
8307 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
8308
8309 __MLXSW_REG_RECR2_HEADER_CNT,
8310};
8311
8312
8313
8314
8315
8316
8317MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
8318
8319enum {
8320
8321 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
8322 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
8323
8324 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
8325 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
8326
8327 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
8328
8329 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
8330 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
8331 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
8332
8333 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
8334 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
8335 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
8336
8337 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
8338
8339 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
8340
8341 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
8342
8343 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
8344
8345 __MLXSW_REG_RECR2_FIELD_CNT,
8346};
8347
8348
8349
8350
8351
8352MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
8353
8354
8355
8356
8357
8358
8359MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_enables, 0x2C, 0x04, 1);
8360
8361enum {
8362
8363 MLXSW_REG_RECR2_INNER_IPV4_SIP0 = 3,
8364 MLXSW_REG_RECR2_INNER_IPV4_SIP3 = 6,
8365
8366 MLXSW_REG_RECR2_INNER_IPV4_DIP0 = 7,
8367 MLXSW_REG_RECR2_INNER_IPV4_DIP3 = 10,
8368
8369 MLXSW_REG_RECR2_INNER_IPV4_PROTOCOL = 11,
8370
8371 MLXSW_REG_RECR2_INNER_IPV6_SIP0_7 = 12,
8372 MLXSW_REG_RECR2_INNER_IPV6_SIP8 = 20,
8373 MLXSW_REG_RECR2_INNER_IPV6_SIP15 = 27,
8374
8375 MLXSW_REG_RECR2_INNER_IPV6_DIP0_7 = 28,
8376 MLXSW_REG_RECR2_INNER_IPV6_DIP8 = 36,
8377 MLXSW_REG_RECR2_INNER_IPV6_DIP15 = 43,
8378
8379 MLXSW_REG_RECR2_INNER_IPV6_NEXT_HEADER = 44,
8380
8381 MLXSW_REG_RECR2_INNER_IPV6_FLOW_LABEL = 45,
8382
8383 MLXSW_REG_RECR2_INNER_TCP_UDP_SPORT = 46,
8384
8385 MLXSW_REG_RECR2_INNER_TCP_UDP_DPORT = 47,
8386
8387 __MLXSW_REG_RECR2_INNER_FIELD_CNT,
8388};
8389
8390
8391
8392
8393
8394MLXSW_ITEM_BIT_ARRAY(reg, recr2, inner_header_fields_enable, 0x30, 0x08, 1);
8395
8396static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
8397{
8398 MLXSW_REG_ZERO(recr2, payload);
8399 mlxsw_reg_recr2_pp_set(payload, false);
8400 mlxsw_reg_recr2_sh_set(payload, true);
8401 mlxsw_reg_recr2_seed_set(payload, seed);
8402}
8403
8404
8405
8406
8407
8408#define MLXSW_REG_RMFT2_ID 0x8027
8409#define MLXSW_REG_RMFT2_LEN 0x174
8410
8411MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
8412
8413
8414
8415
8416
8417MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
8418
8419enum mlxsw_reg_rmft2_type {
8420 MLXSW_REG_RMFT2_TYPE_IPV4,
8421 MLXSW_REG_RMFT2_TYPE_IPV6
8422};
8423
8424
8425
8426
8427MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
8428
8429enum mlxsw_sp_reg_rmft2_op {
8430
8431
8432
8433
8434
8435
8436
8437 MLXSW_REG_RMFT2_OP_READ_WRITE,
8438};
8439
8440
8441
8442
8443
8444MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
8445
8446
8447
8448
8449
8450
8451MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
8452
8453
8454
8455
8456
8457MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
8458
8459
8460
8461
8462
8463MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
8464
8465enum mlxsw_reg_rmft2_irif_mask {
8466 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
8467 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
8468};
8469
8470
8471
8472
8473
8474MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
8475
8476
8477
8478
8479
8480MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
8481
8482
8483
8484
8485
8486MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
8487MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
8488
8489
8490
8491
8492
8493
8494MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
8495MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
8496
8497
8498
8499
8500
8501MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
8502MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
8503
8504
8505
8506
8507
8508
8509MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
8510MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
8511
8512
8513
8514
8515
8516
8517
8518
8519
8520
8521
8522
8523MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
8524 MLXSW_REG_FLEX_ACTION_SET_LEN);
8525
8526static inline void
8527mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
8528 u16 virtual_router,
8529 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8530 const char *flex_action_set)
8531{
8532 MLXSW_REG_ZERO(rmft2, payload);
8533 mlxsw_reg_rmft2_v_set(payload, v);
8534 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
8535 mlxsw_reg_rmft2_offset_set(payload, offset);
8536 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
8537 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
8538 mlxsw_reg_rmft2_irif_set(payload, irif);
8539 if (flex_action_set)
8540 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
8541 flex_action_set);
8542}
8543
8544static inline void
8545mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8546 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8547 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
8548 const char *flexible_action_set)
8549{
8550 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8551 irif_mask, irif, flexible_action_set);
8552 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
8553 mlxsw_reg_rmft2_dip4_set(payload, dip4);
8554 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
8555 mlxsw_reg_rmft2_sip4_set(payload, sip4);
8556 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
8557}
8558
8559static inline void
8560mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
8561 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
8562 struct in6_addr dip6, struct in6_addr dip6_mask,
8563 struct in6_addr sip6, struct in6_addr sip6_mask,
8564 const char *flexible_action_set)
8565{
8566 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
8567 irif_mask, irif, flexible_action_set);
8568 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
8569 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
8570 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
8571 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
8572 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
8573}
8574
8575
8576
8577
8578
8579
8580
8581#define MLXSW_REG_RXLTE_ID 0x8050
8582#define MLXSW_REG_RXLTE_LEN 0x0C
8583
8584MLXSW_REG_DEFINE(rxlte, MLXSW_REG_RXLTE_ID, MLXSW_REG_RXLTE_LEN);
8585
8586
8587
8588
8589
8590
8591MLXSW_ITEM32(reg, rxlte, virtual_router, 0x00, 0, 16);
8592
8593enum mlxsw_reg_rxlte_protocol {
8594 MLXSW_REG_RXLTE_PROTOCOL_IPV4,
8595 MLXSW_REG_RXLTE_PROTOCOL_IPV6,
8596};
8597
8598
8599
8600
8601MLXSW_ITEM32(reg, rxlte, protocol, 0x04, 0, 4);
8602
8603
8604
8605
8606MLXSW_ITEM32(reg, rxlte, lpm_xlt_en, 0x08, 0, 1);
8607
8608static inline void mlxsw_reg_rxlte_pack(char *payload, u16 virtual_router,
8609 enum mlxsw_reg_rxlte_protocol protocol,
8610 bool lpm_xlt_en)
8611{
8612 MLXSW_REG_ZERO(rxlte, payload);
8613 mlxsw_reg_rxlte_virtual_router_set(payload, virtual_router);
8614 mlxsw_reg_rxlte_protocol_set(payload, protocol);
8615 mlxsw_reg_rxlte_lpm_xlt_en_set(payload, lpm_xlt_en);
8616}
8617
8618
8619
8620
8621
8622
8623#define MLXSW_REG_RXLTM_ID 0x8051
8624#define MLXSW_REG_RXLTM_LEN 0x14
8625
8626MLXSW_REG_DEFINE(rxltm, MLXSW_REG_RXLTM_ID, MLXSW_REG_RXLTM_LEN);
8627
8628
8629
8630
8631
8632
8633MLXSW_ITEM32(reg, rxltm, m0_val_v6, 0x10, 16, 8);
8634
8635
8636
8637
8638
8639
8640MLXSW_ITEM32(reg, rxltm, m0_val_v4, 0x10, 0, 6);
8641
8642static inline void mlxsw_reg_rxltm_pack(char *payload, u8 m0_val_v4, u8 m0_val_v6)
8643{
8644 MLXSW_REG_ZERO(rxltm, payload);
8645 mlxsw_reg_rxltm_m0_val_v6_set(payload, m0_val_v6);
8646 mlxsw_reg_rxltm_m0_val_v4_set(payload, m0_val_v4);
8647}
8648
8649
8650
8651
8652
8653
8654
8655
8656#define MLXSW_REG_RLCMLD_ID 0x8055
8657#define MLXSW_REG_RLCMLD_LEN 0x30
8658
8659MLXSW_REG_DEFINE(rlcmld, MLXSW_REG_RLCMLD_ID, MLXSW_REG_RLCMLD_LEN);
8660
8661enum mlxsw_reg_rlcmld_select {
8662 MLXSW_REG_RLCMLD_SELECT_ML_ENTRIES,
8663 MLXSW_REG_RLCMLD_SELECT_M_ENTRIES,
8664 MLXSW_REG_RLCMLD_SELECT_M_AND_ML_ENTRIES,
8665};
8666
8667
8668
8669
8670
8671MLXSW_ITEM32(reg, rlcmld, select, 0x00, 16, 2);
8672
8673enum mlxsw_reg_rlcmld_filter_fields {
8674 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL = 0x04,
8675 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER = 0x08,
8676 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP = 0x10,
8677};
8678
8679
8680
8681
8682
8683MLXSW_ITEM32(reg, rlcmld, filter_fields, 0x00, 0, 8);
8684
8685enum mlxsw_reg_rlcmld_protocol {
8686 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4,
8687 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6,
8688};
8689
8690
8691
8692
8693MLXSW_ITEM32(reg, rlcmld, protocol, 0x08, 0, 4);
8694
8695
8696
8697
8698
8699
8700MLXSW_ITEM32(reg, rlcmld, virtual_router, 0x0C, 0, 16);
8701
8702
8703
8704
8705
8706
8707MLXSW_ITEM32(reg, rlcmld, dip4, 0x1C, 0, 32);
8708MLXSW_ITEM_BUF(reg, rlcmld, dip6, 0x10, 16);
8709
8710
8711
8712
8713
8714
8715
8716MLXSW_ITEM32(reg, rlcmld, dip_mask4, 0x2C, 0, 32);
8717MLXSW_ITEM_BUF(reg, rlcmld, dip_mask6, 0x20, 16);
8718
8719static inline void __mlxsw_reg_rlcmld_pack(char *payload,
8720 enum mlxsw_reg_rlcmld_select select,
8721 enum mlxsw_reg_rlcmld_protocol protocol,
8722 u16 virtual_router)
8723{
8724 u8 filter_fields = MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_PROTOCOL |
8725 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_VIRTUAL_ROUTER |
8726 MLXSW_REG_RLCMLD_FILTER_FIELDS_BY_DIP;
8727
8728 MLXSW_REG_ZERO(rlcmld, payload);
8729 mlxsw_reg_rlcmld_select_set(payload, select);
8730 mlxsw_reg_rlcmld_filter_fields_set(payload, filter_fields);
8731 mlxsw_reg_rlcmld_protocol_set(payload, protocol);
8732 mlxsw_reg_rlcmld_virtual_router_set(payload, virtual_router);
8733}
8734
8735static inline void mlxsw_reg_rlcmld_pack4(char *payload,
8736 enum mlxsw_reg_rlcmld_select select,
8737 u16 virtual_router,
8738 u32 dip, u32 dip_mask)
8739{
8740 __mlxsw_reg_rlcmld_pack(payload, select,
8741 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV4,
8742 virtual_router);
8743 mlxsw_reg_rlcmld_dip4_set(payload, dip);
8744 mlxsw_reg_rlcmld_dip_mask4_set(payload, dip_mask);
8745}
8746
8747static inline void mlxsw_reg_rlcmld_pack6(char *payload,
8748 enum mlxsw_reg_rlcmld_select select,
8749 u16 virtual_router,
8750 const void *dip, const void *dip_mask)
8751{
8752 __mlxsw_reg_rlcmld_pack(payload, select,
8753 MLXSW_REG_RLCMLD_PROTOCOL_UC_IPV6,
8754 virtual_router);
8755 mlxsw_reg_rlcmld_dip6_memcpy_to(payload, dip);
8756 mlxsw_reg_rlcmld_dip_mask6_memcpy_to(payload, dip_mask);
8757}
8758
8759
8760
8761
8762
8763
8764#define MLXSW_REG_RLPMCE_ID 0x8056
8765#define MLXSW_REG_RLPMCE_LEN 0x4
8766
8767MLXSW_REG_DEFINE(rlpmce, MLXSW_REG_RLPMCE_ID, MLXSW_REG_RLPMCE_LEN);
8768
8769
8770
8771
8772
8773
8774
8775MLXSW_ITEM32(reg, rlpmce, flush, 0x00, 4, 1);
8776
8777
8778
8779
8780
8781
8782
8783MLXSW_ITEM32(reg, rlpmce, disable, 0x00, 0, 1);
8784
8785static inline void mlxsw_reg_rlpmce_pack(char *payload, bool flush,
8786 bool disable)
8787{
8788 MLXSW_REG_ZERO(rlpmce, payload);
8789 mlxsw_reg_rlpmce_flush_set(payload, flush);
8790 mlxsw_reg_rlpmce_disable_set(payload, disable);
8791}
8792
8793
8794
8795
8796
8797
8798
8799
8800
8801
8802
8803#define MLXSW_REG_XLTQ_ID 0x7802
8804#define MLXSW_REG_XLTQ_LEN 0x2C
8805
8806MLXSW_REG_DEFINE(xltq, MLXSW_REG_XLTQ_ID, MLXSW_REG_XLTQ_LEN);
8807
8808enum mlxsw_reg_xltq_xm_device_id {
8809 MLXSW_REG_XLTQ_XM_DEVICE_ID_UNKNOWN,
8810 MLXSW_REG_XLTQ_XM_DEVICE_ID_XLT = 0xCF71,
8811};
8812
8813
8814
8815
8816
8817MLXSW_ITEM32(reg, xltq, xm_device_id, 0x04, 0, 16);
8818
8819
8820
8821
8822MLXSW_ITEM32(reg, xltq, xlt_cap_ipv4_lpm, 0x10, 0, 1);
8823
8824
8825
8826
8827MLXSW_ITEM32(reg, xltq, xlt_cap_ipv6_lpm, 0x10, 1, 1);
8828
8829
8830
8831
8832
8833
8834MLXSW_ITEM32(reg, xltq, cap_xlt_entries, 0x20, 0, 32);
8835
8836
8837
8838
8839
8840MLXSW_ITEM32(reg, xltq, cap_xlt_mtable, 0x24, 0, 32);
8841
8842static inline void mlxsw_reg_xltq_pack(char *payload)
8843{
8844 MLXSW_REG_ZERO(xltq, payload);
8845}
8846
8847static inline void mlxsw_reg_xltq_unpack(char *payload, u16 *xm_device_id, bool *xlt_cap_ipv4_lpm,
8848 bool *xlt_cap_ipv6_lpm, u32 *cap_xlt_entries,
8849 u32 *cap_xlt_mtable)
8850{
8851 *xm_device_id = mlxsw_reg_xltq_xm_device_id_get(payload);
8852 *xlt_cap_ipv4_lpm = mlxsw_reg_xltq_xlt_cap_ipv4_lpm_get(payload);
8853 *xlt_cap_ipv6_lpm = mlxsw_reg_xltq_xlt_cap_ipv6_lpm_get(payload);
8854 *cap_xlt_entries = mlxsw_reg_xltq_cap_xlt_entries_get(payload);
8855 *cap_xlt_mtable = mlxsw_reg_xltq_cap_xlt_mtable_get(payload);
8856}
8857
8858
8859
8860
8861
8862
8863
8864#define MLXSW_REG_XMDR_ID 0x7803
8865#define MLXSW_REG_XMDR_BASE_LEN 0x20
8866#define MLXSW_REG_XMDR_TRANS_LEN 0x80
8867#define MLXSW_REG_XMDR_LEN (MLXSW_REG_XMDR_BASE_LEN + \
8868 MLXSW_REG_XMDR_TRANS_LEN)
8869
8870MLXSW_REG_DEFINE(xmdr, MLXSW_REG_XMDR_ID, MLXSW_REG_XMDR_LEN);
8871
8872
8873
8874
8875
8876
8877
8878MLXSW_ITEM32(reg, xmdr, bulk_entry, 0x04, 8, 1);
8879
8880
8881
8882
8883
8884
8885
8886
8887MLXSW_ITEM32(reg, xmdr, num_rec, 0x04, 0, 4);
8888
8889
8890
8891
8892
8893
8894
8895
8896
8897
8898
8899MLXSW_ITEM_BIT_ARRAY(reg, xmdr, reply_vect, 0x08, 4, 1);
8900
8901static inline void mlxsw_reg_xmdr_pack(char *payload, bool bulk_entry)
8902{
8903 MLXSW_REG_ZERO(xmdr, payload);
8904 mlxsw_reg_xmdr_bulk_entry_set(payload, bulk_entry);
8905}
8906
8907enum mlxsw_reg_xmdr_c_cmd_id {
8908 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4 = 0x30,
8909 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6 = 0x31,
8910};
8911
8912#define MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN 32
8913#define MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN 48
8914
8915
8916
8917MLXSW_ITEM32(reg, xmdr_c, cmd_id, 0x00, 24, 8);
8918
8919
8920
8921MLXSW_ITEM32(reg, xmdr_c, seq_number, 0x00, 12, 12);
8922
8923enum mlxsw_reg_xmdr_c_ltr_op {
8924
8925 MLXSW_REG_XMDR_C_LTR_OP_WRITE = 0,
8926
8927 MLXSW_REG_XMDR_C_LTR_OP_UPDATE = 1,
8928 MLXSW_REG_XMDR_C_LTR_OP_DELETE = 2,
8929};
8930
8931
8932
8933
8934MLXSW_ITEM32(reg, xmdr_c, ltr_op, 0x04, 24, 8);
8935
8936
8937
8938
8939
8940MLXSW_ITEM32(reg, xmdr_c, ltr_trap_action, 0x04, 20, 4);
8941
8942enum mlxsw_reg_xmdr_c_ltr_trap_id_num {
8943 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS0,
8944 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS1,
8945 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS2,
8946 MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS3,
8947};
8948
8949
8950
8951
8952MLXSW_ITEM32(reg, xmdr_c, ltr_trap_id_num, 0x04, 16, 4);
8953
8954
8955
8956
8957
8958MLXSW_ITEM32(reg, xmdr_c, ltr_virtual_router, 0x04, 0, 16);
8959
8960
8961
8962
8963MLXSW_ITEM32(reg, xmdr_c, ltr_prefix_len, 0x08, 24, 8);
8964
8965
8966
8967
8968
8969
8970MLXSW_ITEM32(reg, xmdr_c, ltr_bmp_len, 0x08, 16, 8);
8971
8972
8973
8974
8975
8976MLXSW_ITEM32(reg, xmdr_c, ltr_entry_type, 0x08, 4, 4);
8977
8978enum mlxsw_reg_xmdr_c_ltr_action_type {
8979 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL,
8980 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE,
8981 MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME,
8982};
8983
8984
8985
8986
8987MLXSW_ITEM32(reg, xmdr_c, ltr_action_type, 0x08, 0, 4);
8988
8989
8990
8991
8992
8993MLXSW_ITEM32(reg, xmdr_c, ltr_erif, 0x10, 0, 16);
8994
8995
8996
8997
8998
8999MLXSW_ITEM32(reg, xmdr_c, ltr_adjacency_index, 0x10, 0, 24);
9000
9001#define MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC 0xFFFFFF
9002
9003
9004
9005
9006MLXSW_ITEM32(reg, xmdr_c, ltr_pointer_to_tunnel, 0x10, 0, 24);
9007
9008
9009
9010
9011
9012
9013
9014MLXSW_ITEM32(reg, xmdr_c, ltr_ecmp_size, 0x14, 0, 32);
9015
9016
9017
9018
9019
9020
9021
9022MLXSW_ITEM32(reg, xmdr_c, ltr_dip4, 0x1C, 0, 32);
9023MLXSW_ITEM_BUF(reg, xmdr_c, ltr_dip6, 0x1C, 16);
9024
9025static inline void
9026mlxsw_reg_xmdr_c_ltr_pack(char *xmdr_payload, unsigned int trans_offset,
9027 enum mlxsw_reg_xmdr_c_cmd_id cmd_id, u16 seq_number,
9028 enum mlxsw_reg_xmdr_c_ltr_op op, u16 virtual_router,
9029 u8 prefix_len)
9030{
9031 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9032 u8 num_rec = mlxsw_reg_xmdr_num_rec_get(xmdr_payload);
9033
9034 mlxsw_reg_xmdr_num_rec_set(xmdr_payload, num_rec + 1);
9035
9036 mlxsw_reg_xmdr_c_cmd_id_set(payload, cmd_id);
9037 mlxsw_reg_xmdr_c_seq_number_set(payload, seq_number);
9038 mlxsw_reg_xmdr_c_ltr_op_set(payload, op);
9039 mlxsw_reg_xmdr_c_ltr_virtual_router_set(payload, virtual_router);
9040 mlxsw_reg_xmdr_c_ltr_prefix_len_set(payload, prefix_len);
9041 mlxsw_reg_xmdr_c_ltr_entry_type_set(payload,
9042 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
9043 mlxsw_reg_xmdr_c_ltr_bmp_len_set(payload, prefix_len);
9044}
9045
9046static inline unsigned int
9047mlxsw_reg_xmdr_c_ltr_pack4(char *xmdr_payload, unsigned int trans_offset,
9048 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
9049 u16 virtual_router, u8 prefix_len, u32 *dip)
9050{
9051 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9052
9053 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
9054 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4,
9055 seq_number, op, virtual_router, prefix_len);
9056 if (dip)
9057 mlxsw_reg_xmdr_c_ltr_dip4_set(payload, *dip);
9058 return MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN;
9059}
9060
9061static inline unsigned int
9062mlxsw_reg_xmdr_c_ltr_pack6(char *xmdr_payload, unsigned int trans_offset,
9063 u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
9064 u16 virtual_router, u8 prefix_len, const void *dip)
9065{
9066 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9067
9068 mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
9069 MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6,
9070 seq_number, op, virtual_router, prefix_len);
9071 if (dip)
9072 mlxsw_reg_xmdr_c_ltr_dip6_memcpy_to(payload, dip);
9073 return MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN;
9074}
9075
9076static inline void
9077mlxsw_reg_xmdr_c_ltr_act_remote_pack(char *xmdr_payload, unsigned int trans_offset,
9078 enum mlxsw_reg_ralue_trap_action trap_action,
9079 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num,
9080 u32 adjacency_index, u16 ecmp_size)
9081{
9082 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9083
9084 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE);
9085 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
9086 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
9087 mlxsw_reg_xmdr_c_ltr_adjacency_index_set(payload, adjacency_index);
9088 mlxsw_reg_xmdr_c_ltr_ecmp_size_set(payload, ecmp_size);
9089}
9090
9091static inline void
9092mlxsw_reg_xmdr_c_ltr_act_local_pack(char *xmdr_payload, unsigned int trans_offset,
9093 enum mlxsw_reg_ralue_trap_action trap_action,
9094 enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, u16 erif)
9095{
9096 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9097
9098 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL);
9099 mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
9100 mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
9101 mlxsw_reg_xmdr_c_ltr_erif_set(payload, erif);
9102}
9103
9104static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char *xmdr_payload,
9105 unsigned int trans_offset)
9106{
9107 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9108
9109 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
9110 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload,
9111 MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC);
9112}
9113
9114static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload,
9115 unsigned int trans_offset,
9116 u32 pointer_to_tunnel)
9117{
9118 char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
9119
9120 mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
9121 mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel);
9122}
9123
9124
9125
9126
9127
9128#define MLXSW_REG_XRMT_ID 0x7810
9129#define MLXSW_REG_XRMT_LEN 0x14
9130
9131MLXSW_REG_DEFINE(xrmt, MLXSW_REG_XRMT_ID, MLXSW_REG_XRMT_LEN);
9132
9133
9134
9135
9136
9137
9138MLXSW_ITEM32(reg, xrmt, index, 0x04, 0, 20);
9139
9140
9141
9142
9143MLXSW_ITEM32(reg, xrmt, l0_val, 0x10, 24, 8);
9144
9145static inline void mlxsw_reg_xrmt_pack(char *payload, u32 index, u8 l0_val)
9146{
9147 MLXSW_REG_ZERO(xrmt, payload);
9148 mlxsw_reg_xrmt_index_set(payload, index);
9149 mlxsw_reg_xrmt_l0_val_set(payload, l0_val);
9150}
9151
9152
9153
9154
9155
9156
9157
9158#define MLXSW_REG_XRALTA_ID 0x7811
9159#define MLXSW_REG_XRALTA_LEN 0x08
9160#define MLXSW_REG_XRALTA_RALTA_OFFSET 0x04
9161
9162MLXSW_REG_DEFINE(xralta, MLXSW_REG_XRALTA_ID, MLXSW_REG_XRALTA_LEN);
9163
9164static inline void mlxsw_reg_xralta_pack(char *payload, bool alloc,
9165 enum mlxsw_reg_ralxx_protocol protocol,
9166 u8 tree_id)
9167{
9168 char *ralta_payload = payload + MLXSW_REG_XRALTA_RALTA_OFFSET;
9169
9170 MLXSW_REG_ZERO(xralta, payload);
9171 mlxsw_reg_ralta_pack(ralta_payload, alloc, protocol, tree_id);
9172}
9173
9174
9175
9176
9177
9178
9179
9180#define MLXSW_REG_XRALST_ID 0x7812
9181#define MLXSW_REG_XRALST_LEN 0x108
9182#define MLXSW_REG_XRALST_RALST_OFFSET 0x04
9183
9184MLXSW_REG_DEFINE(xralst, MLXSW_REG_XRALST_ID, MLXSW_REG_XRALST_LEN);
9185
9186static inline void mlxsw_reg_xralst_pack(char *payload, u8 root_bin, u8 tree_id)
9187{
9188 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET;
9189
9190 MLXSW_REG_ZERO(xralst, payload);
9191 mlxsw_reg_ralst_pack(ralst_payload, root_bin, tree_id);
9192}
9193
9194static inline void mlxsw_reg_xralst_bin_pack(char *payload, u8 bin_number,
9195 u8 left_child_bin,
9196 u8 right_child_bin)
9197{
9198 char *ralst_payload = payload + MLXSW_REG_XRALST_RALST_OFFSET;
9199
9200 mlxsw_reg_ralst_bin_pack(ralst_payload, bin_number, left_child_bin,
9201 right_child_bin);
9202}
9203
9204
9205
9206
9207
9208
9209
9210
9211#define MLXSW_REG_XRALTB_ID 0x7813
9212#define MLXSW_REG_XRALTB_LEN 0x08
9213#define MLXSW_REG_XRALTB_RALTB_OFFSET 0x04
9214
9215MLXSW_REG_DEFINE(xraltb, MLXSW_REG_XRALTB_ID, MLXSW_REG_XRALTB_LEN);
9216
9217static inline void mlxsw_reg_xraltb_pack(char *payload, u16 virtual_router,
9218 enum mlxsw_reg_ralxx_protocol protocol,
9219 u8 tree_id)
9220{
9221 char *raltb_payload = payload + MLXSW_REG_XRALTB_RALTB_OFFSET;
9222
9223 MLXSW_REG_ZERO(xraltb, payload);
9224 mlxsw_reg_raltb_pack(raltb_payload, virtual_router, protocol, tree_id);
9225}
9226
9227
9228
9229
9230
9231#define MLXSW_REG_MFCR_ID 0x9001
9232#define MLXSW_REG_MFCR_LEN 0x08
9233
9234MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
9235
9236enum mlxsw_reg_mfcr_pwm_frequency {
9237 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
9238 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
9239 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
9240 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
9241 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
9242 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
9243 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
9244 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
9245};
9246
9247
9248
9249
9250
9251MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
9252
9253#define MLXSW_MFCR_TACHOS_MAX 10
9254
9255
9256
9257
9258
9259MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
9260
9261#define MLXSW_MFCR_PWMS_MAX 5
9262
9263
9264
9265
9266
9267MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
9268
9269static inline void
9270mlxsw_reg_mfcr_pack(char *payload,
9271 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
9272{
9273 MLXSW_REG_ZERO(mfcr, payload);
9274 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
9275}
9276
9277static inline void
9278mlxsw_reg_mfcr_unpack(char *payload,
9279 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
9280 u16 *p_tacho_active, u8 *p_pwm_active)
9281{
9282 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
9283 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
9284 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
9285}
9286
9287
9288
9289
9290
9291#define MLXSW_REG_MFSC_ID 0x9002
9292#define MLXSW_REG_MFSC_LEN 0x08
9293
9294MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
9295
9296
9297
9298
9299
9300MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
9301
9302
9303
9304
9305
9306
9307MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
9308
9309static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
9310 u8 pwm_duty_cycle)
9311{
9312 MLXSW_REG_ZERO(mfsc, payload);
9313 mlxsw_reg_mfsc_pwm_set(payload, pwm);
9314 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
9315}
9316
9317
9318
9319
9320
9321
9322#define MLXSW_REG_MFSM_ID 0x9003
9323#define MLXSW_REG_MFSM_LEN 0x08
9324
9325MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
9326
9327
9328
9329
9330
9331MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
9332
9333
9334
9335
9336
9337MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
9338
9339static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
9340{
9341 MLXSW_REG_ZERO(mfsm, payload);
9342 mlxsw_reg_mfsm_tacho_set(payload, tacho);
9343}
9344
9345
9346
9347
9348
9349
9350
9351#define MLXSW_REG_MFSL_ID 0x9004
9352#define MLXSW_REG_MFSL_LEN 0x0C
9353
9354MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
9355
9356
9357
9358
9359
9360MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
9361
9362
9363
9364
9365
9366MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
9367
9368
9369
9370
9371
9372MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
9373
9374static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
9375 u16 tach_min, u16 tach_max)
9376{
9377 MLXSW_REG_ZERO(mfsl, payload);
9378 mlxsw_reg_mfsl_tacho_set(payload, tacho);
9379 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
9380 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
9381}
9382
9383static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
9384 u16 *p_tach_min, u16 *p_tach_max)
9385{
9386 if (p_tach_min)
9387 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
9388
9389 if (p_tach_max)
9390 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
9391}
9392
9393
9394
9395
9396
9397
9398#define MLXSW_REG_FORE_ID 0x9007
9399#define MLXSW_REG_FORE_LEN 0x0C
9400
9401MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
9402
9403
9404
9405
9406
9407
9408
9409MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
9410
9411static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
9412 bool *fault)
9413{
9414 u16 limit;
9415
9416 if (fault) {
9417 limit = mlxsw_reg_fore_fan_under_limit_get(payload);
9418 *fault = limit & BIT(tacho);
9419 }
9420}
9421
9422
9423
9424
9425
9426
9427#define MLXSW_REG_MTCAP_ID 0x9009
9428#define MLXSW_REG_MTCAP_LEN 0x08
9429
9430MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
9431
9432
9433
9434
9435
9436
9437MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
9438
9439
9440
9441
9442
9443
9444
9445#define MLXSW_REG_MTMP_ID 0x900A
9446#define MLXSW_REG_MTMP_LEN 0x20
9447
9448MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
9449
9450#define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
9451#define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
9452
9453
9454
9455
9456
9457
9458MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
9459
9460
9461#define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
9462 ((v_) >= 0) ? ((v_) * 125) : \
9463 ((s16)((GENMASK(15, 0) + (v_) + 1) \
9464 * 125)); })
9465
9466
9467
9468
9469
9470
9471
9472MLXSW_ITEM32(reg, mtmp, max_operational_temperature, 0x04, 16, 16);
9473
9474
9475
9476
9477
9478
9479MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
9480
9481
9482
9483
9484
9485MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
9486
9487
9488
9489
9490
9491MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
9492
9493
9494
9495
9496
9497
9498MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
9499
9500
9501
9502
9503
9504
9505
9506
9507
9508enum mlxsw_reg_mtmp_tee {
9509 MLXSW_REG_MTMP_TEE_NO_EVENT,
9510 MLXSW_REG_MTMP_TEE_GENERATE_EVENT,
9511 MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT,
9512};
9513
9514MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
9515
9516#define MLXSW_REG_MTMP_THRESH_HI 0x348
9517
9518
9519
9520
9521
9522MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
9523
9524#define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28
9525
9526
9527
9528
9529MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
9530
9531#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
9532
9533
9534
9535
9536
9537MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
9538
9539static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
9540 bool max_temp_enable,
9541 bool max_temp_reset)
9542{
9543 MLXSW_REG_ZERO(mtmp, payload);
9544 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
9545 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
9546 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
9547 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
9548 MLXSW_REG_MTMP_THRESH_HI);
9549}
9550
9551static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp,
9552 int *p_max_temp, int *p_temp_hi,
9553 int *p_max_oper_temp,
9554 char *sensor_name)
9555{
9556 s16 temp;
9557
9558 if (p_temp) {
9559 temp = mlxsw_reg_mtmp_temperature_get(payload);
9560 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9561 }
9562 if (p_max_temp) {
9563 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
9564 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9565 }
9566 if (p_temp_hi) {
9567 temp = mlxsw_reg_mtmp_temperature_threshold_hi_get(payload);
9568 *p_temp_hi = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9569 }
9570 if (p_max_oper_temp) {
9571 temp = mlxsw_reg_mtmp_max_operational_temperature_get(payload);
9572 *p_max_oper_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
9573 }
9574 if (sensor_name)
9575 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
9576}
9577
9578
9579
9580
9581
9582#define MLXSW_REG_MTWE_ID 0x900B
9583#define MLXSW_REG_MTWE_LEN 0x10
9584
9585MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN);
9586
9587
9588
9589
9590
9591
9592
9593MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
9594
9595
9596
9597
9598
9599#define MLXSW_REG_MTBR_ID 0x900F
9600#define MLXSW_REG_MTBR_BASE_LEN 0x10
9601#define MLXSW_REG_MTBR_REC_LEN 0x04
9602#define MLXSW_REG_MTBR_REC_MAX_COUNT 47
9603#define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \
9604 MLXSW_REG_MTBR_REC_LEN * \
9605 MLXSW_REG_MTBR_REC_MAX_COUNT)
9606
9607MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
9608
9609
9610
9611
9612
9613
9614MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
9615
9616
9617
9618
9619
9620
9621
9622
9623MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
9624
9625
9626
9627
9628
9629
9630MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
9631 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9632
9633
9634
9635
9636
9637
9638MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
9639 MLXSW_REG_MTBR_REC_LEN, 0x00, false);
9640
9641static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
9642 u8 num_rec)
9643{
9644 MLXSW_REG_ZERO(mtbr, payload);
9645 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
9646 mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
9647}
9648
9649
9650enum mlxsw_reg_mtbr_temp_status {
9651 MLXSW_REG_MTBR_NO_CONN = 0x8000,
9652 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001,
9653 MLXSW_REG_MTBR_INDEX_NA = 0x8002,
9654 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003,
9655};
9656
9657
9658#define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
9659
9660static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
9661 u16 *p_temp, u16 *p_max_temp)
9662{
9663 if (p_temp)
9664 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
9665 if (p_max_temp)
9666 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
9667}
9668
9669
9670
9671
9672
9673
9674#define MLXSW_REG_MCIA_ID 0x9014
9675#define MLXSW_REG_MCIA_LEN 0x40
9676
9677MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
9678
9679
9680
9681
9682
9683
9684
9685MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
9686
9687
9688
9689
9690
9691MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
9692
9693enum {
9694 MLXSW_REG_MCIA_STATUS_GOOD = 0,
9695
9696 MLXSW_REG_MCIA_STATUS_NO_EEPROM_MODULE = 1,
9697
9698 MLXSW_REG_MCIA_STATUS_MODULE_NOT_SUPPORTED = 2,
9699
9700 MLXSW_REG_MCIA_STATUS_MODULE_NOT_CONNECTED = 3,
9701
9702 MLXSW_REG_MCIA_STATUS_I2C_ERROR = 9,
9703
9704 MLXSW_REG_MCIA_STATUS_MODULE_DISABLED = 16,
9705};
9706
9707
9708
9709
9710
9711MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
9712
9713
9714
9715
9716
9717MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
9718
9719
9720
9721
9722
9723MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
9724
9725
9726
9727
9728
9729MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
9730
9731
9732
9733
9734
9735MLXSW_ITEM32(reg, mcia, bank_number, 0x08, 16, 8);
9736
9737
9738
9739
9740
9741MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
9742
9743#define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256
9744#define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128
9745#define MLXSW_REG_MCIA_EEPROM_SIZE 48
9746#define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50
9747#define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51
9748#define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0
9749#define MLXSW_REG_MCIA_TH_ITEM_SIZE 2
9750#define MLXSW_REG_MCIA_TH_PAGE_NUM 3
9751#define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2
9752#define MLXSW_REG_MCIA_PAGE0_LO 0
9753#define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80
9754#define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7)
9755
9756enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
9757 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
9758 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
9759 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
9760};
9761
9762enum mlxsw_reg_mcia_eeprom_module_info_id {
9763 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03,
9764 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
9765 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
9766 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
9767 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18,
9768};
9769
9770enum mlxsw_reg_mcia_eeprom_module_info {
9771 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
9772 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
9773 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID,
9774 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
9775};
9776
9777
9778
9779
9780
9781MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
9782
9783
9784
9785
9786
9787#define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
9788 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
9789 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
9790
9791static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
9792 u8 page_number, u16 device_addr,
9793 u8 size, u8 i2c_device_addr)
9794{
9795 MLXSW_REG_ZERO(mcia, payload);
9796 mlxsw_reg_mcia_module_set(payload, module);
9797 mlxsw_reg_mcia_l_set(payload, lock);
9798 mlxsw_reg_mcia_page_number_set(payload, page_number);
9799 mlxsw_reg_mcia_device_address_set(payload, device_addr);
9800 mlxsw_reg_mcia_size_set(payload, size);
9801 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
9802}
9803
9804
9805
9806
9807
9808
9809#define MLXSW_REG_MPAT_ID 0x901A
9810#define MLXSW_REG_MPAT_LEN 0x78
9811
9812MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
9813
9814
9815
9816
9817
9818MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
9819
9820
9821
9822
9823
9824
9825MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);
9826
9827
9828
9829
9830
9831MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
9832
9833
9834
9835
9836
9837MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
9838
9839
9840
9841
9842
9843
9844
9845
9846
9847
9848MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
9849
9850
9851
9852
9853
9854
9855
9856
9857
9858MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
9859
9860enum mlxsw_reg_mpat_span_type {
9861
9862
9863
9864 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
9865
9866
9867
9868
9869
9870 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1,
9871
9872
9873
9874
9875 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
9876};
9877
9878
9879
9880
9881
9882MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
9883
9884
9885
9886
9887
9888MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);
9889
9890
9891
9892
9893
9894MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);
9895
9896
9897
9898
9899
9900
9901
9902
9903
9904MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
9905
9906
9907
9908
9909
9910enum mlxsw_reg_mpat_eth_rspan_version {
9911 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
9912};
9913
9914
9915
9916
9917
9918MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
9919
9920
9921
9922
9923
9924MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
9925
9926
9927
9928
9929
9930MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
9931
9932
9933
9934
9935
9936enum mlxsw_reg_mpat_eth_rspan_protocol {
9937 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
9938 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
9939};
9940
9941
9942
9943
9944
9945MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
9946
9947
9948
9949
9950
9951MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
9952
9953
9954
9955
9956
9957MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
9958
9959
9960
9961
9962
9963MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
9964MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
9965
9966
9967
9968
9969
9970MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
9971MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
9972
9973static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
9974 u16 system_port, bool e,
9975 enum mlxsw_reg_mpat_span_type span_type)
9976{
9977 MLXSW_REG_ZERO(mpat, payload);
9978 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
9979 mlxsw_reg_mpat_system_port_set(payload, system_port);
9980 mlxsw_reg_mpat_e_set(payload, e);
9981 mlxsw_reg_mpat_qos_set(payload, 1);
9982 mlxsw_reg_mpat_be_set(payload, 1);
9983 mlxsw_reg_mpat_span_type_set(payload, span_type);
9984}
9985
9986static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
9987{
9988 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
9989}
9990
9991static inline void
9992mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
9993 enum mlxsw_reg_mpat_eth_rspan_version version,
9994 const char *mac,
9995 bool tp)
9996{
9997 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
9998 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
9999 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
10000}
10001
10002static inline void
10003mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
10004 const char *smac,
10005 u32 sip, u32 dip)
10006{
10007 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10008 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10009 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10010 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
10011 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
10012 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
10013}
10014
10015static inline void
10016mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
10017 const char *smac,
10018 struct in6_addr sip, struct in6_addr dip)
10019{
10020 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
10021 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
10022 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
10023 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
10024 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
10025 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
10026}
10027
10028
10029
10030
10031
10032
10033#define MLXSW_REG_MPAR_ID 0x901B
10034#define MLXSW_REG_MPAR_LEN 0x0C
10035
10036MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
10037
10038
10039
10040
10041
10042MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
10043
10044enum mlxsw_reg_mpar_i_e {
10045 MLXSW_REG_MPAR_TYPE_EGRESS,
10046 MLXSW_REG_MPAR_TYPE_INGRESS,
10047};
10048
10049
10050
10051
10052
10053MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
10054
10055
10056
10057
10058
10059
10060MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
10061
10062
10063
10064
10065
10066MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
10067
10068#define MLXSW_REG_MPAR_RATE_MAX 3500000000UL
10069
10070
10071
10072
10073
10074
10075
10076
10077MLXSW_ITEM32(reg, mpar, probability_rate, 0x08, 0, 32);
10078
10079static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
10080 enum mlxsw_reg_mpar_i_e i_e,
10081 bool enable, u8 pa_id,
10082 u32 probability_rate)
10083{
10084 MLXSW_REG_ZERO(mpar, payload);
10085 mlxsw_reg_mpar_local_port_set(payload, local_port);
10086 mlxsw_reg_mpar_enable_set(payload, enable);
10087 mlxsw_reg_mpar_i_e_set(payload, i_e);
10088 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
10089 mlxsw_reg_mpar_probability_rate_set(payload, probability_rate);
10090}
10091
10092
10093
10094
10095
10096
10097#define MLXSW_REG_MGIR_ID 0x9020
10098#define MLXSW_REG_MGIR_LEN 0x9C
10099
10100MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
10101
10102
10103
10104
10105MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
10106
10107#define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
10108
10109
10110
10111
10112
10113MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
10114
10115
10116
10117
10118MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
10119
10120
10121
10122
10123MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
10124
10125
10126
10127
10128MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
10129
10130static inline void mlxsw_reg_mgir_pack(char *payload)
10131{
10132 MLXSW_REG_ZERO(mgir, payload);
10133}
10134
10135static inline void
10136mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid,
10137 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor)
10138{
10139 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
10140 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
10141 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
10142 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
10143 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
10144}
10145
10146
10147
10148
10149
10150
10151#define MLXSW_REG_MRSR_ID 0x9023
10152#define MLXSW_REG_MRSR_LEN 0x08
10153
10154MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN);
10155
10156
10157
10158
10159
10160
10161
10162MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4);
10163
10164static inline void mlxsw_reg_mrsr_pack(char *payload)
10165{
10166 MLXSW_REG_ZERO(mrsr, payload);
10167 mlxsw_reg_mrsr_command_set(payload, 1);
10168}
10169
10170
10171
10172
10173
10174#define MLXSW_REG_MLCR_ID 0x902B
10175#define MLXSW_REG_MLCR_LEN 0x0C
10176
10177MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
10178
10179
10180
10181
10182
10183MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
10184
10185#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
10186
10187
10188
10189
10190
10191
10192
10193MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
10194
10195
10196
10197
10198
10199
10200MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
10201
10202static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
10203 bool active)
10204{
10205 MLXSW_REG_ZERO(mlcr, payload);
10206 mlxsw_reg_mlcr_local_port_set(payload, local_port);
10207 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
10208 MLXSW_REG_MLCR_DURATION_MAX : 0);
10209}
10210
10211
10212
10213
10214
10215
10216#define MLXSW_REG_MTPPS_ID 0x9053
10217#define MLXSW_REG_MTPPS_LEN 0x3C
10218
10219MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
10220
10221
10222
10223
10224
10225
10226MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
10227
10228enum mlxsw_reg_mtpps_pin_mode {
10229 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
10230};
10231
10232
10233
10234
10235
10236
10237MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
10238
10239#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
10240
10241
10242
10243
10244
10245MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
10246
10247
10248
10249
10250
10251
10252
10253
10254
10255MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
10256
10257static inline void
10258mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
10259{
10260 MLXSW_REG_ZERO(mtpps, payload);
10261 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
10262 mlxsw_reg_mtpps_pin_mode_set(payload,
10263 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
10264 mlxsw_reg_mtpps_enable_set(payload, true);
10265 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
10266}
10267
10268
10269
10270
10271
10272#define MLXSW_REG_MTUTC_ID 0x9055
10273#define MLXSW_REG_MTUTC_LEN 0x1C
10274
10275MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
10276
10277enum mlxsw_reg_mtutc_operation {
10278 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
10279 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
10280};
10281
10282
10283
10284
10285
10286MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
10287
10288
10289
10290
10291
10292
10293
10294MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
10295
10296
10297
10298
10299
10300MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
10301
10302static inline void
10303mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
10304 u32 freq_adj, u32 utc_sec)
10305{
10306 MLXSW_REG_ZERO(mtutc, payload);
10307 mlxsw_reg_mtutc_operation_set(payload, oper);
10308 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
10309 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
10310}
10311
10312
10313
10314
10315
10316#define MLXSW_REG_MCQI_ID 0x9061
10317#define MLXSW_REG_MCQI_BASE_LEN 0x18
10318#define MLXSW_REG_MCQI_CAP_LEN 0x14
10319#define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
10320
10321MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
10322
10323
10324
10325
10326
10327MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
10328
10329enum mlxfw_reg_mcqi_info_type {
10330 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
10331};
10332
10333
10334
10335
10336
10337MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
10338
10339
10340
10341
10342
10343
10344MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
10345
10346
10347
10348
10349
10350
10351MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
10352
10353
10354
10355
10356
10357MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
10358
10359
10360
10361
10362
10363
10364MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
10365
10366
10367
10368
10369
10370MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
10371
10372static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
10373{
10374 MLXSW_REG_ZERO(mcqi, payload);
10375 mlxsw_reg_mcqi_component_index_set(payload, component_index);
10376 mlxsw_reg_mcqi_info_type_set(payload,
10377 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
10378 mlxsw_reg_mcqi_offset_set(payload, 0);
10379 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
10380}
10381
10382static inline void mlxsw_reg_mcqi_unpack(char *payload,
10383 u32 *p_cap_max_component_size,
10384 u8 *p_cap_log_mcda_word_size,
10385 u16 *p_cap_mcda_max_write_size)
10386{
10387 *p_cap_max_component_size =
10388 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
10389 *p_cap_log_mcda_word_size =
10390 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
10391 *p_cap_mcda_max_write_size =
10392 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
10393}
10394
10395
10396
10397
10398
10399#define MLXSW_REG_MCC_ID 0x9062
10400#define MLXSW_REG_MCC_LEN 0x1C
10401
10402MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
10403
10404enum mlxsw_reg_mcc_instruction {
10405 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
10406 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
10407 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
10408 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
10409 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
10410 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
10411};
10412
10413
10414
10415
10416
10417
10418MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
10419
10420
10421
10422
10423
10424
10425MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
10426
10427
10428
10429
10430
10431MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
10432
10433
10434
10435
10436
10437
10438MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
10439
10440
10441
10442
10443
10444MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
10445
10446
10447
10448
10449
10450
10451
10452MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
10453
10454static inline void mlxsw_reg_mcc_pack(char *payload,
10455 enum mlxsw_reg_mcc_instruction instr,
10456 u16 component_index, u32 update_handle,
10457 u32 component_size)
10458{
10459 MLXSW_REG_ZERO(mcc, payload);
10460 mlxsw_reg_mcc_instruction_set(payload, instr);
10461 mlxsw_reg_mcc_component_index_set(payload, component_index);
10462 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
10463 mlxsw_reg_mcc_component_size_set(payload, component_size);
10464}
10465
10466static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
10467 u8 *p_error_code, u8 *p_control_state)
10468{
10469 if (p_update_handle)
10470 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
10471 if (p_error_code)
10472 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
10473 if (p_control_state)
10474 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
10475}
10476
10477
10478
10479
10480
10481#define MLXSW_REG_MCDA_ID 0x9063
10482#define MLXSW_REG_MCDA_BASE_LEN 0x10
10483#define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
10484#define MLXSW_REG_MCDA_LEN \
10485 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
10486
10487MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
10488
10489
10490
10491
10492
10493MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
10494
10495
10496
10497
10498
10499
10500MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
10501
10502
10503
10504
10505
10506MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
10507
10508
10509
10510
10511
10512MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
10513
10514static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
10515 u32 offset, u16 size, u8 *data)
10516{
10517 int i;
10518
10519 MLXSW_REG_ZERO(mcda, payload);
10520 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
10521 mlxsw_reg_mcda_offset_set(payload, offset);
10522 mlxsw_reg_mcda_size_set(payload, size);
10523
10524 for (i = 0; i < size / 4; i++)
10525 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
10526}
10527
10528
10529
10530
10531
10532#define MLXSW_REG_MPSC_ID 0x9080
10533#define MLXSW_REG_MPSC_LEN 0x1C
10534
10535MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
10536
10537
10538
10539
10540
10541
10542MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
10543
10544
10545
10546
10547
10548MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
10549
10550#define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
10551
10552
10553
10554
10555
10556
10557MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
10558
10559static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
10560 u32 rate)
10561{
10562 MLXSW_REG_ZERO(mpsc, payload);
10563 mlxsw_reg_mpsc_local_port_set(payload, local_port);
10564 mlxsw_reg_mpsc_e_set(payload, e);
10565 mlxsw_reg_mpsc_rate_set(payload, rate);
10566}
10567
10568
10569
10570
10571#define MLXSW_REG_MGPC_ID 0x9081
10572#define MLXSW_REG_MGPC_LEN 0x18
10573
10574MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
10575
10576
10577
10578
10579
10580MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
10581
10582
10583
10584
10585
10586MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
10587
10588enum mlxsw_reg_mgpc_opcode {
10589
10590 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
10591
10592 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
10593};
10594
10595
10596
10597
10598
10599MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
10600
10601
10602
10603
10604
10605MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
10606
10607
10608
10609
10610
10611MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
10612
10613static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
10614 enum mlxsw_reg_mgpc_opcode opcode,
10615 enum mlxsw_reg_flow_counter_set_type set_type)
10616{
10617 MLXSW_REG_ZERO(mgpc, payload);
10618 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
10619 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
10620 mlxsw_reg_mgpc_opcode_set(payload, opcode);
10621}
10622
10623
10624
10625
10626
10627
10628#define MLXSW_REG_MPRS_ID 0x9083
10629#define MLXSW_REG_MPRS_LEN 0x14
10630
10631MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
10632
10633
10634
10635
10636
10637
10638
10639MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
10640
10641
10642
10643
10644
10645
10646
10647MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
10648
10649
10650
10651
10652
10653
10654
10655MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
10656
10657static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
10658 u16 vxlan_udp_dport)
10659{
10660 MLXSW_REG_ZERO(mprs, payload);
10661 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
10662 mlxsw_reg_mprs_parsing_en_set(payload, true);
10663 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
10664}
10665
10666
10667
10668
10669#define MLXSW_REG_MOGCR_ID 0x9086
10670#define MLXSW_REG_MOGCR_LEN 0x20
10671
10672MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
10673
10674
10675
10676
10677
10678
10679
10680
10681MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
10682
10683
10684
10685
10686
10687
10688
10689
10690MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
10691
10692
10693
10694
10695
10696
10697
10698MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
10699
10700
10701
10702
10703
10704
10705#define MLXSW_REG_MPAGR_ID 0x9089
10706#define MLXSW_REG_MPAGR_LEN 0x0C
10707
10708MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN);
10709
10710enum mlxsw_reg_mpagr_trigger {
10711 MLXSW_REG_MPAGR_TRIGGER_EGRESS,
10712 MLXSW_REG_MPAGR_TRIGGER_INGRESS,
10713 MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED,
10714 MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER,
10715 MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG,
10716 MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG,
10717 MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN,
10718 MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY,
10719};
10720
10721
10722
10723
10724
10725MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);
10726
10727
10728
10729
10730
10731MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);
10732
10733#define MLXSW_REG_MPAGR_RATE_MAX 3500000000UL
10734
10735
10736
10737
10738
10739
10740
10741MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);
10742
10743static inline void mlxsw_reg_mpagr_pack(char *payload,
10744 enum mlxsw_reg_mpagr_trigger trigger,
10745 u8 pa_id, u32 probability_rate)
10746{
10747 MLXSW_REG_ZERO(mpagr, payload);
10748 mlxsw_reg_mpagr_trigger_set(payload, trigger);
10749 mlxsw_reg_mpagr_pa_id_set(payload, pa_id);
10750 mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate);
10751}
10752
10753
10754
10755
10756
10757
10758#define MLXSW_REG_MOMTE_ID 0x908D
10759#define MLXSW_REG_MOMTE_LEN 0x10
10760
10761MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN);
10762
10763
10764
10765
10766
10767MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8);
10768
10769enum mlxsw_reg_momte_type {
10770 MLXSW_REG_MOMTE_TYPE_WRED = 0x20,
10771 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31,
10772 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32,
10773 MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33,
10774 MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40,
10775 MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50,
10776 MLXSW_REG_MOMTE_TYPE_ECN = 0x60,
10777 MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70,
10778};
10779
10780
10781
10782
10783
10784MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);
10785
10786
10787
10788
10789
10790
10791
10792MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
10793
10794static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port,
10795 enum mlxsw_reg_momte_type type)
10796{
10797 MLXSW_REG_ZERO(momte, payload);
10798 mlxsw_reg_momte_local_port_set(payload, local_port);
10799 mlxsw_reg_momte_type_set(payload, type);
10800}
10801
10802
10803
10804
10805
10806
10807
10808
10809#define MLXSW_REG_MTPPPC_ID 0x9090
10810#define MLXSW_REG_MTPPPC_LEN 0x28
10811
10812MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
10813
10814
10815
10816
10817
10818
10819
10820
10821MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
10822
10823
10824
10825
10826
10827
10828
10829
10830MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
10831
10832static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
10833{
10834 MLXSW_REG_ZERO(mtpppc, payload);
10835 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
10836 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
10837}
10838
10839
10840
10841
10842
10843
10844
10845
10846
10847
10848
10849#define MLXSW_REG_MTPPTR_ID 0x9091
10850#define MLXSW_REG_MTPPTR_BASE_LEN 0x10
10851#define MLXSW_REG_MTPPTR_REC_LEN 0x10
10852#define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
10853#define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
10854 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
10855
10856MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
10857
10858
10859
10860
10861
10862MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
10863
10864enum mlxsw_reg_mtpptr_dir {
10865 MLXSW_REG_MTPPTR_DIR_INGRESS,
10866 MLXSW_REG_MTPPTR_DIR_EGRESS,
10867};
10868
10869
10870
10871
10872
10873MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
10874
10875
10876
10877
10878
10879MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
10880
10881
10882
10883
10884
10885
10886MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
10887
10888
10889
10890
10891
10892
10893MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
10894 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
10895 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
10896
10897
10898
10899
10900
10901MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
10902 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
10903 MLXSW_REG_MTPPTR_REC_LEN, 0, false);
10904
10905
10906
10907
10908
10909MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
10910 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
10911 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
10912
10913
10914
10915
10916
10917
10918
10919MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
10920 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
10921 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
10922
10923
10924
10925
10926
10927MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
10928 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
10929 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
10930
10931static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
10932 unsigned int rec,
10933 u8 *p_message_type,
10934 u8 *p_domain_number,
10935 u16 *p_sequence_id,
10936 u64 *p_timestamp)
10937{
10938 u32 timestamp_high, timestamp_low;
10939
10940 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
10941 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
10942 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
10943 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
10944 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
10945 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low;
10946}
10947
10948
10949
10950
10951
10952
10953#define MLXSW_REG_MTPTPT_ID 0x9092
10954#define MLXSW_REG_MTPTPT_LEN 0x08
10955
10956MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
10957
10958enum mlxsw_reg_mtptpt_trap_id {
10959 MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
10960 MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
10961};
10962
10963
10964
10965
10966
10967MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
10968
10969
10970
10971
10972
10973
10974
10975MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
10976
10977static inline void mlxsw_reg_mtptptp_pack(char *payload,
10978 enum mlxsw_reg_mtptpt_trap_id trap_id,
10979 u16 message_type)
10980{
10981 MLXSW_REG_ZERO(mtptpt, payload);
10982 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
10983 mlxsw_reg_mtptpt_message_type_set(payload, message_type);
10984}
10985
10986
10987
10988
10989#define MLXSW_REG_MFGD_ID 0x90F0
10990#define MLXSW_REG_MFGD_LEN 0x0C
10991
10992MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN);
10993
10994
10995
10996
10997
10998
10999MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);
11000
11001
11002
11003
11004MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);
11005
11006
11007
11008
11009
11010
11011#define MLXSW_REG_MGPIR_ID 0x9100
11012#define MLXSW_REG_MGPIR_LEN 0xA0
11013
11014MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
11015
11016enum mlxsw_reg_mgpir_device_type {
11017 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
11018 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
11019};
11020
11021
11022
11023
11024MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
11025
11026
11027
11028
11029
11030MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
11031
11032
11033
11034
11035
11036MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
11037
11038
11039
11040
11041
11042MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
11043
11044static inline void mlxsw_reg_mgpir_pack(char *payload)
11045{
11046 MLXSW_REG_ZERO(mgpir, payload);
11047}
11048
11049static inline void
11050mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
11051 enum mlxsw_reg_mgpir_device_type *device_type,
11052 u8 *devices_per_flash, u8 *num_of_modules)
11053{
11054 if (num_of_devices)
11055 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
11056 if (device_type)
11057 *device_type = mlxsw_reg_mgpir_device_type_get(payload);
11058 if (devices_per_flash)
11059 *devices_per_flash =
11060 mlxsw_reg_mgpir_devices_per_flash_get(payload);
11061 if (num_of_modules)
11062 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
11063}
11064
11065
11066
11067
11068#define MLXSW_REG_MFDE_ID 0x9200
11069#define MLXSW_REG_MFDE_LEN 0x18
11070
11071MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
11072
11073
11074
11075
11076
11077MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 24, 8);
11078
11079enum mlxsw_reg_mfde_event_id {
11080 MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
11081
11082 MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,
11083};
11084
11085
11086
11087
11088MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 16);
11089
11090enum mlxsw_reg_mfde_method {
11091 MLXSW_REG_MFDE_METHOD_QUERY,
11092 MLXSW_REG_MFDE_METHOD_WRITE,
11093};
11094
11095
11096
11097
11098MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);
11099
11100
11101
11102
11103
11104MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);
11105
11106enum mlxsw_reg_mfde_command_type {
11107 MLXSW_REG_MFDE_COMMAND_TYPE_MAD,
11108 MLXSW_REG_MFDE_COMMAND_TYPE_EMAD,
11109 MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF,
11110};
11111
11112
11113
11114
11115MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
11116
11117
11118
11119
11120
11121MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
11122
11123
11124
11125
11126
11127
11128MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32);
11129
11130
11131
11132
11133
11134
11135MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4);
11136
11137
11138
11139
11140
11141
11142MLXSW_ITEM64(reg, mfde, log_ip, 0x18, 0, 64);
11143
11144
11145
11146
11147
11148MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16);
11149
11150
11151
11152
11153
11154#define MLXSW_REG_TNGCR_ID 0xA001
11155#define MLXSW_REG_TNGCR_LEN 0x44
11156
11157MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
11158
11159enum mlxsw_reg_tngcr_type {
11160 MLXSW_REG_TNGCR_TYPE_VXLAN,
11161 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
11162 MLXSW_REG_TNGCR_TYPE_GENEVE,
11163 MLXSW_REG_TNGCR_TYPE_NVGRE,
11164};
11165
11166
11167
11168
11169
11170
11171
11172MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
11173
11174
11175
11176
11177
11178MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
11179
11180
11181
11182
11183
11184MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
11185
11186
11187
11188
11189
11190MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
11191
11192enum {
11193
11194 MLXSW_REG_TNGCR_FL_NO_COPY,
11195
11196
11197
11198
11199 MLXSW_REG_TNGCR_FL_COPY,
11200};
11201
11202
11203
11204
11205
11206MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
11207
11208enum {
11209
11210
11211
11212 MLXSW_REG_TNGCR_FL_NO_HASH,
11213
11214
11215
11216 MLXSW_REG_TNGCR_FL_HASH,
11217};
11218
11219
11220
11221
11222
11223MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
11224
11225
11226
11227
11228
11229MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
11230
11231
11232
11233
11234
11235
11236MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
11237
11238enum {
11239
11240 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
11241
11242 MLXSW_REG_TNGCR_UDP_SPORT_HASH,
11243};
11244
11245
11246
11247
11248
11249
11250
11251
11252
11253MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
11254
11255
11256
11257
11258
11259
11260MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
11261
11262
11263
11264
11265
11266
11267
11268
11269
11270MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
11271
11272
11273
11274
11275
11276
11277
11278
11279
11280MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
11281
11282
11283
11284
11285
11286
11287MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
11288
11289
11290
11291
11292
11293
11294MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
11295
11296
11297
11298
11299
11300
11301MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
11302
11303
11304
11305
11306
11307MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
11308
11309
11310
11311
11312
11313
11314MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
11315
11316static inline void mlxsw_reg_tngcr_pack(char *payload,
11317 enum mlxsw_reg_tngcr_type type,
11318 bool valid, u8 ttl)
11319{
11320 MLXSW_REG_ZERO(tngcr, payload);
11321 mlxsw_reg_tngcr_type_set(payload, type);
11322 mlxsw_reg_tngcr_nve_valid_set(payload, valid);
11323 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
11324 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
11325 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
11326 mlxsw_reg_tngcr_nve_flh_set(payload, 0);
11327 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
11328 MLXSW_REG_TNGCR_UDP_SPORT_HASH);
11329 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
11330 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
11331 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
11332}
11333
11334
11335
11336
11337
11338
11339#define MLXSW_REG_TNUMT_ID 0xA003
11340#define MLXSW_REG_TNUMT_LEN 0x20
11341
11342MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
11343
11344enum mlxsw_reg_tnumt_record_type {
11345 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
11346 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
11347 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
11348};
11349
11350
11351
11352
11353
11354MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
11355
11356
11357
11358
11359
11360MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
11361
11362
11363
11364
11365
11366
11367MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
11368
11369
11370
11371
11372
11373MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
11374
11375
11376
11377
11378
11379MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
11380
11381
11382
11383
11384
11385
11386MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
11387
11388
11389
11390
11391
11392MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
11393
11394
11395
11396
11397
11398
11399MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
11400
11401static inline void mlxsw_reg_tnumt_pack(char *payload,
11402 enum mlxsw_reg_tnumt_record_type type,
11403 enum mlxsw_reg_tunnel_port tport,
11404 u32 underlay_mc_ptr, bool vnext,
11405 u32 next_underlay_mc_ptr,
11406 u8 record_size)
11407{
11408 MLXSW_REG_ZERO(tnumt, payload);
11409 mlxsw_reg_tnumt_record_type_set(payload, type);
11410 mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
11411 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
11412 mlxsw_reg_tnumt_vnext_set(payload, vnext);
11413 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
11414 mlxsw_reg_tnumt_record_size_set(payload, record_size);
11415}
11416
11417
11418
11419
11420
11421
11422#define MLXSW_REG_TNQCR_ID 0xA010
11423#define MLXSW_REG_TNQCR_LEN 0x0C
11424
11425MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
11426
11427
11428
11429
11430
11431
11432
11433
11434MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
11435
11436static inline void mlxsw_reg_tnqcr_pack(char *payload)
11437{
11438 MLXSW_REG_ZERO(tnqcr, payload);
11439 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
11440}
11441
11442
11443
11444
11445
11446
11447#define MLXSW_REG_TNQDR_ID 0xA011
11448#define MLXSW_REG_TNQDR_LEN 0x08
11449
11450MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
11451
11452
11453
11454
11455
11456MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
11457
11458
11459
11460
11461
11462MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
11463
11464static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
11465{
11466 MLXSW_REG_ZERO(tnqdr, payload);
11467 mlxsw_reg_tnqdr_local_port_set(payload, local_port);
11468 mlxsw_reg_tnqdr_dscp_set(payload, 0);
11469}
11470
11471
11472
11473
11474
11475
11476#define MLXSW_REG_TNEEM_ID 0xA012
11477#define MLXSW_REG_TNEEM_LEN 0x0C
11478
11479MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
11480
11481
11482
11483
11484
11485MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
11486
11487
11488
11489
11490
11491MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
11492
11493static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
11494 u8 underlay_ecn)
11495{
11496 MLXSW_REG_ZERO(tneem, payload);
11497 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
11498 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
11499}
11500
11501
11502
11503
11504
11505
11506#define MLXSW_REG_TNDEM_ID 0xA013
11507#define MLXSW_REG_TNDEM_LEN 0x0C
11508
11509MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
11510
11511
11512
11513
11514
11515MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
11516
11517
11518
11519
11520
11521MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
11522
11523
11524
11525
11526
11527
11528MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
11529
11530
11531
11532
11533
11534
11535
11536MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
11537
11538
11539
11540
11541
11542
11543MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
11544
11545static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
11546 u8 overlay_ecn, u8 ecn, bool trap_en,
11547 u16 trap_id)
11548{
11549 MLXSW_REG_ZERO(tndem, payload);
11550 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
11551 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
11552 mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
11553 mlxsw_reg_tndem_trap_en_set(payload, trap_en);
11554 mlxsw_reg_tndem_trap_id_set(payload, trap_id);
11555}
11556
11557
11558
11559
11560
11561
11562#define MLXSW_REG_TNPC_ID 0xA020
11563#define MLXSW_REG_TNPC_LEN 0x18
11564
11565MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
11566
11567
11568
11569
11570
11571MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
11572
11573
11574
11575
11576
11577MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
11578
11579
11580
11581
11582
11583MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
11584
11585static inline void mlxsw_reg_tnpc_pack(char *payload,
11586 enum mlxsw_reg_tunnel_port tport,
11587 bool learn_enable)
11588{
11589 MLXSW_REG_ZERO(tnpc, payload);
11590 mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
11591 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
11592 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
11593}
11594
11595
11596
11597
11598
11599#define MLXSW_REG_TIGCR_ID 0xA801
11600#define MLXSW_REG_TIGCR_LEN 0x10
11601
11602MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
11603
11604
11605
11606
11607
11608
11609MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
11610
11611
11612
11613
11614
11615
11616MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
11617
11618static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
11619{
11620 MLXSW_REG_ZERO(tigcr, payload);
11621 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
11622 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
11623}
11624
11625
11626
11627
11628
11629
11630#define MLXSW_REG_TIEEM_ID 0xA812
11631#define MLXSW_REG_TIEEM_LEN 0x0C
11632
11633MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);
11634
11635
11636
11637
11638
11639MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
11640
11641
11642
11643
11644
11645MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
11646
11647static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,
11648 u8 underlay_ecn)
11649{
11650 MLXSW_REG_ZERO(tieem, payload);
11651 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);
11652 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);
11653}
11654
11655
11656
11657
11658
11659
11660#define MLXSW_REG_TIDEM_ID 0xA813
11661#define MLXSW_REG_TIDEM_LEN 0x0C
11662
11663MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);
11664
11665
11666
11667
11668
11669MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
11670
11671
11672
11673
11674
11675MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
11676
11677
11678
11679
11680
11681
11682MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
11683
11684
11685
11686
11687
11688
11689
11690MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
11691
11692
11693
11694
11695
11696
11697MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
11698
11699static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,
11700 u8 overlay_ecn, u8 eip_ecn,
11701 bool trap_en, u16 trap_id)
11702{
11703 MLXSW_REG_ZERO(tidem, payload);
11704 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);
11705 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);
11706 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);
11707 mlxsw_reg_tidem_trap_en_set(payload, trap_en);
11708 mlxsw_reg_tidem_trap_id_set(payload, trap_id);
11709}
11710
11711
11712
11713
11714
11715#define MLXSW_REG_SBPR_ID 0xB001
11716#define MLXSW_REG_SBPR_LEN 0x14
11717
11718MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
11719
11720
11721enum mlxsw_reg_sbxx_dir {
11722 MLXSW_REG_SBXX_DIR_INGRESS,
11723 MLXSW_REG_SBXX_DIR_EGRESS,
11724};
11725
11726
11727
11728
11729
11730MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
11731
11732
11733
11734
11735
11736MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
11737
11738
11739
11740
11741
11742MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
11743
11744
11745
11746
11747
11748
11749MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
11750
11751enum mlxsw_reg_sbpr_mode {
11752 MLXSW_REG_SBPR_MODE_STATIC,
11753 MLXSW_REG_SBPR_MODE_DYNAMIC,
11754};
11755
11756
11757
11758
11759
11760MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
11761
11762static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
11763 enum mlxsw_reg_sbxx_dir dir,
11764 enum mlxsw_reg_sbpr_mode mode, u32 size,
11765 bool infi_size)
11766{
11767 MLXSW_REG_ZERO(sbpr, payload);
11768 mlxsw_reg_sbpr_pool_set(payload, pool);
11769 mlxsw_reg_sbpr_dir_set(payload, dir);
11770 mlxsw_reg_sbpr_mode_set(payload, mode);
11771 mlxsw_reg_sbpr_size_set(payload, size);
11772 mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
11773}
11774
11775
11776
11777
11778
11779
11780
11781#define MLXSW_REG_SBCM_ID 0xB002
11782#define MLXSW_REG_SBCM_LEN 0x28
11783
11784MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
11785
11786
11787
11788
11789
11790
11791
11792MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
11793
11794
11795
11796
11797
11798
11799
11800
11801
11802MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
11803
11804
11805
11806
11807
11808MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
11809
11810
11811
11812
11813
11814MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
11815
11816
11817#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
11818#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
11819
11820
11821
11822
11823
11824MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
11825
11826
11827
11828
11829
11830
11831
11832
11833
11834
11835
11836
11837
11838MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
11839
11840
11841
11842
11843
11844MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
11845
11846static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
11847 enum mlxsw_reg_sbxx_dir dir,
11848 u32 min_buff, u32 max_buff,
11849 bool infi_max, u8 pool)
11850{
11851 MLXSW_REG_ZERO(sbcm, payload);
11852 mlxsw_reg_sbcm_local_port_set(payload, local_port);
11853 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
11854 mlxsw_reg_sbcm_dir_set(payload, dir);
11855 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
11856 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
11857 mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
11858 mlxsw_reg_sbcm_pool_set(payload, pool);
11859}
11860
11861
11862
11863
11864
11865
11866
11867#define MLXSW_REG_SBPM_ID 0xB003
11868#define MLXSW_REG_SBPM_LEN 0x28
11869
11870MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
11871
11872
11873
11874
11875
11876
11877
11878MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
11879
11880
11881
11882
11883
11884MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
11885
11886
11887
11888
11889
11890MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
11891
11892
11893
11894
11895
11896MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
11897
11898
11899
11900
11901
11902
11903
11904MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
11905
11906
11907
11908
11909
11910
11911MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
11912
11913
11914
11915
11916
11917MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
11918
11919
11920
11921
11922
11923
11924
11925
11926
11927
11928
11929
11930MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
11931
11932static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
11933 enum mlxsw_reg_sbxx_dir dir, bool clr,
11934 u32 min_buff, u32 max_buff)
11935{
11936 MLXSW_REG_ZERO(sbpm, payload);
11937 mlxsw_reg_sbpm_local_port_set(payload, local_port);
11938 mlxsw_reg_sbpm_pool_set(payload, pool);
11939 mlxsw_reg_sbpm_dir_set(payload, dir);
11940 mlxsw_reg_sbpm_clr_set(payload, clr);
11941 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
11942 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
11943}
11944
11945static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
11946 u32 *p_max_buff_occupancy)
11947{
11948 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
11949 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
11950}
11951
11952
11953
11954
11955
11956
11957
11958#define MLXSW_REG_SBMM_ID 0xB004
11959#define MLXSW_REG_SBMM_LEN 0x28
11960
11961MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
11962
11963
11964
11965
11966
11967MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
11968
11969
11970
11971
11972
11973MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
11974
11975
11976
11977
11978
11979
11980
11981
11982
11983
11984
11985
11986MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
11987
11988
11989
11990
11991
11992MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
11993
11994static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
11995 u32 max_buff, u8 pool)
11996{
11997 MLXSW_REG_ZERO(sbmm, payload);
11998 mlxsw_reg_sbmm_prio_set(payload, prio);
11999 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
12000 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
12001 mlxsw_reg_sbmm_pool_set(payload, pool);
12002}
12003
12004
12005
12006
12007
12008
12009
12010
12011
12012#define MLXSW_REG_SBSR_ID 0xB005
12013#define MLXSW_REG_SBSR_BASE_LEN 0x5C
12014#define MLXSW_REG_SBSR_REC_LEN 0x8
12015#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
12016#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
12017 MLXSW_REG_SBSR_REC_LEN * \
12018 MLXSW_REG_SBSR_REC_MAX_COUNT)
12019
12020MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
12021
12022
12023
12024
12025
12026
12027
12028MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
12029
12030
12031
12032
12033
12034
12035
12036
12037MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
12038
12039
12040
12041
12042
12043
12044
12045
12046
12047MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
12048
12049
12050
12051
12052
12053
12054
12055
12056MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
12057
12058
12059
12060
12061
12062
12063
12064
12065
12066MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
12067
12068static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
12069{
12070 MLXSW_REG_ZERO(sbsr, payload);
12071 mlxsw_reg_sbsr_clr_set(payload, clr);
12072}
12073
12074
12075
12076
12077
12078MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12079 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
12080
12081
12082
12083
12084
12085
12086MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
12087 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
12088
12089static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
12090 u32 *p_buff_occupancy,
12091 u32 *p_max_buff_occupancy)
12092{
12093 *p_buff_occupancy =
12094 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
12095 *p_max_buff_occupancy =
12096 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
12097}
12098
12099
12100
12101
12102
12103
12104
12105
12106
12107#define MLXSW_REG_SBIB_ID 0xB006
12108#define MLXSW_REG_SBIB_LEN 0x10
12109
12110MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
12111
12112
12113
12114
12115
12116
12117MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
12118
12119
12120
12121
12122
12123
12124
12125MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
12126
12127static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
12128 u32 buff_size)
12129{
12130 MLXSW_REG_ZERO(sbib, payload);
12131 mlxsw_reg_sbib_local_port_set(payload, local_port);
12132 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
12133}
12134
12135static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
12136 MLXSW_REG(sgcr),
12137 MLXSW_REG(spad),
12138 MLXSW_REG(smid),
12139 MLXSW_REG(sspr),
12140 MLXSW_REG(sfdat),
12141 MLXSW_REG(sfd),
12142 MLXSW_REG(sfn),
12143 MLXSW_REG(spms),
12144 MLXSW_REG(spvid),
12145 MLXSW_REG(spvm),
12146 MLXSW_REG(spaft),
12147 MLXSW_REG(sfgc),
12148 MLXSW_REG(sftr),
12149 MLXSW_REG(sfdf),
12150 MLXSW_REG(sldr),
12151 MLXSW_REG(slcr),
12152 MLXSW_REG(slcor),
12153 MLXSW_REG(spmlr),
12154 MLXSW_REG(svfa),
12155 MLXSW_REG(spvtr),
12156 MLXSW_REG(svpe),
12157 MLXSW_REG(sfmr),
12158 MLXSW_REG(spvmlr),
12159 MLXSW_REG(spvc),
12160 MLXSW_REG(spevet),
12161 MLXSW_REG(cwtp),
12162 MLXSW_REG(cwtpm),
12163 MLXSW_REG(pgcr),
12164 MLXSW_REG(ppbt),
12165 MLXSW_REG(pacl),
12166 MLXSW_REG(pagt),
12167 MLXSW_REG(ptar),
12168 MLXSW_REG(ppbs),
12169 MLXSW_REG(prcr),
12170 MLXSW_REG(pefa),
12171 MLXSW_REG(pemrbt),
12172 MLXSW_REG(ptce2),
12173 MLXSW_REG(perpt),
12174 MLXSW_REG(peabfe),
12175 MLXSW_REG(perar),
12176 MLXSW_REG(ptce3),
12177 MLXSW_REG(percr),
12178 MLXSW_REG(pererp),
12179 MLXSW_REG(iedr),
12180 MLXSW_REG(qpts),
12181 MLXSW_REG(qpcr),
12182 MLXSW_REG(qtct),
12183 MLXSW_REG(qeec),
12184 MLXSW_REG(qrwe),
12185 MLXSW_REG(qpdsm),
12186 MLXSW_REG(qpdp),
12187 MLXSW_REG(qpdpm),
12188 MLXSW_REG(qtctm),
12189 MLXSW_REG(qpsc),
12190 MLXSW_REG(pmlp),
12191 MLXSW_REG(pmtu),
12192 MLXSW_REG(ptys),
12193 MLXSW_REG(ppad),
12194 MLXSW_REG(paos),
12195 MLXSW_REG(pfcc),
12196 MLXSW_REG(ppcnt),
12197 MLXSW_REG(plib),
12198 MLXSW_REG(pptb),
12199 MLXSW_REG(pbmc),
12200 MLXSW_REG(pspa),
12201 MLXSW_REG(pmaos),
12202 MLXSW_REG(pplr),
12203 MLXSW_REG(pmpe),
12204 MLXSW_REG(pddr),
12205 MLXSW_REG(pmtm),
12206 MLXSW_REG(htgt),
12207 MLXSW_REG(hpkt),
12208 MLXSW_REG(rgcr),
12209 MLXSW_REG(ritr),
12210 MLXSW_REG(rtar),
12211 MLXSW_REG(ratr),
12212 MLXSW_REG(rtdp),
12213 MLXSW_REG(ratrad),
12214 MLXSW_REG(rdpm),
12215 MLXSW_REG(ricnt),
12216 MLXSW_REG(rrcr),
12217 MLXSW_REG(ralta),
12218 MLXSW_REG(ralst),
12219 MLXSW_REG(raltb),
12220 MLXSW_REG(ralue),
12221 MLXSW_REG(rauht),
12222 MLXSW_REG(raleu),
12223 MLXSW_REG(rauhtd),
12224 MLXSW_REG(rigr2),
12225 MLXSW_REG(recr2),
12226 MLXSW_REG(rmft2),
12227 MLXSW_REG(rxlte),
12228 MLXSW_REG(rxltm),
12229 MLXSW_REG(rlcmld),
12230 MLXSW_REG(rlpmce),
12231 MLXSW_REG(xltq),
12232 MLXSW_REG(xmdr),
12233 MLXSW_REG(xrmt),
12234 MLXSW_REG(xralta),
12235 MLXSW_REG(xralst),
12236 MLXSW_REG(xraltb),
12237 MLXSW_REG(mfcr),
12238 MLXSW_REG(mfsc),
12239 MLXSW_REG(mfsm),
12240 MLXSW_REG(mfsl),
12241 MLXSW_REG(fore),
12242 MLXSW_REG(mtcap),
12243 MLXSW_REG(mtmp),
12244 MLXSW_REG(mtwe),
12245 MLXSW_REG(mtbr),
12246 MLXSW_REG(mcia),
12247 MLXSW_REG(mpat),
12248 MLXSW_REG(mpar),
12249 MLXSW_REG(mgir),
12250 MLXSW_REG(mrsr),
12251 MLXSW_REG(mlcr),
12252 MLXSW_REG(mtpps),
12253 MLXSW_REG(mtutc),
12254 MLXSW_REG(mpsc),
12255 MLXSW_REG(mcqi),
12256 MLXSW_REG(mcc),
12257 MLXSW_REG(mcda),
12258 MLXSW_REG(mgpc),
12259 MLXSW_REG(mprs),
12260 MLXSW_REG(mogcr),
12261 MLXSW_REG(mpagr),
12262 MLXSW_REG(momte),
12263 MLXSW_REG(mtpppc),
12264 MLXSW_REG(mtpptr),
12265 MLXSW_REG(mtptpt),
12266 MLXSW_REG(mfgd),
12267 MLXSW_REG(mgpir),
12268 MLXSW_REG(mfde),
12269 MLXSW_REG(tngcr),
12270 MLXSW_REG(tnumt),
12271 MLXSW_REG(tnqcr),
12272 MLXSW_REG(tnqdr),
12273 MLXSW_REG(tneem),
12274 MLXSW_REG(tndem),
12275 MLXSW_REG(tnpc),
12276 MLXSW_REG(tigcr),
12277 MLXSW_REG(tieem),
12278 MLXSW_REG(tidem),
12279 MLXSW_REG(sbpr),
12280 MLXSW_REG(sbcm),
12281 MLXSW_REG(sbpm),
12282 MLXSW_REG(sbmm),
12283 MLXSW_REG(sbsr),
12284 MLXSW_REG(sbib),
12285};
12286
12287static inline const char *mlxsw_reg_id_str(u16 reg_id)
12288{
12289 const struct mlxsw_reg_info *reg_info;
12290 int i;
12291
12292 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
12293 reg_info = mlxsw_reg_infos[i];
12294 if (reg_info->id == reg_id)
12295 return reg_info->name;
12296 }
12297 return "*UNKNOWN*";
12298}
12299
12300
12301
12302
12303
12304#define MLXSW_REG_PUDE_LEN 0x10
12305
12306
12307
12308
12309
12310MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
12311
12312
12313
12314
12315
12316MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
12317
12318
12319
12320
12321
12322
12323
12324
12325
12326
12327MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
12328
12329
12330
12331
12332
12333
12334
12335
12336
12337MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
12338
12339#endif
12340