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2#define VERSION "0.23"
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82#define dprintk(x...) do { } while (0)
83
84#include <linux/module.h>
85#include <linux/moduleparam.h>
86#include <linux/types.h>
87#include <linux/pci.h>
88#include <linux/dma-mapping.h>
89#include <linux/netdevice.h>
90#include <linux/etherdevice.h>
91#include <linux/delay.h>
92#include <linux/workqueue.h>
93#include <linux/init.h>
94#include <linux/interrupt.h>
95#include <linux/ip.h>
96#include <linux/in.h>
97#include <linux/compiler.h>
98#include <linux/prefetch.h>
99#include <linux/ethtool.h>
100#include <linux/sched.h>
101#include <linux/timer.h>
102#include <linux/if_vlan.h>
103#include <linux/rtnetlink.h>
104#include <linux/jiffies.h>
105#include <linux/slab.h>
106
107#include <asm/io.h>
108#include <linux/uaccess.h>
109
110#define DRV_NAME "ns83820"
111
112
113static int ihr = 2;
114static int reset_phy = 0;
115static int lnksts = 0;
116
117
118#undef Dprintk
119#define Dprintk dprintk
120
121
122#define RX_BUF_SIZE 1500
123#if IS_ENABLED(CONFIG_VLAN_8021Q)
124#define NS83820_VLAN_ACCEL_SUPPORT
125#endif
126
127
128#define NR_RX_DESC 64
129#define NR_TX_DESC 128
130
131
132#define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14)
133
134#define MIN_TX_DESC_FREE 8
135
136
137#define CFGCS 0x04
138
139#define CR_TXE 0x00000001
140#define CR_TXD 0x00000002
141
142
143
144#define CR_RXE 0x00000004
145#define CR_RXD 0x00000008
146#define CR_TXR 0x00000010
147#define CR_RXR 0x00000020
148#define CR_SWI 0x00000080
149#define CR_RST 0x00000100
150
151#define PTSCR_EEBIST_FAIL 0x00000001
152#define PTSCR_EEBIST_EN 0x00000002
153#define PTSCR_EELOAD_EN 0x00000004
154#define PTSCR_RBIST_FAIL 0x000001b8
155#define PTSCR_RBIST_DONE 0x00000200
156#define PTSCR_RBIST_EN 0x00000400
157#define PTSCR_RBIST_RST 0x00002000
158
159#define MEAR_EEDI 0x00000001
160#define MEAR_EEDO 0x00000002
161#define MEAR_EECLK 0x00000004
162#define MEAR_EESEL 0x00000008
163#define MEAR_MDIO 0x00000010
164#define MEAR_MDDIR 0x00000020
165#define MEAR_MDC 0x00000040
166
167#define ISR_TXDESC3 0x40000000
168#define ISR_TXDESC2 0x20000000
169#define ISR_TXDESC1 0x10000000
170#define ISR_TXDESC0 0x08000000
171#define ISR_RXDESC3 0x04000000
172#define ISR_RXDESC2 0x02000000
173#define ISR_RXDESC1 0x01000000
174#define ISR_RXDESC0 0x00800000
175#define ISR_TXRCMP 0x00400000
176#define ISR_RXRCMP 0x00200000
177#define ISR_DPERR 0x00100000
178#define ISR_SSERR 0x00080000
179#define ISR_RMABT 0x00040000
180#define ISR_RTABT 0x00020000
181#define ISR_RXSOVR 0x00010000
182#define ISR_HIBINT 0x00008000
183#define ISR_PHY 0x00004000
184#define ISR_PME 0x00002000
185#define ISR_SWI 0x00001000
186#define ISR_MIB 0x00000800
187#define ISR_TXURN 0x00000400
188#define ISR_TXIDLE 0x00000200
189#define ISR_TXERR 0x00000100
190#define ISR_TXDESC 0x00000080
191#define ISR_TXOK 0x00000040
192#define ISR_RXORN 0x00000020
193#define ISR_RXIDLE 0x00000010
194#define ISR_RXEARLY 0x00000008
195#define ISR_RXERR 0x00000004
196#define ISR_RXDESC 0x00000002
197#define ISR_RXOK 0x00000001
198
199#define TXCFG_CSI 0x80000000
200#define TXCFG_HBI 0x40000000
201#define TXCFG_MLB 0x20000000
202#define TXCFG_ATP 0x10000000
203#define TXCFG_ECRETRY 0x00800000
204#define TXCFG_BRST_DIS 0x00080000
205#define TXCFG_MXDMA1024 0x00000000
206#define TXCFG_MXDMA512 0x00700000
207#define TXCFG_MXDMA256 0x00600000
208#define TXCFG_MXDMA128 0x00500000
209#define TXCFG_MXDMA64 0x00400000
210#define TXCFG_MXDMA32 0x00300000
211#define TXCFG_MXDMA16 0x00200000
212#define TXCFG_MXDMA8 0x00100000
213
214#define CFG_LNKSTS 0x80000000
215#define CFG_SPDSTS 0x60000000
216#define CFG_SPDSTS1 0x40000000
217#define CFG_SPDSTS0 0x20000000
218#define CFG_DUPSTS 0x10000000
219#define CFG_TBI_EN 0x01000000
220#define CFG_MODE_1000 0x00400000
221
222
223#define CFG_AUTO_1000 0x00200000
224#define CFG_PINT_CTL 0x001c0000
225#define CFG_PINT_DUPSTS 0x00100000
226#define CFG_PINT_LNKSTS 0x00080000
227#define CFG_PINT_SPDSTS 0x00040000
228#define CFG_TMRTEST 0x00020000
229#define CFG_MRM_DIS 0x00010000
230#define CFG_MWI_DIS 0x00008000
231#define CFG_T64ADDR 0x00004000
232#define CFG_PCI64_DET 0x00002000
233#define CFG_DATA64_EN 0x00001000
234#define CFG_M64ADDR 0x00000800
235#define CFG_PHY_RST 0x00000400
236#define CFG_PHY_DIS 0x00000200
237#define CFG_EXTSTS_EN 0x00000100
238#define CFG_REQALG 0x00000080
239#define CFG_SB 0x00000040
240#define CFG_POW 0x00000020
241#define CFG_EXD 0x00000010
242#define CFG_PESEL 0x00000008
243#define CFG_BROM_DIS 0x00000004
244#define CFG_EXT_125 0x00000002
245#define CFG_BEM 0x00000001
246
247#define EXTSTS_UDPPKT 0x00200000
248#define EXTSTS_TCPPKT 0x00080000
249#define EXTSTS_IPPKT 0x00020000
250#define EXTSTS_VPKT 0x00010000
251#define EXTSTS_VTG_MASK 0x0000ffff
252
253#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
254
255#define MIBC_MIBS 0x00000008
256#define MIBC_ACLR 0x00000004
257#define MIBC_FRZ 0x00000002
258#define MIBC_WRN 0x00000001
259
260#define PCR_PSEN (1 << 31)
261#define PCR_PS_MCAST (1 << 30)
262#define PCR_PS_DA (1 << 29)
263#define PCR_STHI_8 (3 << 23)
264#define PCR_STLO_4 (1 << 23)
265#define PCR_FFHI_8K (3 << 21)
266#define PCR_FFLO_4K (1 << 21)
267#define PCR_PAUSE_CNT 0xFFFE
268
269#define RXCFG_AEP 0x80000000
270#define RXCFG_ARP 0x40000000
271#define RXCFG_STRIPCRC 0x20000000
272#define RXCFG_RX_FD 0x10000000
273#define RXCFG_ALP 0x08000000
274#define RXCFG_AIRL 0x04000000
275#define RXCFG_MXDMA512 0x00700000
276#define RXCFG_DRTH 0x0000003e
277#define RXCFG_DRTH0 0x00000002
278
279#define RFCR_RFEN 0x80000000
280#define RFCR_AAB 0x40000000
281#define RFCR_AAM 0x20000000
282#define RFCR_AAU 0x10000000
283#define RFCR_APM 0x08000000
284#define RFCR_APAT 0x07800000
285#define RFCR_APAT3 0x04000000
286#define RFCR_APAT2 0x02000000
287#define RFCR_APAT1 0x01000000
288#define RFCR_APAT0 0x00800000
289#define RFCR_AARP 0x00400000
290#define RFCR_MHEN 0x00200000
291#define RFCR_UHEN 0x00100000
292#define RFCR_ULM 0x00080000
293
294#define VRCR_RUDPE 0x00000080
295#define VRCR_RTCPE 0x00000040
296#define VRCR_RIPE 0x00000020
297#define VRCR_IPEN 0x00000010
298#define VRCR_DUTF 0x00000008
299#define VRCR_DVTF 0x00000004
300#define VRCR_VTREN 0x00000002
301#define VRCR_VTDEN 0x00000001
302
303#define VTCR_PPCHK 0x00000008
304#define VTCR_GCHK 0x00000004
305#define VTCR_VPPTI 0x00000002
306#define VTCR_VGTI 0x00000001
307
308#define CR 0x00
309#define CFG 0x04
310#define MEAR 0x08
311#define PTSCR 0x0c
312#define ISR 0x10
313#define IMR 0x14
314#define IER 0x18
315#define IHR 0x1c
316#define TXDP 0x20
317#define TXDP_HI 0x24
318#define TXCFG 0x28
319#define GPIOR 0x2c
320#define RXDP 0x30
321#define RXDP_HI 0x34
322#define RXCFG 0x38
323#define PQCR 0x3c
324#define WCSR 0x40
325#define PCR 0x44
326#define RFCR 0x48
327#define RFDR 0x4c
328
329#define SRR 0x58
330
331#define VRCR 0xbc
332#define VTCR 0xc0
333#define VDR 0xc4
334#define CCSR 0xcc
335
336#define TBICR 0xe0
337#define TBISR 0xe4
338#define TANAR 0xe8
339#define TANLPAR 0xec
340#define TANER 0xf0
341#define TESR 0xf4
342
343#define TBICR_MR_AN_ENABLE 0x00001000
344#define TBICR_MR_RESTART_AN 0x00000200
345
346#define TBISR_MR_LINK_STATUS 0x00000020
347#define TBISR_MR_AN_COMPLETE 0x00000004
348
349#define TANAR_PS2 0x00000100
350#define TANAR_PS1 0x00000080
351#define TANAR_HALF_DUP 0x00000040
352#define TANAR_FULL_DUP 0x00000020
353
354#define GPIOR_GP5_OE 0x00000200
355#define GPIOR_GP4_OE 0x00000100
356#define GPIOR_GP3_OE 0x00000080
357#define GPIOR_GP2_OE 0x00000040
358#define GPIOR_GP1_OE 0x00000020
359#define GPIOR_GP3_OUT 0x00000004
360#define GPIOR_GP1_OUT 0x00000001
361
362#define LINK_AUTONEGOTIATE 0x01
363#define LINK_DOWN 0x02
364#define LINK_UP 0x04
365
366#define HW_ADDR_LEN sizeof(dma_addr_t)
367#define desc_addr_set(desc, addr) \
368 do { \
369 ((desc)[0] = cpu_to_le32(addr)); \
370 if (HW_ADDR_LEN == 8) \
371 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
372 } while(0)
373#define desc_addr_get(desc) \
374 (le32_to_cpu((desc)[0]) | \
375 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
376
377#define DESC_LINK 0
378#define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
379#define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
380#define DESC_EXTSTS (DESC_CMDSTS + 4/4)
381
382#define CMDSTS_OWN 0x80000000
383#define CMDSTS_MORE 0x40000000
384#define CMDSTS_INTR 0x20000000
385#define CMDSTS_ERR 0x10000000
386#define CMDSTS_OK 0x08000000
387#define CMDSTS_RUNT 0x00200000
388#define CMDSTS_LEN_MASK 0x0000ffff
389
390#define CMDSTS_DEST_MASK 0x01800000
391#define CMDSTS_DEST_SELF 0x00800000
392#define CMDSTS_DEST_MULTI 0x01000000
393
394#define DESC_SIZE 8
395
396struct rx_info {
397 spinlock_t lock;
398 int up;
399 unsigned long idle;
400
401 struct sk_buff *skbs[NR_RX_DESC];
402
403 __le32 *next_rx_desc;
404 u16 next_rx, next_empty;
405
406 __le32 *descs;
407 dma_addr_t phy_descs;
408};
409
410
411struct ns83820 {
412 u8 __iomem *base;
413
414 struct pci_dev *pci_dev;
415 struct net_device *ndev;
416
417 struct rx_info rx_info;
418 struct tasklet_struct rx_tasklet;
419
420 unsigned ihr;
421 struct work_struct tq_refill;
422
423
424 spinlock_t misc_lock;
425
426 u32 CFG_cache;
427
428 u32 MEAR_cache;
429 u32 IMR_cache;
430
431 unsigned linkstate;
432
433 spinlock_t tx_lock;
434
435 u16 tx_done_idx;
436 u16 tx_idx;
437 volatile u16 tx_free_idx;
438 u16 tx_intr_idx;
439
440 atomic_t nr_tx_skbs;
441 struct sk_buff *tx_skbs[NR_TX_DESC];
442
443 char pad[16] __attribute__((aligned(16)));
444 __le32 *tx_descs;
445 dma_addr_t tx_phy_descs;
446
447 struct timer_list tx_watchdog;
448};
449
450static inline struct ns83820 *PRIV(struct net_device *dev)
451{
452 return netdev_priv(dev);
453}
454
455#define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
456
457static inline void kick_rx(struct net_device *ndev)
458{
459 struct ns83820 *dev = PRIV(ndev);
460 dprintk("kick_rx: maybe kicking\n");
461 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
462 dprintk("actually kicking\n");
463 writel(dev->rx_info.phy_descs +
464 (4 * DESC_SIZE * dev->rx_info.next_rx),
465 dev->base + RXDP);
466 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
467 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
468 ndev->name);
469 __kick_rx(dev);
470 }
471}
472
473
474#define start_tx_okay(dev) \
475 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
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490static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
491{
492 desc_addr_set(desc + DESC_LINK, link);
493 desc_addr_set(desc + DESC_BUFPTR, buf);
494 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
495 mb();
496 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
497}
498
499#define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
500static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
501{
502 unsigned next_empty;
503 u32 cmdsts;
504 __le32 *sg;
505 dma_addr_t buf;
506
507 next_empty = dev->rx_info.next_empty;
508
509
510 if (unlikely(nr_rx_empty(dev) <= 2)) {
511 kfree_skb(skb);
512 return 1;
513 }
514
515#if 0
516 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
517 dev->rx_info.next_empty,
518 dev->rx_info.nr_used,
519 dev->rx_info.next_rx
520 );
521#endif
522
523 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
524 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
525 dev->rx_info.skbs[next_empty] = skb;
526
527 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
528 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
529 buf = dma_map_single(&dev->pci_dev->dev, skb->data, REAL_RX_BUF_SIZE,
530 DMA_FROM_DEVICE);
531 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
532
533 if (likely(next_empty != dev->rx_info.next_rx))
534 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
535
536 return 0;
537}
538
539static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
540{
541 struct ns83820 *dev = PRIV(ndev);
542 unsigned i;
543 unsigned long flags = 0;
544
545 if (unlikely(nr_rx_empty(dev) <= 2))
546 return 0;
547
548 dprintk("rx_refill(%p)\n", ndev);
549 if (gfp == GFP_ATOMIC)
550 spin_lock_irqsave(&dev->rx_info.lock, flags);
551 for (i=0; i<NR_RX_DESC; i++) {
552 struct sk_buff *skb;
553 long res;
554
555
556 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp);
557 if (unlikely(!skb))
558 break;
559
560 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16));
561 if (gfp != GFP_ATOMIC)
562 spin_lock_irqsave(&dev->rx_info.lock, flags);
563 res = ns83820_add_rx_skb(dev, skb);
564 if (gfp != GFP_ATOMIC)
565 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
566 if (res) {
567 i = 1;
568 break;
569 }
570 }
571 if (gfp == GFP_ATOMIC)
572 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
573
574 return i ? 0 : -ENOMEM;
575}
576
577static void rx_refill_atomic(struct net_device *ndev)
578{
579 rx_refill(ndev, GFP_ATOMIC);
580}
581
582
583static inline void queue_refill(struct work_struct *work)
584{
585 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
586 struct net_device *ndev = dev->ndev;
587
588 rx_refill(ndev, GFP_KERNEL);
589 if (dev->rx_info.up)
590 kick_rx(ndev);
591}
592
593static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
594{
595 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
596}
597
598static void phy_intr(struct net_device *ndev)
599{
600 struct ns83820 *dev = PRIV(ndev);
601 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
602 u32 cfg, new_cfg;
603 u32 tanar, tanlpar;
604 int speed, fullduplex, newlinkstate;
605
606 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
607
608 if (dev->CFG_cache & CFG_TBI_EN) {
609 u32 __maybe_unused tbisr;
610
611
612 tbisr = readl(dev->base + TBISR);
613 tanar = readl(dev->base + TANAR);
614 tanlpar = readl(dev->base + TANLPAR);
615 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
616 tbisr, tanar, tanlpar);
617
618 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) &&
619 (tanar & TANAR_FULL_DUP)) ) {
620
621
622 writel(readl(dev->base + TXCFG)
623 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
624 dev->base + TXCFG);
625 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
626 dev->base + RXCFG);
627
628 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
629 dev->base + GPIOR);
630
631 } else if (((tanlpar & TANAR_HALF_DUP) &&
632 (tanar & TANAR_HALF_DUP)) ||
633 ((tanlpar & TANAR_FULL_DUP) &&
634 (tanar & TANAR_HALF_DUP)) ||
635 ((tanlpar & TANAR_HALF_DUP) &&
636 (tanar & TANAR_FULL_DUP))) {
637
638
639 writel((readl(dev->base + TXCFG)
640 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
641 dev->base + TXCFG);
642 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
643 dev->base + RXCFG);
644
645 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
646 dev->base + GPIOR);
647 }
648
649 speed = 4;
650
651 } else {
652
653 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
654
655 if (cfg & CFG_SPDSTS1)
656 new_cfg |= CFG_MODE_1000;
657 else
658 new_cfg &= ~CFG_MODE_1000;
659
660 speed = ((cfg / CFG_SPDSTS0) & 3);
661 fullduplex = (cfg & CFG_DUPSTS);
662
663 if (fullduplex) {
664 new_cfg |= CFG_SB;
665 writel(readl(dev->base + TXCFG)
666 | TXCFG_CSI | TXCFG_HBI,
667 dev->base + TXCFG);
668 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
669 dev->base + RXCFG);
670 } else {
671 writel(readl(dev->base + TXCFG)
672 & ~(TXCFG_CSI | TXCFG_HBI),
673 dev->base + TXCFG);
674 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
675 dev->base + RXCFG);
676 }
677
678 if ((cfg & CFG_LNKSTS) &&
679 ((new_cfg ^ dev->CFG_cache) != 0)) {
680 writel(new_cfg, dev->base + CFG);
681 dev->CFG_cache = new_cfg;
682 }
683
684 dev->CFG_cache &= ~CFG_SPDSTS;
685 dev->CFG_cache |= cfg & CFG_SPDSTS;
686 }
687
688 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
689
690 if (newlinkstate & LINK_UP &&
691 dev->linkstate != newlinkstate) {
692 netif_start_queue(ndev);
693 netif_wake_queue(ndev);
694 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
695 ndev->name,
696 speeds[speed],
697 fullduplex ? "full" : "half");
698 } else if (newlinkstate & LINK_DOWN &&
699 dev->linkstate != newlinkstate) {
700 netif_stop_queue(ndev);
701 printk(KERN_INFO "%s: link now down.\n", ndev->name);
702 }
703
704 dev->linkstate = newlinkstate;
705}
706
707static int ns83820_setup_rx(struct net_device *ndev)
708{
709 struct ns83820 *dev = PRIV(ndev);
710 unsigned i;
711 int ret;
712
713 dprintk("ns83820_setup_rx(%p)\n", ndev);
714
715 dev->rx_info.idle = 1;
716 dev->rx_info.next_rx = 0;
717 dev->rx_info.next_rx_desc = dev->rx_info.descs;
718 dev->rx_info.next_empty = 0;
719
720 for (i=0; i<NR_RX_DESC; i++)
721 clear_rx_desc(dev, i);
722
723 writel(0, dev->base + RXDP_HI);
724 writel(dev->rx_info.phy_descs, dev->base + RXDP);
725
726 ret = rx_refill(ndev, GFP_KERNEL);
727 if (!ret) {
728 dprintk("starting receiver\n");
729
730 spin_lock_irq(&dev->rx_info.lock);
731
732 writel(0x0001, dev->base + CCSR);
733 writel(0, dev->base + RFCR);
734 writel(0x7fc00000, dev->base + RFCR);
735 writel(0xffc00000, dev->base + RFCR);
736
737 dev->rx_info.up = 1;
738
739 phy_intr(ndev);
740
741
742 spin_lock(&dev->misc_lock);
743 dev->IMR_cache |= ISR_PHY;
744 dev->IMR_cache |= ISR_RXRCMP;
745
746
747 dev->IMR_cache |= ISR_RXORN;
748 dev->IMR_cache |= ISR_RXSOVR;
749 dev->IMR_cache |= ISR_RXDESC;
750 dev->IMR_cache |= ISR_RXIDLE;
751 dev->IMR_cache |= ISR_TXDESC;
752 dev->IMR_cache |= ISR_TXIDLE;
753
754 writel(dev->IMR_cache, dev->base + IMR);
755 writel(1, dev->base + IER);
756 spin_unlock(&dev->misc_lock);
757
758 kick_rx(ndev);
759
760 spin_unlock_irq(&dev->rx_info.lock);
761 }
762 return ret;
763}
764
765static void ns83820_cleanup_rx(struct ns83820 *dev)
766{
767 unsigned i;
768 unsigned long flags;
769
770 dprintk("ns83820_cleanup_rx(%p)\n", dev);
771
772
773 spin_lock_irqsave(&dev->misc_lock, flags);
774 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
775 writel(dev->IMR_cache, dev->base + IMR);
776 spin_unlock_irqrestore(&dev->misc_lock, flags);
777
778
779 dev->rx_info.up = 0;
780 synchronize_irq(dev->pci_dev->irq);
781
782
783 readl(dev->base + IMR);
784
785
786 writel(0, dev->base + RXDP_HI);
787 writel(0, dev->base + RXDP);
788
789 for (i=0; i<NR_RX_DESC; i++) {
790 struct sk_buff *skb = dev->rx_info.skbs[i];
791 dev->rx_info.skbs[i] = NULL;
792 clear_rx_desc(dev, i);
793 kfree_skb(skb);
794 }
795}
796
797static void ns83820_rx_kick(struct net_device *ndev)
798{
799 struct ns83820 *dev = PRIV(ndev);
800 {
801 if (dev->rx_info.up) {
802 rx_refill_atomic(ndev);
803 kick_rx(ndev);
804 }
805 }
806
807 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
808 schedule_work(&dev->tq_refill);
809 else
810 kick_rx(ndev);
811 if (dev->rx_info.idle)
812 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
813}
814
815
816
817
818static void rx_irq(struct net_device *ndev)
819{
820 struct ns83820 *dev = PRIV(ndev);
821 struct rx_info *info = &dev->rx_info;
822 unsigned next_rx;
823 int rx_rc, len;
824 u32 cmdsts;
825 __le32 *desc;
826 unsigned long flags;
827 int nr = 0;
828
829 dprintk("rx_irq(%p)\n", ndev);
830 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
831 readl(dev->base + RXDP),
832 (long)(dev->rx_info.phy_descs),
833 (int)dev->rx_info.next_rx,
834 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
835 (int)dev->rx_info.next_empty,
836 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
837 );
838
839 spin_lock_irqsave(&info->lock, flags);
840 if (!info->up)
841 goto out;
842
843 dprintk("walking descs\n");
844 next_rx = info->next_rx;
845 desc = info->next_rx_desc;
846 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
847 (cmdsts != CMDSTS_OWN)) {
848 struct sk_buff *skb;
849 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
850 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
851
852 dprintk("cmdsts: %08x\n", cmdsts);
853 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
854 dprintk("extsts: %08x\n", extsts);
855
856 skb = info->skbs[next_rx];
857 info->skbs[next_rx] = NULL;
858 info->next_rx = (next_rx + 1) % NR_RX_DESC;
859
860 mb();
861 clear_rx_desc(dev, next_rx);
862
863 dma_unmap_single(&dev->pci_dev->dev, bufptr, RX_BUF_SIZE,
864 DMA_FROM_DEVICE);
865 len = cmdsts & CMDSTS_LEN_MASK;
866#ifdef NS83820_VLAN_ACCEL_SUPPORT
867
868
869
870
871
872
873
874
875
876
877
878 if (likely((CMDSTS_OK & cmdsts) ||
879 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
880#else
881 if (likely(CMDSTS_OK & cmdsts)) {
882#endif
883 skb_put(skb, len);
884 if (unlikely(!skb))
885 goto netdev_mangle_me_harder_failed;
886 if (cmdsts & CMDSTS_DEST_MULTI)
887 ndev->stats.multicast++;
888 ndev->stats.rx_packets++;
889 ndev->stats.rx_bytes += len;
890 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
891 skb->ip_summed = CHECKSUM_UNNECESSARY;
892 } else {
893 skb_checksum_none_assert(skb);
894 }
895 skb->protocol = eth_type_trans(skb, ndev);
896#ifdef NS83820_VLAN_ACCEL_SUPPORT
897 if(extsts & EXTSTS_VPKT) {
898 unsigned short tag;
899
900 tag = ntohs(extsts & EXTSTS_VTG_MASK);
901 __vlan_hwaccel_put_tag(skb, htons(ETH_P_IPV6), tag);
902 }
903#endif
904 rx_rc = netif_rx(skb);
905 if (NET_RX_DROP == rx_rc) {
906netdev_mangle_me_harder_failed:
907 ndev->stats.rx_dropped++;
908 }
909 } else {
910 dev_kfree_skb_irq(skb);
911 }
912
913 nr++;
914 next_rx = info->next_rx;
915 desc = info->descs + (DESC_SIZE * next_rx);
916 }
917 info->next_rx = next_rx;
918 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
919
920out:
921 if (0 && !nr) {
922 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
923 }
924
925 spin_unlock_irqrestore(&info->lock, flags);
926}
927
928static void rx_action(struct tasklet_struct *t)
929{
930 struct ns83820 *dev = from_tasklet(dev, t, rx_tasklet);
931 struct net_device *ndev = dev->ndev;
932 rx_irq(ndev);
933 writel(ihr, dev->base + IHR);
934
935 spin_lock_irq(&dev->misc_lock);
936 dev->IMR_cache |= ISR_RXDESC;
937 writel(dev->IMR_cache, dev->base + IMR);
938 spin_unlock_irq(&dev->misc_lock);
939
940 rx_irq(ndev);
941 ns83820_rx_kick(ndev);
942}
943
944
945
946static inline void kick_tx(struct ns83820 *dev)
947{
948 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
949 dev, dev->tx_idx, dev->tx_free_idx);
950 writel(CR_TXE, dev->base + CR);
951}
952
953
954
955
956static void do_tx_done(struct net_device *ndev)
957{
958 struct ns83820 *dev = PRIV(ndev);
959 u32 cmdsts, tx_done_idx;
960 __le32 *desc;
961
962 dprintk("do_tx_done(%p)\n", ndev);
963 tx_done_idx = dev->tx_done_idx;
964 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
965
966 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
967 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
968 while ((tx_done_idx != dev->tx_free_idx) &&
969 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
970 struct sk_buff *skb;
971 unsigned len;
972 dma_addr_t addr;
973
974 if (cmdsts & CMDSTS_ERR)
975 ndev->stats.tx_errors++;
976 if (cmdsts & CMDSTS_OK)
977 ndev->stats.tx_packets++;
978 if (cmdsts & CMDSTS_OK)
979 ndev->stats.tx_bytes += cmdsts & 0xffff;
980
981 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
982 tx_done_idx, dev->tx_free_idx, cmdsts);
983 skb = dev->tx_skbs[tx_done_idx];
984 dev->tx_skbs[tx_done_idx] = NULL;
985 dprintk("done(%p)\n", skb);
986
987 len = cmdsts & CMDSTS_LEN_MASK;
988 addr = desc_addr_get(desc + DESC_BUFPTR);
989 if (skb) {
990 dma_unmap_single(&dev->pci_dev->dev, addr, len,
991 DMA_TO_DEVICE);
992 dev_consume_skb_irq(skb);
993 atomic_dec(&dev->nr_tx_skbs);
994 } else
995 dma_unmap_page(&dev->pci_dev->dev, addr, len,
996 DMA_TO_DEVICE);
997
998 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
999 dev->tx_done_idx = tx_done_idx;
1000 desc[DESC_CMDSTS] = cpu_to_le32(0);
1001 mb();
1002 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1003 }
1004
1005
1006
1007
1008 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1009 dprintk("start_queue(%p)\n", ndev);
1010 netif_start_queue(ndev);
1011 netif_wake_queue(ndev);
1012 }
1013}
1014
1015static void ns83820_cleanup_tx(struct ns83820 *dev)
1016{
1017 unsigned i;
1018
1019 for (i=0; i<NR_TX_DESC; i++) {
1020 struct sk_buff *skb = dev->tx_skbs[i];
1021 dev->tx_skbs[i] = NULL;
1022 if (skb) {
1023 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1024 dma_unmap_single(&dev->pci_dev->dev,
1025 desc_addr_get(desc + DESC_BUFPTR),
1026 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1027 DMA_TO_DEVICE);
1028 dev_kfree_skb_irq(skb);
1029 atomic_dec(&dev->nr_tx_skbs);
1030 }
1031 }
1032
1033 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1034}
1035
1036
1037
1038
1039
1040
1041
1042static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb,
1043 struct net_device *ndev)
1044{
1045 struct ns83820 *dev = PRIV(ndev);
1046 u32 free_idx, cmdsts, extsts;
1047 int nr_free, nr_frags;
1048 unsigned tx_done_idx, last_idx;
1049 dma_addr_t buf;
1050 unsigned len;
1051 skb_frag_t *frag;
1052 int stopped = 0;
1053 int do_intr = 0;
1054 volatile __le32 *first_desc;
1055
1056 dprintk("ns83820_hard_start_xmit\n");
1057
1058 nr_frags = skb_shinfo(skb)->nr_frags;
1059again:
1060 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1061 netif_stop_queue(ndev);
1062 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1063 return NETDEV_TX_BUSY;
1064 netif_start_queue(ndev);
1065 }
1066
1067 last_idx = free_idx = dev->tx_free_idx;
1068 tx_done_idx = dev->tx_done_idx;
1069 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1070 nr_free -= 1;
1071 if (nr_free <= nr_frags) {
1072 dprintk("stop_queue - not enough(%p)\n", ndev);
1073 netif_stop_queue(ndev);
1074
1075
1076 if (dev->tx_done_idx != tx_done_idx) {
1077 dprintk("restart queue(%p)\n", ndev);
1078 netif_start_queue(ndev);
1079 goto again;
1080 }
1081 return NETDEV_TX_BUSY;
1082 }
1083
1084 if (free_idx == dev->tx_intr_idx) {
1085 do_intr = 1;
1086 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1087 }
1088
1089 nr_free -= nr_frags;
1090 if (nr_free < MIN_TX_DESC_FREE) {
1091 dprintk("stop_queue - last entry(%p)\n", ndev);
1092 netif_stop_queue(ndev);
1093 stopped = 1;
1094 }
1095
1096 frag = skb_shinfo(skb)->frags;
1097 if (!nr_frags)
1098 frag = NULL;
1099 extsts = 0;
1100 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1101 extsts |= EXTSTS_IPPKT;
1102 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1103 extsts |= EXTSTS_TCPPKT;
1104 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1105 extsts |= EXTSTS_UDPPKT;
1106 }
1107
1108#ifdef NS83820_VLAN_ACCEL_SUPPORT
1109 if (skb_vlan_tag_present(skb)) {
1110
1111
1112
1113
1114 short tag = skb_vlan_tag_get(skb);
1115 extsts |= (EXTSTS_VPKT | htons(tag));
1116 }
1117#endif
1118
1119 len = skb->len;
1120 if (nr_frags)
1121 len -= skb->data_len;
1122 buf = dma_map_single(&dev->pci_dev->dev, skb->data, len,
1123 DMA_TO_DEVICE);
1124
1125 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1126
1127 for (;;) {
1128 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1129
1130 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1131 (unsigned long long)buf);
1132 last_idx = free_idx;
1133 free_idx = (free_idx + 1) % NR_TX_DESC;
1134 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1135 desc_addr_set(desc + DESC_BUFPTR, buf);
1136 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1137
1138 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1139 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1140 cmdsts |= len;
1141 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1142
1143 if (!nr_frags)
1144 break;
1145
1146 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0,
1147 skb_frag_size(frag), DMA_TO_DEVICE);
1148 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1149 (long long)buf, (long) page_to_pfn(frag->page),
1150 frag->page_offset);
1151 len = skb_frag_size(frag);
1152 frag++;
1153 nr_frags--;
1154 }
1155 dprintk("done pkt\n");
1156
1157 spin_lock_irq(&dev->tx_lock);
1158 dev->tx_skbs[last_idx] = skb;
1159 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1160 dev->tx_free_idx = free_idx;
1161 atomic_inc(&dev->nr_tx_skbs);
1162 spin_unlock_irq(&dev->tx_lock);
1163
1164 kick_tx(dev);
1165
1166
1167 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1168 netif_start_queue(ndev);
1169
1170 return NETDEV_TX_OK;
1171}
1172
1173static void ns83820_update_stats(struct ns83820 *dev)
1174{
1175 struct net_device *ndev = dev->ndev;
1176 u8 __iomem *base = dev->base;
1177
1178
1179 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1180 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1181 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1182 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1183 readl(base + 0x70);
1184 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1185 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1186 readl(base + 0x7c);
1187 readl(base + 0x80);
1188 readl(base + 0x84);
1189 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1190}
1191
1192static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1193{
1194 struct ns83820 *dev = PRIV(ndev);
1195
1196
1197 spin_lock_irq(&dev->misc_lock);
1198 ns83820_update_stats(dev);
1199 spin_unlock_irq(&dev->misc_lock);
1200
1201 return &ndev->stats;
1202}
1203
1204
1205static int ns83820_get_link_ksettings(struct net_device *ndev,
1206 struct ethtool_link_ksettings *cmd)
1207{
1208 struct ns83820 *dev = PRIV(ndev);
1209 u32 cfg, tbicr;
1210 int fullduplex = 0;
1211 u32 supported;
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1228 readl(dev->base + TANAR);
1229 tbicr = readl(dev->base + TBICR);
1230
1231 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0;
1232
1233 supported = SUPPORTED_Autoneg;
1234
1235 if (dev->CFG_cache & CFG_TBI_EN) {
1236
1237 supported |= SUPPORTED_1000baseT_Half |
1238 SUPPORTED_1000baseT_Full |
1239 SUPPORTED_FIBRE;
1240 cmd->base.port = PORT_FIBRE;
1241 } else {
1242
1243 supported |= SUPPORTED_10baseT_Half |
1244 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half |
1245 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half |
1246 SUPPORTED_1000baseT_Full |
1247 SUPPORTED_MII;
1248 cmd->base.port = PORT_MII;
1249 }
1250
1251 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1252 supported);
1253
1254 cmd->base.duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF;
1255 switch (cfg / CFG_SPDSTS0 & 3) {
1256 case 2:
1257 cmd->base.speed = SPEED_1000;
1258 break;
1259 case 1:
1260 cmd->base.speed = SPEED_100;
1261 break;
1262 default:
1263 cmd->base.speed = SPEED_10;
1264 break;
1265 }
1266 cmd->base.autoneg = (tbicr & TBICR_MR_AN_ENABLE)
1267 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1268 return 0;
1269}
1270
1271
1272static int ns83820_set_link_ksettings(struct net_device *ndev,
1273 const struct ethtool_link_ksettings *cmd)
1274{
1275 struct ns83820 *dev = PRIV(ndev);
1276 u32 cfg, tanar;
1277 int have_optical = 0;
1278 int fullduplex = 0;
1279
1280
1281 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1282 tanar = readl(dev->base + TANAR);
1283
1284 if (dev->CFG_cache & CFG_TBI_EN) {
1285
1286 have_optical = 1;
1287 fullduplex = (tanar & TANAR_FULL_DUP);
1288
1289 } else {
1290
1291 fullduplex = cfg & CFG_DUPSTS;
1292 }
1293
1294 spin_lock_irq(&dev->misc_lock);
1295 spin_lock(&dev->tx_lock);
1296
1297
1298 if (cmd->base.duplex != fullduplex) {
1299 if (have_optical) {
1300
1301 if (cmd->base.duplex == DUPLEX_FULL) {
1302
1303 writel(readl(dev->base + TXCFG)
1304 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
1305 dev->base + TXCFG);
1306 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1307 dev->base + RXCFG);
1308
1309 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1310 dev->base + GPIOR);
1311 } else {
1312
1313 }
1314
1315 } else {
1316
1317
1318 }
1319 printk(KERN_INFO "%s: Duplex set via ethtool\n",
1320 ndev->name);
1321 }
1322
1323
1324 if (1) {
1325 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1326
1327 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1328 dev->base + TBICR);
1329 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1330 dev->linkstate = LINK_AUTONEGOTIATE;
1331
1332 printk(KERN_INFO "%s: autoneg enabled via ethtool\n",
1333 ndev->name);
1334 } else {
1335
1336 writel(0x00000000, dev->base + TBICR);
1337 }
1338
1339 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name,
1340 cmd->base.autoneg ? "ENABLED" : "DISABLED");
1341 }
1342
1343 phy_intr(ndev);
1344 spin_unlock(&dev->tx_lock);
1345 spin_unlock_irq(&dev->misc_lock);
1346
1347 return 0;
1348}
1349
1350
1351static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1352{
1353 struct ns83820 *dev = PRIV(ndev);
1354 strlcpy(info->driver, "ns83820", sizeof(info->driver));
1355 strlcpy(info->version, VERSION, sizeof(info->version));
1356 strlcpy(info->bus_info, pci_name(dev->pci_dev), sizeof(info->bus_info));
1357}
1358
1359static u32 ns83820_get_link(struct net_device *ndev)
1360{
1361 struct ns83820 *dev = PRIV(ndev);
1362 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1363 return cfg & CFG_LNKSTS ? 1 : 0;
1364}
1365
1366static const struct ethtool_ops ops = {
1367 .get_drvinfo = ns83820_get_drvinfo,
1368 .get_link = ns83820_get_link,
1369 .get_link_ksettings = ns83820_get_link_ksettings,
1370 .set_link_ksettings = ns83820_set_link_ksettings,
1371};
1372
1373static inline void ns83820_disable_interrupts(struct ns83820 *dev)
1374{
1375 writel(0, dev->base + IMR);
1376 writel(0, dev->base + IER);
1377 readl(dev->base + IER);
1378}
1379
1380
1381static void ns83820_mib_isr(struct ns83820 *dev)
1382{
1383 unsigned long flags;
1384 spin_lock_irqsave(&dev->misc_lock, flags);
1385 ns83820_update_stats(dev);
1386 spin_unlock_irqrestore(&dev->misc_lock, flags);
1387}
1388
1389static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1390static irqreturn_t ns83820_irq(int foo, void *data)
1391{
1392 struct net_device *ndev = data;
1393 struct ns83820 *dev = PRIV(ndev);
1394 u32 isr;
1395 dprintk("ns83820_irq(%p)\n", ndev);
1396
1397 dev->ihr = 0;
1398
1399 isr = readl(dev->base + ISR);
1400 dprintk("irq: %08x\n", isr);
1401 ns83820_do_isr(ndev, isr);
1402 return IRQ_HANDLED;
1403}
1404
1405static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1406{
1407 struct ns83820 *dev = PRIV(ndev);
1408 unsigned long flags;
1409
1410#ifdef DEBUG
1411 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1412 Dprintk("odd isr? 0x%08x\n", isr);
1413#endif
1414
1415 if (ISR_RXIDLE & isr) {
1416 dev->rx_info.idle = 1;
1417 Dprintk("oh dear, we are idle\n");
1418 ns83820_rx_kick(ndev);
1419 }
1420
1421 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1422 prefetch(dev->rx_info.next_rx_desc);
1423
1424 spin_lock_irqsave(&dev->misc_lock, flags);
1425 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1426 writel(dev->IMR_cache, dev->base + IMR);
1427 spin_unlock_irqrestore(&dev->misc_lock, flags);
1428
1429 tasklet_schedule(&dev->rx_tasklet);
1430
1431
1432 }
1433
1434 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1435 ns83820_rx_kick(ndev);
1436
1437 if (unlikely(ISR_RXSOVR & isr)) {
1438
1439 ndev->stats.rx_fifo_errors++;
1440 }
1441
1442 if (unlikely(ISR_RXORN & isr)) {
1443
1444 ndev->stats.rx_fifo_errors++;
1445 }
1446
1447 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1448 writel(CR_RXE, dev->base + CR);
1449
1450 if (ISR_TXIDLE & isr) {
1451 u32 txdp;
1452 txdp = readl(dev->base + TXDP);
1453 dprintk("txdp: %08x\n", txdp);
1454 txdp -= dev->tx_phy_descs;
1455 dev->tx_idx = txdp / (DESC_SIZE * 4);
1456 if (dev->tx_idx >= NR_TX_DESC) {
1457 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1458 dev->tx_idx = 0;
1459 }
1460
1461
1462
1463
1464
1465 if (dev->tx_idx != dev->tx_free_idx)
1466 kick_tx(dev);
1467 }
1468
1469
1470
1471
1472 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1473 spin_lock_irqsave(&dev->tx_lock, flags);
1474 do_tx_done(ndev);
1475 spin_unlock_irqrestore(&dev->tx_lock, flags);
1476
1477
1478
1479 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1480 (dev->IMR_cache & ISR_TXOK)) {
1481 spin_lock_irqsave(&dev->misc_lock, flags);
1482 dev->IMR_cache &= ~ISR_TXOK;
1483 writel(dev->IMR_cache, dev->base + IMR);
1484 spin_unlock_irqrestore(&dev->misc_lock, flags);
1485 }
1486 }
1487
1488
1489
1490
1491
1492
1493
1494 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1495 spin_lock_irqsave(&dev->misc_lock, flags);
1496 dev->IMR_cache |= ISR_TXOK;
1497 writel(dev->IMR_cache, dev->base + IMR);
1498 spin_unlock_irqrestore(&dev->misc_lock, flags);
1499 }
1500
1501
1502 if (unlikely(ISR_MIB & isr))
1503 ns83820_mib_isr(dev);
1504
1505
1506 if (unlikely(ISR_PHY & isr))
1507 phy_intr(ndev);
1508
1509#if 0
1510 if (dev->ihr)
1511 writel(dev->ihr, dev->base + IHR);
1512#endif
1513}
1514
1515static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1516{
1517 Dprintk("resetting chip...\n");
1518 writel(which, dev->base + CR);
1519 do {
1520 schedule();
1521 } while (readl(dev->base + CR) & which);
1522 Dprintk("okay!\n");
1523}
1524
1525static int ns83820_stop(struct net_device *ndev)
1526{
1527 struct ns83820 *dev = PRIV(ndev);
1528
1529
1530 del_timer_sync(&dev->tx_watchdog);
1531
1532 ns83820_disable_interrupts(dev);
1533
1534 dev->rx_info.up = 0;
1535 synchronize_irq(dev->pci_dev->irq);
1536
1537 ns83820_do_reset(dev, CR_RST);
1538
1539 synchronize_irq(dev->pci_dev->irq);
1540
1541 spin_lock_irq(&dev->misc_lock);
1542 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1543 spin_unlock_irq(&dev->misc_lock);
1544
1545 ns83820_cleanup_rx(dev);
1546 ns83820_cleanup_tx(dev);
1547
1548 return 0;
1549}
1550
1551static void ns83820_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1552{
1553 struct ns83820 *dev = PRIV(ndev);
1554 u32 tx_done_idx;
1555 __le32 *desc;
1556 unsigned long flags;
1557
1558 spin_lock_irqsave(&dev->tx_lock, flags);
1559
1560 tx_done_idx = dev->tx_done_idx;
1561 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1562
1563 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1564 ndev->name,
1565 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1566
1567#if defined(DEBUG)
1568 {
1569 u32 isr;
1570 isr = readl(dev->base + ISR);
1571 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1572 ns83820_do_isr(ndev, isr);
1573 }
1574#endif
1575
1576 do_tx_done(ndev);
1577
1578 tx_done_idx = dev->tx_done_idx;
1579 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1580
1581 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1582 ndev->name,
1583 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1584
1585 spin_unlock_irqrestore(&dev->tx_lock, flags);
1586}
1587
1588static void ns83820_tx_watch(struct timer_list *t)
1589{
1590 struct ns83820 *dev = from_timer(dev, t, tx_watchdog);
1591 struct net_device *ndev = dev->ndev;
1592
1593#if defined(DEBUG)
1594 printk("ns83820_tx_watch: %u %u %d\n",
1595 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1596 );
1597#endif
1598
1599 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) &&
1600 dev->tx_done_idx != dev->tx_free_idx) {
1601 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1602 ndev->name,
1603 dev->tx_done_idx, dev->tx_free_idx,
1604 atomic_read(&dev->nr_tx_skbs));
1605 ns83820_tx_timeout(ndev, UINT_MAX);
1606 }
1607
1608 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1609}
1610
1611static int ns83820_open(struct net_device *ndev)
1612{
1613 struct ns83820 *dev = PRIV(ndev);
1614 unsigned i;
1615 u32 desc;
1616 int ret;
1617
1618 dprintk("ns83820_open\n");
1619
1620 writel(0, dev->base + PQCR);
1621
1622 ret = ns83820_setup_rx(ndev);
1623 if (ret)
1624 goto failed;
1625
1626 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1627 for (i=0; i<NR_TX_DESC; i++) {
1628 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1629 = cpu_to_le32(
1630 dev->tx_phy_descs
1631 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1632 }
1633
1634 dev->tx_idx = 0;
1635 dev->tx_done_idx = 0;
1636 desc = dev->tx_phy_descs;
1637 writel(0, dev->base + TXDP_HI);
1638 writel(desc, dev->base + TXDP);
1639
1640 timer_setup(&dev->tx_watchdog, ns83820_tx_watch, 0);
1641 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1642
1643 netif_start_queue(ndev);
1644
1645 return 0;
1646
1647failed:
1648 ns83820_stop(ndev);
1649 return ret;
1650}
1651
1652static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1653{
1654 unsigned i;
1655 for (i=0; i<3; i++) {
1656 u32 data;
1657
1658
1659
1660
1661 writel(i*2, dev->base + RFCR);
1662 data = readl(dev->base + RFDR);
1663
1664 *mac++ = data;
1665 *mac++ = data >> 8;
1666 }
1667}
1668
1669static void ns83820_set_multicast(struct net_device *ndev)
1670{
1671 struct ns83820 *dev = PRIV(ndev);
1672 u8 __iomem *rfcr = dev->base + RFCR;
1673 u32 and_mask = 0xffffffff;
1674 u32 or_mask = 0;
1675 u32 val;
1676
1677 if (ndev->flags & IFF_PROMISC)
1678 or_mask |= RFCR_AAU | RFCR_AAM;
1679 else
1680 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1681
1682 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev))
1683 or_mask |= RFCR_AAM;
1684 else
1685 and_mask &= ~RFCR_AAM;
1686
1687 spin_lock_irq(&dev->misc_lock);
1688 val = (readl(rfcr) & and_mask) | or_mask;
1689
1690 writel(val & ~RFCR_RFEN, rfcr);
1691 writel(val, rfcr);
1692 spin_unlock_irq(&dev->misc_lock);
1693}
1694
1695static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1696{
1697 struct ns83820 *dev = PRIV(ndev);
1698 int timed_out = 0;
1699 unsigned long start;
1700 u32 status;
1701 int loops = 0;
1702
1703 dprintk("%s: start %s\n", ndev->name, name);
1704
1705 start = jiffies;
1706
1707 writel(enable, dev->base + PTSCR);
1708 for (;;) {
1709 loops++;
1710 status = readl(dev->base + PTSCR);
1711 if (!(status & enable))
1712 break;
1713 if (status & done)
1714 break;
1715 if (status & fail)
1716 break;
1717 if (time_after_eq(jiffies, start + HZ)) {
1718 timed_out = 1;
1719 break;
1720 }
1721 schedule_timeout_uninterruptible(1);
1722 }
1723
1724 if (status & fail)
1725 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1726 ndev->name, name, status, fail);
1727 else if (timed_out)
1728 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1729 ndev->name, name, status);
1730
1731 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1732}
1733
1734#ifdef PHY_CODE_IS_FINISHED
1735static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1736{
1737
1738 dev->MEAR_cache &= ~MEAR_MDC;
1739 writel(dev->MEAR_cache, dev->base + MEAR);
1740 readl(dev->base + MEAR);
1741
1742
1743 dev->MEAR_cache |= MEAR_MDDIR;
1744 if (bit)
1745 dev->MEAR_cache |= MEAR_MDIO;
1746 else
1747 dev->MEAR_cache &= ~MEAR_MDIO;
1748
1749
1750 writel(dev->MEAR_cache, dev->base + MEAR);
1751 readl(dev->base + MEAR);
1752
1753
1754 udelay(1);
1755
1756
1757 dev->MEAR_cache |= MEAR_MDC;
1758 writel(dev->MEAR_cache, dev->base + MEAR);
1759 readl(dev->base + MEAR);
1760
1761
1762 udelay(1);
1763}
1764
1765static int ns83820_mii_read_bit(struct ns83820 *dev)
1766{
1767 int bit;
1768
1769
1770 dev->MEAR_cache &= ~MEAR_MDC;
1771 dev->MEAR_cache &= ~MEAR_MDDIR;
1772 writel(dev->MEAR_cache, dev->base + MEAR);
1773 readl(dev->base + MEAR);
1774
1775
1776 udelay(1);
1777
1778
1779 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1780 dev->MEAR_cache |= MEAR_MDC;
1781 writel(dev->MEAR_cache, dev->base + MEAR);
1782
1783
1784 udelay(1);
1785
1786 return bit;
1787}
1788
1789static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1790{
1791 unsigned data = 0;
1792 int i;
1793
1794
1795 for (i=0; i<64; i++)
1796 ns83820_mii_read_bit(dev);
1797
1798 ns83820_mii_write_bit(dev, 0);
1799 ns83820_mii_write_bit(dev, 1);
1800 ns83820_mii_write_bit(dev, 1);
1801 ns83820_mii_write_bit(dev, 0);
1802
1803
1804 for (i=0; i<5; i++)
1805 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1806
1807
1808 for (i=0; i<5; i++)
1809 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1810
1811 ns83820_mii_read_bit(dev);
1812 ns83820_mii_read_bit(dev);
1813
1814
1815 for (i=0; i<16; i++) {
1816 data <<= 1;
1817 data |= ns83820_mii_read_bit(dev);
1818 }
1819
1820 return data;
1821}
1822
1823static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1824{
1825 int i;
1826
1827
1828 for (i=0; i<64; i++)
1829 ns83820_mii_read_bit(dev);
1830
1831 ns83820_mii_write_bit(dev, 0);
1832 ns83820_mii_write_bit(dev, 1);
1833 ns83820_mii_write_bit(dev, 0);
1834 ns83820_mii_write_bit(dev, 1);
1835
1836
1837 for (i=0; i<5; i++)
1838 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1839
1840
1841 for (i=0; i<5; i++)
1842 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1843
1844 ns83820_mii_read_bit(dev);
1845 ns83820_mii_read_bit(dev);
1846
1847
1848 for (i=0; i<16; i++)
1849 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1850
1851 return data;
1852}
1853
1854static void ns83820_probe_phy(struct net_device *ndev)
1855{
1856 struct ns83820 *dev = PRIV(ndev);
1857 int j;
1858 unsigned a, b;
1859
1860 for (j = 0; j < 0x16; j += 4) {
1861 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1862 ndev->name, j,
1863 ns83820_mii_read_reg(dev, 1, 0 + j),
1864 ns83820_mii_read_reg(dev, 1, 1 + j),
1865 ns83820_mii_read_reg(dev, 1, 2 + j),
1866 ns83820_mii_read_reg(dev, 1, 3 + j)
1867 );
1868 }
1869
1870
1871 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1872 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1873 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1874
1875 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1876 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1877 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1878 dprintk("version: 0x%04x 0x%04x\n", a, b);
1879}
1880#endif
1881
1882static const struct net_device_ops netdev_ops = {
1883 .ndo_open = ns83820_open,
1884 .ndo_stop = ns83820_stop,
1885 .ndo_start_xmit = ns83820_hard_start_xmit,
1886 .ndo_get_stats = ns83820_get_stats,
1887 .ndo_set_rx_mode = ns83820_set_multicast,
1888 .ndo_validate_addr = eth_validate_addr,
1889 .ndo_set_mac_address = eth_mac_addr,
1890 .ndo_tx_timeout = ns83820_tx_timeout,
1891};
1892
1893static int ns83820_init_one(struct pci_dev *pci_dev,
1894 const struct pci_device_id *id)
1895{
1896 struct net_device *ndev;
1897 struct ns83820 *dev;
1898 long addr;
1899 int err;
1900 int using_dac = 0;
1901
1902
1903 if (sizeof(dma_addr_t) == 8 &&
1904 !dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(64))) {
1905 using_dac = 1;
1906 } else if (!dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32))) {
1907 using_dac = 0;
1908 } else {
1909 dev_warn(&pci_dev->dev, "dma_set_mask failed!\n");
1910 return -ENODEV;
1911 }
1912
1913 ndev = alloc_etherdev(sizeof(struct ns83820));
1914 err = -ENOMEM;
1915 if (!ndev)
1916 goto out;
1917
1918 dev = PRIV(ndev);
1919 dev->ndev = ndev;
1920
1921 spin_lock_init(&dev->rx_info.lock);
1922 spin_lock_init(&dev->tx_lock);
1923 spin_lock_init(&dev->misc_lock);
1924 dev->pci_dev = pci_dev;
1925
1926 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1927
1928 INIT_WORK(&dev->tq_refill, queue_refill);
1929 tasklet_setup(&dev->rx_tasklet, rx_action);
1930
1931 err = pci_enable_device(pci_dev);
1932 if (err) {
1933 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1934 goto out_free;
1935 }
1936
1937 pci_set_master(pci_dev);
1938 addr = pci_resource_start(pci_dev, 1);
1939 dev->base = ioremap(addr, PAGE_SIZE);
1940 dev->tx_descs = dma_alloc_coherent(&pci_dev->dev,
1941 4 * DESC_SIZE * NR_TX_DESC,
1942 &dev->tx_phy_descs, GFP_KERNEL);
1943 dev->rx_info.descs = dma_alloc_coherent(&pci_dev->dev,
1944 4 * DESC_SIZE * NR_RX_DESC,
1945 &dev->rx_info.phy_descs, GFP_KERNEL);
1946 err = -ENOMEM;
1947 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1948 goto out_disable;
1949
1950 dprintk("%p: %08lx %p: %08lx\n",
1951 dev->tx_descs, (long)dev->tx_phy_descs,
1952 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1953
1954 ns83820_disable_interrupts(dev);
1955
1956 dev->IMR_cache = 0;
1957
1958 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1959 DRV_NAME, ndev);
1960 if (err) {
1961 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1962 pci_dev->irq, err);
1963 goto out_disable;
1964 }
1965
1966
1967
1968
1969
1970
1971
1972
1973 rtnl_lock();
1974 err = dev_alloc_name(ndev, ndev->name);
1975 if (err < 0) {
1976 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1977 goto out_free_irq;
1978 }
1979
1980 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1981 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1982 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1983
1984 ndev->netdev_ops = &netdev_ops;
1985 ndev->ethtool_ops = &ops;
1986 ndev->watchdog_timeo = 5 * HZ;
1987 pci_set_drvdata(pci_dev, ndev);
1988
1989 ns83820_do_reset(dev, CR_RST);
1990
1991
1992 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1993 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1994 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1995 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1996 PTSCR_EEBIST_FAIL);
1997 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1998
1999
2000 dev->CFG_cache = readl(dev->base + CFG);
2001
2002 if ((dev->CFG_cache & CFG_PCI64_DET)) {
2003 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
2004 ndev->name);
2005
2006 if (!(dev->CFG_cache & CFG_DATA64_EN))
2007 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
2008 ndev->name);
2009 } else
2010 dev->CFG_cache &= ~(CFG_DATA64_EN);
2011
2012 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
2013 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
2014 CFG_M64ADDR);
2015 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
2016 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
2017 dev->CFG_cache |= CFG_REQALG;
2018 dev->CFG_cache |= CFG_POW;
2019 dev->CFG_cache |= CFG_TMRTEST;
2020
2021
2022
2023
2024 if (sizeof(dma_addr_t) == 8)
2025 dev->CFG_cache |= CFG_M64ADDR;
2026 if (using_dac)
2027 dev->CFG_cache |= CFG_T64ADDR;
2028
2029
2030 dev->CFG_cache &= ~CFG_BEM;
2031
2032
2033 if (dev->CFG_cache & CFG_TBI_EN) {
2034 printk(KERN_INFO "%s: enabling optical transceiver\n",
2035 ndev->name);
2036 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2037
2038
2039 writel(readl(dev->base + TANAR)
2040 | TANAR_HALF_DUP | TANAR_FULL_DUP,
2041 dev->base + TANAR);
2042
2043
2044 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
2045 dev->base + TBICR);
2046 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2047 dev->linkstate = LINK_AUTONEGOTIATE;
2048
2049 dev->CFG_cache |= CFG_MODE_1000;
2050 }
2051
2052 writel(dev->CFG_cache, dev->base + CFG);
2053 dprintk("CFG: %08x\n", dev->CFG_cache);
2054
2055 if (reset_phy) {
2056 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
2057 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2058 msleep(10);
2059 writel(dev->CFG_cache, dev->base + CFG);
2060 }
2061
2062#if 0
2063
2064
2065 if (readl(dev->base + SRR))
2066 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2067#endif
2068
2069
2070
2071
2072
2073
2074
2075
2076 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2077 | ((1600 / 32) * 0x100),
2078 dev->base + TXCFG);
2079
2080
2081 writel(0x000, dev->base + IHR);
2082 writel(0x100, dev->base + IHR);
2083 writel(0x000, dev->base + IHR);
2084
2085
2086
2087
2088
2089
2090
2091 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2092 | RXCFG_STRIPCRC
2093
2094 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2095
2096
2097 writel(0, dev->base + PQCR);
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112#ifdef NS83820_VLAN_ACCEL_SUPPORT
2113#define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2114#else
2115#define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2116#endif
2117 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2118
2119
2120
2121
2122
2123#ifdef NS83820_VLAN_ACCEL_SUPPORT
2124#define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2125#else
2126#define VTCR_INIT_VALUE VTCR_PPCHK
2127#endif
2128 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2129
2130
2131
2132 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2133 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2134 dev->base + PCR);
2135
2136
2137 writel(0, dev->base + WCSR);
2138
2139 ns83820_getmac(dev, ndev->dev_addr);
2140
2141
2142 ndev->features |= NETIF_F_SG;
2143 ndev->features |= NETIF_F_IP_CSUM;
2144
2145 ndev->min_mtu = 0;
2146
2147#ifdef NS83820_VLAN_ACCEL_SUPPORT
2148
2149 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2150#endif
2151
2152 if (using_dac) {
2153 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2154 ndev->name);
2155 ndev->features |= NETIF_F_HIGHDMA;
2156 }
2157
2158 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n",
2159 ndev->name,
2160 (unsigned)readl(dev->base + SRR) >> 8,
2161 (unsigned)readl(dev->base + SRR) & 0xff,
2162 ndev->dev_addr, addr, pci_dev->irq,
2163 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2164 );
2165
2166#ifdef PHY_CODE_IS_FINISHED
2167 ns83820_probe_phy(ndev);
2168#endif
2169
2170 err = register_netdevice(ndev);
2171 if (err) {
2172 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2173 goto out_cleanup;
2174 }
2175 rtnl_unlock();
2176
2177 return 0;
2178
2179out_cleanup:
2180 ns83820_disable_interrupts(dev);
2181out_free_irq:
2182 rtnl_unlock();
2183 free_irq(pci_dev->irq, ndev);
2184out_disable:
2185 if (dev->base)
2186 iounmap(dev->base);
2187 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2188 dev->tx_descs, dev->tx_phy_descs);
2189 dma_free_coherent(&pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2190 dev->rx_info.descs, dev->rx_info.phy_descs);
2191 pci_disable_device(pci_dev);
2192out_free:
2193 free_netdev(ndev);
2194out:
2195 return err;
2196}
2197
2198static void ns83820_remove_one(struct pci_dev *pci_dev)
2199{
2200 struct net_device *ndev = pci_get_drvdata(pci_dev);
2201 struct ns83820 *dev = PRIV(ndev);
2202
2203 if (!ndev)
2204 return;
2205
2206 ns83820_disable_interrupts(dev);
2207
2208 unregister_netdev(ndev);
2209 free_irq(dev->pci_dev->irq, ndev);
2210 iounmap(dev->base);
2211 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_TX_DESC,
2212 dev->tx_descs, dev->tx_phy_descs);
2213 dma_free_coherent(&dev->pci_dev->dev, 4 * DESC_SIZE * NR_RX_DESC,
2214 dev->rx_info.descs, dev->rx_info.phy_descs);
2215 pci_disable_device(dev->pci_dev);
2216 free_netdev(ndev);
2217}
2218
2219static const struct pci_device_id ns83820_pci_tbl[] = {
2220 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2221 { 0, },
2222};
2223
2224static struct pci_driver driver = {
2225 .name = "ns83820",
2226 .id_table = ns83820_pci_tbl,
2227 .probe = ns83820_init_one,
2228 .remove = ns83820_remove_one,
2229#if 0
2230 .suspend = ,
2231 .resume = ,
2232#endif
2233};
2234
2235
2236static int __init ns83820_init(void)
2237{
2238 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2239 return pci_register_driver(&driver);
2240}
2241
2242static void __exit ns83820_exit(void)
2243{
2244 pci_unregister_driver(&driver);
2245}
2246
2247MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2248MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2249MODULE_LICENSE("GPL");
2250
2251MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2252
2253module_param(lnksts, int, 0);
2254MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2255
2256module_param(ihr, int, 0);
2257MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2258
2259module_param(reset_phy, int, 0);
2260MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2261
2262module_init(ns83820_init);
2263module_exit(ns83820_exit);
2264