linux/drivers/net/ethernet/neterion/vxge/vxge-traffic.h
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   1/******************************************************************************
   2 * This software may be used and distributed according to the terms of
   3 * the GNU General Public License (GPL), incorporated herein by reference.
   4 * Drivers based on or derived from this code fall under the GPL and must
   5 * retain the authorship, copyright and license notice.  This file is not
   6 * a complete program and may only be used when the entire operating
   7 * system is licensed under the GPL.
   8 * See the file COPYING in this distribution for more information.
   9 *
  10 * vxge-traffic.h: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
  11 *                 Virtualized Server Adapter.
  12 * Copyright(c) 2002-2010 Exar Corp.
  13 ******************************************************************************/
  14#ifndef VXGE_TRAFFIC_H
  15#define VXGE_TRAFFIC_H
  16
  17#include "vxge-reg.h"
  18#include "vxge-version.h"
  19
  20#define VXGE_HW_DTR_MAX_T_CODE          16
  21#define VXGE_HW_ALL_FOXES               0xFFFFFFFFFFFFFFFFULL
  22#define VXGE_HW_INTR_MASK_ALL           0xFFFFFFFFFFFFFFFFULL
  23#define VXGE_HW_MAX_VIRTUAL_PATHS       17
  24
  25#define VXGE_HW_MAC_MAX_MAC_PORT_ID     2
  26
  27#define VXGE_HW_DEFAULT_32              0xffffffff
  28/* frames sizes */
  29#define VXGE_HW_HEADER_802_2_SIZE       3
  30#define VXGE_HW_HEADER_SNAP_SIZE        5
  31#define VXGE_HW_HEADER_VLAN_SIZE        4
  32#define VXGE_HW_MAC_HEADER_MAX_SIZE \
  33                        (ETH_HLEN + \
  34                        VXGE_HW_HEADER_802_2_SIZE + \
  35                        VXGE_HW_HEADER_VLAN_SIZE + \
  36                        VXGE_HW_HEADER_SNAP_SIZE)
  37
  38/* 32bit alignments */
  39#define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN          2
  40#define VXGE_HW_HEADER_802_2_SNAP_ALIGN                 2
  41#define VXGE_HW_HEADER_802_2_ALIGN                      3
  42#define VXGE_HW_HEADER_SNAP_ALIGN                       1
  43
  44#define VXGE_HW_L3_CKSUM_OK                             0xFFFF
  45#define VXGE_HW_L4_CKSUM_OK                             0xFFFF
  46
  47/* Forward declarations */
  48struct __vxge_hw_device;
  49struct __vxge_hw_vpath_handle;
  50struct vxge_hw_vp_config;
  51struct __vxge_hw_virtualpath;
  52struct __vxge_hw_channel;
  53struct __vxge_hw_fifo;
  54struct __vxge_hw_ring;
  55struct vxge_hw_ring_attr;
  56struct vxge_hw_mempool;
  57
  58#ifndef TRUE
  59#define TRUE 1
  60#endif
  61
  62#ifndef FALSE
  63#define FALSE 0
  64#endif
  65
  66/*VXGE_HW_STATUS_H*/
  67
  68#define VXGE_HW_EVENT_BASE                      0
  69#define VXGE_LL_EVENT_BASE                      100
  70
  71/**
  72 * enum vxge_hw_event- Enumerates slow-path HW events.
  73 * @VXGE_HW_EVENT_UNKNOWN: Unknown (and invalid) event.
  74 * @VXGE_HW_EVENT_SERR: Serious vpath hardware error event.
  75 * @VXGE_HW_EVENT_ECCERR: vpath ECC error event.
  76 * @VXGE_HW_EVENT_VPATH_ERR: Error local to the respective vpath
  77 * @VXGE_HW_EVENT_FIFO_ERR: FIFO Doorbell fifo error.
  78 * @VXGE_HW_EVENT_SRPCIM_SERR: srpcim hardware error event.
  79 * @VXGE_HW_EVENT_MRPCIM_SERR: mrpcim hardware error event.
  80 * @VXGE_HW_EVENT_MRPCIM_ECCERR: mrpcim ecc error event.
  81 * @VXGE_HW_EVENT_RESET_START: Privileged entity is starting device reset
  82 * @VXGE_HW_EVENT_RESET_COMPLETE: Device reset has been completed
  83 * @VXGE_HW_EVENT_SLOT_FREEZE: Slot-freeze event. Driver tries to distinguish
  84 * slot-freeze from the rest critical events (e.g. ECC) when it is
  85 * impossible to PIO read "through" the bus, i.e. when getting all-foxes.
  86 *
  87 * enum vxge_hw_event enumerates slow-path HW eventis.
  88 *
  89 * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{},
  90 * vxge_uld_link_down_f{}.
  91 */
  92enum vxge_hw_event {
  93        VXGE_HW_EVENT_UNKNOWN           = 0,
  94        /* HW events */
  95        VXGE_HW_EVENT_RESET_START       = VXGE_HW_EVENT_BASE + 1,
  96        VXGE_HW_EVENT_RESET_COMPLETE    = VXGE_HW_EVENT_BASE + 2,
  97        VXGE_HW_EVENT_LINK_DOWN         = VXGE_HW_EVENT_BASE + 3,
  98        VXGE_HW_EVENT_LINK_UP           = VXGE_HW_EVENT_BASE + 4,
  99        VXGE_HW_EVENT_ALARM_CLEARED     = VXGE_HW_EVENT_BASE + 5,
 100        VXGE_HW_EVENT_ECCERR            = VXGE_HW_EVENT_BASE + 6,
 101        VXGE_HW_EVENT_MRPCIM_ECCERR     = VXGE_HW_EVENT_BASE + 7,
 102        VXGE_HW_EVENT_FIFO_ERR          = VXGE_HW_EVENT_BASE + 8,
 103        VXGE_HW_EVENT_VPATH_ERR         = VXGE_HW_EVENT_BASE + 9,
 104        VXGE_HW_EVENT_CRITICAL_ERR      = VXGE_HW_EVENT_BASE + 10,
 105        VXGE_HW_EVENT_SERR              = VXGE_HW_EVENT_BASE + 11,
 106        VXGE_HW_EVENT_SRPCIM_SERR       = VXGE_HW_EVENT_BASE + 12,
 107        VXGE_HW_EVENT_MRPCIM_SERR       = VXGE_HW_EVENT_BASE + 13,
 108        VXGE_HW_EVENT_SLOT_FREEZE       = VXGE_HW_EVENT_BASE + 14,
 109};
 110
 111#define VXGE_HW_SET_LEVEL(a, b) (((a) > (b)) ? (a) : (b))
 112
 113/*
 114 * struct vxge_hw_mempool_dma - Represents DMA objects passed to the
 115        caller.
 116 */
 117struct vxge_hw_mempool_dma {
 118        dma_addr_t                      addr;
 119        struct pci_dev *handle;
 120        struct pci_dev *acc_handle;
 121};
 122
 123/*
 124 * vxge_hw_mempool_item_f  - Mempool item alloc/free callback
 125 * @mempoolh: Memory pool handle.
 126 * @memblock: Address of memory block
 127 * @memblock_index: Index of memory block
 128 * @item: Item that gets allocated or freed.
 129 * @index: Item's index in the memory pool.
 130 * @is_last: True, if this item is the last one in the pool; false - otherwise.
 131 * userdata: Per-pool user context.
 132 *
 133 * Memory pool allocation/deallocation callback.
 134 */
 135
 136/*
 137 * struct vxge_hw_mempool - Memory pool.
 138 */
 139struct vxge_hw_mempool {
 140
 141        void (*item_func_alloc)(
 142        struct vxge_hw_mempool *mempoolh,
 143        u32                     memblock_index,
 144        struct vxge_hw_mempool_dma      *dma_object,
 145        u32                     index,
 146        u32                     is_last);
 147
 148        void            *userdata;
 149        void            **memblocks_arr;
 150        void            **memblocks_priv_arr;
 151        struct vxge_hw_mempool_dma      *memblocks_dma_arr;
 152        struct __vxge_hw_device *devh;
 153        u32                     memblock_size;
 154        u32                     memblocks_max;
 155        u32                     memblocks_allocated;
 156        u32                     item_size;
 157        u32                     items_max;
 158        u32                     items_initial;
 159        u32                     items_current;
 160        u32                     items_per_memblock;
 161        void            **items_arr;
 162        u32                     items_priv_size;
 163};
 164
 165#define VXGE_HW_MAX_INTR_PER_VP                         4
 166#define VXGE_HW_VPATH_INTR_TX                           0
 167#define VXGE_HW_VPATH_INTR_RX                           1
 168#define VXGE_HW_VPATH_INTR_EINTA                        2
 169#define VXGE_HW_VPATH_INTR_BMAP                         3
 170
 171#define VXGE_HW_BLOCK_SIZE                              4096
 172
 173/**
 174 * struct vxge_hw_tim_intr_config - Titan Tim interrupt configuration.
 175 * @intr_enable: Set to 1, if interrupt is enabled.
 176 * @btimer_val: Boundary Timer Initialization value in units of 272 ns.
 177 * @timer_ac_en: Timer Automatic Cancel. 1 : Automatic Canceling Enable: when
 178 *             asserted, other interrupt-generating entities will cancel the
 179 *             scheduled timer interrupt.
 180 * @timer_ci_en: Timer Continuous Interrupt. 1 : Continuous Interrupting Enable:
 181 *             When asserted, an interrupt will be generated every time the
 182 *             boundary timer expires, even if no traffic has been transmitted
 183 *             on this interrupt.
 184 * @timer_ri_en: Timer Consecutive (Re-) Interrupt 1 : Consecutive
 185 *             (Re-) Interrupt Enable: When asserted, an interrupt will be
 186 *             generated the next time the timer expires, even if no traffic has
 187 *             been transmitted on this interrupt. (This will only happen once
 188 *             each time that this value is written to the TIM.) This bit is
 189 *             cleared by H/W at the end of the current-timer-interval when
 190 *             the interrupt is triggered.
 191 * @rtimer_val: Restriction Timer Initialization value in units of 272 ns.
 192 * @util_sel: Utilization Selector. Selects which of the workload approximations
 193 *             to use (e.g. legacy Tx utilization, Tx/Rx utilization, host
 194 *             specified utilization etc.), selects one of
 195 *             the 17 host configured values.
 196 *             0-Virtual Path 0
 197 *             1-Virtual Path 1
 198 *             ...
 199 *             16-Virtual Path 17
 200 *             17-Legacy Tx network utilization, provided by TPA
 201 *             18-Legacy Rx network utilization, provided by FAU
 202 *             19-Average of legacy Rx and Tx utilization calculated from link
 203 *                utilization values.
 204 *             20-31-Invalid configurations
 205 *             32-Host utilization for Virtual Path 0
 206 *             33-Host utilization for Virtual Path 1
 207 *             ...
 208 *             48-Host utilization for Virtual Path 17
 209 *             49-Legacy Tx network utilization, provided by TPA
 210 *             50-Legacy Rx network utilization, provided by FAU
 211 *             51-Average of legacy Rx and Tx utilization calculated from
 212 *                link utilization values.
 213 *             52-63-Invalid configurations
 214 * @ltimer_val: Latency Timer Initialization Value in units of 272 ns.
 215 * @txd_cnt_en: TxD Return Event Count Enable. This configuration bit when set
 216 *             to 1 enables counting of TxD0 returns (signalled by PCC's),
 217 *             towards utilization event count values.
 218 * @urange_a: Defines the upper limit (in percent) for this utilization range
 219 *             to be active. This range is considered active
 220 *             if 0 = UTIL = URNG_A
 221 *             and the UEC_A field (below) is non-zero.
 222 * @uec_a: Utilization Event Count A. If this range is active, the adapter will
 223 *             wait until UEC_A events have occurred on the interrupt before
 224 *             generating an interrupt.
 225 * @urange_b: Link utilization range B.
 226 * @uec_b: Utilization Event Count B.
 227 * @urange_c: Link utilization range C.
 228 * @uec_c: Utilization Event Count C.
 229 * @urange_d: Link utilization range D.
 230 * @uec_d: Utilization Event Count D.
 231 * Traffic Interrupt Controller Module interrupt configuration.
 232 */
 233struct vxge_hw_tim_intr_config {
 234
 235        u32                             intr_enable;
 236#define VXGE_HW_TIM_INTR_ENABLE                         1
 237#define VXGE_HW_TIM_INTR_DISABLE                                0
 238#define VXGE_HW_TIM_INTR_DEFAULT                                0
 239
 240        u32                             btimer_val;
 241#define VXGE_HW_MIN_TIM_BTIMER_VAL                              0
 242#define VXGE_HW_MAX_TIM_BTIMER_VAL                              67108864
 243#define VXGE_HW_USE_FLASH_DEFAULT                               (~0)
 244
 245        u32                             timer_ac_en;
 246#define VXGE_HW_TIM_TIMER_AC_ENABLE                             1
 247#define VXGE_HW_TIM_TIMER_AC_DISABLE                            0
 248
 249        u32                             timer_ci_en;
 250#define VXGE_HW_TIM_TIMER_CI_ENABLE                             1
 251#define VXGE_HW_TIM_TIMER_CI_DISABLE                            0
 252
 253        u32                             timer_ri_en;
 254#define VXGE_HW_TIM_TIMER_RI_ENABLE                             1
 255#define VXGE_HW_TIM_TIMER_RI_DISABLE                            0
 256
 257        u32                             rtimer_val;
 258#define VXGE_HW_MIN_TIM_RTIMER_VAL                              0
 259#define VXGE_HW_MAX_TIM_RTIMER_VAL                              67108864
 260
 261        u32                             util_sel;
 262#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL         17
 263#define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL         18
 264#define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL          19
 265#define VXGE_HW_TIM_UTIL_SEL_PER_VPATH                          63
 266
 267        u32                             ltimer_val;
 268#define VXGE_HW_MIN_TIM_LTIMER_VAL                              0
 269#define VXGE_HW_MAX_TIM_LTIMER_VAL                              67108864
 270
 271        /* Line utilization interrupts */
 272        u32                             urange_a;
 273#define VXGE_HW_MIN_TIM_URANGE_A                                0
 274#define VXGE_HW_MAX_TIM_URANGE_A                                100
 275
 276        u32                             uec_a;
 277#define VXGE_HW_MIN_TIM_UEC_A                                   0
 278#define VXGE_HW_MAX_TIM_UEC_A                                   65535
 279
 280        u32                             urange_b;
 281#define VXGE_HW_MIN_TIM_URANGE_B                                0
 282#define VXGE_HW_MAX_TIM_URANGE_B                                100
 283
 284        u32                             uec_b;
 285#define VXGE_HW_MIN_TIM_UEC_B                                   0
 286#define VXGE_HW_MAX_TIM_UEC_B                                   65535
 287
 288        u32                             urange_c;
 289#define VXGE_HW_MIN_TIM_URANGE_C                                0
 290#define VXGE_HW_MAX_TIM_URANGE_C                                100
 291
 292        u32                             uec_c;
 293#define VXGE_HW_MIN_TIM_UEC_C                                   0
 294#define VXGE_HW_MAX_TIM_UEC_C                                   65535
 295
 296        u32                             uec_d;
 297#define VXGE_HW_MIN_TIM_UEC_D                                   0
 298#define VXGE_HW_MAX_TIM_UEC_D                                   65535
 299};
 300
 301#define VXGE_HW_STATS_OP_READ                                   0
 302#define VXGE_HW_STATS_OP_CLEAR_STAT                             1
 303#define VXGE_HW_STATS_OP_CLEAR_ALL_VPATH_STATS                  2
 304#define VXGE_HW_STATS_OP_CLEAR_ALL_STATS_OF_LOC                 2
 305#define VXGE_HW_STATS_OP_CLEAR_ALL_STATS                        3
 306
 307#define VXGE_HW_STATS_LOC_AGGR                                  17
 308#define VXGE_HW_STATS_AGGRn_OFFSET                              0x00720
 309
 310#define VXGE_HW_STATS_VPATH_TX_OFFSET                           0x0
 311#define VXGE_HW_STATS_VPATH_RX_OFFSET                           0x00090
 312
 313#define VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET        (0x001d0 >> 3)
 314#define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(bits) \
 315                                                vxge_bVALn(bits, 0, 32)
 316
 317#define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(bits) \
 318                                                vxge_bVALn(bits, 32, 32)
 319
 320#define VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET        (0x001d8 >> 3)
 321#define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(bits) \
 322                                                vxge_bVALn(bits, 0, 32)
 323
 324#define VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(bits) \
 325                                                vxge_bVALn(bits, 32, 32)
 326
 327/**
 328 * struct vxge_hw_xmac_aggr_stats - Per-Aggregator XMAC Statistics
 329 *
 330 * @tx_frms: Count of data frames transmitted on this Aggregator on all
 331 *             its Aggregation ports. Does not include LACPDUs or Marker PDUs.
 332 *             However, does include frames discarded by the Distribution
 333 *             function.
 334 * @tx_data_octets: Count of data and padding octets of frames transmitted
 335 *             on this Aggregator on all its Aggregation ports. Does not include
 336 *             octets of LACPDUs or Marker PDUs. However, does include octets of
 337 *             frames discarded by the Distribution function.
 338 * @tx_mcast_frms: Count of data frames transmitted (to a group destination
 339 *             address other than the broadcast address) on this Aggregator on
 340 *             all its Aggregation ports. Does not include LACPDUs or Marker
 341 *             PDUs. However, does include frames discarded by the Distribution
 342 *             function.
 343 * @tx_bcast_frms: Count of broadcast data frames transmitted on this Aggregator
 344 *             on all its Aggregation ports. Does not include LACPDUs or Marker
 345 *             PDUs. However, does include frames discarded by the Distribution
 346 *             function.
 347 * @tx_discarded_frms: Count of data frames to be transmitted on this Aggregator
 348 *             that are discarded by the Distribution function. This occurs when
 349 *             conversation are allocated to different ports and have to be
 350 *             flushed on old ports
 351 * @tx_errored_frms: Count of data frames transmitted on this Aggregator that
 352 *             experience transmission errors on its Aggregation ports.
 353 * @rx_frms: Count of data frames received on this Aggregator on all its
 354 *             Aggregation ports. Does not include LACPDUs or Marker PDUs.
 355 *             Also, does not include frames discarded by the Collection
 356 *             function.
 357 * @rx_data_octets: Count of data and padding octets of frames received on this
 358 *             Aggregator on all its Aggregation ports. Does not include octets
 359 *             of LACPDUs or Marker PDUs. Also, does not include
 360 *             octets of frames
 361 *             discarded by the Collection function.
 362 * @rx_mcast_frms: Count of data frames received (from a group destination
 363 *             address other than the broadcast address) on this Aggregator on
 364 *             all its Aggregation ports. Does not include LACPDUs or Marker
 365 *             PDUs. Also, does not include frames discarded by the Collection
 366 *             function.
 367 * @rx_bcast_frms: Count of broadcast data frames received on this Aggregator on
 368 *             all its Aggregation ports. Does not include LACPDUs or Marker
 369 *             PDUs. Also, does not include frames discarded by the Collection
 370 *             function.
 371 * @rx_discarded_frms: Count of data frames received on this Aggregator that are
 372 *             discarded by the Collection function because the Collection
 373 *             function was disabled on the port which the frames are received.
 374 * @rx_errored_frms: Count of data frames received on this Aggregator that are
 375 *             discarded by its Aggregation ports, or are discarded by the
 376 *             Collection function of the Aggregator, or that are discarded by
 377 *             the Aggregator due to detection of an illegal Slow Protocols PDU.
 378 * @rx_unknown_slow_proto_frms: Count of data frames received on this Aggregator
 379 *             that are discarded by its Aggregation ports due to detection of
 380 *             an unknown Slow Protocols PDU.
 381 *
 382 * Per aggregator XMAC RX statistics.
 383 */
 384struct vxge_hw_xmac_aggr_stats {
 385/*0x000*/               u64     tx_frms;
 386/*0x008*/               u64     tx_data_octets;
 387/*0x010*/               u64     tx_mcast_frms;
 388/*0x018*/               u64     tx_bcast_frms;
 389/*0x020*/               u64     tx_discarded_frms;
 390/*0x028*/               u64     tx_errored_frms;
 391/*0x030*/               u64     rx_frms;
 392/*0x038*/               u64     rx_data_octets;
 393/*0x040*/               u64     rx_mcast_frms;
 394/*0x048*/               u64     rx_bcast_frms;
 395/*0x050*/               u64     rx_discarded_frms;
 396/*0x058*/               u64     rx_errored_frms;
 397/*0x060*/               u64     rx_unknown_slow_proto_frms;
 398} __packed;
 399
 400/**
 401 * struct vxge_hw_xmac_port_stats - XMAC Port Statistics
 402 *
 403 * @tx_ttl_frms: Count of successfully transmitted MAC frames
 404 * @tx_ttl_octets: Count of total octets of transmitted frames, not including
 405 *            framing characters (i.e. less framing bits). To determine the
 406 *            total octets of transmitted frames, including framing characters,
 407 *            multiply PORTn_TX_TTL_FRMS by 8 and add it to this stat (unless
 408 *            otherwise configured, this stat only counts frames that have
 409 *            8 bytes of preamble for each frame). This stat can be configured
 410 *            (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything
 411 *            including the preamble octets.
 412 * @tx_data_octets: Count of data and padding octets of successfully transmitted
 413 *            frames.
 414 * @tx_mcast_frms: Count of successfully transmitted frames to a group address
 415 *            other than the broadcast address.
 416 * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast
 417 *            group address.
 418 * @tx_ucast_frms: Count of transmitted frames containing a unicast address.
 419 *            Includes discarded frames that are not sent to the network.
 420 * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag.
 421 * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network.
 422 * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that
 423 *            are passed to the network.
 424 * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent
 425 *            due to problems within ICMP.
 426 * @tx_tcp: Count of transmitted TCP segments. Does not include segments
 427 *            containing retransmitted octets.
 428 * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag.
 429 * @tx_udp: Count of transmitted UDP datagrams.
 430 * @tx_parse_error: Increments when the TPA is unable to parse a packet. This
 431 *            generally occurs when a packet is corrupt somehow, including
 432 *            packets that have IP version mismatches, invalid Layer 2 control
 433 *            fields, etc. L3/L4 checksums are not offloaded, but the packet
 434 *            is still be transmitted.
 435 * @tx_unknown_protocol: Increments when the TPA encounters an unknown
 436 *            protocol, such as a new IPv6 extension header, or an unsupported
 437 *            Routing Type. The packet still has a checksum calculated but it
 438 *            may be incorrect.
 439 * @tx_pause_ctrl_frms: Count of MAC PAUSE control frames that are transmitted.
 440 *            Since, the only control frames supported by this device are
 441 *            PAUSE frames, this register is a count of all transmitted MAC
 442 *            control frames.
 443 * @tx_marker_pdu_frms: Count of Marker PDUs transmitted
 444 * on this Aggregation port.
 445 * @tx_lacpdu_frms: Count of LACPDUs transmitted on this Aggregation port.
 446 * @tx_drop_ip: Count of transmitted IP datagrams that could not be passed to
 447 *            the network. Increments because of:
 448 *            1) An internal processing error
 449 *            (such as an uncorrectable ECC error). 2) A frame parsing error
 450 *            during IP checksum calculation.
 451 * @tx_marker_resp_pdu_frms: Count of Marker Response PDUs transmitted on this
 452 *            Aggregation port.
 453 * @tx_xgmii_char2_match: Maintains a count of the number of transmitted XGMII
 454 *            characters that match a pattern that is programmable through
 455 *            register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern
 456 *            is set to /T/ (i.e. the terminate character), thus the statistic
 457 *            tracks the number of transmitted Terminate characters.
 458 * @tx_xgmii_char1_match: Maintains a count of the number of transmitted XGMII
 459 *            characters that match a pattern that is programmable through
 460 *            register XMAC_STATS_TX_XGMII_CHAR_PORTn. By default, the pattern
 461 *            is set to /S/ (i.e. the start character),
 462 *            thus the statistic tracks
 463 *            the number of transmitted Start characters.
 464 * @tx_xgmii_column2_match: Maintains a count of the number of transmitted XGMII
 465 *            columns that match a pattern that is programmable through register
 466 *            XMAC_STATS_TX_XGMII_COLUMN2_PORTn. By default, the pattern is set
 467 *            to 4 x /E/ (i.e. a column containing all error characters), thus
 468 *            the statistic tracks the number of Error columns transmitted at
 469 *            any time. If XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is
 470 *            set to 1, then this stat increments when COLUMN2 is found within
 471 *            'n' clocks after COLUMN1. Here, 'n' is defined by
 472 *            XMAC_STATS_TX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set
 473 *            to 0, then it means to search anywhere for COLUMN2).
 474 * @tx_xgmii_column1_match: Maintains a count of the number of transmitted XGMII
 475 *            columns that match a pattern that is programmable through register
 476 *            XMAC_STATS_TX_XGMII_COLUMN1_PORTn. By default, the pattern is set
 477 *            to 4 x /I/ (i.e. a column containing all idle characters),
 478 *            thus the statistic tracks the number of transmitted Idle columns.
 479 * @tx_any_err_frms: Count of transmitted frames containing any error that
 480 *            prevents them from being passed to the network. Increments if
 481 *            there is an ECC while reading the frame out of the transmit
 482 *            buffer. Also increments if the transmit protocol assist (TPA)
 483 *            block determines that the frame should not be sent.
 484 * @tx_drop_frms: Count of frames that could not be sent for no other reason
 485 *            than internal MAC processing. Increments once whenever the
 486 *            transmit buffer is flushed (due to an ECC error on a memory
 487 *            descriptor).
 488 * @rx_ttl_frms: Count of total received MAC frames, including frames received
 489 *            with frame-too-long, FCS, or length errors. This stat can be
 490 *            configured (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count
 491 *            everything, even "frames" as small one byte of preamble.
 492 * @rx_vld_frms: Count of successfully received MAC frames. Does not include
 493 *            frames received with frame-too-long, FCS, or length errors.
 494 * @rx_offload_frms: Count of offloaded received frames that are passed to
 495 *            the host.
 496 * @rx_ttl_octets: Count of total octets of received frames, not including
 497 *            framing characters (i.e. less framing bits). To determine the
 498 *            total octets of received frames, including framing characters,
 499 *            multiply PORTn_RX_TTL_FRMS by 8 and add it to this stat (unless
 500 *            otherwise configured, this stat only counts frames that have 8
 501 *            bytes of preamble for each frame). This stat can be configured
 502 *            (see XMAC_STATS_GLOBAL_CFG.TTL_FRMS_HANDLING) to count everything,
 503 *            even the preamble octets of "frames" as small one byte of preamble
 504 * @rx_data_octets: Count of data and padding octets of successfully received
 505 *            frames. Does not include frames received with frame-too-long,
 506 *            FCS, or length errors.
 507 * @rx_offload_octets: Count of total octets, not including framing
 508 *            characters, of offloaded received frames that are passed
 509 *            to the host.
 510 * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a
 511 *            nonbroadcast group address. Does not include frames received
 512 *            with frame-too-long, FCS, or length errors.
 513 * @rx_vld_bcast_frms: Count of successfully received MAC frames containing
 514 *            the broadcast group address. Does not include frames received
 515 *            with frame-too-long, FCS, or length errors.
 516 * @rx_accepted_ucast_frms: Count of successfully received frames containing
 517 *            a unicast address. Only includes frames that are passed to
 518 *            the system.
 519 * @rx_accepted_nucast_frms: Count of successfully received frames containing
 520 *            a non-unicast (broadcast or multicast) address. Only includes
 521 *            frames that are passed to the system. Could include, for instance,
 522 *            non-unicast frames that contain FCS errors if the MAC_ERROR_CFG
 523 *            register is set to pass FCS-errored frames to the host.
 524 * @rx_tagged_frms: Count of received frames containing a VLAN tag.
 525 * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN
 526 *            + 18 bytes (+ 22 bytes if VLAN-tagged).
 527 * @rx_usized_frms: Count of received frames of length (including FCS, but not
 528 *            framing bits) less than 64 octets, that are otherwise well-formed.
 529 *            In other words, counts runts.
 530 * @rx_osized_frms: Count of received frames of length (including FCS, but not
 531 *            framing bits) more than 1518 octets, that are otherwise
 532 *            well-formed. Note: If register XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING
 533 *            is set to 1, then "more than 1518 octets" becomes "more than 1518
 534 *            (1522 if VLAN-tagged) octets".
 535 * @rx_frag_frms: Count of received frames of length (including FCS, but not
 536 *            framing bits) less than 64 octets that had bad FCS. In other
 537 *            words, counts fragments.
 538 * @rx_jabber_frms: Count of received frames of length (including FCS, but not
 539 *            framing bits) more than 1518 octets that had bad FCS. In other
 540 *            words, counts jabbers. Note: If register
 541 *            XMAC_STATS_GLOBAL_CFG.VLAN_HANDLING is set to 1, then "more than
 542 *            1518 octets" becomes "more than 1518 (1522 if VLAN-tagged)
 543 *            octets".
 544 * @rx_ttl_64_frms: Count of total received MAC frames with length (including
 545 *            FCS, but not framing bits) of exactly 64 octets. Includes frames
 546 *            received with frame-too-long, FCS, or length errors.
 547 * @rx_ttl_65_127_frms: Count of total received MAC frames with length
 548 *            (including FCS, but not framing bits) of between 65 and 127
 549 *            octets inclusive. Includes frames received with frame-too-long,
 550 *            FCS, or length errors.
 551 * @rx_ttl_128_255_frms: Count of total received MAC frames with length
 552 *            (including FCS, but not framing bits) of between 128 and 255
 553 *            octets inclusive. Includes frames received with frame-too-long,
 554 *            FCS, or length errors.
 555 * @rx_ttl_256_511_frms: Count of total received MAC frames with length
 556 *            (including FCS, but not framing bits) of between 256 and 511
 557 *            octets inclusive. Includes frames received with frame-too-long,
 558 *            FCS, or length errors.
 559 * @rx_ttl_512_1023_frms: Count of total received MAC frames with length
 560 *            (including FCS, but not framing bits) of between 512 and 1023
 561 *            octets inclusive. Includes frames received with frame-too-long,
 562 *            FCS, or length errors.
 563 * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length
 564 *            (including FCS, but not framing bits) of between 1024 and 1518
 565 *            octets inclusive. Includes frames received with frame-too-long,
 566 *            FCS, or length errors.
 567 * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length
 568 *            (including FCS, but not framing bits) of between 1519 and 4095
 569 *            octets inclusive. Includes frames received with frame-too-long,
 570 *            FCS, or length errors.
 571 * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length
 572 *            (including FCS, but not framing bits) of between 4096 and 8191
 573 *            octets inclusive. Includes frames received with frame-too-long,
 574 *            FCS, or length errors.
 575 * @rx_ttl_8192_max_frms: Count of total received MAC frames with length
 576 *            (including FCS, but not framing bits) of between 8192 and
 577 *            RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received
 578 *            with frame-too-long, FCS, or length errors.
 579 * @rx_ttl_gt_max_frms: Count of total received MAC frames with length
 580 *            (including FCS, but not framing bits) exceeding
 581 *            RX_MAX_PYLD_LEN+18 (+22 bytes if VLAN-tagged) octets inclusive.
 582 *            Includes frames received with frame-too-long,
 583 *            FCS, or length errors.
 584 * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams.
 585 * @rx_accepted_ip: Count of received IP datagrams that
 586 *              are passed to the system.
 587 * @rx_ip_octets: Count of number of octets in received IP datagrams. Includes
 588 *            errored IP datagrams.
 589 * @rx_err_ip:  Count of received IP datagrams containing errors. For example,
 590 *            bad IP checksum.
 591 * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages.
 592 * @rx_tcp: Count of received TCP segments. Includes errored TCP segments.
 593 *            Note: This stat contains a count of all received TCP segments,
 594 *            regardless of whether or not they pertain to an established
 595 *            connection.
 596 * @rx_udp: Count of received UDP datagrams.
 597 * @rx_err_tcp: Count of received TCP segments containing errors. For example,
 598 *            bad TCP checksum.
 599 * @rx_pause_count: Count of number of pause quanta that the MAC has been in
 600 *            the paused state. Recall, one pause quantum equates to 512
 601 *            bit times.
 602 * @rx_pause_ctrl_frms: Count of received MAC PAUSE control frames.
 603 * @rx_unsup_ctrl_frms: Count of received MAC control frames that do not
 604 *            contain the PAUSE opcode. The sum of RX_PAUSE_CTRL_FRMS and
 605 *            this register is a count of all received MAC control frames.
 606 *            Note: This stat may be configured to count all layer 2 errors
 607 *            (i.e. length errors and FCS errors).
 608 * @rx_fcs_err_frms: Count of received MAC frames that do not pass FCS. Does
 609 *            not include frames received with frame-too-long or
 610 *            frame-too-short error.
 611 * @rx_in_rng_len_err_frms: Count of received frames with a length/type field
 612 *            value between 46 (42 for VLAN-tagged frames) and 1500 (also 1500
 613 *            for VLAN-tagged frames), inclusive, that does not match the
 614 *            number of data octets (including pad) received. Also contains
 615 *            a count of received frames with a length/type field less than
 616 *            46 (42 for VLAN-tagged frames) and the number of data octets
 617 *            (including pad) received is greater than 46 (42 for VLAN-tagged
 618 *            frames).
 619 * @rx_out_rng_len_err_frms:  Count of received frames with length/type field
 620 *            between 1501 and 1535 decimal, inclusive.
 621 * @rx_drop_frms: Count of received frames that could not be passed to the host.
 622 *            See PORTn_RX_L2_MGMT_DISCARD, PORTn_RX_RPA_DISCARD,
 623 *            PORTn_RX_TRASH_DISCARD, PORTn_RX_RTS_DISCARD, PORTn_RX_RED_DISCARD
 624 *            for a list of reasons. Because the RMAC drops one frame at a time,
 625 *            this stat also indicates the number of drop events.
 626 * @rx_discarded_frms: Count of received frames containing
 627 *              any error that prevents
 628 *            them from being passed to the system. See PORTn_RX_FCS_DISCARD,
 629 *            PORTn_RX_LEN_DISCARD, and PORTn_RX_SWITCH_DISCARD for a list of
 630 *            reasons.
 631 * @rx_drop_ip: Count of received IP datagrams that could not be passed to the
 632 *            host. See PORTn_RX_DROP_FRMS for a list of reasons.
 633 * @rx_drop_udp: Count of received UDP datagrams that are not delivered to the
 634 *            host. See PORTn_RX_DROP_FRMS for a list of reasons.
 635 * @rx_marker_pdu_frms: Count of valid Marker PDUs received on this Aggregation
 636 *            port.
 637 * @rx_lacpdu_frms: Count of valid LACPDUs received on this Aggregation port.
 638 * @rx_unknown_pdu_frms: Count of received frames (on this Aggregation port)
 639 *            that carry the Slow Protocols EtherType, but contain an unknown
 640 *            PDU. Or frames that contain the Slow Protocols group MAC address,
 641 *            but do not carry the Slow Protocols EtherType.
 642 * @rx_marker_resp_pdu_frms: Count of valid Marker Response PDUs received on
 643 *            this Aggregation port.
 644 * @rx_fcs_discard: Count of received frames that are discarded because the
 645 *            FCS check failed.
 646 * @rx_illegal_pdu_frms: Count of received frames (on this Aggregation port)
 647 *            that carry the Slow Protocols EtherType, but contain a badly
 648 *            formed PDU. Or frames that carry the Slow Protocols EtherType,
 649 *            but contain an illegal value of Protocol Subtype.
 650 * @rx_switch_discard: Count of received frames that are discarded by the
 651 *            internal switch because they did not have an entry in the
 652 *            Filtering Database. This includes frames that had an invalid
 653 *            destination MAC address or VLAN ID. It also includes frames are
 654 *            discarded because they did not satisfy the length requirements
 655 *            of the target VPATH.
 656 * @rx_len_discard: Count of received frames that are discarded because of an
 657 *            invalid frame length (includes fragments, oversized frames and
 658 *            mismatch between frame length and length/type field). This stat
 659 *            can be configured
 660 *            (see XMAC_STATS_GLOBAL_CFG.LEN_DISCARD_HANDLING).
 661 * @rx_rpa_discard: Count of received frames that were discarded because the
 662 *            receive protocol assist (RPA) discovered and error in the frame
 663 *            or was unable to parse the frame.
 664 * @rx_l2_mgmt_discard: Count of Layer 2 management frames (eg. pause frames,
 665 *            Link Aggregation Control Protocol (LACP) frames, etc.) that are
 666 *            discarded.
 667 * @rx_rts_discard: Count of received frames that are discarded by the receive
 668 *            traffic steering (RTS) logic. Includes those frame discarded
 669 *            because the SSC response contradicted the switch table, because
 670 *            the SSC timed out, or because the target queue could not fit the
 671 *            frame.
 672 * @rx_trash_discard: Count of received frames that are discarded because
 673 *            receive traffic steering (RTS) steered the frame to the trash
 674 *            queue.
 675 * @rx_buff_full_discard: Count of received frames that are discarded because
 676 *            internal buffers are full. Includes frames discarded because the
 677 *            RTS logic is waiting for an SSC lookup that has no timeout bound.
 678 *            Also, includes frames that are dropped because the MAC2FAU buffer
 679 *            is nearly full -- this can happen if the external receive buffer
 680 *            is full and the receive path is backing up.
 681 * @rx_red_discard: Count of received frames that are discarded because of RED
 682 *            (Random Early Discard).
 683 * @rx_xgmii_ctrl_err_cnt: Maintains a count of unexpected or misplaced control
 684 *            characters occurring between times of normal data transmission
 685 *            (i.e. not included in RX_XGMII_DATA_ERR_CNT). This counter is
 686 *            incremented when either -
 687 *            1) The Reconciliation Sublayer (RS) is expecting one control
 688 *               character and gets another (i.e. is expecting a Start
 689 *               character, but gets another control character).
 690 *            2) Start control character is not in lane 0
 691 *            Only increments the count by one for each XGMII column.
 692 * @rx_xgmii_data_err_cnt: Maintains a count of unexpected control characters
 693 *            during normal data transmission. If the Reconciliation Sublayer
 694 *            (RS) receives a control character, other than a terminate control
 695 *            character, during receipt of data octets then this register is
 696 *            incremented. Also increments if the start frame delimiter is not
 697 *            found in the correct location. Only increments the count by one
 698 *            for each XGMII column.
 699 * @rx_xgmii_char1_match: Maintains a count of the number of XGMII characters
 700 *            that match a pattern that is programmable through register
 701 *            XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set
 702 *            to /E/ (i.e. the error character), thus the statistic tracks the
 703 *            number of Error characters received at any time.
 704 * @rx_xgmii_err_sym: Count of the number of symbol errors in the received
 705 *            XGMII data (i.e. PHY indicates "Receive Error" on the XGMII).
 706 *            Only includes symbol errors that are observed between the XGMII
 707 *            Start Frame Delimiter and End Frame Delimiter, inclusive. And
 708 *            only increments the count by one for each frame.
 709 * @rx_xgmii_column1_match: Maintains a count of the number of XGMII columns
 710 *            that match a pattern that is programmable through register
 711 *            XMAC_STATS_RX_XGMII_COLUMN1_PORTn. By default, the pattern is set
 712 *            to 4 x /E/ (i.e. a column containing all error characters), thus
 713 *            the statistic tracks the number of Error columns received at any
 714 *            time.
 715 * @rx_xgmii_char2_match: Maintains a count of the number of XGMII characters
 716 *            that match a pattern that is programmable through register
 717 *            XMAC_STATS_RX_XGMII_CHAR_PORTn. By default, the pattern is set
 718 *            to /E/ (i.e. the error character), thus the statistic tracks the
 719 *            number of Error characters received at any time.
 720 * @rx_local_fault: Maintains a count of the number of times that link
 721 *            transitioned from "up" to "down" due to a local fault.
 722 * @rx_xgmii_column2_match: Maintains a count of the number of XGMII columns
 723 *            that match a pattern that is programmable through register
 724 *            XMAC_STATS_RX_XGMII_COLUMN2_PORTn. By default, the pattern is set
 725 *            to 4 x /E/ (i.e. a column containing all error characters), thus
 726 *            the statistic tracks the number of Error columns received at any
 727 *            time. If XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NEAR_COL1 is set
 728 *            to 1, then this stat increments when COLUMN2 is found within 'n'
 729 *            clocks after COLUMN1. Here, 'n' is defined by
 730 *            XMAC_STATS_RX_XGMII_BEHAV_COLUMN2_PORTn.NUM_COL (if 'n' is set to
 731 *            0, then it means to search anywhere for COLUMN2).
 732 * @rx_jettison: Count of received frames that are jettisoned because internal
 733 *            buffers are full.
 734 * @rx_remote_fault: Maintains a count of the number of times that link
 735 *            transitioned from "up" to "down" due to a remote fault.
 736 *
 737 * XMAC Port Statistics.
 738 */
 739struct vxge_hw_xmac_port_stats {
 740/*0x000*/               u64     tx_ttl_frms;
 741/*0x008*/               u64     tx_ttl_octets;
 742/*0x010*/               u64     tx_data_octets;
 743/*0x018*/               u64     tx_mcast_frms;
 744/*0x020*/               u64     tx_bcast_frms;
 745/*0x028*/               u64     tx_ucast_frms;
 746/*0x030*/               u64     tx_tagged_frms;
 747/*0x038*/               u64     tx_vld_ip;
 748/*0x040*/               u64     tx_vld_ip_octets;
 749/*0x048*/               u64     tx_icmp;
 750/*0x050*/               u64     tx_tcp;
 751/*0x058*/               u64     tx_rst_tcp;
 752/*0x060*/               u64     tx_udp;
 753/*0x068*/               u32     tx_parse_error;
 754/*0x06c*/               u32     tx_unknown_protocol;
 755/*0x070*/               u64     tx_pause_ctrl_frms;
 756/*0x078*/               u32     tx_marker_pdu_frms;
 757/*0x07c*/               u32     tx_lacpdu_frms;
 758/*0x080*/               u32     tx_drop_ip;
 759/*0x084*/               u32     tx_marker_resp_pdu_frms;
 760/*0x088*/               u32     tx_xgmii_char2_match;
 761/*0x08c*/               u32     tx_xgmii_char1_match;
 762/*0x090*/               u32     tx_xgmii_column2_match;
 763/*0x094*/               u32     tx_xgmii_column1_match;
 764/*0x098*/               u32     unused1;
 765/*0x09c*/               u16     tx_any_err_frms;
 766/*0x09e*/               u16     tx_drop_frms;
 767/*0x0a0*/               u64     rx_ttl_frms;
 768/*0x0a8*/               u64     rx_vld_frms;
 769/*0x0b0*/               u64     rx_offload_frms;
 770/*0x0b8*/               u64     rx_ttl_octets;
 771/*0x0c0*/               u64     rx_data_octets;
 772/*0x0c8*/               u64     rx_offload_octets;
 773/*0x0d0*/               u64     rx_vld_mcast_frms;
 774/*0x0d8*/               u64     rx_vld_bcast_frms;
 775/*0x0e0*/               u64     rx_accepted_ucast_frms;
 776/*0x0e8*/               u64     rx_accepted_nucast_frms;
 777/*0x0f0*/               u64     rx_tagged_frms;
 778/*0x0f8*/               u64     rx_long_frms;
 779/*0x100*/               u64     rx_usized_frms;
 780/*0x108*/               u64     rx_osized_frms;
 781/*0x110*/               u64     rx_frag_frms;
 782/*0x118*/               u64     rx_jabber_frms;
 783/*0x120*/               u64     rx_ttl_64_frms;
 784/*0x128*/               u64     rx_ttl_65_127_frms;
 785/*0x130*/               u64     rx_ttl_128_255_frms;
 786/*0x138*/               u64     rx_ttl_256_511_frms;
 787/*0x140*/               u64     rx_ttl_512_1023_frms;
 788/*0x148*/               u64     rx_ttl_1024_1518_frms;
 789/*0x150*/               u64     rx_ttl_1519_4095_frms;
 790/*0x158*/               u64     rx_ttl_4096_8191_frms;
 791/*0x160*/               u64     rx_ttl_8192_max_frms;
 792/*0x168*/               u64     rx_ttl_gt_max_frms;
 793/*0x170*/               u64     rx_ip;
 794/*0x178*/               u64     rx_accepted_ip;
 795/*0x180*/               u64     rx_ip_octets;
 796/*0x188*/               u64     rx_err_ip;
 797/*0x190*/               u64     rx_icmp;
 798/*0x198*/               u64     rx_tcp;
 799/*0x1a0*/               u64     rx_udp;
 800/*0x1a8*/               u64     rx_err_tcp;
 801/*0x1b0*/               u64     rx_pause_count;
 802/*0x1b8*/               u64     rx_pause_ctrl_frms;
 803/*0x1c0*/               u64     rx_unsup_ctrl_frms;
 804/*0x1c8*/               u64     rx_fcs_err_frms;
 805/*0x1d0*/               u64     rx_in_rng_len_err_frms;
 806/*0x1d8*/               u64     rx_out_rng_len_err_frms;
 807/*0x1e0*/               u64     rx_drop_frms;
 808/*0x1e8*/               u64     rx_discarded_frms;
 809/*0x1f0*/               u64     rx_drop_ip;
 810/*0x1f8*/               u64     rx_drop_udp;
 811/*0x200*/               u32     rx_marker_pdu_frms;
 812/*0x204*/               u32     rx_lacpdu_frms;
 813/*0x208*/               u32     rx_unknown_pdu_frms;
 814/*0x20c*/               u32     rx_marker_resp_pdu_frms;
 815/*0x210*/               u32     rx_fcs_discard;
 816/*0x214*/               u32     rx_illegal_pdu_frms;
 817/*0x218*/               u32     rx_switch_discard;
 818/*0x21c*/               u32     rx_len_discard;
 819/*0x220*/               u32     rx_rpa_discard;
 820/*0x224*/               u32     rx_l2_mgmt_discard;
 821/*0x228*/               u32     rx_rts_discard;
 822/*0x22c*/               u32     rx_trash_discard;
 823/*0x230*/               u32     rx_buff_full_discard;
 824/*0x234*/               u32     rx_red_discard;
 825/*0x238*/               u32     rx_xgmii_ctrl_err_cnt;
 826/*0x23c*/               u32     rx_xgmii_data_err_cnt;
 827/*0x240*/               u32     rx_xgmii_char1_match;
 828/*0x244*/               u32     rx_xgmii_err_sym;
 829/*0x248*/               u32     rx_xgmii_column1_match;
 830/*0x24c*/               u32     rx_xgmii_char2_match;
 831/*0x250*/               u32     rx_local_fault;
 832/*0x254*/               u32     rx_xgmii_column2_match;
 833/*0x258*/               u32     rx_jettison;
 834/*0x25c*/               u32     rx_remote_fault;
 835} __packed;
 836
 837/**
 838 * struct vxge_hw_xmac_vpath_tx_stats - XMAC Vpath Tx Statistics
 839 *
 840 * @tx_ttl_eth_frms: Count of successfully transmitted MAC frames.
 841 * @tx_ttl_eth_octets: Count of total octets of transmitted frames,
 842 *             not including framing characters (i.e. less framing bits).
 843 *             To determine the total octets of transmitted frames, including
 844 *             framing characters, multiply TX_TTL_ETH_FRMS by 8 and add it to
 845 *             this stat (the device always prepends 8 bytes of preamble for
 846 *             each frame)
 847 * @tx_data_octets: Count of data and padding octets of successfully transmitted
 848 *             frames.
 849 * @tx_mcast_frms: Count of successfully transmitted frames to a group address
 850 *             other than the broadcast address.
 851 * @tx_bcast_frms: Count of successfully transmitted frames to the broadcast
 852 *             group address.
 853 * @tx_ucast_frms: Count of transmitted frames containing a unicast address.
 854 *             Includes discarded frames that are not sent to the network.
 855 * @tx_tagged_frms: Count of transmitted frames containing a VLAN tag.
 856 * @tx_vld_ip: Count of transmitted IP datagrams that are passed to the network.
 857 * @tx_vld_ip_octets: Count of total octets of transmitted IP datagrams that
 858 *            are passed to the network.
 859 * @tx_icmp: Count of transmitted ICMP messages. Includes messages not sent due
 860 *            to problems within ICMP.
 861 * @tx_tcp: Count of transmitted TCP segments. Does not include segments
 862 *            containing retransmitted octets.
 863 * @tx_rst_tcp: Count of transmitted TCP segments containing the RST flag.
 864 * @tx_udp: Count of transmitted UDP datagrams.
 865 * @tx_unknown_protocol: Increments when the TPA encounters an unknown protocol,
 866 *            such as a new IPv6 extension header, or an unsupported Routing
 867 *            Type. The packet still has a checksum calculated but it may be
 868 *            incorrect.
 869 * @tx_lost_ip: Count of transmitted IP datagrams that could not be passed
 870 *            to the network. Increments because of: 1) An internal processing
 871 *            error (such as an uncorrectable ECC error). 2) A frame parsing
 872 *            error during IP checksum calculation.
 873 * @tx_parse_error: Increments when the TPA is unable to parse a packet. This
 874 *            generally occurs when a packet is corrupt somehow, including
 875 *            packets that have IP version mismatches, invalid Layer 2 control
 876 *            fields, etc. L3/L4 checksums are not offloaded, but the packet
 877 *            is still be transmitted.
 878 * @tx_tcp_offload: For frames belonging to offloaded sessions only, a count
 879 *            of transmitted TCP segments. Does not include segments containing
 880 *            retransmitted octets.
 881 * @tx_retx_tcp_offload: For frames belonging to offloaded sessions only, the
 882 *            total number of segments retransmitted. Retransmitted segments
 883 *            that are sourced by the host are counted by the host.
 884 * @tx_lost_ip_offload: For frames belonging to offloaded sessions only, a count
 885 *            of transmitted IP datagrams that could not be passed to the
 886 *            network.
 887 *
 888 * XMAC Vpath TX Statistics.
 889 */
 890struct vxge_hw_xmac_vpath_tx_stats {
 891        u64     tx_ttl_eth_frms;
 892        u64     tx_ttl_eth_octets;
 893        u64     tx_data_octets;
 894        u64     tx_mcast_frms;
 895        u64     tx_bcast_frms;
 896        u64     tx_ucast_frms;
 897        u64     tx_tagged_frms;
 898        u64     tx_vld_ip;
 899        u64     tx_vld_ip_octets;
 900        u64     tx_icmp;
 901        u64     tx_tcp;
 902        u64     tx_rst_tcp;
 903        u64     tx_udp;
 904        u32     tx_unknown_protocol;
 905        u32     tx_lost_ip;
 906        u32     unused1;
 907        u32     tx_parse_error;
 908        u64     tx_tcp_offload;
 909        u64     tx_retx_tcp_offload;
 910        u64     tx_lost_ip_offload;
 911} __packed;
 912
 913/**
 914 * struct vxge_hw_xmac_vpath_rx_stats - XMAC Vpath RX Statistics
 915 *
 916 * @rx_ttl_eth_frms: Count of successfully received MAC frames.
 917 * @rx_vld_frms: Count of successfully received MAC frames. Does not include
 918 *            frames received with frame-too-long, FCS, or length errors.
 919 * @rx_offload_frms: Count of offloaded received frames that are passed to
 920 *            the host.
 921 * @rx_ttl_eth_octets: Count of total octets of received frames, not including
 922 *            framing characters (i.e. less framing bits). Only counts octets
 923 *            of frames that are at least 14 bytes (18 bytes for VLAN-tagged)
 924 *            before FCS. To determine the total octets of received frames,
 925 *            including framing characters, multiply RX_TTL_ETH_FRMS by 8 and
 926 *            add it to this stat (the stat RX_TTL_ETH_FRMS only counts frames
 927 *            that have the required 8 bytes of preamble).
 928 * @rx_data_octets: Count of data and padding octets of successfully received
 929 *            frames. Does not include frames received with frame-too-long,
 930 *            FCS, or length errors.
 931 * @rx_offload_octets: Count of total octets, not including framing characters,
 932 *            of offloaded received frames that are passed to the host.
 933 * @rx_vld_mcast_frms: Count of successfully received MAC frames containing a
 934 *            nonbroadcast group address. Does not include frames received with
 935 *            frame-too-long, FCS, or length errors.
 936 * @rx_vld_bcast_frms: Count of successfully received MAC frames containing the
 937 *            broadcast group address. Does not include frames received with
 938 *            frame-too-long, FCS, or length errors.
 939 * @rx_accepted_ucast_frms: Count of successfully received frames containing
 940 *            a unicast address. Only includes frames that are passed to the
 941 *            system.
 942 * @rx_accepted_nucast_frms: Count of successfully received frames containing
 943 *            a non-unicast (broadcast or multicast) address. Only includes
 944 *            frames that are passed to the system. Could include, for instance,
 945 *            non-unicast frames that contain FCS errors if the MAC_ERROR_CFG
 946 *            register is set to pass FCS-errored frames to the host.
 947 * @rx_tagged_frms: Count of received frames containing a VLAN tag.
 948 * @rx_long_frms: Count of received frames that are longer than RX_MAX_PYLD_LEN
 949 *            + 18 bytes (+ 22 bytes if VLAN-tagged).
 950 * @rx_usized_frms: Count of received frames of length (including FCS, but not
 951 *            framing bits) less than 64 octets, that are otherwise well-formed.
 952 *            In other words, counts runts.
 953 * @rx_osized_frms: Count of received frames of length (including FCS, but not
 954 *            framing bits) more than 1518 octets, that are otherwise
 955 *            well-formed.
 956 * @rx_frag_frms: Count of received frames of length (including FCS, but not
 957 *            framing bits) less than 64 octets that had bad FCS.
 958 *            In other words, counts fragments.
 959 * @rx_jabber_frms: Count of received frames of length (including FCS, but not
 960 *            framing bits) more than 1518 octets that had bad FCS. In other
 961 *            words, counts jabbers.
 962 * @rx_ttl_64_frms: Count of total received MAC frames with length (including
 963 *            FCS, but not framing bits) of exactly 64 octets. Includes frames
 964 *            received with frame-too-long, FCS, or length errors.
 965 * @rx_ttl_65_127_frms: Count of total received MAC frames
 966 *              with length (including
 967 *            FCS, but not framing bits) of between 65 and 127 octets inclusive.
 968 *            Includes frames received with frame-too-long, FCS,
 969 *            or length errors.
 970 * @rx_ttl_128_255_frms: Count of total received MAC frames with length
 971 *            (including FCS, but not framing bits)
 972 *            of between 128 and 255 octets
 973 *            inclusive. Includes frames received with frame-too-long, FCS,
 974 *            or length errors.
 975 * @rx_ttl_256_511_frms: Count of total received MAC frames with length
 976 *            (including FCS, but not framing bits)
 977 *            of between 256 and 511 octets
 978 *            inclusive. Includes frames received with frame-too-long, FCS, or
 979 *            length errors.
 980 * @rx_ttl_512_1023_frms: Count of total received MAC frames with length
 981 *            (including FCS, but not framing bits) of between 512 and 1023
 982 *            octets inclusive. Includes frames received with frame-too-long,
 983 *            FCS, or length errors.
 984 * @rx_ttl_1024_1518_frms: Count of total received MAC frames with length
 985 *            (including FCS, but not framing bits) of between 1024 and 1518
 986 *            octets inclusive. Includes frames received with frame-too-long,
 987 *            FCS, or length errors.
 988 * @rx_ttl_1519_4095_frms: Count of total received MAC frames with length
 989 *            (including FCS, but not framing bits) of between 1519 and 4095
 990 *            octets inclusive. Includes frames received with frame-too-long,
 991 *            FCS, or length errors.
 992 * @rx_ttl_4096_8191_frms: Count of total received MAC frames with length
 993 *            (including FCS, but not framing bits) of between 4096 and 8191
 994 *            octets inclusive. Includes frames received with frame-too-long,
 995 *            FCS, or length errors.
 996 * @rx_ttl_8192_max_frms: Count of total received MAC frames with length
 997 *            (including FCS, but not framing bits) of between 8192 and
 998 *            RX_MAX_PYLD_LEN+18 octets inclusive. Includes frames received
 999 *            with frame-too-long, FCS, or length errors.
1000 * @rx_ttl_gt_max_frms: Count of total received MAC frames with length
1001 *            (including FCS, but not framing bits) exceeding RX_MAX_PYLD_LEN+18
1002 *            (+22 bytes if VLAN-tagged) octets inclusive. Includes frames
1003 *            received with frame-too-long, FCS, or length errors.
1004 * @rx_ip: Count of received IP datagrams. Includes errored IP datagrams.
1005 * @rx_accepted_ip: Count of received IP datagrams that
1006 *              are passed to the system.
1007 * @rx_ip_octets: Count of number of octets in received IP datagrams.
1008 *            Includes errored IP datagrams.
1009 * @rx_err_ip: Count of received IP datagrams containing errors. For example,
1010 *            bad IP checksum.
1011 * @rx_icmp: Count of received ICMP messages. Includes errored ICMP messages.
1012 * @rx_tcp: Count of received TCP segments. Includes errored TCP segments.
1013 *             Note: This stat contains a count of all received TCP segments,
1014 *             regardless of whether or not they pertain to an established
1015 *             connection.
1016 * @rx_udp: Count of received UDP datagrams.
1017 * @rx_err_tcp: Count of received TCP segments containing errors. For example,
1018 *             bad TCP checksum.
1019 * @rx_lost_frms: Count of received frames that could not be passed to the host.
1020 *             See RX_QUEUE_FULL_DISCARD and RX_RED_DISCARD
1021 *             for a list of reasons.
1022 * @rx_lost_ip: Count of received IP datagrams that could not be passed to
1023 *             the host. See RX_LOST_FRMS for a list of reasons.
1024 * @rx_lost_ip_offload: For frames belonging to offloaded sessions only, a count
1025 *             of received IP datagrams that could not be passed to the host.
1026 *             See RX_LOST_FRMS for a list of reasons.
1027 * @rx_various_discard: Count of received frames that are discarded because
1028 *             the target receive queue is full.
1029 * @rx_sleep_discard: Count of received frames that are discarded because the
1030 *            target VPATH is asleep (a Wake-on-LAN magic packet can be used
1031 *            to awaken the VPATH).
1032 * @rx_red_discard: Count of received frames that are discarded because of RED
1033 *            (Random Early Discard).
1034 * @rx_queue_full_discard: Count of received frames that are discarded because
1035 *             the target receive queue is full.
1036 * @rx_mpa_ok_frms: Count of received frames that pass the MPA checks.
1037 *
1038 * XMAC Vpath RX Statistics.
1039 */
1040struct vxge_hw_xmac_vpath_rx_stats {
1041        u64     rx_ttl_eth_frms;
1042        u64     rx_vld_frms;
1043        u64     rx_offload_frms;
1044        u64     rx_ttl_eth_octets;
1045        u64     rx_data_octets;
1046        u64     rx_offload_octets;
1047        u64     rx_vld_mcast_frms;
1048        u64     rx_vld_bcast_frms;
1049        u64     rx_accepted_ucast_frms;
1050        u64     rx_accepted_nucast_frms;
1051        u64     rx_tagged_frms;
1052        u64     rx_long_frms;
1053        u64     rx_usized_frms;
1054        u64     rx_osized_frms;
1055        u64     rx_frag_frms;
1056        u64     rx_jabber_frms;
1057        u64     rx_ttl_64_frms;
1058        u64     rx_ttl_65_127_frms;
1059        u64     rx_ttl_128_255_frms;
1060        u64     rx_ttl_256_511_frms;
1061        u64     rx_ttl_512_1023_frms;
1062        u64     rx_ttl_1024_1518_frms;
1063        u64     rx_ttl_1519_4095_frms;
1064        u64     rx_ttl_4096_8191_frms;
1065        u64     rx_ttl_8192_max_frms;
1066        u64     rx_ttl_gt_max_frms;
1067        u64     rx_ip;
1068        u64     rx_accepted_ip;
1069        u64     rx_ip_octets;
1070        u64     rx_err_ip;
1071        u64     rx_icmp;
1072        u64     rx_tcp;
1073        u64     rx_udp;
1074        u64     rx_err_tcp;
1075        u64     rx_lost_frms;
1076        u64     rx_lost_ip;
1077        u64     rx_lost_ip_offload;
1078        u16     rx_various_discard;
1079        u16     rx_sleep_discard;
1080        u16     rx_red_discard;
1081        u16     rx_queue_full_discard;
1082        u64     rx_mpa_ok_frms;
1083} __packed;
1084
1085/**
1086 * struct vxge_hw_xmac_stats - XMAC Statistics
1087 *
1088 * @aggr_stats: Statistics on aggregate port(port 0, port 1)
1089 * @port_stats: Staticstics on ports(wire 0, wire 1, lag)
1090 * @vpath_tx_stats: Per vpath XMAC TX stats
1091 * @vpath_rx_stats: Per vpath XMAC RX stats
1092 *
1093 * XMAC Statistics.
1094 */
1095struct vxge_hw_xmac_stats {
1096        struct vxge_hw_xmac_aggr_stats
1097                                aggr_stats[VXGE_HW_MAC_MAX_MAC_PORT_ID];
1098        struct vxge_hw_xmac_port_stats
1099                                port_stats[VXGE_HW_MAC_MAX_MAC_PORT_ID+1];
1100        struct vxge_hw_xmac_vpath_tx_stats
1101                                vpath_tx_stats[VXGE_HW_MAX_VIRTUAL_PATHS];
1102        struct vxge_hw_xmac_vpath_rx_stats
1103                                vpath_rx_stats[VXGE_HW_MAX_VIRTUAL_PATHS];
1104};
1105
1106/**
1107 * struct vxge_hw_vpath_stats_hw_info - Titan vpath hardware statistics.
1108 * @ini_num_mwr_sent: The number of PCI memory writes initiated by the PIC block
1109 *             for the given VPATH
1110 * @ini_num_mrd_sent: The number of PCI memory reads initiated by the PIC block
1111 * @ini_num_cpl_rcvd: The number of PCI read completions received by the
1112 *             PIC block
1113 * @ini_num_mwr_byte_sent: The number of PCI memory write bytes sent by the PIC
1114 *             block to the host
1115 * @ini_num_cpl_byte_rcvd: The number of PCI read completion bytes received by
1116 *             the PIC block
1117 * @wrcrdtarb_xoff: TBD
1118 * @rdcrdtarb_xoff: TBD
1119 * @vpath_genstats_count0: TBD
1120 * @vpath_genstats_count1: TBD
1121 * @vpath_genstats_count2: TBD
1122 * @vpath_genstats_count3: TBD
1123 * @vpath_genstats_count4: TBD
1124 * @vpath_gennstats_count5: TBD
1125 * @tx_stats: Transmit stats
1126 * @rx_stats: Receive stats
1127 * @prog_event_vnum1: Programmable statistic. Increments when internal logic
1128 *             detects a certain event. See register
1129 *             XMAC_STATS_CFG.EVENT_VNUM1_CFG for more information.
1130 * @prog_event_vnum0: Programmable statistic. Increments when internal logic
1131 *             detects a certain event. See register
1132 *             XMAC_STATS_CFG.EVENT_VNUM0_CFG for more information.
1133 * @prog_event_vnum3: Programmable statistic. Increments when internal logic
1134 *             detects a certain event. See register
1135 *             XMAC_STATS_CFG.EVENT_VNUM3_CFG for more information.
1136 * @prog_event_vnum2: Programmable statistic. Increments when internal logic
1137 *             detects a certain event. See register
1138 *             XMAC_STATS_CFG.EVENT_VNUM2_CFG for more information.
1139 * @rx_multi_cast_frame_discard: TBD
1140 * @rx_frm_transferred: TBD
1141 * @rxd_returned: TBD
1142 * @rx_mpa_len_fail_frms: Count of received frames
1143 *              that fail the MPA length check
1144 * @rx_mpa_mrk_fail_frms: Count of received frames
1145 *              that fail the MPA marker check
1146 * @rx_mpa_crc_fail_frms: Count of received frames that fail the MPA CRC check
1147 * @rx_permitted_frms: Count of frames that pass through the FAU and on to the
1148 *             frame buffer (and subsequently to the host).
1149 * @rx_vp_reset_discarded_frms: Count of receive frames that are discarded
1150 *             because the VPATH is in reset
1151 * @rx_wol_frms: Count of received "magic packet" frames. Stat increments
1152 *             whenever the received frame matches the VPATH's Wake-on-LAN
1153 *             signature(s) CRC.
1154 * @tx_vp_reset_discarded_frms: Count of transmit frames that are discarded
1155 *             because the VPATH is in reset. Includes frames that are discarded
1156 *             because the current VPIN does not match that VPIN of the frame
1157 *
1158 * Titan vpath hardware statistics.
1159 */
1160struct vxge_hw_vpath_stats_hw_info {
1161/*0x000*/       u32 ini_num_mwr_sent;
1162/*0x004*/       u32 unused1;
1163/*0x008*/       u32 ini_num_mrd_sent;
1164/*0x00c*/       u32 unused2;
1165/*0x010*/       u32 ini_num_cpl_rcvd;
1166/*0x014*/       u32 unused3;
1167/*0x018*/       u64 ini_num_mwr_byte_sent;
1168/*0x020*/       u64 ini_num_cpl_byte_rcvd;
1169/*0x028*/       u32 wrcrdtarb_xoff;
1170/*0x02c*/       u32 unused4;
1171/*0x030*/       u32 rdcrdtarb_xoff;
1172/*0x034*/       u32 unused5;
1173/*0x038*/       u32 vpath_genstats_count0;
1174/*0x03c*/       u32 vpath_genstats_count1;
1175/*0x040*/       u32 vpath_genstats_count2;
1176/*0x044*/       u32 vpath_genstats_count3;
1177/*0x048*/       u32 vpath_genstats_count4;
1178/*0x04c*/       u32 unused6;
1179/*0x050*/       u32 vpath_genstats_count5;
1180/*0x054*/       u32 unused7;
1181/*0x058*/       struct vxge_hw_xmac_vpath_tx_stats tx_stats;
1182/*0x0e8*/       struct vxge_hw_xmac_vpath_rx_stats rx_stats;
1183/*0x220*/       u64 unused9;
1184/*0x228*/       u32 prog_event_vnum1;
1185/*0x22c*/       u32 prog_event_vnum0;
1186/*0x230*/       u32 prog_event_vnum3;
1187/*0x234*/       u32 prog_event_vnum2;
1188/*0x238*/       u16 rx_multi_cast_frame_discard;
1189/*0x23a*/       u8 unused10[6];
1190/*0x240*/       u32 rx_frm_transferred;
1191/*0x244*/       u32 unused11;
1192/*0x248*/       u16 rxd_returned;
1193/*0x24a*/       u8 unused12[6];
1194/*0x252*/       u16 rx_mpa_len_fail_frms;
1195/*0x254*/       u16 rx_mpa_mrk_fail_frms;
1196/*0x256*/       u16 rx_mpa_crc_fail_frms;
1197/*0x258*/       u16 rx_permitted_frms;
1198/*0x25c*/       u64 rx_vp_reset_discarded_frms;
1199/*0x25e*/       u64 rx_wol_frms;
1200/*0x260*/       u64 tx_vp_reset_discarded_frms;
1201} __packed;
1202
1203
1204/**
1205 * struct vxge_hw_device_stats_mrpcim_info - Titan mrpcim hardware statistics.
1206 * @pic.ini_rd_drop      0x0000          4       Number of DMA reads initiated
1207 *  by the adapter that were discarded because the VPATH is out of service
1208 * @pic.ini_wr_drop     0x0004  4       Number of DMA writes initiated by the
1209 *  adapter that were discared because the VPATH is out of service
1210 * @pic.wrcrdtarb_ph_crdt_depleted[vplane0]     0x0008  4       Number of times
1211 *  the posted header credits for upstream PCI writes were depleted
1212 * @pic.wrcrdtarb_ph_crdt_depleted[vplane1]     0x0010  4       Number of times
1213 *  the posted header credits for upstream PCI writes were depleted
1214 * @pic.wrcrdtarb_ph_crdt_depleted[vplane2]     0x0018  4       Number of times
1215 *  the posted header credits for upstream PCI writes were depleted
1216 * @pic.wrcrdtarb_ph_crdt_depleted[vplane3]     0x0020  4       Number of times
1217 *  the posted header credits for upstream PCI writes were depleted
1218 * @pic.wrcrdtarb_ph_crdt_depleted[vplane4]     0x0028  4       Number of times
1219 *  the posted header credits for upstream PCI writes were depleted
1220 * @pic.wrcrdtarb_ph_crdt_depleted[vplane5]     0x0030  4       Number of times
1221 *  the posted header credits for upstream PCI writes were depleted
1222 * @pic.wrcrdtarb_ph_crdt_depleted[vplane6]     0x0038  4       Number of times
1223 *  the posted header credits for upstream PCI writes were depleted
1224 * @pic.wrcrdtarb_ph_crdt_depleted[vplane7]     0x0040  4       Number of times
1225 *  the posted header credits for upstream PCI writes were depleted
1226 * @pic.wrcrdtarb_ph_crdt_depleted[vplane8]     0x0048  4       Number of times
1227 *  the posted header credits for upstream PCI writes were depleted
1228 * @pic.wrcrdtarb_ph_crdt_depleted[vplane9]     0x0050  4       Number of times
1229 *  the posted header credits for upstream PCI writes were depleted
1230 * @pic.wrcrdtarb_ph_crdt_depleted[vplane10]    0x0058  4       Number of times
1231 *  the posted header credits for upstream PCI writes were depleted
1232 * @pic.wrcrdtarb_ph_crdt_depleted[vplane11]    0x0060  4       Number of times
1233 *  the posted header credits for upstream PCI writes were depleted
1234 * @pic.wrcrdtarb_ph_crdt_depleted[vplane12]    0x0068  4       Number of times
1235 *  the posted header credits for upstream PCI writes were depleted
1236 * @pic.wrcrdtarb_ph_crdt_depleted[vplane13]    0x0070  4       Number of times
1237 *  the posted header credits for upstream PCI writes were depleted
1238 * @pic.wrcrdtarb_ph_crdt_depleted[vplane14]    0x0078  4       Number of times
1239 *  the posted header credits for upstream PCI writes were depleted
1240 * @pic.wrcrdtarb_ph_crdt_depleted[vplane15]    0x0080  4       Number of times
1241 *  the posted header credits for upstream PCI writes were depleted
1242 * @pic.wrcrdtarb_ph_crdt_depleted[vplane16]    0x0088  4       Number of times
1243 *  the posted header credits for upstream PCI writes were depleted
1244 * @pic.wrcrdtarb_pd_crdt_depleted[vplane0]     0x0090  4       Number of times
1245 *  the posted data credits for upstream PCI writes were depleted
1246 * @pic.wrcrdtarb_pd_crdt_depleted[vplane1]     0x0098  4       Number of times
1247 *  the posted data credits for upstream PCI writes were depleted
1248 * @pic.wrcrdtarb_pd_crdt_depleted[vplane2]     0x00a0  4       Number of times
1249 *  the posted data credits for upstream PCI writes were depleted
1250 * @pic.wrcrdtarb_pd_crdt_depleted[vplane3]     0x00a8  4       Number of times
1251 *  the posted data credits for upstream PCI writes were depleted
1252 * @pic.wrcrdtarb_pd_crdt_depleted[vplane4]     0x00b0  4       Number of times
1253 *  the posted data credits for upstream PCI writes were depleted
1254 * @pic.wrcrdtarb_pd_crdt_depleted[vplane5]     0x00b8  4       Number of times
1255 *  the posted data credits for upstream PCI writes were depleted
1256 * @pic.wrcrdtarb_pd_crdt_depleted[vplane6]     0x00c0  4       Number of times
1257 *  the posted data credits for upstream PCI writes were depleted
1258 * @pic.wrcrdtarb_pd_crdt_depleted[vplane7]     0x00c8  4       Number of times
1259 *  the posted data credits for upstream PCI writes were depleted
1260 * @pic.wrcrdtarb_pd_crdt_depleted[vplane8]     0x00d0  4       Number of times
1261 *  the posted data credits for upstream PCI writes were depleted
1262 * @pic.wrcrdtarb_pd_crdt_depleted[vplane9]     0x00d8  4       Number of times
1263 *  the posted data credits for upstream PCI writes were depleted
1264 * @pic.wrcrdtarb_pd_crdt_depleted[vplane10]    0x00e0  4       Number of times
1265 *  the posted data credits for upstream PCI writes were depleted
1266 * @pic.wrcrdtarb_pd_crdt_depleted[vplane11]    0x00e8  4       Number of times
1267 *  the posted data credits for upstream PCI writes were depleted
1268 * @pic.wrcrdtarb_pd_crdt_depleted[vplane12]    0x00f0  4       Number of times
1269 *  the posted data credits for upstream PCI writes were depleted
1270 * @pic.wrcrdtarb_pd_crdt_depleted[vplane13]    0x00f8  4       Number of times
1271 *  the posted data credits for upstream PCI writes were depleted
1272 * @pic.wrcrdtarb_pd_crdt_depleted[vplane14]    0x0100  4       Number of times
1273 *  the posted data credits for upstream PCI writes were depleted
1274 * @pic.wrcrdtarb_pd_crdt_depleted[vplane15]    0x0108  4       Number of times
1275 *  the posted data credits for upstream PCI writes were depleted
1276 * @pic.wrcrdtarb_pd_crdt_depleted[vplane16]    0x0110  4       Number of times
1277 *  the posted data credits for upstream PCI writes were depleted
1278 * @pic.rdcrdtarb_nph_crdt_depleted[vplane0]    0x0118  4       Number of times
1279 *  the non-posted header credits for upstream PCI reads were depleted
1280 * @pic.rdcrdtarb_nph_crdt_depleted[vplane1]    0x0120  4       Number of times
1281 *  the non-posted header credits for upstream PCI reads were depleted
1282 * @pic.rdcrdtarb_nph_crdt_depleted[vplane2]    0x0128  4       Number of times
1283 *  the non-posted header credits for upstream PCI reads were depleted
1284 * @pic.rdcrdtarb_nph_crdt_depleted[vplane3]    0x0130  4       Number of times
1285 *  the non-posted header credits for upstream PCI reads were depleted
1286 * @pic.rdcrdtarb_nph_crdt_depleted[vplane4]    0x0138  4       Number of times
1287 *  the non-posted header credits for upstream PCI reads were depleted
1288 * @pic.rdcrdtarb_nph_crdt_depleted[vplane5]    0x0140  4       Number of times
1289 *  the non-posted header credits for upstream PCI reads were depleted
1290 * @pic.rdcrdtarb_nph_crdt_depleted[vplane6]    0x0148  4       Number of times
1291 *  the non-posted header credits for upstream PCI reads were depleted
1292 * @pic.rdcrdtarb_nph_crdt_depleted[vplane7]    0x0150  4       Number of times
1293 *  the non-posted header credits for upstream PCI reads were depleted
1294 * @pic.rdcrdtarb_nph_crdt_depleted[vplane8]    0x0158  4       Number of times
1295 *  the non-posted header credits for upstream PCI reads were depleted
1296 * @pic.rdcrdtarb_nph_crdt_depleted[vplane9]    0x0160  4       Number of times
1297 *  the non-posted header credits for upstream PCI reads were depleted
1298 * @pic.rdcrdtarb_nph_crdt_depleted[vplane10]   0x0168  4       Number of times
1299 *  the non-posted header credits for upstream PCI reads were depleted
1300 * @pic.rdcrdtarb_nph_crdt_depleted[vplane11]   0x0170  4       Number of times
1301 *  the non-posted header credits for upstream PCI reads were depleted
1302 * @pic.rdcrdtarb_nph_crdt_depleted[vplane12]   0x0178  4       Number of times
1303 *  the non-posted header credits for upstream PCI reads were depleted
1304 * @pic.rdcrdtarb_nph_crdt_depleted[vplane13]   0x0180  4       Number of times
1305 *  the non-posted header credits for upstream PCI reads were depleted
1306 * @pic.rdcrdtarb_nph_crdt_depleted[vplane14]   0x0188  4       Number of times
1307 *  the non-posted header credits for upstream PCI reads were depleted
1308 * @pic.rdcrdtarb_nph_crdt_depleted[vplane15]   0x0190  4       Number of times
1309 *  the non-posted header credits for upstream PCI reads were depleted
1310 * @pic.rdcrdtarb_nph_crdt_depleted[vplane16]   0x0198  4       Number of times
1311 *  the non-posted header credits for upstream PCI reads were depleted
1312 * @pic.ini_rd_vpin_drop        0x01a0  4       Number of DMA reads initiated by
1313 *  the adapter that were discarded because the VPATH instance number does
1314 *  not match
1315 * @pic.ini_wr_vpin_drop        0x01a4  4       Number of DMA writes initiated
1316 *  by the adapter that were discarded because the VPATH instance number
1317 *  does not match
1318 * @pic.genstats_count0         0x01a8  4       Configurable statistic #1. Refer
1319 *  to the GENSTATS0_CFG for information on configuring this statistic
1320 * @pic.genstats_count1         0x01ac  4       Configurable statistic #2. Refer
1321 *  to the GENSTATS1_CFG for information on configuring this statistic
1322 * @pic.genstats_count2         0x01b0  4       Configurable statistic #3. Refer
1323 *  to the GENSTATS2_CFG for information on configuring this statistic
1324 * @pic.genstats_count3         0x01b4  4       Configurable statistic #4. Refer
1325 *  to the GENSTATS3_CFG for information on configuring this statistic
1326 * @pic.genstats_count4         0x01b8  4       Configurable statistic #5. Refer
1327 *  to the GENSTATS4_CFG for information on configuring this statistic
1328 * @pic.genstats_count5         0x01c0  4       Configurable statistic #6. Refer
1329 *  to the GENSTATS5_CFG for information on configuring this statistic
1330 * @pci.rstdrop_cpl     0x01c8  4
1331 * @pci.rstdrop_msg     0x01cc  4
1332 * @pci.rstdrop_client1         0x01d0  4
1333 * @pci.rstdrop_client0         0x01d4  4
1334 * @pci.rstdrop_client2         0x01d8  4
1335 * @pci.depl_cplh[vplane0]      0x01e2  2       Number of times completion
1336 *  header credits were depleted
1337 * @pci.depl_nph[vplane0]       0x01e4  2       Number of times non posted
1338 *  header credits were depleted
1339 * @pci.depl_ph[vplane0]        0x01e6  2       Number of times the posted
1340 *  header credits were depleted
1341 * @pci.depl_cplh[vplane1]      0x01ea  2
1342 * @pci.depl_nph[vplane1]       0x01ec  2
1343 * @pci.depl_ph[vplane1]        0x01ee  2
1344 * @pci.depl_cplh[vplane2]      0x01f2  2
1345 * @pci.depl_nph[vplane2]       0x01f4  2
1346 * @pci.depl_ph[vplane2]        0x01f6  2
1347 * @pci.depl_cplh[vplane3]      0x01fa  2
1348 * @pci.depl_nph[vplane3]       0x01fc  2
1349 * @pci.depl_ph[vplane3]        0x01fe  2
1350 * @pci.depl_cplh[vplane4]      0x0202  2
1351 * @pci.depl_nph[vplane4]       0x0204  2
1352 * @pci.depl_ph[vplane4]        0x0206  2
1353 * @pci.depl_cplh[vplane5]      0x020a  2
1354 * @pci.depl_nph[vplane5]       0x020c  2
1355 * @pci.depl_ph[vplane5]        0x020e  2
1356 * @pci.depl_cplh[vplane6]      0x0212  2
1357 * @pci.depl_nph[vplane6]       0x0214  2
1358 * @pci.depl_ph[vplane6]        0x0216  2
1359 * @pci.depl_cplh[vplane7]      0x021a  2
1360 * @pci.depl_nph[vplane7]       0x021c  2
1361 * @pci.depl_ph[vplane7]        0x021e  2
1362 * @pci.depl_cplh[vplane8]      0x0222  2
1363 * @pci.depl_nph[vplane8]       0x0224  2
1364 * @pci.depl_ph[vplane8]        0x0226  2
1365 * @pci.depl_cplh[vplane9]      0x022a  2
1366 * @pci.depl_nph[vplane9]       0x022c  2
1367 * @pci.depl_ph[vplane9]        0x022e  2
1368 * @pci.depl_cplh[vplane10]     0x0232  2
1369 * @pci.depl_nph[vplane10]      0x0234  2
1370 * @pci.depl_ph[vplane10]       0x0236  2
1371 * @pci.depl_cplh[vplane11]     0x023a  2
1372 * @pci.depl_nph[vplane11]      0x023c  2
1373 * @pci.depl_ph[vplane11]       0x023e  2
1374 * @pci.depl_cplh[vplane12]     0x0242  2
1375 * @pci.depl_nph[vplane12]      0x0244  2
1376 * @pci.depl_ph[vplane12]       0x0246  2
1377 * @pci.depl_cplh[vplane13]     0x024a  2
1378 * @pci.depl_nph[vplane13]      0x024c  2
1379 * @pci.depl_ph[vplane13]       0x024e  2
1380 * @pci.depl_cplh[vplane14]     0x0252  2
1381 * @pci.depl_nph[vplane14]      0x0254  2
1382 * @pci.depl_ph[vplane14]       0x0256  2
1383 * @pci.depl_cplh[vplane15]     0x025a  2
1384 * @pci.depl_nph[vplane15]      0x025c  2
1385 * @pci.depl_ph[vplane15]       0x025e  2
1386 * @pci.depl_cplh[vplane16]     0x0262  2
1387 * @pci.depl_nph[vplane16]      0x0264  2
1388 * @pci.depl_ph[vplane16]       0x0266  2
1389 * @pci.depl_cpld[vplane0]      0x026a  2       Number of times completion data
1390 *  credits were depleted
1391 * @pci.depl_npd[vplane0]       0x026c  2       Number of times non posted data
1392 *  credits were depleted
1393 * @pci.depl_pd[vplane0]        0x026e  2       Number of times the posted data
1394 *  credits were depleted
1395 * @pci.depl_cpld[vplane1]      0x0272  2
1396 * @pci.depl_npd[vplane1]       0x0274  2
1397 * @pci.depl_pd[vplane1]        0x0276  2
1398 * @pci.depl_cpld[vplane2]      0x027a  2
1399 * @pci.depl_npd[vplane2]       0x027c  2
1400 * @pci.depl_pd[vplane2]        0x027e  2
1401 * @pci.depl_cpld[vplane3]      0x0282  2
1402 * @pci.depl_npd[vplane3]       0x0284  2
1403 * @pci.depl_pd[vplane3]        0x0286  2
1404 * @pci.depl_cpld[vplane4]      0x028a  2
1405 * @pci.depl_npd[vplane4]       0x028c  2
1406 * @pci.depl_pd[vplane4]        0x028e  2
1407 * @pci.depl_cpld[vplane5]      0x0292  2
1408 * @pci.depl_npd[vplane5]       0x0294  2
1409 * @pci.depl_pd[vplane5]        0x0296  2
1410 * @pci.depl_cpld[vplane6]      0x029a  2
1411 * @pci.depl_npd[vplane6]       0x029c  2
1412 * @pci.depl_pd[vplane6]        0x029e  2
1413 * @pci.depl_cpld[vplane7]      0x02a2  2
1414 * @pci.depl_npd[vplane7]       0x02a4  2
1415 * @pci.depl_pd[vplane7]        0x02a6  2
1416 * @pci.depl_cpld[vplane8]      0x02aa  2
1417 * @pci.depl_npd[vplane8]       0x02ac  2
1418 * @pci.depl_pd[vplane8]        0x02ae  2
1419 * @pci.depl_cpld[vplane9]      0x02b2  2
1420 * @pci.depl_npd[vplane9]       0x02b4  2
1421 * @pci.depl_pd[vplane9]        0x02b6  2
1422 * @pci.depl_cpld[vplane10]     0x02ba  2
1423 * @pci.depl_npd[vplane10]      0x02bc  2
1424 * @pci.depl_pd[vplane10]       0x02be  2
1425 * @pci.depl_cpld[vplane11]     0x02c2  2
1426 * @pci.depl_npd[vplane11]      0x02c4  2
1427 * @pci.depl_pd[vplane11]       0x02c6  2
1428 * @pci.depl_cpld[vplane12]     0x02ca  2
1429 * @pci.depl_npd[vplane12]      0x02cc  2
1430 * @pci.depl_pd[vplane12]       0x02ce  2
1431 * @pci.depl_cpld[vplane13]     0x02d2  2
1432 * @pci.depl_npd[vplane13]      0x02d4  2
1433 * @pci.depl_pd[vplane13]       0x02d6  2
1434 * @pci.depl_cpld[vplane14]     0x02da  2
1435 * @pci.depl_npd[vplane14]      0x02dc  2
1436 * @pci.depl_pd[vplane14]       0x02de  2
1437 * @pci.depl_cpld[vplane15]     0x02e2  2
1438 * @pci.depl_npd[vplane15]      0x02e4  2
1439 * @pci.depl_pd[vplane15]       0x02e6  2
1440 * @pci.depl_cpld[vplane16]     0x02ea  2
1441 * @pci.depl_npd[vplane16]      0x02ec  2
1442 * @pci.depl_pd[vplane16]       0x02ee  2
1443 * @xgmac_port[3];
1444 * @xgmac_aggr[2];
1445 * @xgmac.global_prog_event_gnum0       0x0ae0  8       Programmable statistic.
1446 *  Increments when internal logic detects a certain event. See register
1447 *  XMAC_STATS_GLOBAL_CFG.EVENT_GNUM0_CFG for more information.
1448 * @xgmac.global_prog_event_gnum1       0x0ae8  8       Programmable statistic.
1449 *  Increments when internal logic detects a certain event. See register
1450 *  XMAC_STATS_GLOBAL_CFG.EVENT_GNUM1_CFG for more information.
1451 * @xgmac.orp_lro_events        0x0af8  8
1452 * @xgmac.orp_bs_events         0x0b00  8
1453 * @xgmac.orp_iwarp_events      0x0b08  8
1454 * @xgmac.tx_permitted_frms     0x0b14  4
1455 * @xgmac.port2_tx_any_frms     0x0b1d  1
1456 * @xgmac.port1_tx_any_frms     0x0b1e  1
1457 * @xgmac.port0_tx_any_frms     0x0b1f  1
1458 * @xgmac.port2_rx_any_frms     0x0b25  1
1459 * @xgmac.port1_rx_any_frms     0x0b26  1
1460 * @xgmac.port0_rx_any_frms     0x0b27  1
1461 *
1462 * Titan mrpcim hardware statistics.
1463 */
1464struct vxge_hw_device_stats_mrpcim_info {
1465/*0x0000*/      u32     pic_ini_rd_drop;
1466/*0x0004*/      u32     pic_ini_wr_drop;
1467/*0x0008*/      struct {
1468        /*0x0000*/      u32     pic_wrcrdtarb_ph_crdt_depleted;
1469        /*0x0004*/      u32     unused1;
1470                } pic_wrcrdtarb_ph_crdt_depleted_vplane[17];
1471/*0x0090*/      struct {
1472        /*0x0000*/      u32     pic_wrcrdtarb_pd_crdt_depleted;
1473        /*0x0004*/      u32     unused2;
1474                } pic_wrcrdtarb_pd_crdt_depleted_vplane[17];
1475/*0x0118*/      struct {
1476        /*0x0000*/      u32     pic_rdcrdtarb_nph_crdt_depleted;
1477        /*0x0004*/      u32     unused3;
1478                } pic_rdcrdtarb_nph_crdt_depleted_vplane[17];
1479/*0x01a0*/      u32     pic_ini_rd_vpin_drop;
1480/*0x01a4*/      u32     pic_ini_wr_vpin_drop;
1481/*0x01a8*/      u32     pic_genstats_count0;
1482/*0x01ac*/      u32     pic_genstats_count1;
1483/*0x01b0*/      u32     pic_genstats_count2;
1484/*0x01b4*/      u32     pic_genstats_count3;
1485/*0x01b8*/      u32     pic_genstats_count4;
1486/*0x01bc*/      u32     unused4;
1487/*0x01c0*/      u32     pic_genstats_count5;
1488/*0x01c4*/      u32     unused5;
1489/*0x01c8*/      u32     pci_rstdrop_cpl;
1490/*0x01cc*/      u32     pci_rstdrop_msg;
1491/*0x01d0*/      u32     pci_rstdrop_client1;
1492/*0x01d4*/      u32     pci_rstdrop_client0;
1493/*0x01d8*/      u32     pci_rstdrop_client2;
1494/*0x01dc*/      u32     unused6;
1495/*0x01e0*/      struct {
1496        /*0x0000*/      u16     unused7;
1497        /*0x0002*/      u16     pci_depl_cplh;
1498        /*0x0004*/      u16     pci_depl_nph;
1499        /*0x0006*/      u16     pci_depl_ph;
1500                } pci_depl_h_vplane[17];
1501/*0x0268*/      struct {
1502        /*0x0000*/      u16     unused8;
1503        /*0x0002*/      u16     pci_depl_cpld;
1504        /*0x0004*/      u16     pci_depl_npd;
1505        /*0x0006*/      u16     pci_depl_pd;
1506                } pci_depl_d_vplane[17];
1507/*0x02f0*/      struct vxge_hw_xmac_port_stats xgmac_port[3];
1508/*0x0a10*/      struct vxge_hw_xmac_aggr_stats xgmac_aggr[2];
1509/*0x0ae0*/      u64     xgmac_global_prog_event_gnum0;
1510/*0x0ae8*/      u64     xgmac_global_prog_event_gnum1;
1511/*0x0af0*/      u64     unused7;
1512/*0x0af8*/      u64     unused8;
1513/*0x0b00*/      u64     unused9;
1514/*0x0b08*/      u64     unused10;
1515/*0x0b10*/      u32     unused11;
1516/*0x0b14*/      u32     xgmac_tx_permitted_frms;
1517/*0x0b18*/      u32     unused12;
1518/*0x0b1c*/      u8      unused13;
1519/*0x0b1d*/      u8      xgmac_port2_tx_any_frms;
1520/*0x0b1e*/      u8      xgmac_port1_tx_any_frms;
1521/*0x0b1f*/      u8      xgmac_port0_tx_any_frms;
1522/*0x0b20*/      u32     unused14;
1523/*0x0b24*/      u8      unused15;
1524/*0x0b25*/      u8      xgmac_port2_rx_any_frms;
1525/*0x0b26*/      u8      xgmac_port1_rx_any_frms;
1526/*0x0b27*/      u8      xgmac_port0_rx_any_frms;
1527} __packed;
1528
1529/**
1530 * struct vxge_hw_device_stats_hw_info - Titan hardware statistics.
1531 * @vpath_info: VPath statistics
1532 * @vpath_info_sav: Vpath statistics saved
1533 *
1534 * Titan hardware statistics.
1535 */
1536struct vxge_hw_device_stats_hw_info {
1537        struct vxge_hw_vpath_stats_hw_info
1538                *vpath_info[VXGE_HW_MAX_VIRTUAL_PATHS];
1539        struct vxge_hw_vpath_stats_hw_info
1540                vpath_info_sav[VXGE_HW_MAX_VIRTUAL_PATHS];
1541};
1542
1543/**
1544 * struct vxge_hw_vpath_stats_sw_common_info - HW common
1545 * statistics for queues.
1546 * @full_cnt: Number of times the queue was full
1547 * @usage_cnt: usage count.
1548 * @usage_max: Maximum usage
1549 * @reserve_free_swaps_cnt: Reserve/free swap counter. Internal usage.
1550 * @total_compl_cnt: Total descriptor completion count.
1551 *
1552 * Hw queue counters
1553 * See also: struct vxge_hw_vpath_stats_sw_fifo_info{},
1554 * struct vxge_hw_vpath_stats_sw_ring_info{},
1555 */
1556struct vxge_hw_vpath_stats_sw_common_info {
1557        u32     full_cnt;
1558        u32     usage_cnt;
1559        u32     usage_max;
1560        u32     reserve_free_swaps_cnt;
1561        u32 total_compl_cnt;
1562};
1563
1564/**
1565 * struct vxge_hw_vpath_stats_sw_fifo_info - HW fifo statistics
1566 * @common_stats: Common counters for all queues
1567 * @total_posts: Total number of postings on the queue.
1568 * @total_buffers: Total number of buffers posted.
1569 * @txd_t_code_err_cnt: Array of transmit transfer codes. The position
1570 * (index) in this array reflects the transfer code type, for instance
1571 * 0xA - "loss of link".
1572 * Value txd_t_code_err_cnt[i] reflects the
1573 * number of times the corresponding transfer code was encountered.
1574 *
1575 * HW fifo counters
1576 * See also: struct vxge_hw_vpath_stats_sw_common_info{},
1577 * struct vxge_hw_vpath_stats_sw_ring_info{},
1578 */
1579struct vxge_hw_vpath_stats_sw_fifo_info {
1580        struct vxge_hw_vpath_stats_sw_common_info common_stats;
1581        u32 total_posts;
1582        u32 total_buffers;
1583        u32 txd_t_code_err_cnt[VXGE_HW_DTR_MAX_T_CODE];
1584};
1585
1586/**
1587 * struct vxge_hw_vpath_stats_sw_ring_info - HW ring statistics
1588 * @common_stats: Common counters for all queues
1589 * @rxd_t_code_err_cnt: Array of receive transfer codes. The position
1590 *             (index) in this array reflects the transfer code type,
1591 *             for instance
1592 *             0x7 - for "invalid receive buffer size", or 0x8 - for ECC.
1593 *             Value rxd_t_code_err_cnt[i] reflects the
1594 *             number of times the corresponding transfer code was encountered.
1595 *
1596 * HW ring counters
1597 * See also: struct vxge_hw_vpath_stats_sw_common_info{},
1598 * struct vxge_hw_vpath_stats_sw_fifo_info{},
1599 */
1600struct vxge_hw_vpath_stats_sw_ring_info {
1601        struct vxge_hw_vpath_stats_sw_common_info common_stats;
1602        u32 rxd_t_code_err_cnt[VXGE_HW_DTR_MAX_T_CODE];
1603
1604};
1605
1606/**
1607 * struct vxge_hw_vpath_stats_sw_err - HW vpath error statistics
1608 * @unknown_alarms:
1609 * @network_sustained_fault:
1610 * @network_sustained_ok:
1611 * @kdfcctl_fifo0_overwrite:
1612 * @kdfcctl_fifo0_poison:
1613 * @kdfcctl_fifo0_dma_error:
1614 * @dblgen_fifo0_overflow:
1615 * @statsb_pif_chain_error:
1616 * @statsb_drop_timeout:
1617 * @target_illegal_access:
1618 * @ini_serr_det:
1619 * @prc_ring_bumps:
1620 * @prc_rxdcm_sc_err:
1621 * @prc_rxdcm_sc_abort:
1622 * @prc_quanta_size_err:
1623 *
1624 * HW vpath error statistics
1625 */
1626struct vxge_hw_vpath_stats_sw_err {
1627        u32     unknown_alarms;
1628        u32     network_sustained_fault;
1629        u32     network_sustained_ok;
1630        u32     kdfcctl_fifo0_overwrite;
1631        u32     kdfcctl_fifo0_poison;
1632        u32     kdfcctl_fifo0_dma_error;
1633        u32     dblgen_fifo0_overflow;
1634        u32     statsb_pif_chain_error;
1635        u32     statsb_drop_timeout;
1636        u32     target_illegal_access;
1637        u32     ini_serr_det;
1638        u32     prc_ring_bumps;
1639        u32     prc_rxdcm_sc_err;
1640        u32     prc_rxdcm_sc_abort;
1641        u32     prc_quanta_size_err;
1642};
1643
1644/**
1645 * struct vxge_hw_vpath_stats_sw_info - HW vpath sw statistics
1646 * @soft_reset_cnt: Number of times soft reset is done on this vpath.
1647 * @error_stats: error counters for the vpath
1648 * @ring_stats: counters for ring belonging to the vpath
1649 * @fifo_stats: counters for fifo belonging to the vpath
1650 *
1651 * HW vpath sw statistics
1652 * See also: struct vxge_hw_device_info{} }.
1653 */
1654struct vxge_hw_vpath_stats_sw_info {
1655        u32    soft_reset_cnt;
1656        struct vxge_hw_vpath_stats_sw_err       error_stats;
1657        struct vxge_hw_vpath_stats_sw_ring_info ring_stats;
1658        struct vxge_hw_vpath_stats_sw_fifo_info fifo_stats;
1659};
1660
1661/**
1662 * struct vxge_hw_device_stats_sw_info - HW own per-device statistics.
1663 *
1664 * @not_traffic_intr_cnt: Number of times the host was interrupted
1665 *                        without new completions.
1666 *                        "Non-traffic interrupt counter".
1667 * @traffic_intr_cnt: Number of traffic interrupts for the device.
1668 * @total_intr_cnt: Total number of traffic interrupts for the device.
1669 *                  @total_intr_cnt == @traffic_intr_cnt +
1670 *                              @not_traffic_intr_cnt
1671 * @soft_reset_cnt: Number of times soft reset is done on this device.
1672 * @vpath_info: please see struct vxge_hw_vpath_stats_sw_info{}
1673 * HW per-device statistics.
1674 */
1675struct vxge_hw_device_stats_sw_info {
1676        u32     not_traffic_intr_cnt;
1677        u32     traffic_intr_cnt;
1678        u32     total_intr_cnt;
1679        u32     soft_reset_cnt;
1680        struct vxge_hw_vpath_stats_sw_info
1681                vpath_info[VXGE_HW_MAX_VIRTUAL_PATHS];
1682};
1683
1684/**
1685 * struct vxge_hw_device_stats_sw_err - HW device error statistics.
1686 * @vpath_alarms: Number of vpath alarms
1687 *
1688 * HW Device error stats
1689 */
1690struct vxge_hw_device_stats_sw_err {
1691        u32     vpath_alarms;
1692};
1693
1694/**
1695 * struct vxge_hw_device_stats - Contains HW per-device statistics,
1696 * including hw.
1697 * @devh: HW device handle.
1698 * @dma_addr: DMA address of the %hw_info. Given to device to fill-in the stats.
1699 * @hw_info_dmah: DMA handle used to map hw statistics onto the device memory
1700 *                space.
1701 * @hw_info_dma_acch: One more DMA handle used subsequently to free the
1702 *                    DMA object. Note that this and the previous handle have
1703 *                    physical meaning for Solaris; on Windows and Linux the
1704 *                    corresponding value will be simply pointer to PCI device.
1705 *
1706 * @hw_dev_info_stats: Titan statistics maintained by the hardware.
1707 * @sw_dev_info_stats: HW's "soft" device informational statistics, e.g. number
1708 *                     of completions per interrupt.
1709 * @sw_dev_err_stats: HW's "soft" device error statistics.
1710 *
1711 * Structure-container of HW per-device statistics. Note that per-channel
1712 * statistics are kept in separate structures under HW's fifo and ring
1713 * channels.
1714 */
1715struct vxge_hw_device_stats {
1716        /* handles */
1717        struct __vxge_hw_device *devh;
1718
1719        /* HW device hardware statistics */
1720        struct vxge_hw_device_stats_hw_info     hw_dev_info_stats;
1721
1722        /* HW device "soft" stats */
1723        struct vxge_hw_device_stats_sw_err   sw_dev_err_stats;
1724        struct vxge_hw_device_stats_sw_info  sw_dev_info_stats;
1725
1726};
1727
1728enum vxge_hw_status vxge_hw_device_hw_stats_enable(
1729                        struct __vxge_hw_device *devh);
1730
1731enum vxge_hw_status vxge_hw_device_stats_get(
1732                        struct __vxge_hw_device *devh,
1733                        struct vxge_hw_device_stats_hw_info *hw_stats);
1734
1735enum vxge_hw_status vxge_hw_driver_stats_get(
1736                        struct __vxge_hw_device *devh,
1737                        struct vxge_hw_device_stats_sw_info *sw_stats);
1738
1739enum vxge_hw_status vxge_hw_mrpcim_stats_enable(struct __vxge_hw_device *devh);
1740
1741enum vxge_hw_status vxge_hw_mrpcim_stats_disable(struct __vxge_hw_device *devh);
1742
1743enum vxge_hw_status
1744vxge_hw_mrpcim_stats_access(
1745        struct __vxge_hw_device *devh,
1746        u32 operation,
1747        u32 location,
1748        u32 offset,
1749        u64 *stat);
1750
1751enum vxge_hw_status
1752vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *devh,
1753                              struct vxge_hw_xmac_stats *xmac_stats);
1754
1755/**
1756 * enum enum vxge_hw_mgmt_reg_type - Register types.
1757 *
1758 * @vxge_hw_mgmt_reg_type_legacy: Legacy registers
1759 * @vxge_hw_mgmt_reg_type_toc: TOC Registers
1760 * @vxge_hw_mgmt_reg_type_common: Common Registers
1761 * @vxge_hw_mgmt_reg_type_mrpcim: mrpcim registers
1762 * @vxge_hw_mgmt_reg_type_srpcim: srpcim registers
1763 * @vxge_hw_mgmt_reg_type_vpmgmt: vpath management registers
1764 * @vxge_hw_mgmt_reg_type_vpath: vpath registers
1765 *
1766 * Register type enumaration
1767 */
1768enum vxge_hw_mgmt_reg_type {
1769        vxge_hw_mgmt_reg_type_legacy = 0,
1770        vxge_hw_mgmt_reg_type_toc = 1,
1771        vxge_hw_mgmt_reg_type_common = 2,
1772        vxge_hw_mgmt_reg_type_mrpcim = 3,
1773        vxge_hw_mgmt_reg_type_srpcim = 4,
1774        vxge_hw_mgmt_reg_type_vpmgmt = 5,
1775        vxge_hw_mgmt_reg_type_vpath = 6
1776};
1777
1778enum vxge_hw_status
1779vxge_hw_mgmt_reg_read(struct __vxge_hw_device *devh,
1780                      enum vxge_hw_mgmt_reg_type type,
1781                      u32 index,
1782                      u32 offset,
1783                      u64 *value);
1784
1785enum vxge_hw_status
1786vxge_hw_mgmt_reg_write(struct __vxge_hw_device *devh,
1787                      enum vxge_hw_mgmt_reg_type type,
1788                      u32 index,
1789                      u32 offset,
1790                      u64 value);
1791
1792/**
1793 * enum enum vxge_hw_rxd_state - Descriptor (RXD) state.
1794 * @VXGE_HW_RXD_STATE_NONE: Invalid state.
1795 * @VXGE_HW_RXD_STATE_AVAIL: Descriptor is available for reservation.
1796 * @VXGE_HW_RXD_STATE_POSTED: Descriptor is posted for processing by the
1797 * device.
1798 * @VXGE_HW_RXD_STATE_FREED: Descriptor is free and can be reused for
1799 * filling-in and posting later.
1800 *
1801 * Titan/HW descriptor states.
1802 *
1803 */
1804enum vxge_hw_rxd_state {
1805        VXGE_HW_RXD_STATE_NONE          = 0,
1806        VXGE_HW_RXD_STATE_AVAIL         = 1,
1807        VXGE_HW_RXD_STATE_POSTED        = 2,
1808        VXGE_HW_RXD_STATE_FREED         = 3
1809};
1810
1811/**
1812 * struct vxge_hw_ring_rxd_info - Extended information associated with a
1813 * completed ring descriptor.
1814 * @syn_flag: SYN flag
1815 * @is_icmp: Is ICMP
1816 * @fast_path_eligible: Fast Path Eligible flag
1817 * @l3_cksum: in L3 checksum is valid
1818 * @l3_cksum: Result of IP checksum check (by Titan hardware).
1819 *            This field containing VXGE_HW_L3_CKSUM_OK would mean that
1820 *            the checksum is correct, otherwise - the datagram is
1821 *            corrupted.
1822 * @l4_cksum: in L4 checksum is valid
1823 * @l4_cksum: Result of TCP/UDP checksum check (by Titan hardware).
1824 *            This field containing VXGE_HW_L4_CKSUM_OK would mean that
1825 *            the checksum is correct. Otherwise - the packet is
1826 *            corrupted.
1827 * @frame: Zero or more of enum vxge_hw_frame_type flags.
1828 *              See enum vxge_hw_frame_type{}.
1829 * @proto: zero or more of enum vxge_hw_frame_proto flags.  Reporting bits for
1830 *            various higher-layer protocols, including (but note restricted to)
1831 *            TCP and UDP. See enum vxge_hw_frame_proto{}.
1832 * @is_vlan: If vlan tag is valid
1833 * @vlan: VLAN tag extracted from the received frame.
1834 * @rth_bucket: RTH bucket
1835 * @rth_it_hit: Set, If RTH hash value calculated by the Titan hardware
1836 *             has a matching entry in the Indirection table.
1837 * @rth_spdm_hit: Set, If RTH hash value calculated by the Titan hardware
1838 *             has a matching entry in the Socket Pair Direct Match table.
1839 * @rth_hash_type: RTH hash code of the function used to calculate the hash.
1840 * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Titan
1841 *             hardware if RTH is enabled.
1842 */
1843struct vxge_hw_ring_rxd_info {
1844        u32     syn_flag;
1845        u32     is_icmp;
1846        u32     fast_path_eligible;
1847        u32     l3_cksum_valid;
1848        u32     l3_cksum;
1849        u32     l4_cksum_valid;
1850        u32     l4_cksum;
1851        u32     frame;
1852        u32     proto;
1853        u32     is_vlan;
1854        u32     vlan;
1855        u32     rth_bucket;
1856        u32     rth_it_hit;
1857        u32     rth_spdm_hit;
1858        u32     rth_hash_type;
1859        u32     rth_value;
1860};
1861/**
1862 * enum vxge_hw_ring_tcode - Transfer codes returned by adapter
1863 * @VXGE_HW_RING_T_CODE_OK: Transfer ok.
1864 * @VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation
1865 *              configuration mismatch.
1866 * @VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation
1867 *              configuration mismatch.
1868 * @VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum
1869 *              presentation configuration mismatch.
1870 * @VXGE_HW_RING_T_CODE_L3_PKT_ERR: Layer 3 error unparseable packet,
1871 *              such as unknown IPv6 header.
1872 * @VXGE_HW_RING_T_CODE_L2_FRM_ERR: Layer 2 error frame integrity
1873 *              error, such as FCS or ECC).
1874 * @VXGE_HW_RING_T_CODE_BUF_SIZE_ERR: Buffer size error the RxD buffer(
1875 *              s) were not appropriately sized and data loss occurred.
1876 * @VXGE_HW_RING_T_CODE_INT_ECC_ERR: Internal ECC error RxD corrupted.
1877 * @VXGE_HW_RING_T_CODE_BENIGN_OVFLOW: Benign overflow the contents of
1878 *              Segment1 exceeded the capacity of Buffer1 and the remainder
1879 *              was placed in Buffer2. Segment2 now starts in Buffer3.
1880 *              No data loss or errors occurred.
1881 * @VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0 one of the RxDs
1882 *              assigned buffers has a size of 0 bytes.
1883 * @VXGE_HW_RING_T_CODE_FRM_DROP: Frame dropped either due to
1884 *              VPath Reset or because of a VPIN mismatch.
1885 * @VXGE_HW_RING_T_CODE_UNUSED: Unused
1886 * @VXGE_HW_RING_T_CODE_MULTI_ERR: Multiple errors more than one
1887 *              transfer code condition occurred.
1888 *
1889 * Transfer codes returned by adapter.
1890 */
1891enum vxge_hw_ring_tcode {
1892        VXGE_HW_RING_T_CODE_OK                          = 0x0,
1893        VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH           = 0x1,
1894        VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH           = 0x2,
1895        VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH        = 0x3,
1896        VXGE_HW_RING_T_CODE_L3_PKT_ERR                  = 0x5,
1897        VXGE_HW_RING_T_CODE_L2_FRM_ERR                  = 0x6,
1898        VXGE_HW_RING_T_CODE_BUF_SIZE_ERR                = 0x7,
1899        VXGE_HW_RING_T_CODE_INT_ECC_ERR                 = 0x8,
1900        VXGE_HW_RING_T_CODE_BENIGN_OVFLOW               = 0x9,
1901        VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF               = 0xA,
1902        VXGE_HW_RING_T_CODE_FRM_DROP                    = 0xC,
1903        VXGE_HW_RING_T_CODE_UNUSED                      = 0xE,
1904        VXGE_HW_RING_T_CODE_MULTI_ERR                   = 0xF
1905};
1906
1907enum vxge_hw_status vxge_hw_ring_rxd_reserve(
1908        struct __vxge_hw_ring *ring_handle,
1909        void **rxdh);
1910
1911void
1912vxge_hw_ring_rxd_pre_post(
1913        struct __vxge_hw_ring *ring_handle,
1914        void *rxdh);
1915
1916void
1917vxge_hw_ring_rxd_post_post(
1918        struct __vxge_hw_ring *ring_handle,
1919        void *rxdh);
1920
1921void
1922vxge_hw_ring_rxd_post_post_wmb(
1923        struct __vxge_hw_ring *ring_handle,
1924        void *rxdh);
1925
1926void vxge_hw_ring_rxd_post(
1927        struct __vxge_hw_ring *ring_handle,
1928        void *rxdh);
1929
1930enum vxge_hw_status vxge_hw_ring_rxd_next_completed(
1931        struct __vxge_hw_ring *ring_handle,
1932        void **rxdh,
1933        u8 *t_code);
1934
1935enum vxge_hw_status vxge_hw_ring_handle_tcode(
1936        struct __vxge_hw_ring *ring_handle,
1937        void *rxdh,
1938        u8 t_code);
1939
1940void vxge_hw_ring_rxd_free(
1941        struct __vxge_hw_ring *ring_handle,
1942        void *rxdh);
1943
1944/**
1945 * enum enum vxge_hw_frame_proto - Higher-layer ethernet protocols.
1946 * @VXGE_HW_FRAME_PROTO_VLAN_TAGGED: VLAN.
1947 * @VXGE_HW_FRAME_PROTO_IPV4: IPv4.
1948 * @VXGE_HW_FRAME_PROTO_IPV6: IPv6.
1949 * @VXGE_HW_FRAME_PROTO_IP_FRAG: IP fragmented.
1950 * @VXGE_HW_FRAME_PROTO_TCP: TCP.
1951 * @VXGE_HW_FRAME_PROTO_UDP: UDP.
1952 * @VXGE_HW_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
1953 *
1954 * Higher layer ethernet protocols and options.
1955 */
1956enum vxge_hw_frame_proto {
1957        VXGE_HW_FRAME_PROTO_VLAN_TAGGED = 0x80,
1958        VXGE_HW_FRAME_PROTO_IPV4                = 0x10,
1959        VXGE_HW_FRAME_PROTO_IPV6                = 0x08,
1960        VXGE_HW_FRAME_PROTO_IP_FRAG             = 0x04,
1961        VXGE_HW_FRAME_PROTO_TCP                 = 0x02,
1962        VXGE_HW_FRAME_PROTO_UDP                 = 0x01,
1963        VXGE_HW_FRAME_PROTO_TCP_OR_UDP  = (VXGE_HW_FRAME_PROTO_TCP | \
1964                                                   VXGE_HW_FRAME_PROTO_UDP)
1965};
1966
1967/**
1968 * enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD
1969 * @VXGE_HW_FIFO_GATHER_CODE_FIRST: First TxDL
1970 * @VXGE_HW_FIFO_GATHER_CODE_MIDDLE: Middle TxDL
1971 * @VXGE_HW_FIFO_GATHER_CODE_LAST: Last TxDL
1972 * @VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL.
1973 *
1974 * These gather codes are used to indicate the position of a TxD in a TxD list
1975 */
1976enum vxge_hw_fifo_gather_code {
1977        VXGE_HW_FIFO_GATHER_CODE_FIRST          = 0x2,
1978        VXGE_HW_FIFO_GATHER_CODE_MIDDLE         = 0x0,
1979        VXGE_HW_FIFO_GATHER_CODE_LAST           = 0x1,
1980        VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST     = 0x3
1981};
1982
1983/**
1984 * enum enum vxge_hw_fifo_tcode - tcodes used in fifo
1985 * @VXGE_HW_FIFO_T_CODE_OK: Transfer OK
1986 * @VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or
1987 *             frame data) returned with corrupt data.
1988 * @VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned
1989 *             with no data.
1990 * @VXGE_HW_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a
1991 *             frame or LSO MSS that was too long (>9800B).
1992 * @VXGE_HW_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send
1993        *              Offload operation, due to improper header template,
1994        *              unsupported protocol, etc.
1995 * @VXGE_HW_FIFO_T_CODE_UNUSED: Unused
1996 * @VXGE_HW_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple
1997 *             data buffer transfer errors are encountered (see below).
1998 *             Otherwise it is set to 0.
1999 *
2000 * These tcodes are returned in various API for TxD status
2001 */
2002enum vxge_hw_fifo_tcode {
2003        VXGE_HW_FIFO_T_CODE_OK                  = 0x0,
2004        VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT    = 0x1,
2005        VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL       = 0x2,
2006        VXGE_HW_FIFO_T_CODE_INVALID_MSS         = 0x3,
2007        VXGE_HW_FIFO_T_CODE_LSO_ERROR           = 0x4,
2008        VXGE_HW_FIFO_T_CODE_UNUSED              = 0x7,
2009        VXGE_HW_FIFO_T_CODE_MULTI_ERROR         = 0x8
2010};
2011
2012enum vxge_hw_status vxge_hw_fifo_txdl_reserve(
2013        struct __vxge_hw_fifo *fifoh,
2014        void **txdlh,
2015        void **txdl_priv);
2016
2017void vxge_hw_fifo_txdl_buffer_set(
2018                        struct __vxge_hw_fifo *fifo_handle,
2019                        void *txdlh,
2020                        u32 frag_idx,
2021                        dma_addr_t dma_pointer,
2022                        u32 size);
2023
2024void vxge_hw_fifo_txdl_post(
2025                        struct __vxge_hw_fifo *fifo_handle,
2026                        void *txdlh);
2027
2028u32 vxge_hw_fifo_free_txdl_count_get(
2029                        struct __vxge_hw_fifo *fifo_handle);
2030
2031enum vxge_hw_status vxge_hw_fifo_txdl_next_completed(
2032        struct __vxge_hw_fifo *fifoh,
2033        void **txdlh,
2034        enum vxge_hw_fifo_tcode *t_code);
2035
2036enum vxge_hw_status vxge_hw_fifo_handle_tcode(
2037        struct __vxge_hw_fifo *fifoh,
2038        void *txdlh,
2039        enum vxge_hw_fifo_tcode t_code);
2040
2041void vxge_hw_fifo_txdl_free(
2042        struct __vxge_hw_fifo *fifoh,
2043        void *txdlh);
2044
2045/*
2046 * Device
2047 */
2048
2049#define VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET  (VXGE_HW_BLOCK_SIZE-8)
2050#define VXGE_HW_RING_MEMBLOCK_IDX_OFFSET                (VXGE_HW_BLOCK_SIZE-16)
2051
2052/*
2053 * struct __vxge_hw_ring_rxd_priv - Receive descriptor HW-private data.
2054 * @dma_addr: DMA (mapped) address of _this_ descriptor.
2055 * @dma_handle: DMA handle used to map the descriptor onto device.
2056 * @dma_offset: Descriptor's offset in the memory block. HW allocates
2057 *              descriptors in memory blocks of %VXGE_HW_BLOCK_SIZE
2058 *              bytes. Each memblock is contiguous DMA-able memory. Each
2059 *              memblock contains 1 or more 4KB RxD blocks visible to the
2060 *              Titan hardware.
2061 * @dma_object: DMA address and handle of the memory block that contains
2062 *              the descriptor. This member is used only in the "checked"
2063 *              version of the HW (to enforce certain assertions);
2064 *              otherwise it gets compiled out.
2065 * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
2066 *
2067 * Per-receive decsriptor HW-private data. HW uses the space to keep DMA
2068 * information associated with the descriptor. Note that driver can ask HW
2069 * to allocate additional per-descriptor space for its own (driver-specific)
2070 * purposes.
2071 */
2072struct __vxge_hw_ring_rxd_priv {
2073        dma_addr_t      dma_addr;
2074        struct pci_dev *dma_handle;
2075        ptrdiff_t       dma_offset;
2076#ifdef VXGE_DEBUG_ASSERT
2077        struct vxge_hw_mempool_dma      *dma_object;
2078#endif
2079};
2080
2081struct vxge_hw_mempool_cbs {
2082        void (*item_func_alloc)(
2083                        struct vxge_hw_mempool *mempoolh,
2084                        u32                     memblock_index,
2085                        struct vxge_hw_mempool_dma      *dma_object,
2086                        u32                     index,
2087                        u32                     is_last);
2088};
2089
2090#define VXGE_HW_VIRTUAL_PATH_HANDLE(vpath)                              \
2091                ((struct __vxge_hw_vpath_handle *)(vpath)->vpath_handles.next)
2092
2093enum vxge_hw_status
2094__vxge_hw_vpath_rts_table_get(
2095        struct __vxge_hw_vpath_handle *vpath_handle,
2096        u32                     action,
2097        u32                     rts_table,
2098        u32                     offset,
2099        u64                     *data1,
2100        u64                     *data2);
2101
2102enum vxge_hw_status
2103__vxge_hw_vpath_rts_table_set(
2104        struct __vxge_hw_vpath_handle *vpath_handle,
2105        u32                     action,
2106        u32                     rts_table,
2107        u32                     offset,
2108        u64                     data1,
2109        u64                     data2);
2110
2111enum vxge_hw_status
2112__vxge_hw_vpath_enable(
2113        struct __vxge_hw_device *devh,
2114        u32                     vp_id);
2115
2116void vxge_hw_device_intr_enable(
2117        struct __vxge_hw_device *devh);
2118
2119u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *devh, u32 intr_mode);
2120
2121void vxge_hw_device_intr_disable(
2122        struct __vxge_hw_device *devh);
2123
2124void vxge_hw_device_mask_all(
2125        struct __vxge_hw_device *devh);
2126
2127void vxge_hw_device_unmask_all(
2128        struct __vxge_hw_device *devh);
2129
2130enum vxge_hw_status vxge_hw_device_begin_irq(
2131        struct __vxge_hw_device *devh,
2132        u32 skip_alarms,
2133        u64 *reason);
2134
2135void vxge_hw_device_clear_tx_rx(
2136        struct __vxge_hw_device *devh);
2137
2138/*
2139 *  Virtual Paths
2140 */
2141
2142void vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring);
2143
2144void vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo);
2145
2146u32 vxge_hw_vpath_id(
2147        struct __vxge_hw_vpath_handle *vpath_handle);
2148
2149enum vxge_hw_vpath_mac_addr_add_mode {
2150        VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE = 0,
2151        VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE = 1,
2152        VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE = 2
2153};
2154
2155enum vxge_hw_status
2156vxge_hw_vpath_mac_addr_add(
2157        struct __vxge_hw_vpath_handle *vpath_handle,
2158        u8 *macaddr,
2159        u8 *macaddr_mask,
2160        enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode);
2161
2162enum vxge_hw_status
2163vxge_hw_vpath_mac_addr_get(
2164        struct __vxge_hw_vpath_handle *vpath_handle,
2165        u8 *macaddr,
2166        u8 *macaddr_mask);
2167
2168enum vxge_hw_status
2169vxge_hw_vpath_mac_addr_get_next(
2170        struct __vxge_hw_vpath_handle *vpath_handle,
2171        u8 *macaddr,
2172        u8 *macaddr_mask);
2173
2174enum vxge_hw_status
2175vxge_hw_vpath_mac_addr_delete(
2176        struct __vxge_hw_vpath_handle *vpath_handle,
2177        u8 *macaddr,
2178        u8 *macaddr_mask);
2179
2180enum vxge_hw_status
2181vxge_hw_vpath_vid_add(
2182        struct __vxge_hw_vpath_handle *vpath_handle,
2183        u64                     vid);
2184
2185enum vxge_hw_status
2186vxge_hw_vpath_vid_delete(
2187        struct __vxge_hw_vpath_handle *vpath_handle,
2188        u64                     vid);
2189
2190enum vxge_hw_status
2191vxge_hw_vpath_etype_add(
2192        struct __vxge_hw_vpath_handle *vpath_handle,
2193        u64                     etype);
2194
2195enum vxge_hw_status
2196vxge_hw_vpath_etype_get(
2197        struct __vxge_hw_vpath_handle *vpath_handle,
2198        u64                     *etype);
2199
2200enum vxge_hw_status
2201vxge_hw_vpath_etype_get_next(
2202        struct __vxge_hw_vpath_handle *vpath_handle,
2203        u64                     *etype);
2204
2205enum vxge_hw_status
2206vxge_hw_vpath_etype_delete(
2207        struct __vxge_hw_vpath_handle *vpath_handle,
2208        u64                     etype);
2209
2210enum vxge_hw_status vxge_hw_vpath_promisc_enable(
2211        struct __vxge_hw_vpath_handle *vpath_handle);
2212
2213enum vxge_hw_status vxge_hw_vpath_promisc_disable(
2214        struct __vxge_hw_vpath_handle *vpath_handle);
2215
2216enum vxge_hw_status vxge_hw_vpath_bcast_enable(
2217        struct __vxge_hw_vpath_handle *vpath_handle);
2218
2219enum vxge_hw_status vxge_hw_vpath_mcast_enable(
2220        struct __vxge_hw_vpath_handle *vpath_handle);
2221
2222enum vxge_hw_status vxge_hw_vpath_mcast_disable(
2223        struct __vxge_hw_vpath_handle *vpath_handle);
2224
2225enum vxge_hw_status vxge_hw_vpath_poll_rx(
2226        struct __vxge_hw_ring *ringh);
2227
2228enum vxge_hw_status vxge_hw_vpath_poll_tx(
2229        struct __vxge_hw_fifo *fifoh,
2230        struct sk_buff ***skb_ptr, int nr_skb, int *more);
2231
2232enum vxge_hw_status vxge_hw_vpath_alarm_process(
2233        struct __vxge_hw_vpath_handle *vpath_handle,
2234        u32 skip_alarms);
2235
2236void
2237vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vpath_handle,
2238                       int *tim_msix_id, int alarm_msix_id);
2239
2240void
2241vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vpath_handle,
2242                        int msix_id);
2243
2244void vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id);
2245
2246void vxge_hw_device_flush_io(struct __vxge_hw_device *devh);
2247
2248void
2249vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vpath_handle,
2250                          int msix_id);
2251
2252enum vxge_hw_status vxge_hw_vpath_intr_enable(
2253                                struct __vxge_hw_vpath_handle *vpath_handle);
2254
2255enum vxge_hw_status vxge_hw_vpath_intr_disable(
2256                                struct __vxge_hw_vpath_handle *vpath_handle);
2257
2258void vxge_hw_vpath_inta_mask_tx_rx(
2259        struct __vxge_hw_vpath_handle *vpath_handle);
2260
2261void vxge_hw_vpath_inta_unmask_tx_rx(
2262        struct __vxge_hw_vpath_handle *vpath_handle);
2263
2264void
2265vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channelh, int msix_id);
2266
2267void
2268vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channelh, int msix_id);
2269
2270void
2271vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channelh, int msix_id);
2272
2273void
2274vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel,
2275                                 void **dtrh);
2276
2277void
2278vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel);
2279
2280void
2281vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh);
2282
2283int
2284vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel);
2285
2286void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo);
2287
2288void vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring);
2289
2290#endif
2291