linux/drivers/net/ethernet/netronome/nfp/nfpcore/nfp_arm.h
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   1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2/* Copyright (C) 2015-2017 Netronome Systems, Inc. */
   3
   4/*
   5 * nfp_arm.h
   6 * Definitions for ARM-based registers and memory spaces
   7 */
   8
   9#ifndef NFP_ARM_H
  10#define NFP_ARM_H
  11
  12#define NFP_ARM_QUEUE(_q)              (0x100000 + (0x800 * ((_q) & 0xff)))
  13#define NFP_ARM_IM                     0x200000
  14#define NFP_ARM_EM                     0x300000
  15#define NFP_ARM_GCSR                   0x400000
  16#define NFP_ARM_MPCORE                 0x800000
  17#define NFP_ARM_PL310                  0xa00000
  18/* Register Type: BulkBARConfig */
  19#define NFP_ARM_GCSR_BULK_BAR(_bar)    (0x0 + (0x4 * ((_bar) & 0x7)))
  20#define   NFP_ARM_GCSR_BULK_BAR_TYPE                    (0x1 << 31)
  21#define     NFP_ARM_GCSR_BULK_BAR_TYPE_BULK             (0x0)
  22#define     NFP_ARM_GCSR_BULK_BAR_TYPE_EXPA             (0x80000000)
  23#define   NFP_ARM_GCSR_BULK_BAR_TGT(_x)                 (((_x) & 0xf) << 27)
  24#define   NFP_ARM_GCSR_BULK_BAR_TGT_of(_x)              (((_x) >> 27) & 0xf)
  25#define   NFP_ARM_GCSR_BULK_BAR_TOK(_x)                 (((_x) & 0x3) << 25)
  26#define   NFP_ARM_GCSR_BULK_BAR_TOK_of(_x)              (((_x) >> 25) & 0x3)
  27#define   NFP_ARM_GCSR_BULK_BAR_LEN                     (0x1 << 24)
  28#define     NFP_ARM_GCSR_BULK_BAR_LEN_32BIT             (0x0)
  29#define     NFP_ARM_GCSR_BULK_BAR_LEN_64BIT             (0x1000000)
  30#define   NFP_ARM_GCSR_BULK_BAR_ADDR(_x)                ((_x) & 0x7ff)
  31#define   NFP_ARM_GCSR_BULK_BAR_ADDR_of(_x)             ((_x) & 0x7ff)
  32/* Register Type: ExpansionBARConfig */
  33#define NFP_ARM_GCSR_EXPA_BAR(_bar)    (0x20 + (0x4 * ((_bar) & 0xf)))
  34#define   NFP_ARM_GCSR_EXPA_BAR_TYPE                    (0x1 << 31)
  35#define     NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPA             (0x0)
  36#define     NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPL             (0x80000000)
  37#define   NFP_ARM_GCSR_EXPA_BAR_TGT(_x)                 (((_x) & 0xf) << 27)
  38#define   NFP_ARM_GCSR_EXPA_BAR_TGT_of(_x)              (((_x) >> 27) & 0xf)
  39#define   NFP_ARM_GCSR_EXPA_BAR_TOK(_x)                 (((_x) & 0x3) << 25)
  40#define   NFP_ARM_GCSR_EXPA_BAR_TOK_of(_x)              (((_x) >> 25) & 0x3)
  41#define   NFP_ARM_GCSR_EXPA_BAR_LEN                     (0x1 << 24)
  42#define     NFP_ARM_GCSR_EXPA_BAR_LEN_32BIT             (0x0)
  43#define     NFP_ARM_GCSR_EXPA_BAR_LEN_64BIT             (0x1000000)
  44#define   NFP_ARM_GCSR_EXPA_BAR_ACT(_x)                 (((_x) & 0x1f) << 19)
  45#define   NFP_ARM_GCSR_EXPA_BAR_ACT_of(_x)              (((_x) >> 19) & 0x1f)
  46#define     NFP_ARM_GCSR_EXPA_BAR_ACT_DERIVED           (0)
  47#define   NFP_ARM_GCSR_EXPA_BAR_ADDR(_x)                ((_x) & 0x7fff)
  48#define   NFP_ARM_GCSR_EXPA_BAR_ADDR_of(_x)             ((_x) & 0x7fff)
  49/* Register Type: ExplicitBARConfig0_Reg */
  50#define NFP_ARM_GCSR_EXPL0_BAR(_bar)   (0x60 + (0x4 * ((_bar) & 0x7)))
  51#define   NFP_ARM_GCSR_EXPL0_BAR_ADDR(_x)               ((_x) & 0x3ffff)
  52#define   NFP_ARM_GCSR_EXPL0_BAR_ADDR_of(_x)            ((_x) & 0x3ffff)
  53/* Register Type: ExplicitBARConfig1_Reg */
  54#define NFP_ARM_GCSR_EXPL1_BAR(_bar)   (0x80 + (0x4 * ((_bar) & 0x7)))
  55#define   NFP_ARM_GCSR_EXPL1_BAR_POSTED                 (0x1 << 31)
  56#define   NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF(_x)         (((_x) & 0x7f) << 24)
  57#define   NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF_of(_x)      (((_x) >> 24) & 0x7f)
  58#define   NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER(_x)        (((_x) & 0xff) << 16)
  59#define   NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER_of(_x)     (((_x) >> 16) & 0xff)
  60#define   NFP_ARM_GCSR_EXPL1_BAR_DATA_REF(_x)           ((_x) & 0x3fff)
  61#define   NFP_ARM_GCSR_EXPL1_BAR_DATA_REF_of(_x)        ((_x) & 0x3fff)
  62/* Register Type: ExplicitBARConfig2_Reg */
  63#define NFP_ARM_GCSR_EXPL2_BAR(_bar)   (0xa0 + (0x4 * ((_bar) & 0x7)))
  64#define   NFP_ARM_GCSR_EXPL2_BAR_TGT(_x)                (((_x) & 0xf) << 28)
  65#define   NFP_ARM_GCSR_EXPL2_BAR_TGT_of(_x)             (((_x) >> 28) & 0xf)
  66#define   NFP_ARM_GCSR_EXPL2_BAR_ACT(_x)                (((_x) & 0x1f) << 23)
  67#define   NFP_ARM_GCSR_EXPL2_BAR_ACT_of(_x)             (((_x) >> 23) & 0x1f)
  68#define   NFP_ARM_GCSR_EXPL2_BAR_LEN(_x)                (((_x) & 0x1f) << 18)
  69#define   NFP_ARM_GCSR_EXPL2_BAR_LEN_of(_x)             (((_x) >> 18) & 0x1f)
  70#define   NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK(_x)          (((_x) & 0xff) << 10)
  71#define   NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK_of(_x)       (((_x) >> 10) & 0xff)
  72#define   NFP_ARM_GCSR_EXPL2_BAR_TOK(_x)                (((_x) & 0x3) << 8)
  73#define   NFP_ARM_GCSR_EXPL2_BAR_TOK_of(_x)             (((_x) >> 8) & 0x3)
  74#define   NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER(_x)      ((_x) & 0xff)
  75#define   NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER_of(_x)   ((_x) & 0xff)
  76/* Register Type: PostedCommandSignal */
  77#define NFP_ARM_GCSR_EXPL_POST(_bar)   (0xc0 + (0x4 * ((_bar) & 0x7)))
  78#define   NFP_ARM_GCSR_EXPL_POST_SIG_B(_x)              (((_x) & 0x7f) << 25)
  79#define   NFP_ARM_GCSR_EXPL_POST_SIG_B_of(_x)           (((_x) >> 25) & 0x7f)
  80#define   NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS              (0x1 << 24)
  81#define     NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PULL       (0x0)
  82#define     NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PUSH       (0x1000000)
  83#define   NFP_ARM_GCSR_EXPL_POST_SIG_A(_x)              (((_x) & 0x7f) << 17)
  84#define   NFP_ARM_GCSR_EXPL_POST_SIG_A_of(_x)           (((_x) >> 17) & 0x7f)
  85#define   NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS              (0x1 << 16)
  86#define     NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PULL       (0x0)
  87#define     NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PUSH       (0x10000)
  88#define   NFP_ARM_GCSR_EXPL_POST_SIG_B_RCVD             (0x1 << 7)
  89#define   NFP_ARM_GCSR_EXPL_POST_SIG_B_VALID            (0x1 << 6)
  90#define   NFP_ARM_GCSR_EXPL_POST_SIG_A_RCVD             (0x1 << 5)
  91#define   NFP_ARM_GCSR_EXPL_POST_SIG_A_VALID            (0x1 << 4)
  92#define   NFP_ARM_GCSR_EXPL_POST_CMD_COMPLETE           (0x1)
  93/* Register Type: MPCoreBaseAddress */
  94#define NFP_ARM_GCSR_MPCORE_BASE       0x00e0
  95#define   NFP_ARM_GCSR_MPCORE_BASE_ADDR(_x)             (((_x) & 0x7ffff) << 13)
  96#define   NFP_ARM_GCSR_MPCORE_BASE_ADDR_of(_x)          (((_x) >> 13) & 0x7ffff)
  97/* Register Type: PL310BaseAddress */
  98#define NFP_ARM_GCSR_PL310_BASE        0x00e4
  99#define   NFP_ARM_GCSR_PL310_BASE_ADDR(_x)              (((_x) & 0xfffff) << 12)
 100#define   NFP_ARM_GCSR_PL310_BASE_ADDR_of(_x)           (((_x) >> 12) & 0xfffff)
 101/* Register Type: MPCoreConfig */
 102#define NFP_ARM_GCSR_MP0_CFG           0x00e8
 103#define   NFP_ARM_GCSR_MP0_CFG_SPI_BOOT                 (0x1 << 14)
 104#define   NFP_ARM_GCSR_MP0_CFG_ENDIAN(_x)               (((_x) & 0x3) << 12)
 105#define   NFP_ARM_GCSR_MP0_CFG_ENDIAN_of(_x)            (((_x) >> 12) & 0x3)
 106#define     NFP_ARM_GCSR_MP0_CFG_ENDIAN_LITTLE          (0)
 107#define     NFP_ARM_GCSR_MP0_CFG_ENDIAN_BIG             (1)
 108#define   NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR             (0x1 << 8)
 109#define     NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR_LO        (0x0)
 110#define     NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR_HI        (0x100)
 111#define   NFP_ARM_GCSR_MP0_CFG_OUTCLK_EN(_x)            (((_x) & 0xf) << 4)
 112#define   NFP_ARM_GCSR_MP0_CFG_OUTCLK_EN_of(_x)         (((_x) >> 4) & 0xf)
 113#define   NFP_ARM_GCSR_MP0_CFG_ARMID(_x)                ((_x) & 0xf)
 114#define   NFP_ARM_GCSR_MP0_CFG_ARMID_of(_x)             ((_x) & 0xf)
 115/* Register Type: MPCoreIDCacheDataError */
 116#define NFP_ARM_GCSR_MP0_CACHE_ERR     0x00ec
 117#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D7             (0x1 << 15)
 118#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D6             (0x1 << 14)
 119#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D5             (0x1 << 13)
 120#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D4             (0x1 << 12)
 121#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D3             (0x1 << 11)
 122#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D2             (0x1 << 10)
 123#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D1             (0x1 << 9)
 124#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D0             (0x1 << 8)
 125#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I7             (0x1 << 7)
 126#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I6             (0x1 << 6)
 127#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I5             (0x1 << 5)
 128#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I4             (0x1 << 4)
 129#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I3             (0x1 << 3)
 130#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I2             (0x1 << 2)
 131#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I1             (0x1 << 1)
 132#define   NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I0             (0x1)
 133/* Register Type: ARMDFT */
 134#define NFP_ARM_GCSR_DFT               0x0100
 135#define   NFP_ARM_GCSR_DFT_DBG_REQ                      (0x1 << 20)
 136#define   NFP_ARM_GCSR_DFT_DBG_EN                       (0x1 << 19)
 137#define   NFP_ARM_GCSR_DFT_WFE_EVT_TRG                  (0x1 << 18)
 138#define   NFP_ARM_GCSR_DFT_ETM_WFI_RDY                  (0x1 << 17)
 139#define   NFP_ARM_GCSR_DFT_ETM_PWR_ON                   (0x1 << 16)
 140#define   NFP_ARM_GCSR_DFT_BIST_FAIL_of(_x)             (((_x) >> 8) & 0xf)
 141#define   NFP_ARM_GCSR_DFT_BIST_DONE_of(_x)             (((_x) >> 4) & 0xf)
 142#define   NFP_ARM_GCSR_DFT_BIST_RUN(_x)                 ((_x) & 0x7)
 143#define   NFP_ARM_GCSR_DFT_BIST_RUN_of(_x)              ((_x) & 0x7)
 144
 145/* Gasket CSRs */
 146/* NOTE: These cannot be remapped, and are always at this location.
 147 */
 148#define NFP_ARM_GCSR_START      (0xd6000000 + NFP_ARM_GCSR)
 149#define NFP_ARM_GCSR_SIZE       SZ_64K
 150
 151/* BAR CSRs
 152 */
 153#define NFP_ARM_GCSR_BULK_BITS  11
 154#define NFP_ARM_GCSR_EXPA_BITS  15
 155#define NFP_ARM_GCSR_EXPL_BITS  18
 156
 157#define NFP_ARM_GCSR_BULK_SHIFT (40 - 11)
 158#define NFP_ARM_GCSR_EXPA_SHIFT (40 - 15)
 159#define NFP_ARM_GCSR_EXPL_SHIFT (40 - 18)
 160
 161#define NFP_ARM_GCSR_BULK_SIZE  (1 << NFP_ARM_GCSR_BULK_SHIFT)
 162#define NFP_ARM_GCSR_EXPA_SIZE  (1 << NFP_ARM_GCSR_EXPA_SHIFT)
 163#define NFP_ARM_GCSR_EXPL_SIZE  (1 << NFP_ARM_GCSR_EXPL_SHIFT)
 164
 165#define NFP_ARM_GCSR_EXPL2_CSR(target, action, length, \
 166                               byte_mask, token, signal_master) \
 167        (NFP_ARM_GCSR_EXPL2_BAR_TGT(target) | \
 168         NFP_ARM_GCSR_EXPL2_BAR_ACT(action) | \
 169         NFP_ARM_GCSR_EXPL2_BAR_LEN(length) | \
 170         NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK(byte_mask) | \
 171         NFP_ARM_GCSR_EXPL2_BAR_TOK(token) | \
 172         NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER(signal_master))
 173#define NFP_ARM_GCSR_EXPL1_CSR(posted, signal_ref, data_master, data_ref) \
 174        (((posted) ? NFP_ARM_GCSR_EXPL1_BAR_POSTED : 0) | \
 175         NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF(signal_ref) | \
 176         NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER(data_master) | \
 177         NFP_ARM_GCSR_EXPL1_BAR_DATA_REF(data_ref))
 178#define NFP_ARM_GCSR_EXPL0_CSR(address) \
 179        NFP_ARM_GCSR_EXPL0_BAR_ADDR((address) >> NFP_ARM_GCSR_EXPL_SHIFT)
 180#define NFP_ARM_GCSR_EXPL_POST_EXPECT_A(sig_ref, is_push, is_required) \
 181        (NFP_ARM_GCSR_EXPL_POST_SIG_A(sig_ref) | \
 182         ((is_push) ? NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PUSH : \
 183                      NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PULL) | \
 184         ((is_required) ? NFP_ARM_GCSR_EXPL_POST_SIG_A_VALID : 0))
 185#define NFP_ARM_GCSR_EXPL_POST_EXPECT_B(sig_ref, is_push, is_required) \
 186        (NFP_ARM_GCSR_EXPL_POST_SIG_B(sig_ref) | \
 187         ((is_push) ? NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PUSH : \
 188                      NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PULL) | \
 189         ((is_required) ? NFP_ARM_GCSR_EXPL_POST_SIG_B_VALID : 0))
 190
 191#define NFP_ARM_GCSR_EXPA_CSR(mode, target, token, is_64, action, address) \
 192        (((mode) ? NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPL : \
 193                   NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPA) | \
 194         NFP_ARM_GCSR_EXPA_BAR_TGT(target) | \
 195         NFP_ARM_GCSR_EXPA_BAR_TOK(token) | \
 196         ((is_64) ? NFP_ARM_GCSR_EXPA_BAR_LEN_64BIT : \
 197                    NFP_ARM_GCSR_EXPA_BAR_LEN_32BIT) | \
 198         NFP_ARM_GCSR_EXPA_BAR_ACT(action) | \
 199         NFP_ARM_GCSR_EXPA_BAR_ADDR((address) >> NFP_ARM_GCSR_EXPA_SHIFT))
 200
 201#define NFP_ARM_GCSR_BULK_CSR(mode, target, token, is_64, address) \
 202        (((mode) ? NFP_ARM_GCSR_BULK_BAR_TYPE_EXPA : \
 203                   NFP_ARM_GCSR_BULK_BAR_TYPE_BULK) | \
 204         NFP_ARM_GCSR_BULK_BAR_TGT(target) | \
 205         NFP_ARM_GCSR_BULK_BAR_TOK(token) | \
 206         ((is_64) ? NFP_ARM_GCSR_BULK_BAR_LEN_64BIT : \
 207                    NFP_ARM_GCSR_BULK_BAR_LEN_32BIT) | \
 208         NFP_ARM_GCSR_BULK_BAR_ADDR((address) >> NFP_ARM_GCSR_BULK_SHIFT))
 209
 210        /* MP Core CSRs */
 211#define NFP_ARM_MPCORE_SIZE     SZ_128K
 212
 213        /* PL320 CSRs */
 214#define NFP_ARM_PCSR_SIZE       SZ_64K
 215
 216#endif /* NFP_ARM_H */
 217