1
2
3
4#ifndef _IONIC_IF_H_
5#define _IONIC_IF_H_
6
7#define IONIC_DEV_INFO_SIGNATURE 0x44455649
8#define IONIC_DEV_INFO_VERSION 1
9#define IONIC_IFNAMSIZ 16
10
11
12
13
14enum ionic_cmd_opcode {
15 IONIC_CMD_NOP = 0,
16
17
18 IONIC_CMD_IDENTIFY = 1,
19 IONIC_CMD_INIT = 2,
20 IONIC_CMD_RESET = 3,
21 IONIC_CMD_GETATTR = 4,
22 IONIC_CMD_SETATTR = 5,
23
24
25 IONIC_CMD_PORT_IDENTIFY = 10,
26 IONIC_CMD_PORT_INIT = 11,
27 IONIC_CMD_PORT_RESET = 12,
28 IONIC_CMD_PORT_GETATTR = 13,
29 IONIC_CMD_PORT_SETATTR = 14,
30
31
32 IONIC_CMD_LIF_IDENTIFY = 20,
33 IONIC_CMD_LIF_INIT = 21,
34 IONIC_CMD_LIF_RESET = 22,
35 IONIC_CMD_LIF_GETATTR = 23,
36 IONIC_CMD_LIF_SETATTR = 24,
37 IONIC_CMD_LIF_SETPHC = 25,
38
39 IONIC_CMD_RX_MODE_SET = 30,
40 IONIC_CMD_RX_FILTER_ADD = 31,
41 IONIC_CMD_RX_FILTER_DEL = 32,
42
43
44 IONIC_CMD_Q_IDENTIFY = 39,
45 IONIC_CMD_Q_INIT = 40,
46 IONIC_CMD_Q_CONTROL = 41,
47
48
49 IONIC_CMD_RDMA_RESET_LIF = 50,
50 IONIC_CMD_RDMA_CREATE_EQ = 51,
51 IONIC_CMD_RDMA_CREATE_CQ = 52,
52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
53
54
55 IONIC_CMD_VF_GETATTR = 60,
56 IONIC_CMD_VF_SETATTR = 61,
57
58
59 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
60 IONIC_CMD_QOS_CLASS_INIT = 241,
61 IONIC_CMD_QOS_CLASS_RESET = 242,
62 IONIC_CMD_QOS_CLASS_UPDATE = 243,
63 IONIC_CMD_QOS_CLEAR_STATS = 244,
64 IONIC_CMD_QOS_RESET = 245,
65
66
67 IONIC_CMD_FW_DOWNLOAD = 252,
68 IONIC_CMD_FW_CONTROL = 253,
69 IONIC_CMD_FW_DOWNLOAD_V1 = 254,
70 IONIC_CMD_FW_CONTROL_V1 = 255,
71};
72
73
74
75
76enum ionic_status_code {
77 IONIC_RC_SUCCESS = 0,
78 IONIC_RC_EVERSION = 1,
79 IONIC_RC_EOPCODE = 2,
80 IONIC_RC_EIO = 3,
81 IONIC_RC_EPERM = 4,
82 IONIC_RC_EQID = 5,
83 IONIC_RC_EQTYPE = 6,
84 IONIC_RC_ENOENT = 7,
85 IONIC_RC_EINTR = 8,
86 IONIC_RC_EAGAIN = 9,
87 IONIC_RC_ENOMEM = 10,
88 IONIC_RC_EFAULT = 11,
89 IONIC_RC_EBUSY = 12,
90 IONIC_RC_EEXIST = 13,
91 IONIC_RC_EINVAL = 14,
92 IONIC_RC_ENOSPC = 15,
93 IONIC_RC_ERANGE = 16,
94 IONIC_RC_BAD_ADDR = 17,
95 IONIC_RC_DEV_CMD = 18,
96 IONIC_RC_ENOSUPP = 19,
97 IONIC_RC_ERROR = 29,
98 IONIC_RC_ERDMA = 30,
99 IONIC_RC_EVFID = 31,
100 IONIC_RC_EBAD_FW = 32,
101};
102
103enum ionic_notifyq_opcode {
104 IONIC_EVENT_LINK_CHANGE = 1,
105 IONIC_EVENT_RESET = 2,
106 IONIC_EVENT_HEARTBEAT = 3,
107 IONIC_EVENT_LOG = 4,
108 IONIC_EVENT_XCVR = 5,
109};
110
111
112
113
114
115
116
117struct ionic_admin_cmd {
118 u8 opcode;
119 u8 rsvd;
120 __le16 lif_index;
121 u8 cmd_data[60];
122};
123
124
125
126
127
128
129
130
131
132struct ionic_admin_comp {
133 u8 status;
134 u8 rsvd;
135 __le16 comp_index;
136 u8 cmd_data[11];
137 u8 color;
138#define IONIC_COMP_COLOR_MASK 0x80
139};
140
141static inline u8 color_match(u8 color, u8 done_color)
142{
143 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
144}
145
146
147
148
149
150struct ionic_nop_cmd {
151 u8 opcode;
152 u8 rsvd[63];
153};
154
155
156
157
158
159struct ionic_nop_comp {
160 u8 status;
161 u8 rsvd[15];
162};
163
164
165
166
167
168
169struct ionic_dev_init_cmd {
170 u8 opcode;
171 u8 type;
172 u8 rsvd[62];
173};
174
175
176
177
178
179struct ionic_dev_init_comp {
180 u8 status;
181 u8 rsvd[15];
182};
183
184
185
186
187
188struct ionic_dev_reset_cmd {
189 u8 opcode;
190 u8 rsvd[63];
191};
192
193
194
195
196
197struct ionic_dev_reset_comp {
198 u8 status;
199 u8 rsvd[15];
200};
201
202#define IONIC_IDENTITY_VERSION_1 1
203
204
205
206
207
208
209struct ionic_dev_identify_cmd {
210 u8 opcode;
211 u8 ver;
212 u8 rsvd[62];
213};
214
215
216
217
218
219
220struct ionic_dev_identify_comp {
221 u8 status;
222 u8 ver;
223 u8 rsvd[14];
224};
225
226enum ionic_os_type {
227 IONIC_OS_TYPE_LINUX = 1,
228 IONIC_OS_TYPE_WIN = 2,
229 IONIC_OS_TYPE_DPDK = 3,
230 IONIC_OS_TYPE_FREEBSD = 4,
231 IONIC_OS_TYPE_IPXE = 5,
232 IONIC_OS_TYPE_ESXI = 6,
233};
234
235
236
237
238
239
240
241
242
243
244union ionic_drv_identity {
245 struct {
246 __le32 os_type;
247 __le32 os_dist;
248 char os_dist_str[128];
249 __le32 kernel_ver;
250 char kernel_ver_str[32];
251 char driver_ver_str[32];
252 };
253 __le32 words[478];
254};
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277union ionic_dev_identity {
278 struct {
279 u8 version;
280 u8 type;
281 u8 rsvd[2];
282 u8 nports;
283 u8 rsvd2[3];
284 __le32 nlifs;
285 __le32 nintrs;
286 __le32 ndbpgs_per_lif;
287 __le32 intr_coal_mult;
288 __le32 intr_coal_div;
289 __le32 eq_count;
290 __le64 hwstamp_mask;
291 __le32 hwstamp_mult;
292 __le32 hwstamp_shift;
293 };
294 __le32 words[478];
295};
296
297enum ionic_lif_type {
298 IONIC_LIF_TYPE_CLASSIC = 0,
299 IONIC_LIF_TYPE_MACVLAN = 1,
300 IONIC_LIF_TYPE_NETQUEUE = 2,
301};
302
303
304
305
306
307
308
309struct ionic_lif_identify_cmd {
310 u8 opcode;
311 u8 type;
312 u8 ver;
313 u8 rsvd[61];
314};
315
316
317
318
319
320
321struct ionic_lif_identify_comp {
322 u8 status;
323 u8 ver;
324 u8 rsvd2[14];
325};
326
327
328
329
330
331
332enum ionic_lif_capability {
333 IONIC_LIF_CAP_ETH = BIT(0),
334 IONIC_LIF_CAP_RDMA = BIT(1),
335};
336
337
338
339
340
341
342
343
344
345
346enum ionic_logical_qtype {
347 IONIC_QTYPE_ADMINQ = 0,
348 IONIC_QTYPE_NOTIFYQ = 1,
349 IONIC_QTYPE_RXQ = 2,
350 IONIC_QTYPE_TXQ = 3,
351 IONIC_QTYPE_EQ = 4,
352 IONIC_QTYPE_MAX = 16,
353};
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371enum ionic_q_feature {
372 IONIC_QIDENT_F_CQ = BIT_ULL(0),
373 IONIC_QIDENT_F_SG = BIT_ULL(1),
374 IONIC_QIDENT_F_EQ = BIT_ULL(2),
375 IONIC_QIDENT_F_CMB = BIT_ULL(3),
376 IONIC_Q_F_2X_DESC = BIT_ULL(4),
377 IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5),
378 IONIC_Q_F_2X_SG_DESC = BIT_ULL(6),
379 IONIC_Q_F_4X_DESC = BIT_ULL(7),
380 IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8),
381 IONIC_Q_F_4X_SG_DESC = BIT_ULL(9),
382};
383
384
385
386
387
388
389
390
391enum ionic_rxq_feature {
392 IONIC_RXQ_F_HWSTAMP = BIT_ULL(16),
393};
394
395
396
397
398
399
400
401
402enum ionic_txq_feature {
403 IONIC_TXQ_F_HWSTAMP = BIT(16),
404};
405
406
407
408
409
410
411
412enum ionic_hwstamp_bits {
413 IONIC_HWSTAMP_INVALID = ~0ull,
414 IONIC_HWSTAMP_CQ_NEGOFFSET = 8,
415};
416
417
418
419
420
421
422
423struct ionic_lif_logical_qtype {
424 u8 qtype;
425 u8 rsvd[3];
426 __le32 qid_count;
427 __le32 qid_base;
428};
429
430
431
432
433
434
435
436enum ionic_lif_state {
437 IONIC_LIF_QUIESCE = 0,
438 IONIC_LIF_ENABLE = 1,
439 IONIC_LIF_DISABLE = 2,
440};
441
442
443
444
445
446
447
448
449
450
451
452union ionic_lif_config {
453 struct {
454 u8 state;
455 u8 rsvd[3];
456 char name[IONIC_IFNAMSIZ];
457 __le32 mtu;
458 u8 mac[6];
459 __le16 vlan;
460 __le64 features;
461 __le32 queue_count[IONIC_QTYPE_MAX];
462 } __packed;
463 __le32 words[64];
464};
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500union ionic_lif_identity {
501 struct {
502 __le64 capabilities;
503
504 struct {
505 u8 version;
506 u8 rsvd[3];
507 __le32 max_ucast_filters;
508 __le32 max_mcast_filters;
509 __le16 rss_ind_tbl_sz;
510 __le32 min_frame_size;
511 __le32 max_frame_size;
512 u8 rsvd2[2];
513 __le64 hwstamp_tx_modes;
514 __le64 hwstamp_rx_filters;
515 u8 rsvd3[88];
516 union ionic_lif_config config;
517 } __packed eth;
518
519 struct {
520 u8 version;
521 u8 qp_opcodes;
522 u8 admin_opcodes;
523 u8 rsvd;
524 __le32 npts_per_lif;
525 __le32 nmrs_per_lif;
526 __le32 nahs_per_lif;
527 u8 max_stride;
528 u8 cl_stride;
529 u8 pte_stride;
530 u8 rrq_stride;
531 u8 rsq_stride;
532 u8 dcqcn_profiles;
533 u8 rsvd_dimensions[10];
534 struct ionic_lif_logical_qtype aq_qtype;
535 struct ionic_lif_logical_qtype sq_qtype;
536 struct ionic_lif_logical_qtype rq_qtype;
537 struct ionic_lif_logical_qtype cq_qtype;
538 struct ionic_lif_logical_qtype eq_qtype;
539 } __packed rdma;
540 } __packed;
541 __le32 words[478];
542};
543
544
545
546
547
548
549
550
551struct ionic_lif_init_cmd {
552 u8 opcode;
553 u8 type;
554 __le16 index;
555 __le32 rsvd;
556 __le64 info_pa;
557 u8 rsvd2[48];
558};
559
560
561
562
563
564
565struct ionic_lif_init_comp {
566 u8 status;
567 u8 rsvd;
568 __le16 hw_index;
569 u8 rsvd2[12];
570};
571
572
573
574
575
576
577
578
579struct ionic_q_identify_cmd {
580 u8 opcode;
581 u8 rsvd;
582 __le16 lif_type;
583 u8 type;
584 u8 ver;
585 u8 rsvd2[58];
586};
587
588
589
590
591
592
593
594struct ionic_q_identify_comp {
595 u8 status;
596 u8 rsvd;
597 __le16 comp_index;
598 u8 ver;
599 u8 rsvd2[11];
600};
601
602
603
604
605
606
607
608
609
610
611
612
613union ionic_q_identity {
614 struct {
615 u8 version;
616 u8 supported;
617 u8 rsvd[6];
618 __le64 features;
619 __le16 desc_sz;
620 __le16 comp_sz;
621 __le16 sg_desc_sz;
622 __le16 max_sg_elems;
623 __le16 sg_desc_stride;
624 };
625 __le32 words[478];
626};
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660struct ionic_q_init_cmd {
661 u8 opcode;
662 u8 rsvd;
663 __le16 lif_index;
664 u8 type;
665 u8 ver;
666 u8 rsvd1[2];
667 __le32 index;
668 __le16 pid;
669 __le16 intr_index;
670 __le16 flags;
671#define IONIC_QINIT_F_IRQ 0x01
672#define IONIC_QINIT_F_ENA 0x02
673#define IONIC_QINIT_F_SG 0x04
674#define IONIC_QINIT_F_EQ 0x08
675#define IONIC_QINIT_F_CMB 0x10
676#define IONIC_QINIT_F_DEBUG 0x80
677 u8 cos;
678 u8 ring_size;
679 __le64 ring_base;
680 __le64 cq_ring_base;
681 __le64 sg_ring_base;
682 u8 rsvd2[12];
683 __le64 features;
684} __packed;
685
686
687
688
689
690
691
692
693
694struct ionic_q_init_comp {
695 u8 status;
696 u8 rsvd;
697 __le16 comp_index;
698 __le32 hw_index;
699 u8 hw_type;
700 u8 rsvd2[6];
701 u8 color;
702};
703
704
705#define IONIC_ADDR_LEN 52
706#define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
707
708enum ionic_txq_desc_opcode {
709 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
710 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
711 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
712 IONIC_TXQ_DESC_OPCODE_TSO = 3,
713};
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826struct ionic_txq_desc {
827 __le64 cmd;
828#define IONIC_TXQ_DESC_OPCODE_MASK 0xf
829#define IONIC_TXQ_DESC_OPCODE_SHIFT 4
830#define IONIC_TXQ_DESC_FLAGS_MASK 0xf
831#define IONIC_TXQ_DESC_FLAGS_SHIFT 0
832#define IONIC_TXQ_DESC_NSGE_MASK 0xf
833#define IONIC_TXQ_DESC_NSGE_SHIFT 8
834#define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
835#define IONIC_TXQ_DESC_ADDR_SHIFT 12
836
837
838#define IONIC_TXQ_DESC_FLAG_VLAN 0x1
839#define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
840
841
842#define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
843#define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
844
845
846#define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
847#define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
848
849 __le16 len;
850 union {
851 __le16 vlan_tci;
852 __le16 hword0;
853 };
854 union {
855 __le16 csum_start;
856 __le16 hdr_len;
857 __le16 hword1;
858 };
859 union {
860 __le16 csum_offset;
861 __le16 mss;
862 __le16 hword2;
863 };
864};
865
866static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
867 u8 nsge, u64 addr)
868{
869 u64 cmd;
870
871 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
872 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
873 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
874 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
875
876 return cmd;
877};
878
879static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
880 u8 *nsge, u64 *addr)
881{
882 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
883 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
884 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
885 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
886};
887
888
889
890
891
892
893struct ionic_txq_sg_elem {
894 __le64 addr;
895 __le16 len;
896 __le16 rsvd[3];
897};
898
899
900
901
902
903struct ionic_txq_sg_desc {
904#define IONIC_TX_MAX_SG_ELEMS 8
905#define IONIC_TX_SG_DESC_STRIDE 8
906 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
907};
908
909struct ionic_txq_sg_desc_v1 {
910#define IONIC_TX_MAX_SG_ELEMS_V1 15
911#define IONIC_TX_SG_DESC_STRIDE_V1 16
912 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
913};
914
915
916
917
918
919
920
921struct ionic_txq_comp {
922 u8 status;
923 u8 rsvd;
924 __le16 comp_index;
925 u8 rsvd2[11];
926 u8 color;
927};
928
929enum ionic_rxq_desc_opcode {
930 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
931 IONIC_RXQ_DESC_OPCODE_SG = 1,
932};
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947struct ionic_rxq_desc {
948 u8 opcode;
949 u8 rsvd[5];
950 __le16 len;
951 __le64 addr;
952};
953
954
955
956
957
958
959struct ionic_rxq_sg_elem {
960 __le64 addr;
961 __le16 len;
962 __le16 rsvd[3];
963};
964
965
966
967
968
969struct ionic_rxq_sg_desc {
970#define IONIC_RX_MAX_SG_ELEMS 8
971#define IONIC_RX_SG_DESC_STRIDE 8
972 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
973};
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035struct ionic_rxq_comp {
1036 u8 status;
1037 u8 num_sg_elems;
1038 __le16 comp_index;
1039 __le32 rss_hash;
1040 __le16 csum;
1041 __le16 vlan_tci;
1042 __le16 len;
1043 u8 csum_flags;
1044#define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
1045#define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
1046#define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
1047#define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
1048#define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
1049#define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
1050#define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
1051#define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
1052 u8 pkt_type_color;
1053#define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
1054};
1055
1056enum ionic_pkt_type {
1057 IONIC_PKT_TYPE_NON_IP = 0x00,
1058 IONIC_PKT_TYPE_IPV4 = 0x01,
1059 IONIC_PKT_TYPE_IPV4_TCP = 0x03,
1060 IONIC_PKT_TYPE_IPV4_UDP = 0x05,
1061 IONIC_PKT_TYPE_IPV6 = 0x08,
1062 IONIC_PKT_TYPE_IPV6_TCP = 0x18,
1063 IONIC_PKT_TYPE_IPV6_UDP = 0x28,
1064
1065 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
1066 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
1067 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
1068 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
1069 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
1070 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
1071 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
1072};
1073
1074enum ionic_eth_hw_features {
1075 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
1076 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
1077 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
1078 IONIC_ETH_HW_RX_HASH = BIT(3),
1079 IONIC_ETH_HW_RX_CSUM = BIT(4),
1080 IONIC_ETH_HW_TX_SG = BIT(5),
1081 IONIC_ETH_HW_RX_SG = BIT(6),
1082 IONIC_ETH_HW_TX_CSUM = BIT(7),
1083 IONIC_ETH_HW_TSO = BIT(8),
1084 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
1085 IONIC_ETH_HW_TSO_ECN = BIT(10),
1086 IONIC_ETH_HW_TSO_GRE = BIT(11),
1087 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
1088 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
1089 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
1090 IONIC_ETH_HW_TSO_UDP = BIT(15),
1091 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
1092 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17),
1093 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
1094 IONIC_ETH_HW_TSO_GENEVE = BIT(19),
1095 IONIC_ETH_HW_TIMESTAMP = BIT(20),
1096};
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121enum ionic_pkt_class {
1122 IONIC_PKT_CLS_NTP_ALL = BIT(0),
1123
1124 IONIC_PKT_CLS_PTP1_SYNC = BIT(1),
1125 IONIC_PKT_CLS_PTP1_DREQ = BIT(2),
1126 IONIC_PKT_CLS_PTP1_ALL = BIT(3) |
1127 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ,
1128
1129 IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4),
1130 IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5),
1131 IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) |
1132 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ,
1133
1134 IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7),
1135 IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8),
1136 IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) |
1137 IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ,
1138
1139 IONIC_PKT_CLS_PTP2_SYNC =
1140 IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC,
1141 IONIC_PKT_CLS_PTP2_DREQ =
1142 IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ,
1143 IONIC_PKT_CLS_PTP2_ALL =
1144 IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL,
1145
1146 IONIC_PKT_CLS_PTP_SYNC =
1147 IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC,
1148 IONIC_PKT_CLS_PTP_DREQ =
1149 IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ,
1150 IONIC_PKT_CLS_PTP_ALL =
1151 IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL,
1152};
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162struct ionic_q_control_cmd {
1163 u8 opcode;
1164 u8 type;
1165 __le16 lif_index;
1166 __le32 index;
1167 u8 oper;
1168 u8 rsvd[55];
1169};
1170
1171typedef struct ionic_admin_comp ionic_q_control_comp;
1172
1173enum q_control_oper {
1174 IONIC_Q_DISABLE = 0,
1175 IONIC_Q_ENABLE = 1,
1176 IONIC_Q_HANG_RESET = 2,
1177};
1178
1179
1180
1181
1182
1183
1184
1185enum ionic_phy_type {
1186 IONIC_PHY_TYPE_NONE = 0,
1187 IONIC_PHY_TYPE_COPPER = 1,
1188 IONIC_PHY_TYPE_FIBER = 2,
1189};
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199enum ionic_xcvr_state {
1200 IONIC_XCVR_STATE_REMOVED = 0,
1201 IONIC_XCVR_STATE_INSERTED = 1,
1202 IONIC_XCVR_STATE_PENDING = 2,
1203 IONIC_XCVR_STATE_SPROM_READ = 3,
1204 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
1205};
1206
1207
1208
1209
1210enum ionic_xcvr_pid {
1211 IONIC_XCVR_PID_UNKNOWN = 0,
1212
1213
1214 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
1215 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
1216 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
1217 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
1218 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
1219
1220
1221 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
1222 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
1223 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
1224 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
1225 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
1226 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1227 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1228 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1229 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1230 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
1231 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
1232 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
1233 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
1234 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
1235 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
1236 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
1237 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
1238 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
1239 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
1240 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
1241 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
1242 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
1243 IONIC_XCVR_PID_SFP_10GBASE_T = 72,
1244 IONIC_XCVR_PID_SFP_1000BASE_T = 73,
1245};
1246
1247
1248
1249
1250
1251
1252
1253enum ionic_port_type {
1254 IONIC_PORT_TYPE_NONE = 0,
1255 IONIC_PORT_TYPE_ETH = 1,
1256 IONIC_PORT_TYPE_MGMT = 2,
1257};
1258
1259
1260
1261
1262
1263
1264
1265enum ionic_port_admin_state {
1266 IONIC_PORT_ADMIN_STATE_NONE = 0,
1267 IONIC_PORT_ADMIN_STATE_DOWN = 1,
1268 IONIC_PORT_ADMIN_STATE_UP = 2,
1269};
1270
1271
1272
1273
1274
1275
1276
1277enum ionic_port_oper_status {
1278 IONIC_PORT_OPER_STATUS_NONE = 0,
1279 IONIC_PORT_OPER_STATUS_UP = 1,
1280 IONIC_PORT_OPER_STATUS_DOWN = 2,
1281};
1282
1283
1284
1285
1286
1287
1288
1289enum ionic_port_fec_type {
1290 IONIC_PORT_FEC_TYPE_NONE = 0,
1291 IONIC_PORT_FEC_TYPE_FC = 1,
1292 IONIC_PORT_FEC_TYPE_RS = 2,
1293};
1294
1295
1296
1297
1298
1299
1300
1301enum ionic_port_pause_type {
1302 IONIC_PORT_PAUSE_TYPE_NONE = 0,
1303 IONIC_PORT_PAUSE_TYPE_LINK = 1,
1304 IONIC_PORT_PAUSE_TYPE_PFC = 2,
1305};
1306
1307
1308
1309
1310
1311
1312
1313enum ionic_port_loopback_mode {
1314 IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1315 IONIC_PORT_LOOPBACK_MODE_MAC = 1,
1316 IONIC_PORT_LOOPBACK_MODE_PHY = 2,
1317};
1318
1319
1320
1321
1322
1323
1324
1325
1326struct ionic_xcvr_status {
1327 u8 state;
1328 u8 phy;
1329 __le16 pid;
1330 u8 sprom[256];
1331};
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343union ionic_port_config {
1344 struct {
1345#define IONIC_SPEED_100G 100000
1346#define IONIC_SPEED_50G 50000
1347#define IONIC_SPEED_40G 40000
1348#define IONIC_SPEED_25G 25000
1349#define IONIC_SPEED_10G 10000
1350#define IONIC_SPEED_1G 1000
1351 __le32 speed;
1352 __le32 mtu;
1353 u8 state;
1354 u8 an_enable;
1355 u8 fec_type;
1356#define IONIC_PAUSE_TYPE_MASK 0x0f
1357#define IONIC_PAUSE_FLAGS_MASK 0xf0
1358#define IONIC_PAUSE_F_TX 0x10
1359#define IONIC_PAUSE_F_RX 0x20
1360 u8 pause_type;
1361 u8 loopback_mode;
1362 };
1363 __le32 words[64];
1364};
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375struct ionic_port_status {
1376 __le32 id;
1377 __le32 speed;
1378 u8 status;
1379 __le16 link_down_count;
1380 u8 fec_type;
1381 u8 rsvd[48];
1382 struct ionic_xcvr_status xcvr;
1383} __packed;
1384
1385
1386
1387
1388
1389
1390
1391struct ionic_port_identify_cmd {
1392 u8 opcode;
1393 u8 index;
1394 u8 ver;
1395 u8 rsvd[61];
1396};
1397
1398
1399
1400
1401
1402
1403struct ionic_port_identify_comp {
1404 u8 status;
1405 u8 ver;
1406 u8 rsvd[14];
1407};
1408
1409
1410
1411
1412
1413
1414
1415struct ionic_port_init_cmd {
1416 u8 opcode;
1417 u8 index;
1418 u8 rsvd[6];
1419 __le64 info_pa;
1420 u8 rsvd2[48];
1421};
1422
1423
1424
1425
1426
1427struct ionic_port_init_comp {
1428 u8 status;
1429 u8 rsvd[15];
1430};
1431
1432
1433
1434
1435
1436
1437struct ionic_port_reset_cmd {
1438 u8 opcode;
1439 u8 index;
1440 u8 rsvd[62];
1441};
1442
1443
1444
1445
1446
1447struct ionic_port_reset_comp {
1448 u8 status;
1449 u8 rsvd[15];
1450};
1451
1452
1453
1454
1455
1456enum ionic_stats_ctl_cmd {
1457 IONIC_STATS_CTL_RESET = 0,
1458};
1459
1460
1461
1462
1463
1464
1465
1466
1467enum ionic_txstamp_mode {
1468 IONIC_TXSTAMP_OFF = 0,
1469 IONIC_TXSTAMP_ON = 1,
1470 IONIC_TXSTAMP_ONESTEP_SYNC = 2,
1471 IONIC_TXSTAMP_ONESTEP_P2P = 3,
1472};
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485enum ionic_port_attr {
1486 IONIC_PORT_ATTR_STATE = 0,
1487 IONIC_PORT_ATTR_SPEED = 1,
1488 IONIC_PORT_ATTR_MTU = 2,
1489 IONIC_PORT_ATTR_AUTONEG = 3,
1490 IONIC_PORT_ATTR_FEC = 4,
1491 IONIC_PORT_ATTR_PAUSE = 5,
1492 IONIC_PORT_ATTR_LOOPBACK = 6,
1493 IONIC_PORT_ATTR_STATS_CTRL = 7,
1494};
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510struct ionic_port_setattr_cmd {
1511 u8 opcode;
1512 u8 index;
1513 u8 attr;
1514 u8 rsvd;
1515 union {
1516 u8 state;
1517 __le32 speed;
1518 __le32 mtu;
1519 u8 an_enable;
1520 u8 fec_type;
1521 u8 pause_type;
1522 u8 loopback_mode;
1523 u8 stats_ctl;
1524 u8 rsvd2[60];
1525 };
1526};
1527
1528
1529
1530
1531
1532
1533struct ionic_port_setattr_comp {
1534 u8 status;
1535 u8 rsvd[14];
1536 u8 color;
1537};
1538
1539
1540
1541
1542
1543
1544
1545struct ionic_port_getattr_cmd {
1546 u8 opcode;
1547 u8 index;
1548 u8 attr;
1549 u8 rsvd[61];
1550};
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564struct ionic_port_getattr_comp {
1565 u8 status;
1566 u8 rsvd[3];
1567 union {
1568 u8 state;
1569 __le32 speed;
1570 __le32 mtu;
1571 u8 an_enable;
1572 u8 fec_type;
1573 u8 pause_type;
1574 u8 loopback_mode;
1575 u8 rsvd2[11];
1576 } __packed;
1577 u8 color;
1578};
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588struct ionic_lif_status {
1589 __le64 eid;
1590 u8 port_num;
1591 u8 rsvd;
1592 __le16 link_status;
1593 __le32 link_speed;
1594 __le16 link_down_count;
1595 u8 rsvd2[46];
1596};
1597
1598
1599
1600
1601
1602
1603struct ionic_lif_reset_cmd {
1604 u8 opcode;
1605 u8 rsvd;
1606 __le16 index;
1607 __le32 rsvd2[15];
1608};
1609
1610typedef struct ionic_admin_comp ionic_lif_reset_comp;
1611
1612enum ionic_dev_state {
1613 IONIC_DEV_DISABLE = 0,
1614 IONIC_DEV_ENABLE = 1,
1615 IONIC_DEV_HANG_RESET = 2,
1616};
1617
1618
1619
1620
1621
1622
1623
1624enum ionic_dev_attr {
1625 IONIC_DEV_ATTR_STATE = 0,
1626 IONIC_DEV_ATTR_NAME = 1,
1627 IONIC_DEV_ATTR_FEATURES = 2,
1628};
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638struct ionic_dev_setattr_cmd {
1639 u8 opcode;
1640 u8 attr;
1641 __le16 rsvd;
1642 union {
1643 u8 state;
1644 char name[IONIC_IFNAMSIZ];
1645 __le64 features;
1646 u8 rsvd2[60];
1647 } __packed;
1648};
1649
1650
1651
1652
1653
1654
1655
1656struct ionic_dev_setattr_comp {
1657 u8 status;
1658 u8 rsvd[3];
1659 union {
1660 __le64 features;
1661 u8 rsvd2[11];
1662 } __packed;
1663 u8 color;
1664};
1665
1666
1667
1668
1669
1670
1671struct ionic_dev_getattr_cmd {
1672 u8 opcode;
1673 u8 attr;
1674 u8 rsvd[62];
1675};
1676
1677
1678
1679
1680
1681
1682
1683struct ionic_dev_getattr_comp {
1684 u8 status;
1685 u8 rsvd[3];
1686 union {
1687 __le64 features;
1688 u8 rsvd2[11];
1689 } __packed;
1690 u8 color;
1691};
1692
1693
1694
1695
1696#define IONIC_RSS_HASH_KEY_SIZE 40
1697
1698enum ionic_rss_hash_types {
1699 IONIC_RSS_TYPE_IPV4 = BIT(0),
1700 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1701 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1702 IONIC_RSS_TYPE_IPV6 = BIT(3),
1703 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1704 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1705};
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718enum ionic_lif_attr {
1719 IONIC_LIF_ATTR_STATE = 0,
1720 IONIC_LIF_ATTR_NAME = 1,
1721 IONIC_LIF_ATTR_MTU = 2,
1722 IONIC_LIF_ATTR_MAC = 3,
1723 IONIC_LIF_ATTR_FEATURES = 4,
1724 IONIC_LIF_ATTR_RSS = 5,
1725 IONIC_LIF_ATTR_STATS_CTRL = 6,
1726 IONIC_LIF_ATTR_TXSTAMP = 7,
1727};
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746struct ionic_lif_setattr_cmd {
1747 u8 opcode;
1748 u8 attr;
1749 __le16 index;
1750 union {
1751 u8 state;
1752 char name[IONIC_IFNAMSIZ];
1753 __le32 mtu;
1754 u8 mac[6];
1755 __le64 features;
1756 struct {
1757 __le16 types;
1758 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1759 u8 rsvd[6];
1760 __le64 addr;
1761 } rss;
1762 u8 stats_ctl;
1763 __le16 txstamp_mode;
1764 u8 rsvd[60];
1765 } __packed;
1766};
1767
1768
1769
1770
1771
1772
1773
1774
1775struct ionic_lif_setattr_comp {
1776 u8 status;
1777 u8 rsvd;
1778 __le16 comp_index;
1779 union {
1780 __le64 features;
1781 u8 rsvd2[11];
1782 } __packed;
1783 u8 color;
1784};
1785
1786
1787
1788
1789
1790
1791
1792struct ionic_lif_getattr_cmd {
1793 u8 opcode;
1794 u8 attr;
1795 __le16 index;
1796 u8 rsvd[60];
1797};
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811struct ionic_lif_getattr_comp {
1812 u8 status;
1813 u8 rsvd;
1814 __le16 comp_index;
1815 union {
1816 u8 state;
1817 __le32 mtu;
1818 u8 mac[6];
1819 __le64 features;
1820 __le16 txstamp_mode;
1821 u8 rsvd2[11];
1822 } __packed;
1823 u8 color;
1824};
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836struct ionic_lif_setphc_cmd {
1837 u8 opcode;
1838 u8 rsvd1;
1839 __le16 lif_index;
1840 u8 rsvd2[4];
1841 __le64 tick;
1842 __le64 nsec;
1843 __le64 frac;
1844 __le32 mult;
1845 __le32 shift;
1846 u8 rsvd3[24];
1847};
1848
1849enum ionic_rx_mode {
1850 IONIC_RX_MODE_F_UNICAST = BIT(0),
1851 IONIC_RX_MODE_F_MULTICAST = BIT(1),
1852 IONIC_RX_MODE_F_BROADCAST = BIT(2),
1853 IONIC_RX_MODE_F_PROMISC = BIT(3),
1854 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
1855 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
1856};
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870struct ionic_rx_mode_set_cmd {
1871 u8 opcode;
1872 u8 rsvd;
1873 __le16 lif_index;
1874 __le16 rx_mode;
1875 __le16 rsvd2[29];
1876};
1877
1878typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1879
1880enum ionic_rx_filter_match_type {
1881 IONIC_RX_FILTER_MATCH_VLAN = 0x0,
1882 IONIC_RX_FILTER_MATCH_MAC = 0x1,
1883 IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2,
1884 IONIC_RX_FILTER_STEER_PKTCLASS = 0x10,
1885};
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903struct ionic_rx_filter_add_cmd {
1904 u8 opcode;
1905 u8 qtype;
1906 __le16 lif_index;
1907 __le32 qid;
1908 __le16 match;
1909 union {
1910 struct {
1911 __le16 vlan;
1912 } vlan;
1913 struct {
1914 u8 addr[6];
1915 } mac;
1916 struct {
1917 __le16 vlan;
1918 u8 addr[6];
1919 } mac_vlan;
1920 __le64 pkt_class;
1921 u8 rsvd[54];
1922 } __packed;
1923};
1924
1925
1926
1927
1928
1929
1930
1931
1932struct ionic_rx_filter_add_comp {
1933 u8 status;
1934 u8 rsvd;
1935 __le16 comp_index;
1936 __le32 filter_id;
1937 u8 rsvd2[7];
1938 u8 color;
1939};
1940
1941
1942
1943
1944
1945
1946
1947struct ionic_rx_filter_del_cmd {
1948 u8 opcode;
1949 u8 rsvd;
1950 __le16 lif_index;
1951 __le32 filter_id;
1952 u8 rsvd2[56];
1953};
1954
1955typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1956
1957enum ionic_vf_attr {
1958 IONIC_VF_ATTR_SPOOFCHK = 1,
1959 IONIC_VF_ATTR_TRUST = 2,
1960 IONIC_VF_ATTR_MAC = 3,
1961 IONIC_VF_ATTR_LINKSTATE = 4,
1962 IONIC_VF_ATTR_VLAN = 5,
1963 IONIC_VF_ATTR_RATE = 6,
1964 IONIC_VF_ATTR_STATSADDR = 7,
1965};
1966
1967
1968
1969
1970
1971
1972
1973enum ionic_vf_link_status {
1974 IONIC_VF_LINK_STATUS_AUTO = 0,
1975 IONIC_VF_LINK_STATUS_UP = 1,
1976 IONIC_VF_LINK_STATUS_DOWN = 2,
1977};
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992struct ionic_vf_setattr_cmd {
1993 u8 opcode;
1994 u8 attr;
1995 __le16 vf_index;
1996 union {
1997 u8 macaddr[6];
1998 __le16 vlanid;
1999 __le32 maxrate;
2000 u8 spoofchk;
2001 u8 trust;
2002 u8 linkstate;
2003 __le64 stats_pa;
2004 u8 pad[60];
2005 } __packed;
2006};
2007
2008struct ionic_vf_setattr_comp {
2009 u8 status;
2010 u8 attr;
2011 __le16 vf_index;
2012 __le16 comp_index;
2013 u8 rsvd[9];
2014 u8 color;
2015};
2016
2017
2018
2019
2020
2021
2022
2023struct ionic_vf_getattr_cmd {
2024 u8 opcode;
2025 u8 attr;
2026 __le16 vf_index;
2027 u8 rsvd[60];
2028};
2029
2030struct ionic_vf_getattr_comp {
2031 u8 status;
2032 u8 attr;
2033 __le16 vf_index;
2034 union {
2035 u8 macaddr[6];
2036 __le16 vlanid;
2037 __le32 maxrate;
2038 u8 spoofchk;
2039 u8 trust;
2040 u8 linkstate;
2041 __le64 stats_pa;
2042 u8 pad[11];
2043 } __packed;
2044 u8 color;
2045};
2046
2047
2048
2049
2050
2051
2052
2053struct ionic_qos_identify_cmd {
2054 u8 opcode;
2055 u8 ver;
2056 u8 rsvd[62];
2057};
2058
2059
2060
2061
2062
2063
2064struct ionic_qos_identify_comp {
2065 u8 status;
2066 u8 ver;
2067 u8 rsvd[14];
2068};
2069
2070#define IONIC_QOS_TC_MAX 8
2071#define IONIC_QOS_ALL_TC 0xFF
2072
2073#define IONIC_QOS_CLASS_MAX 7
2074#define IONIC_QOS_PCP_MAX 8
2075#define IONIC_QOS_CLASS_NAME_SZ 32
2076#define IONIC_QOS_DSCP_MAX 64
2077#define IONIC_QOS_ALL_PCP 0xFF
2078#define IONIC_DSCP_BLOCK_SIZE 8
2079
2080
2081
2082
2083enum ionic_qos_class {
2084 IONIC_QOS_CLASS_DEFAULT = 0,
2085 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
2086 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
2087 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
2088 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
2089 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
2090 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
2091};
2092
2093
2094
2095
2096
2097
2098
2099enum ionic_qos_class_type {
2100 IONIC_QOS_CLASS_TYPE_NONE = 0,
2101 IONIC_QOS_CLASS_TYPE_PCP = 1,
2102 IONIC_QOS_CLASS_TYPE_DSCP = 2,
2103};
2104
2105
2106
2107
2108
2109
2110enum ionic_qos_sched_type {
2111 IONIC_QOS_SCHED_TYPE_STRICT = 0,
2112 IONIC_QOS_SCHED_TYPE_DWRR = 1,
2113};
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137union ionic_qos_config {
2138 struct {
2139#define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
2140#define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
2141
2142#define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
2143#define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
2144
2145#define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
2146 u8 flags;
2147 u8 sched_type;
2148 u8 class_type;
2149 u8 pause_type;
2150 char name[IONIC_QOS_CLASS_NAME_SZ];
2151 __le32 mtu;
2152
2153 u8 pfc_cos;
2154
2155 union {
2156 u8 dwrr_weight;
2157 __le64 strict_rlmt;
2158 };
2159
2160
2161 union {
2162 u8 rw_dot1q_pcp;
2163 u8 rw_ip_dscp;
2164 };
2165
2166 union {
2167 u8 dot1q_pcp;
2168 struct {
2169 u8 ndscp;
2170 u8 ip_dscp[IONIC_QOS_DSCP_MAX];
2171 };
2172 };
2173 };
2174 __le32 words[64];
2175};
2176
2177
2178
2179
2180
2181
2182
2183
2184union ionic_qos_identity {
2185 struct {
2186 u8 version;
2187 u8 type;
2188 u8 rsvd[62];
2189 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2190 };
2191 __le32 words[478];
2192};
2193
2194
2195
2196
2197
2198
2199
2200struct ionic_qos_init_cmd {
2201 u8 opcode;
2202 u8 group;
2203 u8 rsvd[6];
2204 __le64 info_pa;
2205 u8 rsvd1[48];
2206};
2207
2208typedef struct ionic_admin_comp ionic_qos_init_comp;
2209
2210
2211
2212
2213
2214
2215struct ionic_qos_reset_cmd {
2216 u8 opcode;
2217 u8 group;
2218 u8 rsvd[62];
2219};
2220
2221
2222
2223
2224
2225struct ionic_qos_clear_stats_cmd {
2226 u8 opcode;
2227 u8 group_bitmap;
2228 u8 rsvd[62];
2229};
2230
2231typedef struct ionic_admin_comp ionic_qos_reset_comp;
2232
2233
2234
2235
2236
2237
2238
2239
2240struct ionic_fw_download_cmd {
2241 u8 opcode;
2242 u8 rsvd[3];
2243 __le32 offset;
2244 __le64 addr;
2245 __le32 length;
2246};
2247
2248typedef struct ionic_admin_comp ionic_fw_download_comp;
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260enum ionic_fw_control_oper {
2261 IONIC_FW_RESET = 0,
2262 IONIC_FW_INSTALL = 1,
2263 IONIC_FW_ACTIVATE = 2,
2264 IONIC_FW_INSTALL_ASYNC = 3,
2265 IONIC_FW_INSTALL_STATUS = 4,
2266 IONIC_FW_ACTIVATE_ASYNC = 5,
2267 IONIC_FW_ACTIVATE_STATUS = 6,
2268 IONIC_FW_UPDATE_CLEANUP = 7,
2269};
2270
2271
2272
2273
2274
2275
2276
2277struct ionic_fw_control_cmd {
2278 u8 opcode;
2279 u8 rsvd[3];
2280 u8 oper;
2281 u8 slot;
2282 u8 rsvd1[58];
2283};
2284
2285
2286
2287
2288
2289
2290
2291
2292struct ionic_fw_control_comp {
2293 u8 status;
2294 u8 rsvd;
2295 __le16 comp_index;
2296 u8 slot;
2297 u8 rsvd1[10];
2298 u8 color;
2299};
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314struct ionic_rdma_reset_cmd {
2315 u8 opcode;
2316 u8 rsvd;
2317 __le16 lif_index;
2318 u8 rsvd2[60];
2319};
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349struct ionic_rdma_queue_cmd {
2350 u8 opcode;
2351 u8 rsvd;
2352 __le16 lif_index;
2353 __le32 qid_ver;
2354 __le32 cid;
2355 __le16 dbid;
2356 u8 depth_log2;
2357 u8 stride_log2;
2358 __le64 dma_addr;
2359 u8 rsvd2[40];
2360};
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375struct ionic_notifyq_event {
2376 __le64 eid;
2377 __le16 ecode;
2378 u8 data[54];
2379};
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390struct ionic_link_change_event {
2391 __le64 eid;
2392 __le16 ecode;
2393 __le16 link_status;
2394 __le32 link_speed;
2395 u8 rsvd[48];
2396};
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408struct ionic_reset_event {
2409 __le64 eid;
2410 __le16 ecode;
2411 u8 reset_code;
2412 u8 state;
2413 u8 rsvd[52];
2414};
2415
2416
2417
2418
2419
2420
2421struct ionic_heartbeat_event {
2422 __le64 eid;
2423 __le16 ecode;
2424 u8 rsvd[54];
2425};
2426
2427
2428
2429
2430
2431
2432
2433struct ionic_log_event {
2434 __le64 eid;
2435 __le16 ecode;
2436 u8 data[54];
2437};
2438
2439
2440
2441
2442
2443
2444struct ionic_xcvr_event {
2445 __le64 eid;
2446 __le16 ecode;
2447 u8 rsvd[54];
2448};
2449
2450
2451
2452
2453struct ionic_port_stats {
2454 __le64 frames_rx_ok;
2455 __le64 frames_rx_all;
2456 __le64 frames_rx_bad_fcs;
2457 __le64 frames_rx_bad_all;
2458 __le64 octets_rx_ok;
2459 __le64 octets_rx_all;
2460 __le64 frames_rx_unicast;
2461 __le64 frames_rx_multicast;
2462 __le64 frames_rx_broadcast;
2463 __le64 frames_rx_pause;
2464 __le64 frames_rx_bad_length;
2465 __le64 frames_rx_undersized;
2466 __le64 frames_rx_oversized;
2467 __le64 frames_rx_fragments;
2468 __le64 frames_rx_jabber;
2469 __le64 frames_rx_pripause;
2470 __le64 frames_rx_stomped_crc;
2471 __le64 frames_rx_too_long;
2472 __le64 frames_rx_vlan_good;
2473 __le64 frames_rx_dropped;
2474 __le64 frames_rx_less_than_64b;
2475 __le64 frames_rx_64b;
2476 __le64 frames_rx_65b_127b;
2477 __le64 frames_rx_128b_255b;
2478 __le64 frames_rx_256b_511b;
2479 __le64 frames_rx_512b_1023b;
2480 __le64 frames_rx_1024b_1518b;
2481 __le64 frames_rx_1519b_2047b;
2482 __le64 frames_rx_2048b_4095b;
2483 __le64 frames_rx_4096b_8191b;
2484 __le64 frames_rx_8192b_9215b;
2485 __le64 frames_rx_other;
2486 __le64 frames_tx_ok;
2487 __le64 frames_tx_all;
2488 __le64 frames_tx_bad;
2489 __le64 octets_tx_ok;
2490 __le64 octets_tx_total;
2491 __le64 frames_tx_unicast;
2492 __le64 frames_tx_multicast;
2493 __le64 frames_tx_broadcast;
2494 __le64 frames_tx_pause;
2495 __le64 frames_tx_pripause;
2496 __le64 frames_tx_vlan;
2497 __le64 frames_tx_less_than_64b;
2498 __le64 frames_tx_64b;
2499 __le64 frames_tx_65b_127b;
2500 __le64 frames_tx_128b_255b;
2501 __le64 frames_tx_256b_511b;
2502 __le64 frames_tx_512b_1023b;
2503 __le64 frames_tx_1024b_1518b;
2504 __le64 frames_tx_1519b_2047b;
2505 __le64 frames_tx_2048b_4095b;
2506 __le64 frames_tx_4096b_8191b;
2507 __le64 frames_tx_8192b_9215b;
2508 __le64 frames_tx_other;
2509 __le64 frames_tx_pri_0;
2510 __le64 frames_tx_pri_1;
2511 __le64 frames_tx_pri_2;
2512 __le64 frames_tx_pri_3;
2513 __le64 frames_tx_pri_4;
2514 __le64 frames_tx_pri_5;
2515 __le64 frames_tx_pri_6;
2516 __le64 frames_tx_pri_7;
2517 __le64 frames_rx_pri_0;
2518 __le64 frames_rx_pri_1;
2519 __le64 frames_rx_pri_2;
2520 __le64 frames_rx_pri_3;
2521 __le64 frames_rx_pri_4;
2522 __le64 frames_rx_pri_5;
2523 __le64 frames_rx_pri_6;
2524 __le64 frames_rx_pri_7;
2525 __le64 tx_pripause_0_1us_count;
2526 __le64 tx_pripause_1_1us_count;
2527 __le64 tx_pripause_2_1us_count;
2528 __le64 tx_pripause_3_1us_count;
2529 __le64 tx_pripause_4_1us_count;
2530 __le64 tx_pripause_5_1us_count;
2531 __le64 tx_pripause_6_1us_count;
2532 __le64 tx_pripause_7_1us_count;
2533 __le64 rx_pripause_0_1us_count;
2534 __le64 rx_pripause_1_1us_count;
2535 __le64 rx_pripause_2_1us_count;
2536 __le64 rx_pripause_3_1us_count;
2537 __le64 rx_pripause_4_1us_count;
2538 __le64 rx_pripause_5_1us_count;
2539 __le64 rx_pripause_6_1us_count;
2540 __le64 rx_pripause_7_1us_count;
2541 __le64 rx_pause_1us_count;
2542 __le64 frames_tx_truncated;
2543};
2544
2545struct ionic_mgmt_port_stats {
2546 __le64 frames_rx_ok;
2547 __le64 frames_rx_all;
2548 __le64 frames_rx_bad_fcs;
2549 __le64 frames_rx_bad_all;
2550 __le64 octets_rx_ok;
2551 __le64 octets_rx_all;
2552 __le64 frames_rx_unicast;
2553 __le64 frames_rx_multicast;
2554 __le64 frames_rx_broadcast;
2555 __le64 frames_rx_pause;
2556 __le64 frames_rx_bad_length;
2557 __le64 frames_rx_undersized;
2558 __le64 frames_rx_oversized;
2559 __le64 frames_rx_fragments;
2560 __le64 frames_rx_jabber;
2561 __le64 frames_rx_64b;
2562 __le64 frames_rx_65b_127b;
2563 __le64 frames_rx_128b_255b;
2564 __le64 frames_rx_256b_511b;
2565 __le64 frames_rx_512b_1023b;
2566 __le64 frames_rx_1024b_1518b;
2567 __le64 frames_rx_gt_1518b;
2568 __le64 frames_rx_fifo_full;
2569 __le64 frames_tx_ok;
2570 __le64 frames_tx_all;
2571 __le64 frames_tx_bad;
2572 __le64 octets_tx_ok;
2573 __le64 octets_tx_total;
2574 __le64 frames_tx_unicast;
2575 __le64 frames_tx_multicast;
2576 __le64 frames_tx_broadcast;
2577 __le64 frames_tx_pause;
2578};
2579
2580enum ionic_pb_buffer_drop_stats {
2581 IONIC_BUFFER_INTRINSIC_DROP = 0,
2582 IONIC_BUFFER_DISCARDED,
2583 IONIC_BUFFER_ADMITTED,
2584 IONIC_BUFFER_OUT_OF_CELLS_DROP,
2585 IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
2586 IONIC_BUFFER_OUT_OF_CREDIT_DROP,
2587 IONIC_BUFFER_TRUNCATION_DROP,
2588 IONIC_BUFFER_PORT_DISABLED_DROP,
2589 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
2590 IONIC_BUFFER_SPAN_TAIL_DROP,
2591 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
2592 IONIC_BUFFER_ENQUEUE_ERROR_DROP,
2593 IONIC_BUFFER_INVALID_PORT_DROP,
2594 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
2595 IONIC_BUFFER_DROP_MAX,
2596};
2597
2598enum ionic_oflow_drop_stats {
2599 IONIC_OFLOW_OCCUPANCY_DROP,
2600 IONIC_OFLOW_EMERGENCY_STOP_DROP,
2601 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,
2602 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,
2603 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP,
2604 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP,
2605 IONIC_OFLOW_DROP_MAX,
2606};
2607
2608
2609
2610
2611
2612struct ionic_port_pb_stats {
2613 __le64 sop_count_in;
2614 __le64 eop_count_in;
2615 __le64 sop_count_out;
2616 __le64 eop_count_out;
2617 __le64 drop_counts[IONIC_BUFFER_DROP_MAX];
2618 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2619 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
2620 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
2621 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];
2622 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];
2623 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];
2624 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];
2625 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];
2626 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];
2627 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];
2628 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2629};
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645union ionic_port_identity {
2646 struct {
2647 u8 version;
2648 u8 type;
2649 u8 num_lanes;
2650 u8 autoneg;
2651 __le32 min_frame_size;
2652 __le32 max_frame_size;
2653 u8 fec_type[4];
2654 u8 pause_type[2];
2655 u8 loopback_mode[2];
2656 __le32 speeds[16];
2657 u8 rsvd2[44];
2658 union ionic_port_config config;
2659 };
2660 __le32 words[478];
2661};
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671struct ionic_port_info {
2672 union ionic_port_config config;
2673 struct ionic_port_status status;
2674 union {
2675 struct ionic_port_stats stats;
2676 struct ionic_mgmt_port_stats mgmt_stats;
2677 };
2678
2679 u8 rsvd[760];
2680 struct ionic_port_pb_stats pb_stats;
2681};
2682
2683
2684
2685
2686struct ionic_lif_stats {
2687
2688 __le64 rx_ucast_bytes;
2689 __le64 rx_ucast_packets;
2690 __le64 rx_mcast_bytes;
2691 __le64 rx_mcast_packets;
2692 __le64 rx_bcast_bytes;
2693 __le64 rx_bcast_packets;
2694 __le64 rsvd0;
2695 __le64 rsvd1;
2696
2697 __le64 rx_ucast_drop_bytes;
2698 __le64 rx_ucast_drop_packets;
2699 __le64 rx_mcast_drop_bytes;
2700 __le64 rx_mcast_drop_packets;
2701 __le64 rx_bcast_drop_bytes;
2702 __le64 rx_bcast_drop_packets;
2703 __le64 rx_dma_error;
2704 __le64 rsvd2;
2705
2706 __le64 tx_ucast_bytes;
2707 __le64 tx_ucast_packets;
2708 __le64 tx_mcast_bytes;
2709 __le64 tx_mcast_packets;
2710 __le64 tx_bcast_bytes;
2711 __le64 tx_bcast_packets;
2712 __le64 rsvd3;
2713 __le64 rsvd4;
2714
2715 __le64 tx_ucast_drop_bytes;
2716 __le64 tx_ucast_drop_packets;
2717 __le64 tx_mcast_drop_bytes;
2718 __le64 tx_mcast_drop_packets;
2719 __le64 tx_bcast_drop_bytes;
2720 __le64 tx_bcast_drop_packets;
2721 __le64 tx_dma_error;
2722 __le64 rsvd5;
2723
2724 __le64 rx_queue_disabled;
2725 __le64 rx_queue_empty;
2726 __le64 rx_queue_error;
2727 __le64 rx_desc_fetch_error;
2728 __le64 rx_desc_data_error;
2729 __le64 rsvd6;
2730 __le64 rsvd7;
2731 __le64 rsvd8;
2732
2733 __le64 tx_queue_disabled;
2734 __le64 tx_queue_error;
2735 __le64 tx_desc_fetch_error;
2736 __le64 tx_desc_data_error;
2737 __le64 tx_queue_empty;
2738 __le64 rsvd10;
2739 __le64 rsvd11;
2740 __le64 rsvd12;
2741
2742
2743 __le64 tx_rdma_ucast_bytes;
2744 __le64 tx_rdma_ucast_packets;
2745 __le64 tx_rdma_mcast_bytes;
2746 __le64 tx_rdma_mcast_packets;
2747 __le64 tx_rdma_cnp_packets;
2748 __le64 rsvd13;
2749 __le64 rsvd14;
2750 __le64 rsvd15;
2751
2752
2753 __le64 rx_rdma_ucast_bytes;
2754 __le64 rx_rdma_ucast_packets;
2755 __le64 rx_rdma_mcast_bytes;
2756 __le64 rx_rdma_mcast_packets;
2757 __le64 rx_rdma_cnp_packets;
2758 __le64 rx_rdma_ecn_packets;
2759 __le64 rsvd16;
2760 __le64 rsvd17;
2761
2762 __le64 rsvd18;
2763 __le64 rsvd19;
2764 __le64 rsvd20;
2765 __le64 rsvd21;
2766 __le64 rsvd22;
2767 __le64 rsvd23;
2768 __le64 rsvd24;
2769 __le64 rsvd25;
2770
2771 __le64 rsvd26;
2772 __le64 rsvd27;
2773 __le64 rsvd28;
2774 __le64 rsvd29;
2775 __le64 rsvd30;
2776 __le64 rsvd31;
2777 __le64 rsvd32;
2778 __le64 rsvd33;
2779
2780 __le64 rsvd34;
2781 __le64 rsvd35;
2782 __le64 rsvd36;
2783 __le64 rsvd37;
2784 __le64 rsvd38;
2785 __le64 rsvd39;
2786 __le64 rsvd40;
2787 __le64 rsvd41;
2788
2789 __le64 rsvd42;
2790 __le64 rsvd43;
2791 __le64 rsvd44;
2792 __le64 rsvd45;
2793 __le64 rsvd46;
2794 __le64 rsvd47;
2795 __le64 rsvd48;
2796 __le64 rsvd49;
2797
2798
2799 __le64 rdma_req_rx_pkt_seq_err;
2800 __le64 rdma_req_rx_rnr_retry_err;
2801 __le64 rdma_req_rx_remote_access_err;
2802 __le64 rdma_req_rx_remote_inv_req_err;
2803 __le64 rdma_req_rx_remote_oper_err;
2804 __le64 rdma_req_rx_implied_nak_seq_err;
2805 __le64 rdma_req_rx_cqe_err;
2806 __le64 rdma_req_rx_cqe_flush_err;
2807
2808 __le64 rdma_req_rx_dup_responses;
2809 __le64 rdma_req_rx_invalid_packets;
2810 __le64 rdma_req_tx_local_access_err;
2811 __le64 rdma_req_tx_local_oper_err;
2812 __le64 rdma_req_tx_memory_mgmt_err;
2813 __le64 rsvd52;
2814 __le64 rsvd53;
2815 __le64 rsvd54;
2816
2817
2818 __le64 rdma_resp_rx_dup_requests;
2819 __le64 rdma_resp_rx_out_of_buffer;
2820 __le64 rdma_resp_rx_out_of_seq_pkts;
2821 __le64 rdma_resp_rx_cqe_err;
2822 __le64 rdma_resp_rx_cqe_flush_err;
2823 __le64 rdma_resp_rx_local_len_err;
2824 __le64 rdma_resp_rx_inv_request_err;
2825 __le64 rdma_resp_rx_local_qp_oper_err;
2826
2827 __le64 rdma_resp_rx_out_of_atomic_resource;
2828 __le64 rdma_resp_tx_pkt_seq_err;
2829 __le64 rdma_resp_tx_remote_inv_req_err;
2830 __le64 rdma_resp_tx_remote_access_err;
2831 __le64 rdma_resp_tx_remote_oper_err;
2832 __le64 rdma_resp_tx_rnr_retry_err;
2833 __le64 rsvd57;
2834 __le64 rsvd58;
2835};
2836
2837
2838
2839
2840
2841
2842
2843struct ionic_lif_info {
2844 union ionic_lif_config config;
2845 struct ionic_lif_status status;
2846 struct ionic_lif_stats stats;
2847};
2848
2849union ionic_dev_cmd {
2850 u32 words[16];
2851 struct ionic_admin_cmd cmd;
2852 struct ionic_nop_cmd nop;
2853
2854 struct ionic_dev_identify_cmd identify;
2855 struct ionic_dev_init_cmd init;
2856 struct ionic_dev_reset_cmd reset;
2857 struct ionic_dev_getattr_cmd getattr;
2858 struct ionic_dev_setattr_cmd setattr;
2859
2860 struct ionic_port_identify_cmd port_identify;
2861 struct ionic_port_init_cmd port_init;
2862 struct ionic_port_reset_cmd port_reset;
2863 struct ionic_port_getattr_cmd port_getattr;
2864 struct ionic_port_setattr_cmd port_setattr;
2865
2866 struct ionic_vf_setattr_cmd vf_setattr;
2867 struct ionic_vf_getattr_cmd vf_getattr;
2868
2869 struct ionic_lif_identify_cmd lif_identify;
2870 struct ionic_lif_init_cmd lif_init;
2871 struct ionic_lif_reset_cmd lif_reset;
2872
2873 struct ionic_qos_identify_cmd qos_identify;
2874 struct ionic_qos_init_cmd qos_init;
2875 struct ionic_qos_reset_cmd qos_reset;
2876 struct ionic_qos_clear_stats_cmd qos_clear_stats;
2877
2878 struct ionic_q_identify_cmd q_identify;
2879 struct ionic_q_init_cmd q_init;
2880 struct ionic_q_control_cmd q_control;
2881
2882 struct ionic_fw_download_cmd fw_download;
2883 struct ionic_fw_control_cmd fw_control;
2884};
2885
2886union ionic_dev_cmd_comp {
2887 u32 words[4];
2888 u8 status;
2889 struct ionic_admin_comp comp;
2890 struct ionic_nop_comp nop;
2891
2892 struct ionic_dev_identify_comp identify;
2893 struct ionic_dev_init_comp init;
2894 struct ionic_dev_reset_comp reset;
2895 struct ionic_dev_getattr_comp getattr;
2896 struct ionic_dev_setattr_comp setattr;
2897
2898 struct ionic_port_identify_comp port_identify;
2899 struct ionic_port_init_comp port_init;
2900 struct ionic_port_reset_comp port_reset;
2901 struct ionic_port_getattr_comp port_getattr;
2902 struct ionic_port_setattr_comp port_setattr;
2903
2904 struct ionic_vf_setattr_comp vf_setattr;
2905 struct ionic_vf_getattr_comp vf_getattr;
2906
2907 struct ionic_lif_identify_comp lif_identify;
2908 struct ionic_lif_init_comp lif_init;
2909 ionic_lif_reset_comp lif_reset;
2910
2911 struct ionic_qos_identify_comp qos_identify;
2912 ionic_qos_init_comp qos_init;
2913 ionic_qos_reset_comp qos_reset;
2914
2915 struct ionic_q_identify_comp q_identify;
2916 struct ionic_q_init_comp q_init;
2917
2918 ionic_fw_download_comp fw_download;
2919 struct ionic_fw_control_comp fw_control;
2920};
2921
2922
2923
2924
2925
2926
2927struct ionic_hwstamp_regs {
2928 u32 tick_low;
2929 u32 tick_high;
2930};
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946union ionic_dev_info_regs {
2947#define IONIC_DEVINFO_FWVERS_BUFLEN 32
2948#define IONIC_DEVINFO_SERIAL_BUFLEN 32
2949 struct {
2950 u32 signature;
2951 u8 version;
2952 u8 asic_type;
2953 u8 asic_rev;
2954#define IONIC_FW_STS_F_RUNNING 0x01
2955#define IONIC_FW_STS_F_GENERATION 0xF0
2956 u8 fw_status;
2957 u32 fw_heartbeat;
2958 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
2959 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
2960 u8 rsvd_pad1024[948];
2961 struct ionic_hwstamp_regs hwstamp;
2962 };
2963 u32 words[512];
2964};
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976union ionic_dev_cmd_regs {
2977 struct {
2978 u32 doorbell;
2979 u32 done;
2980 union ionic_dev_cmd cmd;
2981 union ionic_dev_cmd_comp comp;
2982 u8 rsvd[48];
2983 u32 data[478];
2984 } __packed;
2985 u32 words[512];
2986};
2987
2988
2989
2990
2991
2992
2993union ionic_dev_regs {
2994 struct {
2995 union ionic_dev_info_regs info;
2996 union ionic_dev_cmd_regs devcmd;
2997 } __packed;
2998 __le32 words[1024];
2999};
3000
3001union ionic_adminq_cmd {
3002 struct ionic_admin_cmd cmd;
3003 struct ionic_nop_cmd nop;
3004 struct ionic_q_identify_cmd q_identify;
3005 struct ionic_q_init_cmd q_init;
3006 struct ionic_q_control_cmd q_control;
3007 struct ionic_lif_setattr_cmd lif_setattr;
3008 struct ionic_lif_getattr_cmd lif_getattr;
3009 struct ionic_lif_setphc_cmd lif_setphc;
3010 struct ionic_rx_mode_set_cmd rx_mode_set;
3011 struct ionic_rx_filter_add_cmd rx_filter_add;
3012 struct ionic_rx_filter_del_cmd rx_filter_del;
3013 struct ionic_rdma_reset_cmd rdma_reset;
3014 struct ionic_rdma_queue_cmd rdma_queue;
3015 struct ionic_fw_download_cmd fw_download;
3016 struct ionic_fw_control_cmd fw_control;
3017};
3018
3019union ionic_adminq_comp {
3020 struct ionic_admin_comp comp;
3021 struct ionic_nop_comp nop;
3022 struct ionic_q_identify_comp q_identify;
3023 struct ionic_q_init_comp q_init;
3024 struct ionic_lif_setattr_comp lif_setattr;
3025 struct ionic_lif_getattr_comp lif_getattr;
3026 struct ionic_admin_comp lif_setphc;
3027 struct ionic_rx_filter_add_comp rx_filter_add;
3028 struct ionic_fw_control_comp fw_control;
3029};
3030
3031#define IONIC_BARS_MAX 6
3032#define IONIC_PCI_BAR_DBELL 1
3033
3034
3035#define IONIC_BAR0_SIZE 0x8000
3036
3037#define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
3038#define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
3039#define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
3040#define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
3041#define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
3042#define IONIC_DEV_CMD_DONE 0x00000001
3043
3044#define IONIC_ASIC_TYPE_CAPRI 0
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058struct ionic_doorbell {
3059 __le16 p_index;
3060 u8 ring;
3061 u8 qid_lo;
3062 __le16 qid_hi;
3063 u16 rsvd2;
3064};
3065
3066struct ionic_intr_status {
3067 u32 status[2];
3068};
3069
3070struct ionic_notifyq_cmd {
3071 __le32 data;
3072};
3073
3074union ionic_notifyq_comp {
3075 struct ionic_notifyq_event event;
3076 struct ionic_link_change_event link_change;
3077 struct ionic_reset_event reset;
3078 struct ionic_heartbeat_event heartbeat;
3079 struct ionic_log_event log;
3080};
3081
3082
3083struct ionic_identity {
3084 union ionic_drv_identity drv;
3085 union ionic_dev_identity dev;
3086 union ionic_lif_identity lif;
3087 union ionic_port_identity port;
3088 union ionic_qos_identity qos;
3089 union ionic_q_identity txq;
3090};
3091
3092#endif
3093