LXR linux/drivers/net/ethernet/qlogic/netxen/netxen_nic

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Copyright (C) 2003 - 2009 NetXen, Inc.
   4 * Copyright (C) 2009 - QLogic Corporation.
   5 * All rights reserved.
   6 */
   7
   8#ifndef __NETXEN_NIC_HW_H_
   9#define __NETXEN_NIC_HW_H_
  10
  11/* Hardware memory size of 128 meg */
  12#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
  13
  14struct netxen_adapter;
  15
  16#define NETXEN_PCI_MAPSIZE_BYTES  (NETXEN_PCI_MAPSIZE << 20)
  17
  18void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
  19
  20/* Nibble or Byte mode for phy interface (GbE mode only) */
  21
  22#define _netxen_crb_get_bit(var, bit)  ((var >> bit) & 0x1)
  23
  24/*
  25 * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
  26 *
  27 *      Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
  28 *      Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
  29 *      Bit 2 : enable_rx => 1:enable frame recv, 0:disable
  30 *      Bit 3 : rx_synced => R/O: recv enable synched to recv stream
  31 *      Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
  32 *      Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
  33 *      Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
  34 *      Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
  35 *      Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
  36 *      Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
  37 *      Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
  38 *      Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
  39 */
  40
  41#define netxen_gb_tx_flowctl(config_word)       \
  42        ((config_word) |= 1 << 4)
  43#define netxen_gb_rx_flowctl(config_word)       \
  44        ((config_word) |= 1 << 5)
  45#define netxen_gb_tx_reset_pb(config_word)      \
  46        ((config_word) |= 1 << 16)
  47#define netxen_gb_rx_reset_pb(config_word)      \
  48        ((config_word) |= 1 << 17)
  49#define netxen_gb_tx_reset_mac(config_word)     \
  50        ((config_word) |= 1 << 18)
  51#define netxen_gb_rx_reset_mac(config_word)     \
  52        ((config_word) |= 1 << 19)
  53
  54#define netxen_gb_unset_tx_flowctl(config_word) \
  55        ((config_word) &= ~(1 << 4))
  56#define netxen_gb_unset_rx_flowctl(config_word) \
  57        ((config_word) &= ~(1 << 5))
  58
  59#define netxen_gb_get_tx_synced(config_word)    \
  60                _netxen_crb_get_bit((config_word), 1)
  61#define netxen_gb_get_rx_synced(config_word)    \
  62                _netxen_crb_get_bit((config_word), 3)
  63#define netxen_gb_get_tx_flowctl(config_word)   \
  64                _netxen_crb_get_bit((config_word), 4)
  65#define netxen_gb_get_rx_flowctl(config_word)   \
  66                _netxen_crb_get_bit((config_word), 5)
  67#define netxen_gb_get_soft_reset(config_word)   \
  68                _netxen_crb_get_bit((config_word), 31)
  69
  70#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
  71
  72#define netxen_gb_set_mii_mgmt_clockselect(config_word, val)    \
  73                ((config_word) |= ((val) & 0x07))
  74#define netxen_gb_mii_mgmt_reset(config_word)   \
  75                ((config_word) |= 1 << 31)
  76#define netxen_gb_mii_mgmt_unset(config_word)   \
  77                ((config_word) &= ~(1 << 31))
  78
  79/*
  80 * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
  81 * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
  82 * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
  83 */
  84
  85#define netxen_gb_mii_mgmt_set_read_cycle(config_word)  \
  86                ((config_word) |= 1 << 0)
  87#define netxen_gb_mii_mgmt_reg_addr(config_word, val)   \
  88                ((config_word) |= ((val) & 0x1F))
  89#define netxen_gb_mii_mgmt_phy_addr(config_word, val)   \
  90                ((config_word) |= (((val) & 0x1F) << 8))
  91
  92/*
  93 * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
  94 * Read-only register.
  95 * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
  96 * Bit 1 : scanning => 1:scan operation in progress, 0:idle
  97 * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
  98 */
  99#define netxen_get_gb_mii_mgmt_busy(config_word)        \
 100                _netxen_crb_get_bit(config_word, 0)
 101#define netxen_get_gb_mii_mgmt_scanning(config_word)    \
 102                _netxen_crb_get_bit(config_word, 1)
 103#define netxen_get_gb_mii_mgmt_notvalid(config_word)    \
 104                _netxen_crb_get_bit(config_word, 2)
 105/*
 106 * NIU XG Pause Ctl Register
 107 *
 108 *      Bit 0       : xg0_mask => 1:disable tx pause frames
 109 *      Bit 1       : xg0_request => 1:request single pause frame
 110 *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 111 *      Bit 3       : xg1_mask => 1:disable tx pause frames
 112 *      Bit 4       : xg1_request => 1:request single pause frame
 113 *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 114 */
 115
 116#define netxen_xg_set_xg0_mask(config_word)    \
 117        ((config_word) |= 1 << 0)
 118#define netxen_xg_set_xg1_mask(config_word)    \
 119        ((config_word) |= 1 << 3)
 120
 121#define netxen_xg_get_xg0_mask(config_word)    \
 122        _netxen_crb_get_bit((config_word), 0)
 123#define netxen_xg_get_xg1_mask(config_word)    \
 124        _netxen_crb_get_bit((config_word), 3)
 125
 126#define netxen_xg_unset_xg0_mask(config_word)  \
 127        ((config_word) &= ~(1 << 0))
 128#define netxen_xg_unset_xg1_mask(config_word)  \
 129        ((config_word) &= ~(1 << 3))
 130
 131/*
 132 * NIU XG Pause Ctl Register
 133 *
 134 *      Bit 0       : xg0_mask => 1:disable tx pause frames
 135 *      Bit 1       : xg0_request => 1:request single pause frame
 136 *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 137 *      Bit 3       : xg1_mask => 1:disable tx pause frames
 138 *      Bit 4       : xg1_request => 1:request single pause frame
 139 *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 140 */
 141#define netxen_gb_set_gb0_mask(config_word)    \
 142        ((config_word) |= 1 << 0)
 143#define netxen_gb_set_gb1_mask(config_word)    \
 144        ((config_word) |= 1 << 2)
 145#define netxen_gb_set_gb2_mask(config_word)    \
 146        ((config_word) |= 1 << 4)
 147#define netxen_gb_set_gb3_mask(config_word)    \
 148        ((config_word) |= 1 << 6)
 149
 150#define netxen_gb_get_gb0_mask(config_word)    \
 151        _netxen_crb_get_bit((config_word), 0)
 152#define netxen_gb_get_gb1_mask(config_word)    \
 153        _netxen_crb_get_bit((config_word), 2)
 154#define netxen_gb_get_gb2_mask(config_word)    \
 155        _netxen_crb_get_bit((config_word), 4)
 156#define netxen_gb_get_gb3_mask(config_word)    \
 157        _netxen_crb_get_bit((config_word), 6)
 158
 159#define netxen_gb_unset_gb0_mask(config_word)  \
 160        ((config_word) &= ~(1 << 0))
 161#define netxen_gb_unset_gb1_mask(config_word)  \
 162        ((config_word) &= ~(1 << 2))
 163#define netxen_gb_unset_gb2_mask(config_word)  \
 164        ((config_word) &= ~(1 << 4))
 165#define netxen_gb_unset_gb3_mask(config_word)  \
 166        ((config_word) &= ~(1 << 6))
 167
 168
 169/*
 170 * PHY-Specific MII control/status registers.
 171 */
 172#define NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL             0
 173#define NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS              1
 174#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0            2
 175#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1            3
 176#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG             4
 177#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART             5
 178#define NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE        6
 179#define NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT       7
 180#define NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE    8
 181#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL      9
 182#define NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS       10
 183#define NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS     15
 184#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL         16
 185#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS          17
 186#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE          18
 187#define NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS          19
 188#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE    20
 189#define NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT    21
 190#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL         24
 191#define NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE        25
 192#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET        26
 193#define NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE     27
 194
 195/*
 196 * PHY-Specific Status Register (reg 17).
 197 *
 198 * Bit 0      : jabber => 1:jabber detected, 0:not
 199 * Bit 1      : polarity => 1:polarity reversed, 0:normal
 200 * Bit 2      : recvpause => 1:receive pause enabled, 0:disabled
 201 * Bit 3      : xmitpause => 1:transmit pause enabled, 0:disabled
 202 * Bit 4      : energydetect => 1:sleep, 0:active
 203 * Bit 5      : downshift => 1:downshift, 0:no downshift
 204 * Bit 6      : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
 205 * Bits 7-9   : cablelen => not valid in 10Mb/s mode
 206 *                      0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
 207 * Bit 10     : link => 1:link up, 0:link down
 208 * Bit 11     : resolved => 1:speed and duplex resolved, 0:not yet
 209 * Bit 12     : pagercvd => 1:page received, 0:page not received
 210 * Bit 13     : duplex => 1:full duplex, 0:half duplex
 211 * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
 212 */
 213
 214#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
 215
 216#define netxen_set_phy_speed(config_word, val)  \
 217                ((config_word) |= ((val & 0x03) << 14))
 218#define netxen_set_phy_duplex(config_word)      \
 219                ((config_word) |= 1 << 13)
 220#define netxen_clear_phy_duplex(config_word)    \
 221                ((config_word) &= ~(1 << 13))
 222
 223#define netxen_get_phy_link(config_word)        \
 224                _netxen_crb_get_bit(config_word, 10)
 225#define netxen_get_phy_duplex(config_word)      \
 226                _netxen_crb_get_bit(config_word, 13)
 227
 228/*
 229 * NIU Mode Register.
 230 * Bit 0 : enable FibreChannel
 231 * Bit 1 : enable 10/100/1000 Ethernet
 232 * Bit 2 : enable 10Gb Ethernet
 233 */
 234
 235#define netxen_get_niu_enable_ge(config_word)   \
 236                _netxen_crb_get_bit(config_word, 1)
 237
 238#define NETXEN_NIU_NON_PROMISC_MODE     0
 239#define NETXEN_NIU_PROMISC_MODE         1
 240#define NETXEN_NIU_ALLMULTI_MODE        2
 241
 242/*
 243 * NIU XG MAC Config Register
 244 *
 245 * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
 246 * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
 247 * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
 248 * Bit 27: xaui_framer_reset
 249 * Bit 28: xaui_rx_reset
 250 * Bit 29: xaui_tx_reset
 251 * Bit 30: xg_ingress_afifo_reset
 252 * Bit 31: xg_egress_afifo_reset
 253 */
 254
 255#define netxen_xg_soft_reset(config_word)       \
 256                ((config_word) |= 1 << 4)
 257
 258typedef struct {
 259        unsigned valid;
 260        unsigned start_128M;
 261        unsigned end_128M;
 262        unsigned start_2M;
 263} crb_128M_2M_sub_block_map_t;
 264
 265typedef struct {
 266        crb_128M_2M_sub_block_map_t sub_block[16];
 267} crb_128M_2M_block_map_t;
 268
 269#endif                          /* __NETXEN_NIC_HW_H_ */
 270