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7#ifndef _QED_H
8#define _QED_H
9
10#include <linux/types.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/firmware.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/mutex.h>
17#include <linux/pci.h>
18#include <linux/slab.h>
19#include <linux/string.h>
20#include <linux/workqueue.h>
21#include <linux/zlib.h>
22#include <linux/hashtable.h>
23#include <linux/qed/qed_if.h>
24#include "qed_debug.h"
25#include "qed_hsi.h"
26
27extern const struct qed_common_ops qed_common_ops_pass;
28
29#define STORM_FW_VERSION \
30 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
31 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
32
33#define MAX_HWFNS_PER_DEVICE (4)
34#define NAME_SIZE 16
35#define VER_SIZE 16
36
37#define QED_WFQ_UNIT 100
38
39#define QED_WID_SIZE (1024)
40#define QED_MIN_WIDS (4)
41#define QED_PF_DEMS_SIZE (4)
42
43#define QED_LLH_DONT_CARE 0
44
45
46enum qed_coalescing_mode {
47 QED_COAL_MODE_DISABLE,
48 QED_COAL_MODE_ENABLE
49};
50
51enum qed_nvm_cmd {
52 QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
53 QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
54 QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
55 QED_GET_MCP_NVM_RESP = 0xFFFFFF00
56};
57
58struct qed_eth_cb_ops;
59struct qed_dev_info;
60union qed_mcp_protocol_stats;
61enum qed_mcp_protocol_type;
62enum qed_mfw_tlv_type;
63union qed_mfw_tlv_data;
64
65
66#define QED_MFW_GET_FIELD(name, field) \
67 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
68
69#define QED_MFW_SET_FIELD(name, field, value) \
70 do { \
71 (name) &= ~(field ## _MASK); \
72 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
73 } while (0)
74
75static inline u32 qed_db_addr(u32 cid, u32 DEMS)
76{
77 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
78 (cid * QED_PF_DEMS_SIZE);
79
80 return db_addr;
81}
82
83static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
84{
85 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
86 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
87
88 return db_addr;
89}
90
91#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
92 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
93 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
94
95#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
96
97#define D_TRINE(val, cond1, cond2, true1, true2, def) \
98 (val == (cond1) ? true1 : \
99 (val == (cond2) ? true2 : def))
100
101
102struct qed_ptt_pool;
103struct qed_spq;
104struct qed_sb_info;
105struct qed_sb_attn_info;
106struct qed_cxt_mngr;
107struct qed_sb_sp_info;
108struct qed_ll2_info;
109struct qed_mcp_info;
110struct qed_llh_info;
111
112struct qed_rt_data {
113 u32 *init_val;
114 bool *b_valid;
115};
116
117enum qed_tunn_mode {
118 QED_MODE_L2GENEVE_TUNN,
119 QED_MODE_IPGENEVE_TUNN,
120 QED_MODE_L2GRE_TUNN,
121 QED_MODE_IPGRE_TUNN,
122 QED_MODE_VXLAN_TUNN,
123};
124
125enum qed_tunn_clss {
126 QED_TUNN_CLSS_MAC_VLAN,
127 QED_TUNN_CLSS_MAC_VNI,
128 QED_TUNN_CLSS_INNER_MAC_VLAN,
129 QED_TUNN_CLSS_INNER_MAC_VNI,
130 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
131 MAX_QED_TUNN_CLSS,
132};
133
134struct qed_tunn_update_type {
135 bool b_update_mode;
136 bool b_mode_enabled;
137 enum qed_tunn_clss tun_cls;
138};
139
140struct qed_tunn_update_udp_port {
141 bool b_update_port;
142 u16 port;
143};
144
145struct qed_tunnel_info {
146 struct qed_tunn_update_type vxlan;
147 struct qed_tunn_update_type l2_geneve;
148 struct qed_tunn_update_type ip_geneve;
149 struct qed_tunn_update_type l2_gre;
150 struct qed_tunn_update_type ip_gre;
151
152 struct qed_tunn_update_udp_port vxlan_port;
153 struct qed_tunn_update_udp_port geneve_port;
154
155 bool b_update_rx_cls;
156 bool b_update_tx_cls;
157};
158
159struct qed_tunn_start_params {
160 unsigned long tunn_mode;
161 u16 vxlan_udp_port;
162 u16 geneve_udp_port;
163 u8 update_vxlan_udp_port;
164 u8 update_geneve_udp_port;
165 u8 tunn_clss_vxlan;
166 u8 tunn_clss_l2geneve;
167 u8 tunn_clss_ipgeneve;
168 u8 tunn_clss_l2gre;
169 u8 tunn_clss_ipgre;
170};
171
172struct qed_tunn_update_params {
173 unsigned long tunn_mode_update_mask;
174 unsigned long tunn_mode;
175 u16 vxlan_udp_port;
176 u16 geneve_udp_port;
177 u8 update_rx_pf_clss;
178 u8 update_tx_pf_clss;
179 u8 update_vxlan_udp_port;
180 u8 update_geneve_udp_port;
181 u8 tunn_clss_vxlan;
182 u8 tunn_clss_l2geneve;
183 u8 tunn_clss_ipgeneve;
184 u8 tunn_clss_l2gre;
185 u8 tunn_clss_ipgre;
186};
187
188
189
190
191
192enum qed_pci_personality {
193 QED_PCI_ETH,
194 QED_PCI_FCOE,
195 QED_PCI_ISCSI,
196 QED_PCI_NVMETCP,
197 QED_PCI_ETH_ROCE,
198 QED_PCI_ETH_IWARP,
199 QED_PCI_ETH_RDMA,
200 QED_PCI_DEFAULT,
201};
202
203
204struct qed_qm_iids {
205 u32 cids;
206 u32 vf_cids;
207 u32 tids;
208};
209
210
211
212
213enum qed_resources {
214 QED_SB,
215 QED_L2_QUEUE,
216 QED_VPORT,
217 QED_RSS_ENG,
218 QED_PQ,
219 QED_RL,
220 QED_MAC,
221 QED_VLAN,
222 QED_RDMA_CNQ_RAM,
223 QED_ILT,
224 QED_LL2_RAM_QUEUE,
225 QED_LL2_CTX_QUEUE,
226 QED_CMDQS_CQS,
227 QED_RDMA_STATS_QUEUE,
228 QED_BDQ,
229 QED_MAX_RESC,
230};
231
232enum QED_FEATURE {
233 QED_PF_L2_QUE,
234 QED_VF,
235 QED_RDMA_CNQ,
236 QED_NVMETCP_CQ,
237 QED_ISCSI_CQ,
238 QED_FCOE_CQ,
239 QED_VF_L2_QUE,
240 QED_MAX_FEATURES,
241};
242
243enum qed_dev_cap {
244 QED_DEV_CAP_ETH,
245 QED_DEV_CAP_FCOE,
246 QED_DEV_CAP_ISCSI,
247 QED_DEV_CAP_ROCE,
248 QED_DEV_CAP_IWARP,
249};
250
251enum qed_wol_support {
252 QED_WOL_SUPPORT_NONE,
253 QED_WOL_SUPPORT_PME,
254};
255
256enum qed_db_rec_exec {
257 DB_REC_DRY_RUN,
258 DB_REC_REAL_DEAL,
259 DB_REC_ONCE,
260};
261
262struct qed_hw_info {
263
264 enum qed_pci_personality personality;
265#define QED_IS_RDMA_PERSONALITY(dev) \
266 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
267 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
268 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
269#define QED_IS_ROCE_PERSONALITY(dev) \
270 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
271 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
272#define QED_IS_IWARP_PERSONALITY(dev) \
273 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
274 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
275#define QED_IS_L2_PERSONALITY(dev) \
276 ((dev)->hw_info.personality == QED_PCI_ETH || \
277 QED_IS_RDMA_PERSONALITY(dev))
278#define QED_IS_FCOE_PERSONALITY(dev) \
279 ((dev)->hw_info.personality == QED_PCI_FCOE)
280#define QED_IS_ISCSI_PERSONALITY(dev) \
281 ((dev)->hw_info.personality == QED_PCI_ISCSI)
282#define QED_IS_NVMETCP_PERSONALITY(dev) \
283 ((dev)->hw_info.personality == QED_PCI_NVMETCP)
284
285
286 u32 resc_start[QED_MAX_RESC];
287 u32 resc_num[QED_MAX_RESC];
288#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
289#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
290#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
291 RESC_NUM(_p_hwfn, resc))
292
293 u32 feat_num[QED_MAX_FEATURES];
294#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
295
296
297 u8 num_hw_tc;
298
299
300
301
302 u8 num_active_tc;
303
304 u8 offload_tc;
305 bool offload_tc_set;
306
307 bool multi_tc_roce_en;
308#define IS_QED_MULTI_TC_ROCE(p_hwfn) ((p_hwfn)->hw_info.multi_tc_roce_en)
309
310 u32 concrete_fid;
311 u16 opaque_fid;
312 u16 ovlan;
313 u32 part_num[4];
314
315 unsigned char hw_mac_addr[ETH_ALEN];
316 u64 node_wwn;
317 u64 port_wwn;
318
319 u16 num_fcoe_conns;
320
321 struct qed_igu_info *p_igu_info;
322
323 u32 hw_mode;
324 unsigned long device_capabilities;
325 u16 mtu;
326
327 enum qed_wol_support b_wol_support;
328};
329
330
331#define DMAE_MAX_RW_SIZE 0x2000
332
333struct qed_dmae_info {
334
335 struct mutex mutex;
336
337 u8 channel;
338
339 dma_addr_t completion_word_phys_addr;
340
341
342
343
344 u32 *p_completion_word;
345
346 dma_addr_t intermediate_buffer_phys_addr;
347
348
349
350
351
352 u32 *p_intermediate_buffer;
353
354 dma_addr_t dmae_cmd_phys_addr;
355 struct dmae_cmd *p_dmae_cmd;
356};
357
358struct qed_wfq_data {
359
360 u32 min_speed;
361 bool configured;
362};
363
364struct qed_qm_info {
365 struct init_qm_pq_params *qm_pq_params;
366 struct init_qm_vport_params *qm_vport_params;
367 struct init_qm_port_params *qm_port_params;
368 u16 start_pq;
369 u8 start_vport;
370 u16 pure_lb_pq;
371 u16 first_ofld_pq;
372 u16 first_llt_pq;
373 u16 pure_ack_pq;
374 u16 ooo_pq;
375 u16 first_vf_pq;
376 u16 first_mcos_pq;
377 u16 first_rl_pq;
378 u16 num_pqs;
379 u16 num_vf_pqs;
380 u8 num_vports;
381 u8 max_phys_tcs_per_port;
382 u8 ooo_tc;
383 bool pf_rl_en;
384 bool pf_wfq_en;
385 bool vport_rl_en;
386 bool vport_wfq_en;
387 u8 pf_wfq;
388 u32 pf_rl;
389 struct qed_wfq_data *wfq_data;
390 u8 num_pf_rls;
391};
392
393#define QED_OVERFLOW_BIT 1
394
395struct qed_db_recovery_info {
396 struct list_head list;
397
398
399 spinlock_t lock;
400 bool dorq_attn;
401 u32 db_recovery_counter;
402 unsigned long overflow;
403};
404
405struct storm_stats {
406 u32 address;
407 u32 len;
408};
409
410struct qed_storm_stats {
411 struct storm_stats mstats;
412 struct storm_stats pstats;
413 struct storm_stats tstats;
414 struct storm_stats ustats;
415};
416
417struct qed_fw_data {
418 struct fw_ver_info *fw_ver_info;
419 const u8 *modes_tree_buf;
420 union init_op *init_ops;
421 const u32 *arr_data;
422 const u32 *fw_overlays;
423 u32 fw_overlays_len;
424 u32 init_ops_size;
425};
426
427enum qed_mf_mode_bit {
428
429 QED_MF_OVLAN_CLSS,
430
431
432 QED_MF_LLH_MAC_CLSS,
433
434
435 QED_MF_LLH_PROTO_CLSS,
436
437
438 QED_MF_NEED_DEF_PF,
439
440
441 QED_MF_LL2_NON_UNICAST,
442
443
444 QED_MF_INTER_PF_SWITCH,
445
446
447 QED_MF_UFP_SPECIFIC,
448
449
450 QED_MF_DISABLE_ARFS,
451
452
453 QED_MF_8021Q_TAGGING,
454
455
456 QED_MF_8021AD_TAGGING,
457
458
459 QED_MF_DSCP_TO_TC_MAP,
460
461
462 QED_MF_DONT_ADD_VLAN0_TAG,
463};
464
465enum qed_ufp_mode {
466 QED_UFP_MODE_ETS,
467 QED_UFP_MODE_VNIC_BW,
468 QED_UFP_MODE_UNKNOWN
469};
470
471enum qed_ufp_pri_type {
472 QED_UFP_PRI_OS,
473 QED_UFP_PRI_VNIC,
474 QED_UFP_PRI_UNKNOWN
475};
476
477struct qed_ufp_info {
478 enum qed_ufp_pri_type pri_type;
479 enum qed_ufp_mode mode;
480 u8 tc;
481};
482
483enum BAR_ID {
484 BAR_ID_0,
485 BAR_ID_1
486};
487
488struct qed_nvm_image_info {
489 u32 num_images;
490 struct bist_nvm_image_att *image_att;
491 bool valid;
492};
493
494enum qed_hsi_def_type {
495 QED_HSI_DEF_MAX_NUM_VFS,
496 QED_HSI_DEF_MAX_NUM_L2_QUEUES,
497 QED_HSI_DEF_MAX_NUM_PORTS,
498 QED_HSI_DEF_MAX_SB_PER_PATH,
499 QED_HSI_DEF_MAX_NUM_PFS,
500 QED_HSI_DEF_MAX_NUM_VPORTS,
501 QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
502 QED_HSI_DEF_MAX_QM_TX_QUEUES,
503 QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
504 QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
505 QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
506 QED_HSI_DEF_MAX_PBF_CMD_LINES,
507 QED_HSI_DEF_MAX_BTB_BLOCKS,
508 QED_NUM_HSI_DEFS
509};
510
511struct qed_simd_fp_handler {
512 void *token;
513 void (*func)(void *);
514};
515
516enum qed_slowpath_wq_flag {
517 QED_SLOWPATH_MFW_TLV_REQ,
518 QED_SLOWPATH_PERIODIC_DB_REC,
519};
520
521struct qed_hwfn {
522 struct qed_dev *cdev;
523 u8 my_id;
524#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
525 u8 rel_pf_id;
526 u8 abs_pf_id;
527#define QED_PATH_ID(_p_hwfn) \
528 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
529 u8 port_id;
530 bool b_active;
531
532 u32 dp_module;
533 u8 dp_level;
534 char name[NAME_SIZE];
535
536 bool hw_init_done;
537
538 u8 num_funcs_on_engine;
539 u8 enabled_func_idx;
540
541
542 void __iomem *regview;
543 void __iomem *doorbells;
544 u64 db_phys_addr;
545 unsigned long db_size;
546
547
548 struct qed_ptt_pool *p_ptt_pool;
549
550
551 struct qed_hw_info hw_info;
552
553
554 struct qed_rt_data rt_data;
555
556
557 struct qed_spq *p_spq;
558
559
560 struct qed_eq *p_eq;
561
562
563 struct qed_consq *p_consq;
564
565
566 struct tasklet_struct sp_dpc;
567 bool b_sp_dpc_enabled;
568
569 struct qed_ptt *p_main_ptt;
570 struct qed_ptt *p_dpc_ptt;
571
572
573
574
575 struct qed_ptt *p_ptp_ptt;
576
577 struct qed_sb_sp_info *p_sp_sb;
578 struct qed_sb_attn_info *p_sb_attn;
579
580
581 bool using_ll2;
582 struct qed_ll2_info *p_ll2_info;
583 struct qed_ooo_info *p_ooo_info;
584 struct qed_rdma_info *p_rdma_info;
585 struct qed_iscsi_info *p_iscsi_info;
586 struct qed_nvmetcp_info *p_nvmetcp_info;
587 struct qed_fcoe_info *p_fcoe_info;
588 struct qed_pf_params pf_params;
589
590 bool b_rdma_enabled_in_prs;
591 u32 rdma_prs_search_reg;
592
593 struct qed_cxt_mngr *p_cxt_mngr;
594
595
596 bool b_int_enabled;
597 bool b_int_requested;
598
599
600 bool b_drv_link_init;
601
602 struct qed_vf_iov *vf_iov_info;
603 struct qed_pf_iov *pf_iov_info;
604 struct qed_mcp_info *mcp_info;
605
606 struct qed_dcbx_info *p_dcbx_info;
607
608 struct qed_ufp_info ufp_info;
609
610 struct qed_dmae_info dmae_info;
611
612
613 struct qed_qm_info qm_info;
614 struct qed_storm_stats storm_stats;
615
616
617 void *unzip_buf;
618
619 struct dbg_tools_data dbg_info;
620 void *dbg_user_info;
621 struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
622
623
624 u16 wid_count;
625 u32 dpi_size;
626 u32 dpi_count;
627
628
629 u32 dpi_start_offset;
630
631
632 u8 dcbx_no_edpm;
633 u8 db_bar_no_edpm;
634
635
636 struct qed_l2_info *p_l2_info;
637
638
639 struct qed_db_recovery_info db_recovery_info;
640
641
642 struct qed_nvm_image_info nvm_info;
643
644 struct phys_mem_desc *fw_overlay_mem;
645 struct qed_ptt *p_arfs_ptt;
646
647 struct qed_simd_fp_handler simd_proto_handler[64];
648
649#ifdef CONFIG_QED_SRIOV
650 struct workqueue_struct *iov_wq;
651 struct delayed_work iov_task;
652 unsigned long iov_task_flags;
653#endif
654 struct z_stream_s *stream;
655 bool slowpath_wq_active;
656 struct workqueue_struct *slowpath_wq;
657 struct delayed_work slowpath_task;
658 unsigned long slowpath_task_flags;
659 u32 periodic_db_rec_count;
660};
661
662struct pci_params {
663 int pm_cap;
664
665 unsigned long mem_start;
666 unsigned long mem_end;
667 unsigned int irq;
668 u8 pf_num;
669};
670
671struct qed_int_param {
672 u32 int_mode;
673 u8 num_vectors;
674 u8 min_msix_cnt;
675};
676
677struct qed_int_params {
678 struct qed_int_param in;
679 struct qed_int_param out;
680 struct msix_entry *msix_table;
681 bool fp_initialized;
682 u8 fp_msix_base;
683 u8 fp_msix_cnt;
684 u8 rdma_msix_base;
685 u8 rdma_msix_cnt;
686};
687
688struct qed_dbg_feature {
689 struct dentry *dentry;
690 u8 *dump_buf;
691 u32 buf_size;
692 u32 dumped_dwords;
693};
694
695struct qed_dev {
696 u32 dp_module;
697 u8 dp_level;
698 char name[NAME_SIZE];
699
700 enum qed_dev_type type;
701
702#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
703#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
704#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
705#define QED_IS_K2(dev) QED_IS_AH(dev)
706#define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev))
707#define QED_IS_E5(dev) ((dev)->type == QED_DEV_TYPE_E5)
708
709 u16 vendor_id;
710
711 u16 device_id;
712#define QED_DEV_ID_MASK 0xff00
713#define QED_DEV_ID_MASK_BB 0x1600
714#define QED_DEV_ID_MASK_AH 0x8000
715
716 u16 chip_num;
717#define CHIP_NUM_MASK 0xffff
718#define CHIP_NUM_SHIFT 16
719
720 u16 chip_rev;
721#define CHIP_REV_MASK 0xf
722#define CHIP_REV_SHIFT 12
723#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
724
725 u16 chip_metal;
726#define CHIP_METAL_MASK 0xff
727#define CHIP_METAL_SHIFT 4
728
729 u16 chip_bond_id;
730#define CHIP_BOND_ID_MASK 0xf
731#define CHIP_BOND_ID_SHIFT 0
732
733 u8 num_engines;
734 u8 num_ports;
735 u8 num_ports_in_engine;
736 u8 num_funcs_in_port;
737
738 u8 path_id;
739
740 unsigned long mf_bits;
741
742 int pcie_width;
743 int pcie_speed;
744
745
746 u8 mcp_rev;
747 u8 boot_mode;
748
749
750 u8 wol_config;
751 u8 wol_mac[ETH_ALEN];
752
753 u32 int_mode;
754 enum qed_coalescing_mode int_coalescing_mode;
755 u16 rx_coalesce_usecs;
756 u16 tx_coalesce_usecs;
757
758
759 void __iomem *regview;
760 void __iomem *doorbells;
761 u64 db_phys_addr;
762 unsigned long db_size;
763
764
765 u8 cache_shift;
766
767
768 const u32 *iro_arr;
769#define IRO ((const struct iro *)p_hwfn->cdev->iro_arr)
770
771
772 u8 num_hwfns;
773 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
774
775
776 u8 l2_affin_hint;
777 u8 fir_affin;
778 u8 iwarp_affin;
779
780
781 struct qed_hw_sriov_info *p_iov_info;
782#define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
783 struct qed_tunnel_info tunnel;
784 bool b_is_vf;
785 u32 drv_type;
786 struct qed_eth_stats *reset_stats;
787 struct qed_fw_data *fw_data;
788
789 u32 mcp_nvm_resp;
790
791
792 bool recov_in_prog;
793
794
795 bool attn_clr_en;
796
797
798 u8 ppfid_bitmap;
799 struct qed_llh_info *p_llh_info;
800
801
802 struct qed_dev_info common_dev_info;
803 struct qede_dev *edev;
804 struct pci_dev *pdev;
805 u32 flags;
806#define QED_FLAG_STORAGE_STARTED (BIT(0))
807 int msg_enable;
808
809 struct pci_params pci_params;
810
811 struct qed_int_params int_params;
812
813 u8 protocol;
814#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
815#define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
816
817
818 union {
819 struct qed_common_cb_ops *common;
820 struct qed_eth_cb_ops *eth;
821 struct qed_fcoe_cb_ops *fcoe;
822 struct qed_iscsi_cb_ops *iscsi;
823 struct qed_nvmetcp_cb_ops *nvmetcp;
824 } protocol_ops;
825 void *ops_cookie;
826
827#ifdef CONFIG_QED_LL2
828 struct qed_cb_ll2_info *ll2;
829 u8 ll2_mac_address[ETH_ALEN];
830#endif
831 struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
832 u8 engine_for_debug;
833 bool disable_ilt_dump;
834 bool dbg_bin_dump;
835
836 DECLARE_HASHTABLE(connections, 10);
837 const struct firmware *firmware;
838
839 bool print_dbg_data;
840
841 u32 rdma_max_sge;
842 u32 rdma_max_inline;
843 u32 rdma_max_srq_sge;
844 u16 tunn_feature_mask;
845
846 bool iwarp_cmt;
847};
848
849u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
850
851#define NUM_OF_VFS(dev) \
852 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
853#define NUM_OF_L2_QUEUES(dev) \
854 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
855#define NUM_OF_PORTS(dev) \
856 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
857#define NUM_OF_SBS(dev) \
858 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
859#define NUM_OF_ENG_PFS(dev) \
860 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
861#define NUM_OF_VPORTS(dev) \
862 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
863#define NUM_OF_RSS_ENGINES(dev) \
864 qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
865#define NUM_OF_QM_TX_QUEUES(dev) \
866 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
867#define NUM_OF_PXP_ILT_RECORDS(dev) \
868 qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
869#define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
870 qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
871#define NUM_OF_QM_GLOBAL_RLS(dev) \
872 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
873#define NUM_OF_PBF_CMD_LINES(dev) \
874 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
875#define NUM_OF_BTB_BLOCKS(dev) \
876 qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
877
878
879
880
881
882
883
884
885
886
887static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
888 u32 concrete_fid)
889{
890 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
891 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
892 u8 vf_valid = GET_FIELD(concrete_fid,
893 PXP_CONCRETE_FID_VFVALID);
894 u8 sw_fid;
895
896 if (vf_valid)
897 sw_fid = vfid + MAX_NUM_PFS;
898 else
899 sw_fid = pfid;
900
901 return sw_fid;
902}
903
904#define PKT_LB_TC 9
905#define MAX_NUM_VOQS_E4 20
906
907int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
908void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
909 struct qed_ptt *p_ptt,
910 u32 min_pf_rate);
911
912void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
913int qed_device_num_engines(struct qed_dev *cdev);
914void qed_set_fw_mac_addr(__le16 *fw_msb,
915 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
916
917#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
918#define QED_IS_CMT(dev) ((dev)->num_hwfns > 1)
919
920#define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin])
921#define QED_IWARP_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->iwarp_affin])
922#define QED_AFFIN_HWFN(dev) \
923 (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \
924 QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev))
925#define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1)
926
927
928#define PQ_FLAGS_RLS (BIT(0))
929#define PQ_FLAGS_MCOS (BIT(1))
930#define PQ_FLAGS_LB (BIT(2))
931#define PQ_FLAGS_OOO (BIT(3))
932#define PQ_FLAGS_ACK (BIT(4))
933#define PQ_FLAGS_OFLD (BIT(5))
934#define PQ_FLAGS_VFS (BIT(6))
935#define PQ_FLAGS_LLT (BIT(7))
936#define PQ_FLAGS_MTC (BIT(8))
937
938
939u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
940u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
941u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
942u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
943u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
944
945
946void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
947void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
948bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
949
950
951#define DP_NAME(cdev) ((cdev)->name)
952
953#define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
954 (cdev->regview) + \
955 (offset))
956
957#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
958#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
959#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
960
961#define DOORBELL(cdev, db_addr, val) \
962 writel((u32)val, (void __iomem *)((u8 __iomem *)\
963 (cdev->doorbells) + (db_addr)))
964
965#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
966 qed_device_num_ports((_p_hwfn)->cdev))
967int qed_device_num_ports(struct qed_dev *cdev);
968
969
970int qed_fill_dev_info(struct qed_dev *cdev,
971 struct qed_dev_info *dev_info);
972void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
973void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
974u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
975 u32 input_len, u8 *input_buf,
976 u32 max_size, u8 *unzip_buf);
977int qed_recovery_process(struct qed_dev *cdev);
978void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
979void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
980 enum qed_hw_err_type err_type);
981void qed_get_protocol_stats(struct qed_dev *cdev,
982 enum qed_mcp_protocol_type type,
983 union qed_mcp_protocol_stats *stats);
984int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
985void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
986int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
987
988int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
989 enum qed_mfw_tlv_type type,
990 union qed_mfw_tlv_data *tlv_data);
991
992void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
993
994void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
995
996int qed_llh_add_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
997int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port);
998void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
999void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
1000void qed_llh_clear_all_filters(struct qed_dev *cdev);
1001#endif
1002
