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7#include <linux/crash_dump.h>
8#include <linux/module.h>
9#include <linux/pci.h>
10#include <linux/device.h>
11#include <linux/netdevice.h>
12#include <linux/etherdevice.h>
13#include <linux/skbuff.h>
14#include <linux/errno.h>
15#include <linux/list.h>
16#include <linux/string.h>
17#include <linux/dma-mapping.h>
18#include <linux/interrupt.h>
19#include <asm/byteorder.h>
20#include <asm/param.h>
21#include <linux/io.h>
22#include <linux/netdev_features.h>
23#include <linux/udp.h>
24#include <linux/tcp.h>
25#include <net/udp_tunnel.h>
26#include <linux/ip.h>
27#include <net/ipv6.h>
28#include <net/tcp.h>
29#include <linux/if_ether.h>
30#include <linux/if_vlan.h>
31#include <linux/pkt_sched.h>
32#include <linux/ethtool.h>
33#include <linux/in.h>
34#include <linux/random.h>
35#include <net/ip6_checksum.h>
36#include <linux/bitops.h>
37#include <linux/vmalloc.h>
38#include <linux/aer.h>
39#include "qede.h"
40#include "qede_ptp.h"
41
42MODULE_DESCRIPTION("QLogic FastLinQ 4xxxx Ethernet Driver");
43MODULE_LICENSE("GPL");
44
45static uint debug;
46module_param(debug, uint, 0);
47MODULE_PARM_DESC(debug, " Default debug msglevel");
48
49static const struct qed_eth_ops *qed_ops;
50
51#define CHIP_NUM_57980S_40 0x1634
52#define CHIP_NUM_57980S_10 0x1666
53#define CHIP_NUM_57980S_MF 0x1636
54#define CHIP_NUM_57980S_100 0x1644
55#define CHIP_NUM_57980S_50 0x1654
56#define CHIP_NUM_57980S_25 0x1656
57#define CHIP_NUM_57980S_IOV 0x1664
58#define CHIP_NUM_AH 0x8070
59#define CHIP_NUM_AH_IOV 0x8090
60
61#ifndef PCI_DEVICE_ID_NX2_57980E
62#define PCI_DEVICE_ID_57980S_40 CHIP_NUM_57980S_40
63#define PCI_DEVICE_ID_57980S_10 CHIP_NUM_57980S_10
64#define PCI_DEVICE_ID_57980S_MF CHIP_NUM_57980S_MF
65#define PCI_DEVICE_ID_57980S_100 CHIP_NUM_57980S_100
66#define PCI_DEVICE_ID_57980S_50 CHIP_NUM_57980S_50
67#define PCI_DEVICE_ID_57980S_25 CHIP_NUM_57980S_25
68#define PCI_DEVICE_ID_57980S_IOV CHIP_NUM_57980S_IOV
69#define PCI_DEVICE_ID_AH CHIP_NUM_AH
70#define PCI_DEVICE_ID_AH_IOV CHIP_NUM_AH_IOV
71
72#endif
73
74enum qede_pci_private {
75 QEDE_PRIVATE_PF,
76 QEDE_PRIVATE_VF
77};
78
79static const struct pci_device_id qede_pci_tbl[] = {
80 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_40), QEDE_PRIVATE_PF},
81 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_10), QEDE_PRIVATE_PF},
82 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_MF), QEDE_PRIVATE_PF},
83 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_100), QEDE_PRIVATE_PF},
84 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_50), QEDE_PRIVATE_PF},
85 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_25), QEDE_PRIVATE_PF},
86#ifdef CONFIG_QED_SRIOV
87 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_57980S_IOV), QEDE_PRIVATE_VF},
88#endif
89 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH), QEDE_PRIVATE_PF},
90#ifdef CONFIG_QED_SRIOV
91 {PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_AH_IOV), QEDE_PRIVATE_VF},
92#endif
93 { 0 }
94};
95
96MODULE_DEVICE_TABLE(pci, qede_pci_tbl);
97
98static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id);
99static pci_ers_result_t
100qede_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state);
101
102#define TX_TIMEOUT (5 * HZ)
103
104
105#define XDP_PI 11
106
107static void qede_remove(struct pci_dev *pdev);
108static void qede_shutdown(struct pci_dev *pdev);
109static void qede_link_update(void *dev, struct qed_link_output *link);
110static void qede_schedule_recovery_handler(void *dev);
111static void qede_recovery_handler(struct qede_dev *edev);
112static void qede_schedule_hw_err_handler(void *dev,
113 enum qed_hw_err_type err_type);
114static void qede_get_eth_tlv_data(void *edev, void *data);
115static void qede_get_generic_tlv_data(void *edev,
116 struct qed_generic_tlvs *data);
117static void qede_generic_hw_err_handler(struct qede_dev *edev);
118#ifdef CONFIG_QED_SRIOV
119static int qede_set_vf_vlan(struct net_device *ndev, int vf, u16 vlan, u8 qos,
120 __be16 vlan_proto)
121{
122 struct qede_dev *edev = netdev_priv(ndev);
123
124 if (vlan > 4095) {
125 DP_NOTICE(edev, "Illegal vlan value %d\n", vlan);
126 return -EINVAL;
127 }
128
129 if (vlan_proto != htons(ETH_P_8021Q))
130 return -EPROTONOSUPPORT;
131
132 DP_VERBOSE(edev, QED_MSG_IOV, "Setting Vlan 0x%04x to VF [%d]\n",
133 vlan, vf);
134
135 return edev->ops->iov->set_vlan(edev->cdev, vlan, vf);
136}
137
138static int qede_set_vf_mac(struct net_device *ndev, int vfidx, u8 *mac)
139{
140 struct qede_dev *edev = netdev_priv(ndev);
141
142 DP_VERBOSE(edev, QED_MSG_IOV, "Setting MAC %pM to VF [%d]\n", mac, vfidx);
143
144 if (!is_valid_ether_addr(mac)) {
145 DP_VERBOSE(edev, QED_MSG_IOV, "MAC address isn't valid\n");
146 return -EINVAL;
147 }
148
149 return edev->ops->iov->set_mac(edev->cdev, mac, vfidx);
150}
151
152static int qede_sriov_configure(struct pci_dev *pdev, int num_vfs_param)
153{
154 struct qede_dev *edev = netdev_priv(pci_get_drvdata(pdev));
155 struct qed_dev_info *qed_info = &edev->dev_info.common;
156 struct qed_update_vport_params *vport_params;
157 int rc;
158
159 vport_params = vzalloc(sizeof(*vport_params));
160 if (!vport_params)
161 return -ENOMEM;
162 DP_VERBOSE(edev, QED_MSG_IOV, "Requested %d VFs\n", num_vfs_param);
163
164 rc = edev->ops->iov->configure(edev->cdev, num_vfs_param);
165
166
167 if ((rc == num_vfs_param) && netif_running(edev->ndev) &&
168 !qed_info->b_inter_pf_switch && qed_info->tx_switching) {
169 vport_params->vport_id = 0;
170 vport_params->update_tx_switching_flg = 1;
171 vport_params->tx_switching_flg = num_vfs_param ? 1 : 0;
172 edev->ops->vport_update(edev->cdev, vport_params);
173 }
174
175 vfree(vport_params);
176 return rc;
177}
178#endif
179
180static const struct pci_error_handlers qede_err_handler = {
181 .error_detected = qede_io_error_detected,
182};
183
184static struct pci_driver qede_pci_driver = {
185 .name = "qede",
186 .id_table = qede_pci_tbl,
187 .probe = qede_probe,
188 .remove = qede_remove,
189 .shutdown = qede_shutdown,
190#ifdef CONFIG_QED_SRIOV
191 .sriov_configure = qede_sriov_configure,
192#endif
193 .err_handler = &qede_err_handler,
194};
195
196static struct qed_eth_cb_ops qede_ll_ops = {
197 {
198#ifdef CONFIG_RFS_ACCEL
199 .arfs_filter_op = qede_arfs_filter_op,
200#endif
201 .link_update = qede_link_update,
202 .schedule_recovery_handler = qede_schedule_recovery_handler,
203 .schedule_hw_err_handler = qede_schedule_hw_err_handler,
204 .get_generic_tlv_data = qede_get_generic_tlv_data,
205 .get_protocol_tlv_data = qede_get_eth_tlv_data,
206 },
207 .force_mac = qede_force_mac,
208 .ports_update = qede_udp_ports_update,
209};
210
211static int qede_netdev_event(struct notifier_block *this, unsigned long event,
212 void *ptr)
213{
214 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
215 struct ethtool_drvinfo drvinfo;
216 struct qede_dev *edev;
217
218 if (event != NETDEV_CHANGENAME && event != NETDEV_CHANGEADDR)
219 goto done;
220
221
222 if (!ndev || !ndev->ethtool_ops || !ndev->ethtool_ops->get_drvinfo)
223 goto done;
224
225 memset(&drvinfo, 0, sizeof(drvinfo));
226 ndev->ethtool_ops->get_drvinfo(ndev, &drvinfo);
227 if (strcmp(drvinfo.driver, "qede"))
228 goto done;
229 edev = netdev_priv(ndev);
230
231 switch (event) {
232 case NETDEV_CHANGENAME:
233
234 if (!edev->ops || !edev->ops->common)
235 goto done;
236 edev->ops->common->set_name(edev->cdev, edev->ndev->name);
237 break;
238 case NETDEV_CHANGEADDR:
239 edev = netdev_priv(ndev);
240 qede_rdma_event_changeaddr(edev);
241 break;
242 }
243
244done:
245 return NOTIFY_DONE;
246}
247
248static struct notifier_block qede_netdev_notifier = {
249 .notifier_call = qede_netdev_event,
250};
251
252static
253int __init qede_init(void)
254{
255 int ret;
256
257 pr_info("qede init: QLogic FastLinQ 4xxxx Ethernet Driver qede\n");
258
259 qede_forced_speed_maps_init();
260
261 qed_ops = qed_get_eth_ops();
262 if (!qed_ops) {
263 pr_notice("Failed to get qed ethtool operations\n");
264 return -EINVAL;
265 }
266
267
268
269
270 ret = register_netdevice_notifier(&qede_netdev_notifier);
271 if (ret) {
272 pr_notice("Failed to register netdevice_notifier\n");
273 qed_put_eth_ops();
274 return -EINVAL;
275 }
276
277 ret = pci_register_driver(&qede_pci_driver);
278 if (ret) {
279 pr_notice("Failed to register driver\n");
280 unregister_netdevice_notifier(&qede_netdev_notifier);
281 qed_put_eth_ops();
282 return -EINVAL;
283 }
284
285 return 0;
286}
287
288static void __exit qede_cleanup(void)
289{
290 if (debug & QED_LOG_INFO_MASK)
291 pr_info("qede_cleanup called\n");
292
293 unregister_netdevice_notifier(&qede_netdev_notifier);
294 pci_unregister_driver(&qede_pci_driver);
295 qed_put_eth_ops();
296}
297
298module_init(qede_init);
299module_exit(qede_cleanup);
300
301static int qede_open(struct net_device *ndev);
302static int qede_close(struct net_device *ndev);
303
304void qede_fill_by_demand_stats(struct qede_dev *edev)
305{
306 struct qede_stats_common *p_common = &edev->stats.common;
307 struct qed_eth_stats stats;
308
309 edev->ops->get_vport_stats(edev->cdev, &stats);
310
311 p_common->no_buff_discards = stats.common.no_buff_discards;
312 p_common->packet_too_big_discard = stats.common.packet_too_big_discard;
313 p_common->ttl0_discard = stats.common.ttl0_discard;
314 p_common->rx_ucast_bytes = stats.common.rx_ucast_bytes;
315 p_common->rx_mcast_bytes = stats.common.rx_mcast_bytes;
316 p_common->rx_bcast_bytes = stats.common.rx_bcast_bytes;
317 p_common->rx_ucast_pkts = stats.common.rx_ucast_pkts;
318 p_common->rx_mcast_pkts = stats.common.rx_mcast_pkts;
319 p_common->rx_bcast_pkts = stats.common.rx_bcast_pkts;
320 p_common->mftag_filter_discards = stats.common.mftag_filter_discards;
321 p_common->mac_filter_discards = stats.common.mac_filter_discards;
322 p_common->gft_filter_drop = stats.common.gft_filter_drop;
323
324 p_common->tx_ucast_bytes = stats.common.tx_ucast_bytes;
325 p_common->tx_mcast_bytes = stats.common.tx_mcast_bytes;
326 p_common->tx_bcast_bytes = stats.common.tx_bcast_bytes;
327 p_common->tx_ucast_pkts = stats.common.tx_ucast_pkts;
328 p_common->tx_mcast_pkts = stats.common.tx_mcast_pkts;
329 p_common->tx_bcast_pkts = stats.common.tx_bcast_pkts;
330 p_common->tx_err_drop_pkts = stats.common.tx_err_drop_pkts;
331 p_common->coalesced_pkts = stats.common.tpa_coalesced_pkts;
332 p_common->coalesced_events = stats.common.tpa_coalesced_events;
333 p_common->coalesced_aborts_num = stats.common.tpa_aborts_num;
334 p_common->non_coalesced_pkts = stats.common.tpa_not_coalesced_pkts;
335 p_common->coalesced_bytes = stats.common.tpa_coalesced_bytes;
336
337 p_common->rx_64_byte_packets = stats.common.rx_64_byte_packets;
338 p_common->rx_65_to_127_byte_packets =
339 stats.common.rx_65_to_127_byte_packets;
340 p_common->rx_128_to_255_byte_packets =
341 stats.common.rx_128_to_255_byte_packets;
342 p_common->rx_256_to_511_byte_packets =
343 stats.common.rx_256_to_511_byte_packets;
344 p_common->rx_512_to_1023_byte_packets =
345 stats.common.rx_512_to_1023_byte_packets;
346 p_common->rx_1024_to_1518_byte_packets =
347 stats.common.rx_1024_to_1518_byte_packets;
348 p_common->rx_crc_errors = stats.common.rx_crc_errors;
349 p_common->rx_mac_crtl_frames = stats.common.rx_mac_crtl_frames;
350 p_common->rx_pause_frames = stats.common.rx_pause_frames;
351 p_common->rx_pfc_frames = stats.common.rx_pfc_frames;
352 p_common->rx_align_errors = stats.common.rx_align_errors;
353 p_common->rx_carrier_errors = stats.common.rx_carrier_errors;
354 p_common->rx_oversize_packets = stats.common.rx_oversize_packets;
355 p_common->rx_jabbers = stats.common.rx_jabbers;
356 p_common->rx_undersize_packets = stats.common.rx_undersize_packets;
357 p_common->rx_fragments = stats.common.rx_fragments;
358 p_common->tx_64_byte_packets = stats.common.tx_64_byte_packets;
359 p_common->tx_65_to_127_byte_packets =
360 stats.common.tx_65_to_127_byte_packets;
361 p_common->tx_128_to_255_byte_packets =
362 stats.common.tx_128_to_255_byte_packets;
363 p_common->tx_256_to_511_byte_packets =
364 stats.common.tx_256_to_511_byte_packets;
365 p_common->tx_512_to_1023_byte_packets =
366 stats.common.tx_512_to_1023_byte_packets;
367 p_common->tx_1024_to_1518_byte_packets =
368 stats.common.tx_1024_to_1518_byte_packets;
369 p_common->tx_pause_frames = stats.common.tx_pause_frames;
370 p_common->tx_pfc_frames = stats.common.tx_pfc_frames;
371 p_common->brb_truncates = stats.common.brb_truncates;
372 p_common->brb_discards = stats.common.brb_discards;
373 p_common->tx_mac_ctrl_frames = stats.common.tx_mac_ctrl_frames;
374 p_common->link_change_count = stats.common.link_change_count;
375 p_common->ptp_skip_txts = edev->ptp_skip_txts;
376
377 if (QEDE_IS_BB(edev)) {
378 struct qede_stats_bb *p_bb = &edev->stats.bb;
379
380 p_bb->rx_1519_to_1522_byte_packets =
381 stats.bb.rx_1519_to_1522_byte_packets;
382 p_bb->rx_1519_to_2047_byte_packets =
383 stats.bb.rx_1519_to_2047_byte_packets;
384 p_bb->rx_2048_to_4095_byte_packets =
385 stats.bb.rx_2048_to_4095_byte_packets;
386 p_bb->rx_4096_to_9216_byte_packets =
387 stats.bb.rx_4096_to_9216_byte_packets;
388 p_bb->rx_9217_to_16383_byte_packets =
389 stats.bb.rx_9217_to_16383_byte_packets;
390 p_bb->tx_1519_to_2047_byte_packets =
391 stats.bb.tx_1519_to_2047_byte_packets;
392 p_bb->tx_2048_to_4095_byte_packets =
393 stats.bb.tx_2048_to_4095_byte_packets;
394 p_bb->tx_4096_to_9216_byte_packets =
395 stats.bb.tx_4096_to_9216_byte_packets;
396 p_bb->tx_9217_to_16383_byte_packets =
397 stats.bb.tx_9217_to_16383_byte_packets;
398 p_bb->tx_lpi_entry_count = stats.bb.tx_lpi_entry_count;
399 p_bb->tx_total_collisions = stats.bb.tx_total_collisions;
400 } else {
401 struct qede_stats_ah *p_ah = &edev->stats.ah;
402
403 p_ah->rx_1519_to_max_byte_packets =
404 stats.ah.rx_1519_to_max_byte_packets;
405 p_ah->tx_1519_to_max_byte_packets =
406 stats.ah.tx_1519_to_max_byte_packets;
407 }
408}
409
410static void qede_get_stats64(struct net_device *dev,
411 struct rtnl_link_stats64 *stats)
412{
413 struct qede_dev *edev = netdev_priv(dev);
414 struct qede_stats_common *p_common;
415
416 qede_fill_by_demand_stats(edev);
417 p_common = &edev->stats.common;
418
419 stats->rx_packets = p_common->rx_ucast_pkts + p_common->rx_mcast_pkts +
420 p_common->rx_bcast_pkts;
421 stats->tx_packets = p_common->tx_ucast_pkts + p_common->tx_mcast_pkts +
422 p_common->tx_bcast_pkts;
423
424 stats->rx_bytes = p_common->rx_ucast_bytes + p_common->rx_mcast_bytes +
425 p_common->rx_bcast_bytes;
426 stats->tx_bytes = p_common->tx_ucast_bytes + p_common->tx_mcast_bytes +
427 p_common->tx_bcast_bytes;
428
429 stats->tx_errors = p_common->tx_err_drop_pkts;
430 stats->multicast = p_common->rx_mcast_pkts + p_common->rx_bcast_pkts;
431
432 stats->rx_fifo_errors = p_common->no_buff_discards;
433
434 if (QEDE_IS_BB(edev))
435 stats->collisions = edev->stats.bb.tx_total_collisions;
436 stats->rx_crc_errors = p_common->rx_crc_errors;
437 stats->rx_frame_errors = p_common->rx_align_errors;
438}
439
440#ifdef CONFIG_QED_SRIOV
441static int qede_get_vf_config(struct net_device *dev, int vfidx,
442 struct ifla_vf_info *ivi)
443{
444 struct qede_dev *edev = netdev_priv(dev);
445
446 if (!edev->ops)
447 return -EINVAL;
448
449 return edev->ops->iov->get_config(edev->cdev, vfidx, ivi);
450}
451
452static int qede_set_vf_rate(struct net_device *dev, int vfidx,
453 int min_tx_rate, int max_tx_rate)
454{
455 struct qede_dev *edev = netdev_priv(dev);
456
457 return edev->ops->iov->set_rate(edev->cdev, vfidx, min_tx_rate,
458 max_tx_rate);
459}
460
461static int qede_set_vf_spoofchk(struct net_device *dev, int vfidx, bool val)
462{
463 struct qede_dev *edev = netdev_priv(dev);
464
465 if (!edev->ops)
466 return -EINVAL;
467
468 return edev->ops->iov->set_spoof(edev->cdev, vfidx, val);
469}
470
471static int qede_set_vf_link_state(struct net_device *dev, int vfidx,
472 int link_state)
473{
474 struct qede_dev *edev = netdev_priv(dev);
475
476 if (!edev->ops)
477 return -EINVAL;
478
479 return edev->ops->iov->set_link_state(edev->cdev, vfidx, link_state);
480}
481
482static int qede_set_vf_trust(struct net_device *dev, int vfidx, bool setting)
483{
484 struct qede_dev *edev = netdev_priv(dev);
485
486 if (!edev->ops)
487 return -EINVAL;
488
489 return edev->ops->iov->set_trust(edev->cdev, vfidx, setting);
490}
491#endif
492
493static int qede_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
494{
495 struct qede_dev *edev = netdev_priv(dev);
496
497 if (!netif_running(dev))
498 return -EAGAIN;
499
500 switch (cmd) {
501 case SIOCSHWTSTAMP:
502 return qede_ptp_hw_ts(edev, ifr);
503 default:
504 DP_VERBOSE(edev, QED_MSG_DEBUG,
505 "default IOCTL cmd 0x%x\n", cmd);
506 return -EOPNOTSUPP;
507 }
508
509 return 0;
510}
511
512static void qede_tx_log_print(struct qede_dev *edev, struct qede_tx_queue *txq)
513{
514 DP_NOTICE(edev,
515 "Txq[%d]: FW cons [host] %04x, SW cons %04x, SW prod %04x [Jiffies %lu]\n",
516 txq->index, le16_to_cpu(*txq->hw_cons_ptr),
517 qed_chain_get_cons_idx(&txq->tx_pbl),
518 qed_chain_get_prod_idx(&txq->tx_pbl),
519 jiffies);
520}
521
522static void qede_tx_timeout(struct net_device *dev, unsigned int txqueue)
523{
524 struct qede_dev *edev = netdev_priv(dev);
525 struct qede_tx_queue *txq;
526 int cos;
527
528 netif_carrier_off(dev);
529 DP_NOTICE(edev, "TX timeout on queue %u!\n", txqueue);
530
531 if (!(edev->fp_array[txqueue].type & QEDE_FASTPATH_TX))
532 return;
533
534 for_each_cos_in_txq(edev, cos) {
535 txq = &edev->fp_array[txqueue].txq[cos];
536
537 if (qed_chain_get_cons_idx(&txq->tx_pbl) !=
538 qed_chain_get_prod_idx(&txq->tx_pbl))
539 qede_tx_log_print(edev, txq);
540 }
541
542 if (IS_VF(edev))
543 return;
544
545 if (test_and_set_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags) ||
546 edev->state == QEDE_STATE_RECOVERY) {
547 DP_INFO(edev,
548 "Avoid handling a Tx timeout while another HW error is being handled\n");
549 return;
550 }
551
552 set_bit(QEDE_ERR_GET_DBG_INFO, &edev->err_flags);
553 set_bit(QEDE_SP_HW_ERR, &edev->sp_flags);
554 schedule_delayed_work(&edev->sp_task, 0);
555}
556
557static int qede_setup_tc(struct net_device *ndev, u8 num_tc)
558{
559 struct qede_dev *edev = netdev_priv(ndev);
560 int cos, count, offset;
561
562 if (num_tc > edev->dev_info.num_tc)
563 return -EINVAL;
564
565 netdev_reset_tc(ndev);
566 netdev_set_num_tc(ndev, num_tc);
567
568 for_each_cos_in_txq(edev, cos) {
569 count = QEDE_TSS_COUNT(edev);
570 offset = cos * QEDE_TSS_COUNT(edev);
571 netdev_set_tc_queue(ndev, cos, count, offset);
572 }
573
574 return 0;
575}
576
577static int
578qede_set_flower(struct qede_dev *edev, struct flow_cls_offload *f,
579 __be16 proto)
580{
581 switch (f->command) {
582 case FLOW_CLS_REPLACE:
583 return qede_add_tc_flower_fltr(edev, proto, f);
584 case FLOW_CLS_DESTROY:
585 return qede_delete_flow_filter(edev, f->cookie);
586 default:
587 return -EOPNOTSUPP;
588 }
589}
590
591static int qede_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
592 void *cb_priv)
593{
594 struct flow_cls_offload *f;
595 struct qede_dev *edev = cb_priv;
596
597 if (!tc_cls_can_offload_and_chain0(edev->ndev, type_data))
598 return -EOPNOTSUPP;
599
600 switch (type) {
601 case TC_SETUP_CLSFLOWER:
602 f = type_data;
603 return qede_set_flower(edev, f, f->common.protocol);
604 default:
605 return -EOPNOTSUPP;
606 }
607}
608
609static LIST_HEAD(qede_block_cb_list);
610
611static int
612qede_setup_tc_offload(struct net_device *dev, enum tc_setup_type type,
613 void *type_data)
614{
615 struct qede_dev *edev = netdev_priv(dev);
616 struct tc_mqprio_qopt *mqprio;
617
618 switch (type) {
619 case TC_SETUP_BLOCK:
620 return flow_block_cb_setup_simple(type_data,
621 &qede_block_cb_list,
622 qede_setup_tc_block_cb,
623 edev, edev, true);
624 case TC_SETUP_QDISC_MQPRIO:
625 mqprio = type_data;
626
627 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
628 return qede_setup_tc(dev, mqprio->num_tc);
629 default:
630 return -EOPNOTSUPP;
631 }
632}
633
634static const struct net_device_ops qede_netdev_ops = {
635 .ndo_open = qede_open,
636 .ndo_stop = qede_close,
637 .ndo_start_xmit = qede_start_xmit,
638 .ndo_select_queue = qede_select_queue,
639 .ndo_set_rx_mode = qede_set_rx_mode,
640 .ndo_set_mac_address = qede_set_mac_addr,
641 .ndo_validate_addr = eth_validate_addr,
642 .ndo_change_mtu = qede_change_mtu,
643 .ndo_eth_ioctl = qede_ioctl,
644 .ndo_tx_timeout = qede_tx_timeout,
645#ifdef CONFIG_QED_SRIOV
646 .ndo_set_vf_mac = qede_set_vf_mac,
647 .ndo_set_vf_vlan = qede_set_vf_vlan,
648 .ndo_set_vf_trust = qede_set_vf_trust,
649#endif
650 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
651 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
652 .ndo_fix_features = qede_fix_features,
653 .ndo_set_features = qede_set_features,
654 .ndo_get_stats64 = qede_get_stats64,
655#ifdef CONFIG_QED_SRIOV
656 .ndo_set_vf_link_state = qede_set_vf_link_state,
657 .ndo_set_vf_spoofchk = qede_set_vf_spoofchk,
658 .ndo_get_vf_config = qede_get_vf_config,
659 .ndo_set_vf_rate = qede_set_vf_rate,
660#endif
661 .ndo_features_check = qede_features_check,
662 .ndo_bpf = qede_xdp,
663#ifdef CONFIG_RFS_ACCEL
664 .ndo_rx_flow_steer = qede_rx_flow_steer,
665#endif
666 .ndo_xdp_xmit = qede_xdp_transmit,
667 .ndo_setup_tc = qede_setup_tc_offload,
668};
669
670static const struct net_device_ops qede_netdev_vf_ops = {
671 .ndo_open = qede_open,
672 .ndo_stop = qede_close,
673 .ndo_start_xmit = qede_start_xmit,
674 .ndo_select_queue = qede_select_queue,
675 .ndo_set_rx_mode = qede_set_rx_mode,
676 .ndo_set_mac_address = qede_set_mac_addr,
677 .ndo_validate_addr = eth_validate_addr,
678 .ndo_change_mtu = qede_change_mtu,
679 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
680 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
681 .ndo_fix_features = qede_fix_features,
682 .ndo_set_features = qede_set_features,
683 .ndo_get_stats64 = qede_get_stats64,
684 .ndo_features_check = qede_features_check,
685};
686
687static const struct net_device_ops qede_netdev_vf_xdp_ops = {
688 .ndo_open = qede_open,
689 .ndo_stop = qede_close,
690 .ndo_start_xmit = qede_start_xmit,
691 .ndo_select_queue = qede_select_queue,
692 .ndo_set_rx_mode = qede_set_rx_mode,
693 .ndo_set_mac_address = qede_set_mac_addr,
694 .ndo_validate_addr = eth_validate_addr,
695 .ndo_change_mtu = qede_change_mtu,
696 .ndo_vlan_rx_add_vid = qede_vlan_rx_add_vid,
697 .ndo_vlan_rx_kill_vid = qede_vlan_rx_kill_vid,
698 .ndo_fix_features = qede_fix_features,
699 .ndo_set_features = qede_set_features,
700 .ndo_get_stats64 = qede_get_stats64,
701 .ndo_features_check = qede_features_check,
702 .ndo_bpf = qede_xdp,
703 .ndo_xdp_xmit = qede_xdp_transmit,
704};
705
706
707
708
709
710
711static struct qede_dev *qede_alloc_etherdev(struct qed_dev *cdev,
712 struct pci_dev *pdev,
713 struct qed_dev_eth_info *info,
714 u32 dp_module, u8 dp_level)
715{
716 struct net_device *ndev;
717 struct qede_dev *edev;
718
719 ndev = alloc_etherdev_mqs(sizeof(*edev),
720 info->num_queues * info->num_tc,
721 info->num_queues);
722 if (!ndev) {
723 pr_err("etherdev allocation failed\n");
724 return NULL;
725 }
726
727 edev = netdev_priv(ndev);
728 edev->ndev = ndev;
729 edev->cdev = cdev;
730 edev->pdev = pdev;
731 edev->dp_module = dp_module;
732 edev->dp_level = dp_level;
733 edev->ops = qed_ops;
734
735 if (is_kdump_kernel()) {
736 edev->q_num_rx_buffers = NUM_RX_BDS_KDUMP_MIN;
737 edev->q_num_tx_buffers = NUM_TX_BDS_KDUMP_MIN;
738 } else {
739 edev->q_num_rx_buffers = NUM_RX_BDS_DEF;
740 edev->q_num_tx_buffers = NUM_TX_BDS_DEF;
741 }
742
743 DP_INFO(edev, "Allocated netdev with %d tx queues and %d rx queues\n",
744 info->num_queues, info->num_queues);
745
746 SET_NETDEV_DEV(ndev, &pdev->dev);
747
748 memset(&edev->stats, 0, sizeof(edev->stats));
749 memcpy(&edev->dev_info, info, sizeof(*info));
750
751
752
753
754 if (edev->dev_info.common.wol_support)
755 edev->wol_enabled = true;
756
757 INIT_LIST_HEAD(&edev->vlan_list);
758
759 return edev;
760}
761
762static void qede_init_ndev(struct qede_dev *edev)
763{
764 struct net_device *ndev = edev->ndev;
765 struct pci_dev *pdev = edev->pdev;
766 bool udp_tunnel_enable = false;
767 netdev_features_t hw_features;
768
769 pci_set_drvdata(pdev, ndev);
770
771 ndev->mem_start = edev->dev_info.common.pci_mem_start;
772 ndev->base_addr = ndev->mem_start;
773 ndev->mem_end = edev->dev_info.common.pci_mem_end;
774 ndev->irq = edev->dev_info.common.pci_irq;
775
776 ndev->watchdog_timeo = TX_TIMEOUT;
777
778 if (IS_VF(edev)) {
779 if (edev->dev_info.xdp_supported)
780 ndev->netdev_ops = &qede_netdev_vf_xdp_ops;
781 else
782 ndev->netdev_ops = &qede_netdev_vf_ops;
783 } else {
784 ndev->netdev_ops = &qede_netdev_ops;
785 }
786
787 qede_set_ethtool_ops(ndev);
788
789 ndev->priv_flags |= IFF_UNICAST_FLT;
790
791
792 hw_features = NETIF_F_GRO | NETIF_F_GRO_HW | NETIF_F_SG |
793 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
794 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_TC;
795
796 if (edev->dev_info.common.b_arfs_capable)
797 hw_features |= NETIF_F_NTUPLE;
798
799 if (edev->dev_info.common.vxlan_enable ||
800 edev->dev_info.common.geneve_enable)
801 udp_tunnel_enable = true;
802
803 if (udp_tunnel_enable || edev->dev_info.common.gre_enable) {
804 hw_features |= NETIF_F_TSO_ECN;
805 ndev->hw_enc_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
806 NETIF_F_SG | NETIF_F_TSO |
807 NETIF_F_TSO_ECN | NETIF_F_TSO6 |
808 NETIF_F_RXCSUM;
809 }
810
811 if (udp_tunnel_enable) {
812 hw_features |= (NETIF_F_GSO_UDP_TUNNEL |
813 NETIF_F_GSO_UDP_TUNNEL_CSUM);
814 ndev->hw_enc_features |= (NETIF_F_GSO_UDP_TUNNEL |
815 NETIF_F_GSO_UDP_TUNNEL_CSUM);
816
817 qede_set_udp_tunnels(edev);
818 }
819
820 if (edev->dev_info.common.gre_enable) {
821 hw_features |= (NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM);
822 ndev->hw_enc_features |= (NETIF_F_GSO_GRE |
823 NETIF_F_GSO_GRE_CSUM);
824 }
825
826 ndev->vlan_features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
827 NETIF_F_HIGHDMA;
828 ndev->features = hw_features | NETIF_F_RXHASH | NETIF_F_RXCSUM |
829 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HIGHDMA |
830 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_TX;
831
832 ndev->hw_features = hw_features;
833
834
835 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
836 ndev->max_mtu = QEDE_MAX_JUMBO_PACKET_SIZE;
837
838
839 ether_addr_copy(edev->ndev->dev_addr, edev->dev_info.common.hw_mac);
840
841 ndev->mtu = edev->dev_info.common.mtu;
842}
843
844
845
846
847
848
849
850
851
852
853
854
855void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level)
856{
857 *p_dp_level = QED_LEVEL_NOTICE;
858 *p_dp_module = 0;
859
860 if (debug & QED_LOG_VERBOSE_MASK) {
861 *p_dp_level = QED_LEVEL_VERBOSE;
862 *p_dp_module = (debug & 0x3FFFFFFF);
863 } else if (debug & QED_LOG_INFO_MASK) {
864 *p_dp_level = QED_LEVEL_INFO;
865 } else if (debug & QED_LOG_NOTICE_MASK) {
866 *p_dp_level = QED_LEVEL_NOTICE;
867 }
868}
869
870static void qede_free_fp_array(struct qede_dev *edev)
871{
872 if (edev->fp_array) {
873 struct qede_fastpath *fp;
874 int i;
875
876 for_each_queue(i) {
877 fp = &edev->fp_array[i];
878
879 kfree(fp->sb_info);
880
881
882
883
884 if (fp->rxq && xdp_rxq_info_is_reg(&fp->rxq->xdp_rxq))
885 xdp_rxq_info_unreg(&fp->rxq->xdp_rxq);
886 kfree(fp->rxq);
887 kfree(fp->xdp_tx);
888 kfree(fp->txq);
889 }
890 kfree(edev->fp_array);
891 }
892
893 edev->num_queues = 0;
894 edev->fp_num_tx = 0;
895 edev->fp_num_rx = 0;
896}
897
898static int qede_alloc_fp_array(struct qede_dev *edev)
899{
900 u8 fp_combined, fp_rx = edev->fp_num_rx;
901 struct qede_fastpath *fp;
902 void *mem;
903 int i;
904
905 edev->fp_array = kcalloc(QEDE_QUEUE_CNT(edev),
906 sizeof(*edev->fp_array), GFP_KERNEL);
907 if (!edev->fp_array) {
908 DP_NOTICE(edev, "fp array allocation failed\n");
909 goto err;
910 }
911
912 mem = krealloc(edev->coal_entry, QEDE_QUEUE_CNT(edev) *
913 sizeof(*edev->coal_entry), GFP_KERNEL);
914 if (!mem) {
915 DP_ERR(edev, "coalesce entry allocation failed\n");
916 kfree(edev->coal_entry);
917 goto err;
918 }
919 edev->coal_entry = mem;
920
921 fp_combined = QEDE_QUEUE_CNT(edev) - fp_rx - edev->fp_num_tx;
922
923
924
925
926
927
928 for_each_queue(i) {
929 fp = &edev->fp_array[i];
930
931 fp->sb_info = kzalloc(sizeof(*fp->sb_info), GFP_KERNEL);
932 if (!fp->sb_info) {
933 DP_NOTICE(edev, "sb info struct allocation failed\n");
934 goto err;
935 }
936
937 if (fp_rx) {
938 fp->type = QEDE_FASTPATH_RX;
939 fp_rx--;
940 } else if (fp_combined) {
941 fp->type = QEDE_FASTPATH_COMBINED;
942 fp_combined--;
943 } else {
944 fp->type = QEDE_FASTPATH_TX;
945 }
946
947 if (fp->type & QEDE_FASTPATH_TX) {
948 fp->txq = kcalloc(edev->dev_info.num_tc,
949 sizeof(*fp->txq), GFP_KERNEL);
950 if (!fp->txq)
951 goto err;
952 }
953
954 if (fp->type & QEDE_FASTPATH_RX) {
955 fp->rxq = kzalloc(sizeof(*fp->rxq), GFP_KERNEL);
956 if (!fp->rxq)
957 goto err;
958
959 if (edev->xdp_prog) {
960 fp->xdp_tx = kzalloc(sizeof(*fp->xdp_tx),
961 GFP_KERNEL);
962 if (!fp->xdp_tx)
963 goto err;
964 fp->type |= QEDE_FASTPATH_XDP;
965 }
966 }
967 }
968
969 return 0;
970err:
971 qede_free_fp_array(edev);
972 return -ENOMEM;
973}
974
975
976
977
978void __qede_lock(struct qede_dev *edev)
979{
980 mutex_lock(&edev->qede_lock);
981}
982
983void __qede_unlock(struct qede_dev *edev)
984{
985 mutex_unlock(&edev->qede_lock);
986}
987
988
989
990
991static void qede_lock(struct qede_dev *edev)
992{
993 rtnl_lock();
994 __qede_lock(edev);
995}
996
997static void qede_unlock(struct qede_dev *edev)
998{
999 __qede_unlock(edev);
1000 rtnl_unlock();
1001}
1002
1003static void qede_sp_task(struct work_struct *work)
1004{
1005 struct qede_dev *edev = container_of(work, struct qede_dev,
1006 sp_task.work);
1007
1008
1009
1010
1011
1012 if (test_bit(QEDE_SP_DISABLE, &edev->sp_flags))
1013 return;
1014
1015
1016
1017
1018
1019
1020
1021 if (test_and_clear_bit(QEDE_SP_RECOVERY, &edev->sp_flags)) {
1022#ifdef CONFIG_QED_SRIOV
1023
1024
1025
1026 if (pci_num_vf(edev->pdev))
1027 qede_sriov_configure(edev->pdev, 0);
1028#endif
1029 qede_lock(edev);
1030 qede_recovery_handler(edev);
1031 qede_unlock(edev);
1032 }
1033
1034 __qede_lock(edev);
1035
1036 if (test_and_clear_bit(QEDE_SP_RX_MODE, &edev->sp_flags))
1037 if (edev->state == QEDE_STATE_OPEN)
1038 qede_config_rx_mode(edev->ndev);
1039
1040#ifdef CONFIG_RFS_ACCEL
1041 if (test_and_clear_bit(QEDE_SP_ARFS_CONFIG, &edev->sp_flags)) {
1042 if (edev->state == QEDE_STATE_OPEN)
1043 qede_process_arfs_filters(edev, false);
1044 }
1045#endif
1046 if (test_and_clear_bit(QEDE_SP_HW_ERR, &edev->sp_flags))
1047 qede_generic_hw_err_handler(edev);
1048 __qede_unlock(edev);
1049
1050 if (test_and_clear_bit(QEDE_SP_AER, &edev->sp_flags)) {
1051#ifdef CONFIG_QED_SRIOV
1052
1053
1054
1055 if (pci_num_vf(edev->pdev))
1056 qede_sriov_configure(edev->pdev, 0);
1057#endif
1058 edev->ops->common->recovery_process(edev->cdev);
1059 }
1060}
1061
1062static void qede_update_pf_params(struct qed_dev *cdev)
1063{
1064 struct qed_pf_params pf_params;
1065 u16 num_cons;
1066
1067
1068 memset(&pf_params, 0, sizeof(struct qed_pf_params));
1069
1070
1071 num_cons = QED_MIN_L2_CONS;
1072
1073 pf_params.eth_pf_params.num_cons = (MAX_SB_PER_PF_MIMD - 1) * num_cons;
1074
1075
1076
1077
1078 pf_params.eth_pf_params.num_vf_cons = 48;
1079
1080 pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
1081 qed_ops->common->update_pf_params(cdev, &pf_params);
1082}
1083
1084#define QEDE_FW_VER_STR_SIZE 80
1085
1086static void qede_log_probe(struct qede_dev *edev)
1087{
1088 struct qed_dev_info *p_dev_info = &edev->dev_info.common;
1089 u8 buf[QEDE_FW_VER_STR_SIZE];
1090 size_t left_size;
1091
1092 snprintf(buf, QEDE_FW_VER_STR_SIZE,
1093 "Storm FW %d.%d.%d.%d, Management FW %d.%d.%d.%d",
1094 p_dev_info->fw_major, p_dev_info->fw_minor, p_dev_info->fw_rev,
1095 p_dev_info->fw_eng,
1096 (p_dev_info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
1097 QED_MFW_VERSION_3_OFFSET,
1098 (p_dev_info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
1099 QED_MFW_VERSION_2_OFFSET,
1100 (p_dev_info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
1101 QED_MFW_VERSION_1_OFFSET,
1102 (p_dev_info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
1103 QED_MFW_VERSION_0_OFFSET);
1104
1105 left_size = QEDE_FW_VER_STR_SIZE - strlen(buf);
1106 if (p_dev_info->mbi_version && left_size)
1107 snprintf(buf + strlen(buf), left_size,
1108 " [MBI %d.%d.%d]",
1109 (p_dev_info->mbi_version & QED_MBI_VERSION_2_MASK) >>
1110 QED_MBI_VERSION_2_OFFSET,
1111 (p_dev_info->mbi_version & QED_MBI_VERSION_1_MASK) >>
1112 QED_MBI_VERSION_1_OFFSET,
1113 (p_dev_info->mbi_version & QED_MBI_VERSION_0_MASK) >>
1114 QED_MBI_VERSION_0_OFFSET);
1115
1116 pr_info("qede %02x:%02x.%02x: %s [%s]\n", edev->pdev->bus->number,
1117 PCI_SLOT(edev->pdev->devfn), PCI_FUNC(edev->pdev->devfn),
1118 buf, edev->ndev->name);
1119}
1120
1121enum qede_probe_mode {
1122 QEDE_PROBE_NORMAL,
1123 QEDE_PROBE_RECOVERY,
1124};
1125
1126static int __qede_probe(struct pci_dev *pdev, u32 dp_module, u8 dp_level,
1127 bool is_vf, enum qede_probe_mode mode)
1128{
1129 struct qed_probe_params probe_params;
1130 struct qed_slowpath_params sp_params;
1131 struct qed_dev_eth_info dev_info;
1132 struct qede_dev *edev;
1133 struct qed_dev *cdev;
1134 int rc;
1135
1136 if (unlikely(dp_level & QED_LEVEL_INFO))
1137 pr_notice("Starting qede probe\n");
1138
1139 memset(&probe_params, 0, sizeof(probe_params));
1140 probe_params.protocol = QED_PROTOCOL_ETH;
1141 probe_params.dp_module = dp_module;
1142 probe_params.dp_level = dp_level;
1143 probe_params.is_vf = is_vf;
1144 probe_params.recov_in_prog = (mode == QEDE_PROBE_RECOVERY);
1145 cdev = qed_ops->common->probe(pdev, &probe_params);
1146 if (!cdev) {
1147 rc = -ENODEV;
1148 goto err0;
1149 }
1150
1151 qede_update_pf_params(cdev);
1152
1153
1154 memset(&sp_params, 0, sizeof(sp_params));
1155 sp_params.int_mode = QED_INT_MODE_MSIX;
1156 strlcpy(sp_params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
1157 rc = qed_ops->common->slowpath_start(cdev, &sp_params);
1158 if (rc) {
1159 pr_notice("Cannot start slowpath\n");
1160 goto err1;
1161 }
1162
1163
1164 rc = qed_ops->fill_dev_info(cdev, &dev_info);
1165 if (rc)
1166 goto err2;
1167
1168 if (mode != QEDE_PROBE_RECOVERY) {
1169 edev = qede_alloc_etherdev(cdev, pdev, &dev_info, dp_module,
1170 dp_level);
1171 if (!edev) {
1172 rc = -ENOMEM;
1173 goto err2;
1174 }
1175
1176 edev->devlink = qed_ops->common->devlink_register(cdev);
1177 if (IS_ERR(edev->devlink)) {
1178 DP_NOTICE(edev, "Cannot register devlink\n");
1179 edev->devlink = NULL;
1180
1181 }
1182 } else {
1183 struct net_device *ndev = pci_get_drvdata(pdev);
1184
1185 edev = netdev_priv(ndev);
1186
1187 if (edev->devlink) {
1188 struct qed_devlink *qdl = devlink_priv(edev->devlink);
1189
1190 qdl->cdev = cdev;
1191 }
1192 edev->cdev = cdev;
1193 memset(&edev->stats, 0, sizeof(edev->stats));
1194 memcpy(&edev->dev_info, &dev_info, sizeof(dev_info));
1195 }
1196
1197 if (is_vf)
1198 set_bit(QEDE_FLAGS_IS_VF, &edev->flags);
1199
1200 qede_init_ndev(edev);
1201
1202 rc = qede_rdma_dev_add(edev, (mode == QEDE_PROBE_RECOVERY));
1203 if (rc)
1204 goto err3;
1205
1206 if (mode != QEDE_PROBE_RECOVERY) {
1207
1208
1209
1210
1211
1212 INIT_DELAYED_WORK(&edev->sp_task, qede_sp_task);
1213 mutex_init(&edev->qede_lock);
1214
1215 rc = register_netdev(edev->ndev);
1216 if (rc) {
1217 DP_NOTICE(edev, "Cannot register net-device\n");
1218 goto err4;
1219 }
1220 }
1221
1222 edev->ops->common->set_name(cdev, edev->ndev->name);
1223
1224
1225 if (!is_vf)
1226 qede_ptp_enable(edev);
1227
1228 edev->ops->register_ops(cdev, &qede_ll_ops, edev);
1229
1230#ifdef CONFIG_DCB
1231 if (!IS_VF(edev))
1232 qede_set_dcbnl_ops(edev->ndev);
1233#endif
1234
1235 edev->rx_copybreak = QEDE_RX_HDR_SIZE;
1236
1237 qede_log_probe(edev);
1238 return 0;
1239
1240err4:
1241 qede_rdma_dev_remove(edev, (mode == QEDE_PROBE_RECOVERY));
1242err3:
1243 if (mode != QEDE_PROBE_RECOVERY)
1244 free_netdev(edev->ndev);
1245 else
1246 edev->cdev = NULL;
1247err2:
1248 qed_ops->common->slowpath_stop(cdev);
1249err1:
1250 qed_ops->common->remove(cdev);
1251err0:
1252 return rc;
1253}
1254
1255static int qede_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1256{
1257 bool is_vf = false;
1258 u32 dp_module = 0;
1259 u8 dp_level = 0;
1260
1261 switch ((enum qede_pci_private)id->driver_data) {
1262 case QEDE_PRIVATE_VF:
1263 if (debug & QED_LOG_VERBOSE_MASK)
1264 dev_err(&pdev->dev, "Probing a VF\n");
1265 is_vf = true;
1266 break;
1267 default:
1268 if (debug & QED_LOG_VERBOSE_MASK)
1269 dev_err(&pdev->dev, "Probing a PF\n");
1270 }
1271
1272 qede_config_debug(debug, &dp_module, &dp_level);
1273
1274 return __qede_probe(pdev, dp_module, dp_level, is_vf,
1275 QEDE_PROBE_NORMAL);
1276}
1277
1278enum qede_remove_mode {
1279 QEDE_REMOVE_NORMAL,
1280 QEDE_REMOVE_RECOVERY,
1281};
1282
1283static void __qede_remove(struct pci_dev *pdev, enum qede_remove_mode mode)
1284{
1285 struct net_device *ndev = pci_get_drvdata(pdev);
1286 struct qede_dev *edev;
1287 struct qed_dev *cdev;
1288
1289 if (!ndev) {
1290 dev_info(&pdev->dev, "Device has already been removed\n");
1291 return;
1292 }
1293
1294 edev = netdev_priv(ndev);
1295 cdev = edev->cdev;
1296
1297 DP_INFO(edev, "Starting qede_remove\n");
1298
1299 qede_rdma_dev_remove(edev, (mode == QEDE_REMOVE_RECOVERY));
1300
1301 if (mode != QEDE_REMOVE_RECOVERY) {
1302 set_bit(QEDE_SP_DISABLE, &edev->sp_flags);
1303 unregister_netdev(ndev);
1304
1305 cancel_delayed_work_sync(&edev->sp_task);
1306
1307 edev->ops->common->set_power_state(cdev, PCI_D0);
1308
1309 pci_set_drvdata(pdev, NULL);
1310 }
1311
1312 qede_ptp_disable(edev);
1313
1314
1315 qed_ops->common->slowpath_stop(cdev);
1316 if (system_state == SYSTEM_POWER_OFF)
1317 return;
1318
1319 if (mode != QEDE_REMOVE_RECOVERY && edev->devlink) {
1320 qed_ops->common->devlink_unregister(edev->devlink);
1321 edev->devlink = NULL;
1322 }
1323 qed_ops->common->remove(cdev);
1324 edev->cdev = NULL;
1325
1326
1327
1328
1329
1330
1331
1332 if (mode != QEDE_REMOVE_RECOVERY) {
1333 kfree(edev->coal_entry);
1334 free_netdev(ndev);
1335 }
1336
1337 dev_info(&pdev->dev, "Ending qede_remove successfully\n");
1338}
1339
1340static void qede_remove(struct pci_dev *pdev)
1341{
1342 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
1343}
1344
1345static void qede_shutdown(struct pci_dev *pdev)
1346{
1347 __qede_remove(pdev, QEDE_REMOVE_NORMAL);
1348}
1349
1350
1351
1352
1353
1354
1355static int qede_set_num_queues(struct qede_dev *edev)
1356{
1357 int rc;
1358 u16 rss_num;
1359
1360
1361 if (edev->req_queues)
1362 rss_num = edev->req_queues;
1363 else
1364 rss_num = netif_get_num_default_rss_queues() *
1365 edev->dev_info.common.num_hwfns;
1366
1367 rss_num = min_t(u16, QEDE_MAX_RSS_CNT(edev), rss_num);
1368
1369 rc = edev->ops->common->set_fp_int(edev->cdev, rss_num);
1370 if (rc > 0) {
1371
1372 edev->num_queues = rc;
1373 DP_INFO(edev, "Managed %d [of %d] RSS queues\n",
1374 QEDE_QUEUE_CNT(edev), rss_num);
1375 rc = 0;
1376 }
1377
1378 edev->fp_num_tx = edev->req_num_tx;
1379 edev->fp_num_rx = edev->req_num_rx;
1380
1381 return rc;
1382}
1383
1384static void qede_free_mem_sb(struct qede_dev *edev, struct qed_sb_info *sb_info,
1385 u16 sb_id)
1386{
1387 if (sb_info->sb_virt) {
1388 edev->ops->common->sb_release(edev->cdev, sb_info, sb_id,
1389 QED_SB_TYPE_L2_QUEUE);
1390 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_info->sb_virt),
1391 (void *)sb_info->sb_virt, sb_info->sb_phys);
1392 memset(sb_info, 0, sizeof(*sb_info));
1393 }
1394}
1395
1396
1397static int qede_alloc_mem_sb(struct qede_dev *edev,
1398 struct qed_sb_info *sb_info, u16 sb_id)
1399{
1400 struct status_block_e4 *sb_virt;
1401 dma_addr_t sb_phys;
1402 int rc;
1403
1404 sb_virt = dma_alloc_coherent(&edev->pdev->dev,
1405 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
1406 if (!sb_virt) {
1407 DP_ERR(edev, "Status block allocation failed\n");
1408 return -ENOMEM;
1409 }
1410
1411 rc = edev->ops->common->sb_init(edev->cdev, sb_info,
1412 sb_virt, sb_phys, sb_id,
1413 QED_SB_TYPE_L2_QUEUE);
1414 if (rc) {
1415 DP_ERR(edev, "Status block initialization failed\n");
1416 dma_free_coherent(&edev->pdev->dev, sizeof(*sb_virt),
1417 sb_virt, sb_phys);
1418 return rc;
1419 }
1420
1421 return 0;
1422}
1423
1424static void qede_free_rx_buffers(struct qede_dev *edev,
1425 struct qede_rx_queue *rxq)
1426{
1427 u16 i;
1428
1429 for (i = rxq->sw_rx_cons; i != rxq->sw_rx_prod; i++) {
1430 struct sw_rx_data *rx_buf;
1431 struct page *data;
1432
1433 rx_buf = &rxq->sw_rx_ring[i & NUM_RX_BDS_MAX];
1434 data = rx_buf->data;
1435
1436 dma_unmap_page(&edev->pdev->dev,
1437 rx_buf->mapping, PAGE_SIZE, rxq->data_direction);
1438
1439 rx_buf->data = NULL;
1440 __free_page(data);
1441 }
1442}
1443
1444static void qede_free_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
1445{
1446
1447 qede_free_rx_buffers(edev, rxq);
1448
1449
1450 kfree(rxq->sw_rx_ring);
1451
1452
1453 edev->ops->common->chain_free(edev->cdev, &rxq->rx_bd_ring);
1454 edev->ops->common->chain_free(edev->cdev, &rxq->rx_comp_ring);
1455}
1456
1457static void qede_set_tpa_param(struct qede_rx_queue *rxq)
1458{
1459 int i;
1460
1461 for (i = 0; i < ETH_TPA_MAX_AGGS_NUM; i++) {
1462 struct qede_agg_info *tpa_info = &rxq->tpa_info[i];
1463
1464 tpa_info->state = QEDE_AGG_STATE_NONE;
1465 }
1466}
1467
1468
1469static int qede_alloc_mem_rxq(struct qede_dev *edev, struct qede_rx_queue *rxq)
1470{
1471 struct qed_chain_init_params params = {
1472 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
1473 .num_elems = RX_RING_SIZE,
1474 };
1475 struct qed_dev *cdev = edev->cdev;
1476 int i, rc, size;
1477
1478 rxq->num_rx_buffers = edev->q_num_rx_buffers;
1479
1480 rxq->rx_buf_size = NET_IP_ALIGN + ETH_OVERHEAD + edev->ndev->mtu;
1481
1482 rxq->rx_headroom = edev->xdp_prog ? XDP_PACKET_HEADROOM : NET_SKB_PAD;
1483 size = rxq->rx_headroom +
1484 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1485
1486
1487 if (rxq->rx_buf_size + size > PAGE_SIZE)
1488 rxq->rx_buf_size = PAGE_SIZE - size;
1489
1490
1491
1492
1493 if (!edev->xdp_prog) {
1494 size = size + rxq->rx_buf_size;
1495 rxq->rx_buf_seg_size = roundup_pow_of_two(size);
1496 } else {
1497 rxq->rx_buf_seg_size = PAGE_SIZE;
1498 edev->ndev->features &= ~NETIF_F_GRO_HW;
1499 }
1500
1501
1502 size = sizeof(*rxq->sw_rx_ring) * RX_RING_SIZE;
1503 rxq->sw_rx_ring = kzalloc(size, GFP_KERNEL);
1504 if (!rxq->sw_rx_ring) {
1505 DP_ERR(edev, "Rx buffers ring allocation failed\n");
1506 rc = -ENOMEM;
1507 goto err;
1508 }
1509
1510
1511 params.mode = QED_CHAIN_MODE_NEXT_PTR;
1512 params.intended_use = QED_CHAIN_USE_TO_CONSUME_PRODUCE;
1513 params.elem_size = sizeof(struct eth_rx_bd);
1514
1515 rc = edev->ops->common->chain_alloc(cdev, &rxq->rx_bd_ring, ¶ms);
1516 if (rc)
1517 goto err;
1518
1519
1520 params.mode = QED_CHAIN_MODE_PBL;
1521 params.intended_use = QED_CHAIN_USE_TO_CONSUME;
1522 params.elem_size = sizeof(union eth_rx_cqe);
1523
1524 rc = edev->ops->common->chain_alloc(cdev, &rxq->rx_comp_ring, ¶ms);
1525 if (rc)
1526 goto err;
1527
1528
1529 rxq->filled_buffers = 0;
1530 for (i = 0; i < rxq->num_rx_buffers; i++) {
1531 rc = qede_alloc_rx_buffer(rxq, false);
1532 if (rc) {
1533 DP_ERR(edev,
1534 "Rx buffers allocation failed at index %d\n", i);
1535 goto err;
1536 }
1537 }
1538
1539 edev->gro_disable = !(edev->ndev->features & NETIF_F_GRO_HW);
1540 if (!edev->gro_disable)
1541 qede_set_tpa_param(rxq);
1542err:
1543 return rc;
1544}
1545
1546static void qede_free_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
1547{
1548
1549 if (txq->is_xdp)
1550 kfree(txq->sw_tx_ring.xdp);
1551 else
1552 kfree(txq->sw_tx_ring.skbs);
1553
1554
1555 edev->ops->common->chain_free(edev->cdev, &txq->tx_pbl);
1556}
1557
1558
1559static int qede_alloc_mem_txq(struct qede_dev *edev, struct qede_tx_queue *txq)
1560{
1561 struct qed_chain_init_params params = {
1562 .mode = QED_CHAIN_MODE_PBL,
1563 .intended_use = QED_CHAIN_USE_TO_CONSUME_PRODUCE,
1564 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
1565 .num_elems = edev->q_num_tx_buffers,
1566 .elem_size = sizeof(union eth_tx_bd_types),
1567 };
1568 int size, rc;
1569
1570 txq->num_tx_buffers = edev->q_num_tx_buffers;
1571
1572
1573 if (txq->is_xdp) {
1574 size = sizeof(*txq->sw_tx_ring.xdp) * txq->num_tx_buffers;
1575 txq->sw_tx_ring.xdp = kzalloc(size, GFP_KERNEL);
1576 if (!txq->sw_tx_ring.xdp)
1577 goto err;
1578 } else {
1579 size = sizeof(*txq->sw_tx_ring.skbs) * txq->num_tx_buffers;
1580 txq->sw_tx_ring.skbs = kzalloc(size, GFP_KERNEL);
1581 if (!txq->sw_tx_ring.skbs)
1582 goto err;
1583 }
1584
1585 rc = edev->ops->common->chain_alloc(edev->cdev, &txq->tx_pbl, ¶ms);
1586 if (rc)
1587 goto err;
1588
1589 return 0;
1590
1591err:
1592 qede_free_mem_txq(edev, txq);
1593 return -ENOMEM;
1594}
1595
1596
1597static void qede_free_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
1598{
1599 qede_free_mem_sb(edev, fp->sb_info, fp->id);
1600
1601 if (fp->type & QEDE_FASTPATH_RX)
1602 qede_free_mem_rxq(edev, fp->rxq);
1603
1604 if (fp->type & QEDE_FASTPATH_XDP)
1605 qede_free_mem_txq(edev, fp->xdp_tx);
1606
1607 if (fp->type & QEDE_FASTPATH_TX) {
1608 int cos;
1609
1610 for_each_cos_in_txq(edev, cos)
1611 qede_free_mem_txq(edev, &fp->txq[cos]);
1612 }
1613}
1614
1615
1616
1617
1618static int qede_alloc_mem_fp(struct qede_dev *edev, struct qede_fastpath *fp)
1619{
1620 int rc = 0;
1621
1622 rc = qede_alloc_mem_sb(edev, fp->sb_info, fp->id);
1623 if (rc)
1624 goto out;
1625
1626 if (fp->type & QEDE_FASTPATH_RX) {
1627 rc = qede_alloc_mem_rxq(edev, fp->rxq);
1628 if (rc)
1629 goto out;
1630 }
1631
1632 if (fp->type & QEDE_FASTPATH_XDP) {
1633 rc = qede_alloc_mem_txq(edev, fp->xdp_tx);
1634 if (rc)
1635 goto out;
1636 }
1637
1638 if (fp->type & QEDE_FASTPATH_TX) {
1639 int cos;
1640
1641 for_each_cos_in_txq(edev, cos) {
1642 rc = qede_alloc_mem_txq(edev, &fp->txq[cos]);
1643 if (rc)
1644 goto out;
1645 }
1646 }
1647
1648out:
1649 return rc;
1650}
1651
1652static void qede_free_mem_load(struct qede_dev *edev)
1653{
1654 int i;
1655
1656 for_each_queue(i) {
1657 struct qede_fastpath *fp = &edev->fp_array[i];
1658
1659 qede_free_mem_fp(edev, fp);
1660 }
1661}
1662
1663
1664static int qede_alloc_mem_load(struct qede_dev *edev)
1665{
1666 int rc = 0, queue_id;
1667
1668 for (queue_id = 0; queue_id < QEDE_QUEUE_CNT(edev); queue_id++) {
1669 struct qede_fastpath *fp = &edev->fp_array[queue_id];
1670
1671 rc = qede_alloc_mem_fp(edev, fp);
1672 if (rc) {
1673 DP_ERR(edev,
1674 "Failed to allocate memory for fastpath - rss id = %d\n",
1675 queue_id);
1676 qede_free_mem_load(edev);
1677 return rc;
1678 }
1679 }
1680
1681 return 0;
1682}
1683
1684static void qede_empty_tx_queue(struct qede_dev *edev,
1685 struct qede_tx_queue *txq)
1686{
1687 unsigned int pkts_compl = 0, bytes_compl = 0;
1688 struct netdev_queue *netdev_txq;
1689 int rc, len = 0;
1690
1691 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->ndev_txq_id);
1692
1693 while (qed_chain_get_cons_idx(&txq->tx_pbl) !=
1694 qed_chain_get_prod_idx(&txq->tx_pbl)) {
1695 DP_VERBOSE(edev, NETIF_MSG_IFDOWN,
1696 "Freeing a packet on tx queue[%d]: chain_cons 0x%x, chain_prod 0x%x\n",
1697 txq->index, qed_chain_get_cons_idx(&txq->tx_pbl),
1698 qed_chain_get_prod_idx(&txq->tx_pbl));
1699
1700 rc = qede_free_tx_pkt(edev, txq, &len);
1701 if (rc) {
1702 DP_NOTICE(edev,
1703 "Failed to free a packet on tx queue[%d]: chain_cons 0x%x, chain_prod 0x%x\n",
1704 txq->index,
1705 qed_chain_get_cons_idx(&txq->tx_pbl),
1706 qed_chain_get_prod_idx(&txq->tx_pbl));
1707 break;
1708 }
1709
1710 bytes_compl += len;
1711 pkts_compl++;
1712 txq->sw_tx_cons++;
1713 }
1714
1715 netdev_tx_completed_queue(netdev_txq, pkts_compl, bytes_compl);
1716}
1717
1718static void qede_empty_tx_queues(struct qede_dev *edev)
1719{
1720 int i;
1721
1722 for_each_queue(i)
1723 if (edev->fp_array[i].type & QEDE_FASTPATH_TX) {
1724 int cos;
1725
1726 for_each_cos_in_txq(edev, cos) {
1727 struct qede_fastpath *fp;
1728
1729 fp = &edev->fp_array[i];
1730 qede_empty_tx_queue(edev,
1731 &fp->txq[cos]);
1732 }
1733 }
1734}
1735
1736
1737static void qede_init_fp(struct qede_dev *edev)
1738{
1739 int queue_id, rxq_index = 0, txq_index = 0;
1740 struct qede_fastpath *fp;
1741 bool init_xdp = false;
1742
1743 for_each_queue(queue_id) {
1744 fp = &edev->fp_array[queue_id];
1745
1746 fp->edev = edev;
1747 fp->id = queue_id;
1748
1749 if (fp->type & QEDE_FASTPATH_XDP) {
1750 fp->xdp_tx->index = QEDE_TXQ_IDX_TO_XDP(edev,
1751 rxq_index);
1752 fp->xdp_tx->is_xdp = 1;
1753
1754 spin_lock_init(&fp->xdp_tx->xdp_tx_lock);
1755 init_xdp = true;
1756 }
1757
1758 if (fp->type & QEDE_FASTPATH_RX) {
1759 fp->rxq->rxq_id = rxq_index++;
1760
1761
1762 if (fp->type & QEDE_FASTPATH_XDP)
1763 fp->rxq->data_direction = DMA_BIDIRECTIONAL;
1764 else
1765 fp->rxq->data_direction = DMA_FROM_DEVICE;
1766 fp->rxq->dev = &edev->pdev->dev;
1767
1768
1769 WARN_ON(xdp_rxq_info_reg(&fp->rxq->xdp_rxq, edev->ndev,
1770 fp->rxq->rxq_id, 0) < 0);
1771
1772 if (xdp_rxq_info_reg_mem_model(&fp->rxq->xdp_rxq,
1773 MEM_TYPE_PAGE_ORDER0,
1774 NULL)) {
1775 DP_NOTICE(edev,
1776 "Failed to register XDP memory model\n");
1777 }
1778 }
1779
1780 if (fp->type & QEDE_FASTPATH_TX) {
1781 int cos;
1782
1783 for_each_cos_in_txq(edev, cos) {
1784 struct qede_tx_queue *txq = &fp->txq[cos];
1785 u16 ndev_tx_id;
1786
1787 txq->cos = cos;
1788 txq->index = txq_index;
1789 ndev_tx_id = QEDE_TXQ_TO_NDEV_TXQ_ID(edev, txq);
1790 txq->ndev_txq_id = ndev_tx_id;
1791
1792 if (edev->dev_info.is_legacy)
1793 txq->is_legacy = true;
1794 txq->dev = &edev->pdev->dev;
1795 }
1796
1797 txq_index++;
1798 }
1799
1800 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1801 edev->ndev->name, queue_id);
1802 }
1803
1804 if (init_xdp) {
1805 edev->total_xdp_queues = QEDE_RSS_COUNT(edev);
1806 DP_INFO(edev, "Total XDP queues: %u\n", edev->total_xdp_queues);
1807 }
1808}
1809
1810static int qede_set_real_num_queues(struct qede_dev *edev)
1811{
1812 int rc = 0;
1813
1814 rc = netif_set_real_num_tx_queues(edev->ndev,
1815 QEDE_TSS_COUNT(edev) *
1816 edev->dev_info.num_tc);
1817 if (rc) {
1818 DP_NOTICE(edev, "Failed to set real number of Tx queues\n");
1819 return rc;
1820 }
1821
1822 rc = netif_set_real_num_rx_queues(edev->ndev, QEDE_RSS_COUNT(edev));
1823 if (rc) {
1824 DP_NOTICE(edev, "Failed to set real number of Rx queues\n");
1825 return rc;
1826 }
1827
1828 return 0;
1829}
1830
1831static void qede_napi_disable_remove(struct qede_dev *edev)
1832{
1833 int i;
1834
1835 for_each_queue(i) {
1836 napi_disable(&edev->fp_array[i].napi);
1837
1838 netif_napi_del(&edev->fp_array[i].napi);
1839 }
1840}
1841
1842static void qede_napi_add_enable(struct qede_dev *edev)
1843{
1844 int i;
1845
1846
1847 for_each_queue(i) {
1848 netif_napi_add(edev->ndev, &edev->fp_array[i].napi,
1849 qede_poll, NAPI_POLL_WEIGHT);
1850 napi_enable(&edev->fp_array[i].napi);
1851 }
1852}
1853
1854static void qede_sync_free_irqs(struct qede_dev *edev)
1855{
1856 int i;
1857
1858 for (i = 0; i < edev->int_info.used_cnt; i++) {
1859 if (edev->int_info.msix_cnt) {
1860 synchronize_irq(edev->int_info.msix[i].vector);
1861 free_irq(edev->int_info.msix[i].vector,
1862 &edev->fp_array[i]);
1863 } else {
1864 edev->ops->common->simd_handler_clean(edev->cdev, i);
1865 }
1866 }
1867
1868 edev->int_info.used_cnt = 0;
1869 edev->int_info.msix_cnt = 0;
1870}
1871
1872static int qede_req_msix_irqs(struct qede_dev *edev)
1873{
1874 int i, rc;
1875
1876
1877 if (QEDE_QUEUE_CNT(edev) > edev->int_info.msix_cnt) {
1878 DP_ERR(edev,
1879 "Interrupt mismatch: %d RSS queues > %d MSI-x vectors\n",
1880 QEDE_QUEUE_CNT(edev), edev->int_info.msix_cnt);
1881 return -EINVAL;
1882 }
1883
1884 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++) {
1885#ifdef CONFIG_RFS_ACCEL
1886 struct qede_fastpath *fp = &edev->fp_array[i];
1887
1888 if (edev->ndev->rx_cpu_rmap && (fp->type & QEDE_FASTPATH_RX)) {
1889 rc = irq_cpu_rmap_add(edev->ndev->rx_cpu_rmap,
1890 edev->int_info.msix[i].vector);
1891 if (rc) {
1892 DP_ERR(edev, "Failed to add CPU rmap\n");
1893 qede_free_arfs(edev);
1894 }
1895 }
1896#endif
1897 rc = request_irq(edev->int_info.msix[i].vector,
1898 qede_msix_fp_int, 0, edev->fp_array[i].name,
1899 &edev->fp_array[i]);
1900 if (rc) {
1901 DP_ERR(edev, "Request fp %d irq failed\n", i);
1902#ifdef CONFIG_RFS_ACCEL
1903 if (edev->ndev->rx_cpu_rmap)
1904 free_irq_cpu_rmap(edev->ndev->rx_cpu_rmap);
1905
1906 edev->ndev->rx_cpu_rmap = NULL;
1907#endif
1908 qede_sync_free_irqs(edev);
1909 return rc;
1910 }
1911 DP_VERBOSE(edev, NETIF_MSG_INTR,
1912 "Requested fp irq for %s [entry %d]. Cookie is at %p\n",
1913 edev->fp_array[i].name, i,
1914 &edev->fp_array[i]);
1915 edev->int_info.used_cnt++;
1916 }
1917
1918 return 0;
1919}
1920
1921static void qede_simd_fp_handler(void *cookie)
1922{
1923 struct qede_fastpath *fp = (struct qede_fastpath *)cookie;
1924
1925 napi_schedule_irqoff(&fp->napi);
1926}
1927
1928static int qede_setup_irqs(struct qede_dev *edev)
1929{
1930 int i, rc = 0;
1931
1932
1933 rc = edev->ops->common->get_fp_int(edev->cdev, &edev->int_info);
1934 if (rc)
1935 return rc;
1936
1937 if (edev->int_info.msix_cnt) {
1938 rc = qede_req_msix_irqs(edev);
1939 if (rc)
1940 return rc;
1941 edev->ndev->irq = edev->int_info.msix[0].vector;
1942 } else {
1943 const struct qed_common_ops *ops;
1944
1945
1946 ops = edev->ops->common;
1947 for (i = 0; i < QEDE_QUEUE_CNT(edev); i++)
1948 ops->simd_handler_config(edev->cdev,
1949 &edev->fp_array[i], i,
1950 qede_simd_fp_handler);
1951 edev->int_info.used_cnt = QEDE_QUEUE_CNT(edev);
1952 }
1953 return 0;
1954}
1955
1956static int qede_drain_txq(struct qede_dev *edev,
1957 struct qede_tx_queue *txq, bool allow_drain)
1958{
1959 int rc, cnt = 1000;
1960
1961 while (txq->sw_tx_cons != txq->sw_tx_prod) {
1962 if (!cnt) {
1963 if (allow_drain) {
1964 DP_NOTICE(edev,
1965 "Tx queue[%d] is stuck, requesting MCP to drain\n",
1966 txq->index);
1967 rc = edev->ops->common->drain(edev->cdev);
1968 if (rc)
1969 return rc;
1970 return qede_drain_txq(edev, txq, false);
1971 }
1972 DP_NOTICE(edev,
1973 "Timeout waiting for tx queue[%d]: PROD=%d, CONS=%d\n",
1974 txq->index, txq->sw_tx_prod,
1975 txq->sw_tx_cons);
1976 return -ENODEV;
1977 }
1978 cnt--;
1979 usleep_range(1000, 2000);
1980 barrier();
1981 }
1982
1983
1984 usleep_range(1000, 2000);
1985
1986 return 0;
1987}
1988
1989static int qede_stop_txq(struct qede_dev *edev,
1990 struct qede_tx_queue *txq, int rss_id)
1991{
1992
1993 edev->ops->common->db_recovery_del(edev->cdev, txq->doorbell_addr,
1994 &txq->tx_db);
1995
1996 return edev->ops->q_tx_stop(edev->cdev, rss_id, txq->handle);
1997}
1998
1999static int qede_stop_queues(struct qede_dev *edev)
2000{
2001 struct qed_update_vport_params *vport_update_params;
2002 struct qed_dev *cdev = edev->cdev;
2003 struct qede_fastpath *fp;
2004 int rc, i;
2005
2006
2007 vport_update_params = vzalloc(sizeof(*vport_update_params));
2008 if (!vport_update_params)
2009 return -ENOMEM;
2010
2011 vport_update_params->vport_id = 0;
2012 vport_update_params->update_vport_active_flg = 1;
2013 vport_update_params->vport_active_flg = 0;
2014 vport_update_params->update_rss_flg = 0;
2015
2016 rc = edev->ops->vport_update(cdev, vport_update_params);
2017 vfree(vport_update_params);
2018
2019 if (rc) {
2020 DP_ERR(edev, "Failed to update vport\n");
2021 return rc;
2022 }
2023
2024
2025 for_each_queue(i) {
2026 fp = &edev->fp_array[i];
2027
2028 if (fp->type & QEDE_FASTPATH_TX) {
2029 int cos;
2030
2031 for_each_cos_in_txq(edev, cos) {
2032 rc = qede_drain_txq(edev, &fp->txq[cos], true);
2033 if (rc)
2034 return rc;
2035 }
2036 }
2037
2038 if (fp->type & QEDE_FASTPATH_XDP) {
2039 rc = qede_drain_txq(edev, fp->xdp_tx, true);
2040 if (rc)
2041 return rc;
2042 }
2043 }
2044
2045
2046 for (i = QEDE_QUEUE_CNT(edev) - 1; i >= 0; i--) {
2047 fp = &edev->fp_array[i];
2048
2049
2050 if (fp->type & QEDE_FASTPATH_TX) {
2051 int cos;
2052
2053 for_each_cos_in_txq(edev, cos) {
2054 rc = qede_stop_txq(edev, &fp->txq[cos], i);
2055 if (rc)
2056 return rc;
2057 }
2058 }
2059
2060
2061 if (fp->type & QEDE_FASTPATH_RX) {
2062 rc = edev->ops->q_rx_stop(cdev, i, fp->rxq->handle);
2063 if (rc) {
2064 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
2065 return rc;
2066 }
2067 }
2068
2069
2070 if (fp->type & QEDE_FASTPATH_XDP) {
2071 rc = qede_stop_txq(edev, fp->xdp_tx, i);
2072 if (rc)
2073 return rc;
2074
2075 bpf_prog_put(fp->rxq->xdp_prog);
2076 }
2077 }
2078
2079
2080 rc = edev->ops->vport_stop(cdev, 0);
2081 if (rc)
2082 DP_ERR(edev, "Failed to stop VPORT\n");
2083
2084 return rc;
2085}
2086
2087static int qede_start_txq(struct qede_dev *edev,
2088 struct qede_fastpath *fp,
2089 struct qede_tx_queue *txq, u8 rss_id, u16 sb_idx)
2090{
2091 dma_addr_t phys_table = qed_chain_get_pbl_phys(&txq->tx_pbl);
2092 u32 page_cnt = qed_chain_get_page_cnt(&txq->tx_pbl);
2093 struct qed_queue_start_common_params params;
2094 struct qed_txq_start_ret_params ret_params;
2095 int rc;
2096
2097 memset(¶ms, 0, sizeof(params));
2098 memset(&ret_params, 0, sizeof(ret_params));
2099
2100
2101
2102
2103 if (txq->is_xdp)
2104 params.queue_id = QEDE_TXQ_XDP_TO_IDX(edev, txq);
2105 else
2106 params.queue_id = txq->index;
2107
2108 params.p_sb = fp->sb_info;
2109 params.sb_idx = sb_idx;
2110 params.tc = txq->cos;
2111
2112 rc = edev->ops->q_tx_start(edev->cdev, rss_id, ¶ms, phys_table,
2113 page_cnt, &ret_params);
2114 if (rc) {
2115 DP_ERR(edev, "Start TXQ #%d failed %d\n", txq->index, rc);
2116 return rc;
2117 }
2118
2119 txq->doorbell_addr = ret_params.p_doorbell;
2120 txq->handle = ret_params.p_handle;
2121
2122
2123 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[sb_idx];
2124
2125
2126 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST, DB_DEST_XCM);
2127 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD, DB_AGG_CMD_SET);
2128 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_VAL_SEL,
2129 DQ_XCM_ETH_TX_BD_PROD_CMD);
2130 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
2131
2132
2133 rc = edev->ops->common->db_recovery_add(edev->cdev, txq->doorbell_addr,
2134 &txq->tx_db, DB_REC_WIDTH_32B,
2135 DB_REC_KERNEL);
2136
2137 return rc;
2138}
2139
2140static int qede_start_queues(struct qede_dev *edev, bool clear_stats)
2141{
2142 int vlan_removal_en = 1;
2143 struct qed_dev *cdev = edev->cdev;
2144 struct qed_dev_info *qed_info = &edev->dev_info.common;
2145 struct qed_update_vport_params *vport_update_params;
2146 struct qed_queue_start_common_params q_params;
2147 struct qed_start_vport_params start = {0};
2148 int rc, i;
2149
2150 if (!edev->num_queues) {
2151 DP_ERR(edev,
2152 "Cannot update V-VPORT as active as there are no Rx queues\n");
2153 return -EINVAL;
2154 }
2155
2156 vport_update_params = vzalloc(sizeof(*vport_update_params));
2157 if (!vport_update_params)
2158 return -ENOMEM;
2159
2160 start.handle_ptp_pkts = !!(edev->ptp);
2161 start.gro_enable = !edev->gro_disable;
2162 start.mtu = edev->ndev->mtu;
2163 start.vport_id = 0;
2164 start.drop_ttl0 = true;
2165 start.remove_inner_vlan = vlan_removal_en;
2166 start.clear_stats = clear_stats;
2167
2168 rc = edev->ops->vport_start(cdev, &start);
2169
2170 if (rc) {
2171 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
2172 goto out;
2173 }
2174
2175 DP_VERBOSE(edev, NETIF_MSG_IFUP,
2176 "Start vport ramrod passed, vport_id = %d, MTU = %d, vlan_removal_en = %d\n",
2177 start.vport_id, edev->ndev->mtu + 0xe, vlan_removal_en);
2178
2179 for_each_queue(i) {
2180 struct qede_fastpath *fp = &edev->fp_array[i];
2181 dma_addr_t p_phys_table;
2182 u32 page_cnt;
2183
2184 if (fp->type & QEDE_FASTPATH_RX) {
2185 struct qed_rxq_start_ret_params ret_params;
2186 struct qede_rx_queue *rxq = fp->rxq;
2187 __le16 *val;
2188
2189 memset(&ret_params, 0, sizeof(ret_params));
2190 memset(&q_params, 0, sizeof(q_params));
2191 q_params.queue_id = rxq->rxq_id;
2192 q_params.vport_id = 0;
2193 q_params.p_sb = fp->sb_info;
2194 q_params.sb_idx = RX_PI;
2195
2196 p_phys_table =
2197 qed_chain_get_pbl_phys(&rxq->rx_comp_ring);
2198 page_cnt = qed_chain_get_page_cnt(&rxq->rx_comp_ring);
2199
2200 rc = edev->ops->q_rx_start(cdev, i, &q_params,
2201 rxq->rx_buf_size,
2202 rxq->rx_bd_ring.p_phys_addr,
2203 p_phys_table,
2204 page_cnt, &ret_params);
2205 if (rc) {
2206 DP_ERR(edev, "Start RXQ #%d failed %d\n", i,
2207 rc);
2208 goto out;
2209 }
2210
2211
2212 rxq->hw_rxq_prod_addr = ret_params.p_prod;
2213 rxq->handle = ret_params.p_handle;
2214
2215 val = &fp->sb_info->sb_virt->pi_array[RX_PI];
2216 rxq->hw_cons_ptr = val;
2217
2218 qede_update_rx_prod(edev, rxq);
2219 }
2220
2221 if (fp->type & QEDE_FASTPATH_XDP) {
2222 rc = qede_start_txq(edev, fp, fp->xdp_tx, i, XDP_PI);
2223 if (rc)
2224 goto out;
2225
2226 bpf_prog_add(edev->xdp_prog, 1);
2227 fp->rxq->xdp_prog = edev->xdp_prog;
2228 }
2229
2230 if (fp->type & QEDE_FASTPATH_TX) {
2231 int cos;
2232
2233 for_each_cos_in_txq(edev, cos) {
2234 rc = qede_start_txq(edev, fp, &fp->txq[cos], i,
2235 TX_PI(cos));
2236 if (rc)
2237 goto out;
2238 }
2239 }
2240 }
2241
2242
2243 vport_update_params->vport_id = start.vport_id;
2244 vport_update_params->update_vport_active_flg = 1;
2245 vport_update_params->vport_active_flg = 1;
2246
2247 if ((qed_info->b_inter_pf_switch || pci_num_vf(edev->pdev)) &&
2248 qed_info->tx_switching) {
2249 vport_update_params->update_tx_switching_flg = 1;
2250 vport_update_params->tx_switching_flg = 1;
2251 }
2252
2253 qede_fill_rss_params(edev, &vport_update_params->rss_params,
2254 &vport_update_params->update_rss_flg);
2255
2256 rc = edev->ops->vport_update(cdev, vport_update_params);
2257 if (rc)
2258 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
2259
2260out:
2261 vfree(vport_update_params);
2262 return rc;
2263}
2264
2265enum qede_unload_mode {
2266 QEDE_UNLOAD_NORMAL,
2267 QEDE_UNLOAD_RECOVERY,
2268};
2269
2270static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode,
2271 bool is_locked)
2272{
2273 struct qed_link_params link_params;
2274 int rc;
2275
2276 DP_INFO(edev, "Starting qede unload\n");
2277
2278 if (!is_locked)
2279 __qede_lock(edev);
2280
2281 clear_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags);
2282
2283 if (mode != QEDE_UNLOAD_RECOVERY)
2284 edev->state = QEDE_STATE_CLOSED;
2285
2286 qede_rdma_dev_event_close(edev);
2287
2288
2289 netif_tx_disable(edev->ndev);
2290 netif_carrier_off(edev->ndev);
2291
2292 if (mode != QEDE_UNLOAD_RECOVERY) {
2293
2294 memset(&link_params, 0, sizeof(link_params));
2295 link_params.link_up = false;
2296 edev->ops->common->set_link(edev->cdev, &link_params);
2297
2298 rc = qede_stop_queues(edev);
2299 if (rc) {
2300#ifdef CONFIG_RFS_ACCEL
2301 if (edev->dev_info.common.b_arfs_capable) {
2302 qede_poll_for_freeing_arfs_filters(edev);
2303 if (edev->ndev->rx_cpu_rmap)
2304 free_irq_cpu_rmap(edev->ndev->rx_cpu_rmap);
2305
2306 edev->ndev->rx_cpu_rmap = NULL;
2307 }
2308#endif
2309 qede_sync_free_irqs(edev);
2310 goto out;
2311 }
2312
2313 DP_INFO(edev, "Stopped Queues\n");
2314 }
2315
2316 qede_vlan_mark_nonconfigured(edev);
2317 edev->ops->fastpath_stop(edev->cdev);
2318
2319 if (edev->dev_info.common.b_arfs_capable) {
2320 qede_poll_for_freeing_arfs_filters(edev);
2321 qede_free_arfs(edev);
2322 }
2323
2324
2325 qede_sync_free_irqs(edev);
2326 edev->ops->common->set_fp_int(edev->cdev, 0);
2327
2328 qede_napi_disable_remove(edev);
2329
2330 if (mode == QEDE_UNLOAD_RECOVERY)
2331 qede_empty_tx_queues(edev);
2332
2333 qede_free_mem_load(edev);
2334 qede_free_fp_array(edev);
2335
2336out:
2337 if (!is_locked)
2338 __qede_unlock(edev);
2339
2340 if (mode != QEDE_UNLOAD_RECOVERY)
2341 DP_NOTICE(edev, "Link is down\n");
2342
2343 edev->ptp_skip_txts = 0;
2344
2345 DP_INFO(edev, "Ending qede unload\n");
2346}
2347
2348enum qede_load_mode {
2349 QEDE_LOAD_NORMAL,
2350 QEDE_LOAD_RELOAD,
2351 QEDE_LOAD_RECOVERY,
2352};
2353
2354static int qede_load(struct qede_dev *edev, enum qede_load_mode mode,
2355 bool is_locked)
2356{
2357 struct qed_link_params link_params;
2358 struct ethtool_coalesce coal = {};
2359 u8 num_tc;
2360 int rc, i;
2361
2362 DP_INFO(edev, "Starting qede load\n");
2363
2364 if (!is_locked)
2365 __qede_lock(edev);
2366
2367 rc = qede_set_num_queues(edev);
2368 if (rc)
2369 goto out;
2370
2371 rc = qede_alloc_fp_array(edev);
2372 if (rc)
2373 goto out;
2374
2375 qede_init_fp(edev);
2376
2377 rc = qede_alloc_mem_load(edev);
2378 if (rc)
2379 goto err1;
2380 DP_INFO(edev, "Allocated %d Rx, %d Tx queues\n",
2381 QEDE_RSS_COUNT(edev), QEDE_TSS_COUNT(edev));
2382
2383 rc = qede_set_real_num_queues(edev);
2384 if (rc)
2385 goto err2;
2386
2387 if (qede_alloc_arfs(edev)) {
2388 edev->ndev->features &= ~NETIF_F_NTUPLE;
2389 edev->dev_info.common.b_arfs_capable = false;
2390 }
2391
2392 qede_napi_add_enable(edev);
2393 DP_INFO(edev, "Napi added and enabled\n");
2394
2395 rc = qede_setup_irqs(edev);
2396 if (rc)
2397 goto err3;
2398 DP_INFO(edev, "Setup IRQs succeeded\n");
2399
2400 rc = qede_start_queues(edev, mode != QEDE_LOAD_RELOAD);
2401 if (rc)
2402 goto err4;
2403 DP_INFO(edev, "Start VPORT, RXQ and TXQ succeeded\n");
2404
2405 num_tc = netdev_get_num_tc(edev->ndev);
2406 num_tc = num_tc ? num_tc : edev->dev_info.num_tc;
2407 qede_setup_tc(edev->ndev, num_tc);
2408
2409
2410 qede_configure_vlan_filters(edev);
2411
2412 set_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags);
2413
2414
2415 memset(&link_params, 0, sizeof(link_params));
2416 link_params.link_up = true;
2417 edev->ops->common->set_link(edev->cdev, &link_params);
2418
2419 edev->state = QEDE_STATE_OPEN;
2420
2421 coal.rx_coalesce_usecs = QED_DEFAULT_RX_USECS;
2422 coal.tx_coalesce_usecs = QED_DEFAULT_TX_USECS;
2423
2424 for_each_queue(i) {
2425 if (edev->coal_entry[i].isvalid) {
2426 coal.rx_coalesce_usecs = edev->coal_entry[i].rxc;
2427 coal.tx_coalesce_usecs = edev->coal_entry[i].txc;
2428 }
2429 __qede_unlock(edev);
2430 qede_set_per_coalesce(edev->ndev, i, &coal);
2431 __qede_lock(edev);
2432 }
2433 DP_INFO(edev, "Ending successfully qede load\n");
2434
2435 goto out;
2436err4:
2437 qede_sync_free_irqs(edev);
2438err3:
2439 qede_napi_disable_remove(edev);
2440err2:
2441 qede_free_mem_load(edev);
2442err1:
2443 edev->ops->common->set_fp_int(edev->cdev, 0);
2444 qede_free_fp_array(edev);
2445 edev->num_queues = 0;
2446 edev->fp_num_tx = 0;
2447 edev->fp_num_rx = 0;
2448out:
2449 if (!is_locked)
2450 __qede_unlock(edev);
2451
2452 return rc;
2453}
2454
2455
2456
2457
2458void qede_reload(struct qede_dev *edev,
2459 struct qede_reload_args *args, bool is_locked)
2460{
2461 if (!is_locked)
2462 __qede_lock(edev);
2463
2464
2465
2466
2467
2468 if (edev->state == QEDE_STATE_OPEN) {
2469 qede_unload(edev, QEDE_UNLOAD_NORMAL, true);
2470 if (args)
2471 args->func(edev, args);
2472 qede_load(edev, QEDE_LOAD_RELOAD, true);
2473
2474
2475 qede_config_rx_mode(edev->ndev);
2476 } else if (args) {
2477 args->func(edev, args);
2478 }
2479
2480 if (!is_locked)
2481 __qede_unlock(edev);
2482}
2483
2484
2485static int qede_open(struct net_device *ndev)
2486{
2487 struct qede_dev *edev = netdev_priv(ndev);
2488 int rc;
2489
2490 netif_carrier_off(ndev);
2491
2492 edev->ops->common->set_power_state(edev->cdev, PCI_D0);
2493
2494 rc = qede_load(edev, QEDE_LOAD_NORMAL, false);
2495 if (rc)
2496 return rc;
2497
2498 udp_tunnel_nic_reset_ntf(ndev);
2499
2500 edev->ops->common->update_drv_state(edev->cdev, true);
2501
2502 return 0;
2503}
2504
2505static int qede_close(struct net_device *ndev)
2506{
2507 struct qede_dev *edev = netdev_priv(ndev);
2508
2509 qede_unload(edev, QEDE_UNLOAD_NORMAL, false);
2510
2511 if (edev->cdev)
2512 edev->ops->common->update_drv_state(edev->cdev, false);
2513
2514 return 0;
2515}
2516
2517static void qede_link_update(void *dev, struct qed_link_output *link)
2518{
2519 struct qede_dev *edev = dev;
2520
2521 if (!test_bit(QEDE_FLAGS_LINK_REQUESTED, &edev->flags)) {
2522 DP_VERBOSE(edev, NETIF_MSG_LINK, "Interface is not ready\n");
2523 return;
2524 }
2525
2526 if (link->link_up) {
2527 if (!netif_carrier_ok(edev->ndev)) {
2528 DP_NOTICE(edev, "Link is up\n");
2529 netif_tx_start_all_queues(edev->ndev);
2530 netif_carrier_on(edev->ndev);
2531 qede_rdma_dev_event_open(edev);
2532 }
2533 } else {
2534 if (netif_carrier_ok(edev->ndev)) {
2535 DP_NOTICE(edev, "Link is down\n");
2536 netif_tx_disable(edev->ndev);
2537 netif_carrier_off(edev->ndev);
2538 qede_rdma_dev_event_close(edev);
2539 }
2540 }
2541}
2542
2543static void qede_schedule_recovery_handler(void *dev)
2544{
2545 struct qede_dev *edev = dev;
2546
2547 if (edev->state == QEDE_STATE_RECOVERY) {
2548 DP_NOTICE(edev,
2549 "Avoid scheduling a recovery handling since already in recovery state\n");
2550 return;
2551 }
2552
2553 set_bit(QEDE_SP_RECOVERY, &edev->sp_flags);
2554 schedule_delayed_work(&edev->sp_task, 0);
2555
2556 DP_INFO(edev, "Scheduled a recovery handler\n");
2557}
2558
2559static void qede_recovery_failed(struct qede_dev *edev)
2560{
2561 netdev_err(edev->ndev, "Recovery handling has failed. Power cycle is needed.\n");
2562
2563 netif_device_detach(edev->ndev);
2564
2565 if (edev->cdev)
2566 edev->ops->common->set_power_state(edev->cdev, PCI_D3hot);
2567}
2568
2569static void qede_recovery_handler(struct qede_dev *edev)
2570{
2571 u32 curr_state = edev->state;
2572 int rc;
2573
2574 DP_NOTICE(edev, "Starting a recovery process\n");
2575
2576
2577
2578
2579 edev->state = QEDE_STATE_RECOVERY;
2580
2581 edev->ops->common->recovery_prolog(edev->cdev);
2582
2583 if (curr_state == QEDE_STATE_OPEN)
2584 qede_unload(edev, QEDE_UNLOAD_RECOVERY, true);
2585
2586 __qede_remove(edev->pdev, QEDE_REMOVE_RECOVERY);
2587
2588 rc = __qede_probe(edev->pdev, edev->dp_module, edev->dp_level,
2589 IS_VF(edev), QEDE_PROBE_RECOVERY);
2590 if (rc) {
2591 edev->cdev = NULL;
2592 goto err;
2593 }
2594
2595 if (curr_state == QEDE_STATE_OPEN) {
2596 rc = qede_load(edev, QEDE_LOAD_RECOVERY, true);
2597 if (rc)
2598 goto err;
2599
2600 qede_config_rx_mode(edev->ndev);
2601 udp_tunnel_nic_reset_ntf(edev->ndev);
2602 }
2603
2604 edev->state = curr_state;
2605
2606 DP_NOTICE(edev, "Recovery handling is done\n");
2607
2608 return;
2609
2610err:
2611 qede_recovery_failed(edev);
2612}
2613
2614static void qede_atomic_hw_err_handler(struct qede_dev *edev)
2615{
2616 struct qed_dev *cdev = edev->cdev;
2617
2618 DP_NOTICE(edev,
2619 "Generic non-sleepable HW error handling started - err_flags 0x%lx\n",
2620 edev->err_flags);
2621
2622
2623 WARN_ON(test_bit(QEDE_ERR_WARN, &edev->err_flags));
2624
2625
2626 if (test_bit(QEDE_ERR_ATTN_CLR_EN, &edev->err_flags))
2627 edev->ops->common->attn_clr_enable(cdev, true);
2628
2629 DP_NOTICE(edev, "Generic non-sleepable HW error handling is done\n");
2630}
2631
2632static void qede_generic_hw_err_handler(struct qede_dev *edev)
2633{
2634 DP_NOTICE(edev,
2635 "Generic sleepable HW error handling started - err_flags 0x%lx\n",
2636 edev->err_flags);
2637
2638 if (edev->devlink) {
2639 DP_NOTICE(edev, "Reporting fatal error to devlink\n");
2640 edev->ops->common->report_fatal_error(edev->devlink, edev->last_err_type);
2641 }
2642
2643 clear_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags);
2644
2645 DP_NOTICE(edev, "Generic sleepable HW error handling is done\n");
2646}
2647
2648static void qede_set_hw_err_flags(struct qede_dev *edev,
2649 enum qed_hw_err_type err_type)
2650{
2651 unsigned long err_flags = 0;
2652
2653 switch (err_type) {
2654 case QED_HW_ERR_DMAE_FAIL:
2655 set_bit(QEDE_ERR_WARN, &err_flags);
2656 fallthrough;
2657 case QED_HW_ERR_MFW_RESP_FAIL:
2658 case QED_HW_ERR_HW_ATTN:
2659 case QED_HW_ERR_RAMROD_FAIL:
2660 case QED_HW_ERR_FW_ASSERT:
2661 set_bit(QEDE_ERR_ATTN_CLR_EN, &err_flags);
2662 set_bit(QEDE_ERR_GET_DBG_INFO, &err_flags);
2663
2664 set_bit(QEDE_ERR_IS_RECOVERABLE, &err_flags);
2665 break;
2666
2667 default:
2668 DP_NOTICE(edev, "Unexpected HW error [%d]\n", err_type);
2669 break;
2670 }
2671
2672 edev->err_flags |= err_flags;
2673}
2674
2675static void qede_schedule_hw_err_handler(void *dev,
2676 enum qed_hw_err_type err_type)
2677{
2678 struct qede_dev *edev = dev;
2679
2680
2681
2682
2683 if ((test_and_set_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags) ||
2684 edev->state == QEDE_STATE_RECOVERY) &&
2685 err_type != QED_HW_ERR_FAN_FAIL) {
2686 DP_INFO(edev,
2687 "Avoid scheduling an error handling while another HW error is being handled\n");
2688 return;
2689 }
2690
2691 if (err_type >= QED_HW_ERR_LAST) {
2692 DP_NOTICE(edev, "Unknown HW error [%d]\n", err_type);
2693 clear_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags);
2694 return;
2695 }
2696
2697 edev->last_err_type = err_type;
2698 qede_set_hw_err_flags(edev, err_type);
2699 qede_atomic_hw_err_handler(edev);
2700 set_bit(QEDE_SP_HW_ERR, &edev->sp_flags);
2701 schedule_delayed_work(&edev->sp_task, 0);
2702
2703 DP_INFO(edev, "Scheduled a error handler [err_type %d]\n", err_type);
2704}
2705
2706static bool qede_is_txq_full(struct qede_dev *edev, struct qede_tx_queue *txq)
2707{
2708 struct netdev_queue *netdev_txq;
2709
2710 netdev_txq = netdev_get_tx_queue(edev->ndev, txq->ndev_txq_id);
2711 if (netif_xmit_stopped(netdev_txq))
2712 return true;
2713
2714 return false;
2715}
2716
2717static void qede_get_generic_tlv_data(void *dev, struct qed_generic_tlvs *data)
2718{
2719 struct qede_dev *edev = dev;
2720 struct netdev_hw_addr *ha;
2721 int i;
2722
2723 if (edev->ndev->features & NETIF_F_IP_CSUM)
2724 data->feat_flags |= QED_TLV_IP_CSUM;
2725 if (edev->ndev->features & NETIF_F_TSO)
2726 data->feat_flags |= QED_TLV_LSO;
2727
2728 ether_addr_copy(data->mac[0], edev->ndev->dev_addr);
2729 eth_zero_addr(data->mac[1]);
2730 eth_zero_addr(data->mac[2]);
2731
2732 netif_addr_lock_bh(edev->ndev);
2733 i = 1;
2734 netdev_for_each_uc_addr(ha, edev->ndev) {
2735 ether_addr_copy(data->mac[i++], ha->addr);
2736 if (i == QED_TLV_MAC_COUNT)
2737 break;
2738 }
2739
2740 netif_addr_unlock_bh(edev->ndev);
2741}
2742
2743static void qede_get_eth_tlv_data(void *dev, void *data)
2744{
2745 struct qed_mfw_tlv_eth *etlv = data;
2746 struct qede_dev *edev = dev;
2747 struct qede_fastpath *fp;
2748 int i;
2749
2750 etlv->lso_maxoff_size = 0XFFFF;
2751 etlv->lso_maxoff_size_set = true;
2752 etlv->lso_minseg_size = (u16)ETH_TX_LSO_WINDOW_MIN_LEN;
2753 etlv->lso_minseg_size_set = true;
2754 etlv->prom_mode = !!(edev->ndev->flags & IFF_PROMISC);
2755 etlv->prom_mode_set = true;
2756 etlv->tx_descr_size = QEDE_TSS_COUNT(edev);
2757 etlv->tx_descr_size_set = true;
2758 etlv->rx_descr_size = QEDE_RSS_COUNT(edev);
2759 etlv->rx_descr_size_set = true;
2760 etlv->iov_offload = QED_MFW_TLV_IOV_OFFLOAD_VEB;
2761 etlv->iov_offload_set = true;
2762
2763
2764
2765
2766 etlv->txqs_empty = true;
2767 etlv->rxqs_empty = true;
2768 etlv->num_txqs_full = 0;
2769 etlv->num_rxqs_full = 0;
2770
2771 __qede_lock(edev);
2772 for_each_queue(i) {
2773 fp = &edev->fp_array[i];
2774 if (fp->type & QEDE_FASTPATH_TX) {
2775 struct qede_tx_queue *txq = QEDE_FP_TC0_TXQ(fp);
2776
2777 if (txq->sw_tx_cons != txq->sw_tx_prod)
2778 etlv->txqs_empty = false;
2779 if (qede_is_txq_full(edev, txq))
2780 etlv->num_txqs_full++;
2781 }
2782 if (fp->type & QEDE_FASTPATH_RX) {
2783 if (qede_has_rx_work(fp->rxq))
2784 etlv->rxqs_empty = false;
2785
2786
2787
2788
2789
2790 if (le16_to_cpu(*fp->rxq->hw_cons_ptr) -
2791 qed_chain_get_cons_idx(&fp->rxq->rx_comp_ring) >
2792 RX_RING_SIZE - 100)
2793 etlv->num_rxqs_full++;
2794 }
2795 }
2796 __qede_unlock(edev);
2797
2798 etlv->txqs_empty_set = true;
2799 etlv->rxqs_empty_set = true;
2800 etlv->num_txqs_full_set = true;
2801 etlv->num_rxqs_full_set = true;
2802}
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812static pci_ers_result_t
2813qede_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2814{
2815 struct net_device *dev = pci_get_drvdata(pdev);
2816 struct qede_dev *edev = netdev_priv(dev);
2817
2818 if (!edev)
2819 return PCI_ERS_RESULT_NONE;
2820
2821 DP_NOTICE(edev, "IO error detected [%d]\n", state);
2822
2823 __qede_lock(edev);
2824 if (edev->state == QEDE_STATE_RECOVERY) {
2825 DP_NOTICE(edev, "Device already in the recovery state\n");
2826 __qede_unlock(edev);
2827 return PCI_ERS_RESULT_NONE;
2828 }
2829
2830
2831 if (IS_VF(edev)) {
2832 DP_VERBOSE(edev, QED_MSG_IOV,
2833 "VF recovery is handled by its PF\n");
2834 __qede_unlock(edev);
2835 return PCI_ERS_RESULT_RECOVERED;
2836 }
2837
2838
2839 netif_tx_disable(edev->ndev);
2840 netif_carrier_off(edev->ndev);
2841
2842 set_bit(QEDE_SP_AER, &edev->sp_flags);
2843 schedule_delayed_work(&edev->sp_task, 0);
2844
2845 __qede_unlock(edev);
2846
2847 return PCI_ERS_RESULT_CAN_RECOVER;
2848}
2849