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7#ifndef __QLCNIC_HW_H
8#define __QLCNIC_HW_H
9
10
11enum qlcnic_regs {
12 QLCNIC_PEG_HALT_STATUS1 = 0,
13 QLCNIC_PEG_HALT_STATUS2,
14 QLCNIC_PEG_ALIVE_COUNTER,
15 QLCNIC_FLASH_LOCK_OWNER,
16 QLCNIC_FW_CAPABILITIES,
17 QLCNIC_CRB_DRV_ACTIVE,
18 QLCNIC_CRB_DEV_STATE,
19 QLCNIC_CRB_DRV_STATE,
20 QLCNIC_CRB_DRV_SCRATCH,
21 QLCNIC_CRB_DEV_PARTITION_INFO,
22 QLCNIC_CRB_DRV_IDC_VER,
23 QLCNIC_FW_VERSION_MAJOR,
24 QLCNIC_FW_VERSION_MINOR,
25 QLCNIC_FW_VERSION_SUB,
26 QLCNIC_CRB_DEV_NPAR_STATE,
27 QLCNIC_FW_IMG_VALID,
28 QLCNIC_CMDPEG_STATE,
29 QLCNIC_RCVPEG_STATE,
30 QLCNIC_ASIC_TEMP,
31 QLCNIC_FW_API,
32 QLCNIC_DRV_OP_MODE,
33 QLCNIC_FLASH_LOCK,
34 QLCNIC_FLASH_UNLOCK,
35};
36
37
38#define QLC_SHARED_REG_RD32(a, addr) \
39 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
40
41
42#define QLC_SHARED_REG_WR32(a, addr, value) \
43 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
44
45
46#define QLCRDX(ahw, addr) \
47 readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))
48
49
50#define QLCWRX(ahw, addr, value) \
51 writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])))
52
53#define QLCNIC_CMD_CONFIGURE_IP_ADDR 0x1
54#define QLCNIC_CMD_CONFIG_INTRPT 0x2
55#define QLCNIC_CMD_CREATE_RX_CTX 0x7
56#define QLCNIC_CMD_DESTROY_RX_CTX 0x8
57#define QLCNIC_CMD_CREATE_TX_CTX 0x9
58#define QLCNIC_CMD_DESTROY_TX_CTX 0xa
59#define QLCNIC_CMD_CONFIGURE_LRO 0xC
60#define QLCNIC_CMD_CONFIGURE_MAC_LEARNING 0xD
61#define QLCNIC_CMD_GET_STATISTICS 0xF
62#define QLCNIC_CMD_INTRPT_TEST 0x11
63#define QLCNIC_CMD_SET_MTU 0x12
64#define QLCNIC_CMD_READ_PHY 0x13
65#define QLCNIC_CMD_WRITE_PHY 0x14
66#define QLCNIC_CMD_READ_HW_REG 0x15
67#define QLCNIC_CMD_GET_FLOW_CTL 0x16
68#define QLCNIC_CMD_SET_FLOW_CTL 0x17
69#define QLCNIC_CMD_READ_MAX_MTU 0x18
70#define QLCNIC_CMD_READ_MAX_LRO 0x19
71#define QLCNIC_CMD_MAC_ADDRESS 0x1f
72#define QLCNIC_CMD_GET_PCI_INFO 0x20
73#define QLCNIC_CMD_GET_NIC_INFO 0x21
74#define QLCNIC_CMD_SET_NIC_INFO 0x22
75#define QLCNIC_CMD_GET_ESWITCH_CAPABILITY 0x24
76#define QLCNIC_CMD_TOGGLE_ESWITCH 0x25
77#define QLCNIC_CMD_GET_ESWITCH_STATUS 0x26
78#define QLCNIC_CMD_SET_PORTMIRRORING 0x27
79#define QLCNIC_CMD_CONFIGURE_ESWITCH 0x28
80#define QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG 0x29
81#define QLCNIC_CMD_GET_ESWITCH_STATS 0x2a
82#define QLCNIC_CMD_CONFIG_PORT 0x2e
83#define QLCNIC_CMD_TEMP_SIZE 0x2f
84#define QLCNIC_CMD_GET_TEMP_HDR 0x30
85#define QLCNIC_CMD_BC_EVENT_SETUP 0x31
86#define QLCNIC_CMD_CONFIG_VPORT 0x32
87#define QLCNIC_CMD_DCB_QUERY_CAP 0x34
88#define QLCNIC_CMD_DCB_QUERY_PARAM 0x35
89#define QLCNIC_CMD_GET_MAC_STATS 0x37
90#define QLCNIC_CMD_82XX_SET_DRV_VER 0x38
91#define QLCNIC_CMD_MQ_TX_CONFIG_INTR 0x39
92#define QLCNIC_CMD_GET_LED_STATUS 0x3C
93#define QLCNIC_CMD_CONFIGURE_RSS 0x41
94#define QLCNIC_CMD_CONFIG_INTR_COAL 0x43
95#define QLCNIC_CMD_CONFIGURE_LED 0x44
96#define QLCNIC_CMD_CONFIG_MAC_VLAN 0x45
97#define QLCNIC_CMD_GET_LINK_EVENT 0x48
98#define QLCNIC_CMD_CONFIGURE_MAC_RX_MODE 0x49
99#define QLCNIC_CMD_CONFIGURE_HW_LRO 0x4A
100#define QLCNIC_CMD_SET_INGRESS_ENCAP 0x4E
101#define QLCNIC_CMD_INIT_NIC_FUNC 0x60
102#define QLCNIC_CMD_STOP_NIC_FUNC 0x61
103#define QLCNIC_CMD_IDC_ACK 0x63
104#define QLCNIC_CMD_SET_PORT_CONFIG 0x66
105#define QLCNIC_CMD_GET_PORT_CONFIG 0x67
106#define QLCNIC_CMD_GET_LINK_STATUS 0x68
107#define QLCNIC_CMD_SET_LED_CONFIG 0x69
108#define QLCNIC_CMD_GET_LED_CONFIG 0x6A
109#define QLCNIC_CMD_83XX_SET_DRV_VER 0x6F
110#define QLCNIC_CMD_ADD_RCV_RINGS 0x0B
111#define QLCNIC_CMD_83XX_EXTEND_ISCSI_DUMP_CAP 0x37
112
113#define QLCNIC_INTRPT_INTX 1
114#define QLCNIC_INTRPT_MSIX 3
115#define QLCNIC_INTRPT_ADD 1
116#define QLCNIC_INTRPT_DEL 2
117
118#define QLCNIC_GET_CURRENT_MAC 1
119#define QLCNIC_SET_STATION_MAC 2
120#define QLCNIC_GET_DEFAULT_MAC 3
121#define QLCNIC_GET_FAC_DEF_MAC 4
122#define QLCNIC_SET_FAC_DEF_MAC 5
123
124#define QLCNIC_MBX_LINK_EVENT 0x8001
125#define QLCNIC_MBX_BC_EVENT 0x8002
126#define QLCNIC_MBX_COMP_EVENT 0x8100
127#define QLCNIC_MBX_REQUEST_EVENT 0x8101
128#define QLCNIC_MBX_TIME_EXTEND_EVENT 0x8102
129#define QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT 0x8110
130#define QLCNIC_MBX_SFP_INSERT_EVENT 0x8130
131#define QLCNIC_MBX_SFP_REMOVE_EVENT 0x8131
132
133struct qlcnic_mailbox_metadata {
134 u32 cmd;
135 u32 in_args;
136 u32 out_args;
137};
138
139
140#define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
141
142#define QLCNIC_SET_OWNER 1
143#define QLCNIC_CLR_OWNER 0
144#define QLCNIC_MBX_TIMEOUT 5000
145
146#define QLCNIC_MBX_RSP_OK 1
147#define QLCNIC_MBX_PORT_RSP_OK 0x1a
148#define QLCNIC_MBX_ASYNC_EVENT BIT_15
149
150
151#define QLCNIC_MAX_HW_TX_RINGS 8
152#define QLCNIC_MAX_HW_VNIC_TX_RINGS 4
153#define QLCNIC_MAX_TX_RINGS 8
154#define QLCNIC_MAX_SDS_RINGS 8
155
156struct qlcnic_pci_info;
157struct qlcnic_info;
158struct qlcnic_cmd_args;
159struct ethtool_stats;
160struct pci_device_id;
161struct qlcnic_host_sds_ring;
162struct qlcnic_host_tx_ring;
163struct qlcnic_hardware_context;
164struct qlcnic_adapter;
165struct qlcnic_fw_dump;
166
167int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong, int *);
168int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *, ulong, u32);
169int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int);
170int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
171int qlcnic_82xx_napi_add(struct qlcnic_adapter *adapter,
172 struct net_device *netdev);
173void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *);
174void qlcnic_82xx_change_filter(struct qlcnic_adapter *adapter,
175 u64 *uaddr, u16 vlan_id,
176 struct qlcnic_host_tx_ring *tx_ring);
177int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *,
178 struct ethtool_coalesce *);
179int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *);
180int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int);
181void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
182 __be32, int);
183int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int);
184void qlcnic_82xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
185int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8);
186int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *, u8);
187void qlcnic_82xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
188void qlcnic_82xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
189int qlcnic_82xx_issue_cmd(struct qlcnic_adapter *adapter,
190 struct qlcnic_cmd_args *);
191int qlcnic_82xx_mq_intrpt(struct qlcnic_adapter *, int);
192int qlcnic_82xx_config_intrpt(struct qlcnic_adapter *, u8);
193int qlcnic_82xx_fw_cmd_create_rx_ctx(struct qlcnic_adapter *);
194int qlcnic_82xx_fw_cmd_create_tx_ctx(struct qlcnic_adapter *,
195 struct qlcnic_host_tx_ring *tx_ring, int);
196void qlcnic_82xx_fw_cmd_del_rx_ctx(struct qlcnic_adapter *);
197void qlcnic_82xx_fw_cmd_del_tx_ctx(struct qlcnic_adapter *,
198 struct qlcnic_host_tx_ring *);
199int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8);
200int qlcnic_82xx_get_mac_address(struct qlcnic_adapter *, u8*, u8);
201int qlcnic_82xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
202int qlcnic_82xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
203int qlcnic_82xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
204int qlcnic_82xx_alloc_mbx_args(struct qlcnic_cmd_args *,
205 struct qlcnic_adapter *, u32);
206int qlcnic_82xx_get_board_info(struct qlcnic_adapter *);
207int qlcnic_82xx_config_led(struct qlcnic_adapter *, u32, u32);
208void qlcnic_82xx_get_func_no(struct qlcnic_adapter *);
209int qlcnic_82xx_api_lock(struct qlcnic_adapter *);
210void qlcnic_82xx_api_unlock(struct qlcnic_adapter *);
211void qlcnic_82xx_napi_enable(struct qlcnic_adapter *);
212void qlcnic_82xx_napi_disable(struct qlcnic_adapter *);
213void qlcnic_82xx_napi_del(struct qlcnic_adapter *);
214int qlcnic_82xx_shutdown(struct pci_dev *);
215int qlcnic_82xx_resume(struct qlcnic_adapter *);
216void qlcnic_clr_all_drv_state(struct qlcnic_adapter *adapter, u8 failed);
217void qlcnic_fw_poll_work(struct work_struct *work);
218
219u32 qlcnic_82xx_get_saved_state(void *, u32);
220void qlcnic_82xx_set_saved_state(void *, u32, u32);
221void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *);
222u32 qlcnic_82xx_get_cap_size(void *, int);
223void qlcnic_82xx_set_sys_info(void *, int, u32);
224void qlcnic_82xx_store_cap_mask(void *, u32);
225#endif
226
