linux/drivers/net/ethernet/realtek/r8169_main.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   4 *
   5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7 * Copyright (c) a lot of people too. Please respect their work.
   8 *
   9 * See MAINTAINERS file for support contact information.
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/moduleparam.h>
  14#include <linux/pci.h>
  15#include <linux/netdevice.h>
  16#include <linux/etherdevice.h>
  17#include <linux/clk.h>
  18#include <linux/delay.h>
  19#include <linux/ethtool.h>
  20#include <linux/phy.h>
  21#include <linux/if_vlan.h>
  22#include <linux/crc32.h>
  23#include <linux/in.h>
  24#include <linux/io.h>
  25#include <linux/ip.h>
  26#include <linux/tcp.h>
  27#include <linux/interrupt.h>
  28#include <linux/dma-mapping.h>
  29#include <linux/pm_runtime.h>
  30#include <linux/prefetch.h>
  31#include <linux/ipv6.h>
  32#include <net/ip6_checksum.h>
  33
  34#include "r8169_firmware.h"
  35
  36#define MODULENAME "r8169"
  37
  38#define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  39#define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  40#define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  41#define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  42#define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  43#define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  44#define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  45#define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46#define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
  47#define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
  48#define FIRMWARE_8411_2         "rtl_nic/rtl8411-2.fw"
  49#define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
  50#define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
  51#define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
  52#define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
  53#define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
  54#define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
  55#define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
  56#define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
  57#define FIRMWARE_8125A_3        "rtl_nic/rtl8125a-3.fw"
  58
  59#define R8169_MSG_DEFAULT \
  60        (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  63   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  64#define MC_FILTER_LIMIT 32
  65
  66#define TX_DMA_BURST    7       /* Maximum PCI burst, '7' is unlimited */
  67#define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  68
  69#define R8169_REGS_SIZE         256
  70#define R8169_RX_BUF_SIZE       (SZ_16K - 1)
  71#define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  72#define NUM_RX_DESC     256U    /* Number of Rx descriptor registers */
  73#define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  74#define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  75
  76#define RTL_CFG_NO_GBIT 1
  77
  78/* write/read MMIO register */
  79#define RTL_W8(tp, reg, val8)   writeb((val8), tp->mmio_addr + (reg))
  80#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
  81#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
  82#define RTL_R8(tp, reg)         readb(tp->mmio_addr + (reg))
  83#define RTL_R16(tp, reg)                readw(tp->mmio_addr + (reg))
  84#define RTL_R32(tp, reg)                readl(tp->mmio_addr + (reg))
  85
  86enum mac_version {
  87        /* support for ancient RTL_GIGA_MAC_VER_01 has been removed */
  88        RTL_GIGA_MAC_VER_02,
  89        RTL_GIGA_MAC_VER_03,
  90        RTL_GIGA_MAC_VER_04,
  91        RTL_GIGA_MAC_VER_05,
  92        RTL_GIGA_MAC_VER_06,
  93        RTL_GIGA_MAC_VER_07,
  94        RTL_GIGA_MAC_VER_08,
  95        RTL_GIGA_MAC_VER_09,
  96        RTL_GIGA_MAC_VER_10,
  97        RTL_GIGA_MAC_VER_11,
  98        RTL_GIGA_MAC_VER_12,
  99        RTL_GIGA_MAC_VER_13,
 100        RTL_GIGA_MAC_VER_14,
 101        RTL_GIGA_MAC_VER_15,
 102        RTL_GIGA_MAC_VER_16,
 103        RTL_GIGA_MAC_VER_17,
 104        RTL_GIGA_MAC_VER_18,
 105        RTL_GIGA_MAC_VER_19,
 106        RTL_GIGA_MAC_VER_20,
 107        RTL_GIGA_MAC_VER_21,
 108        RTL_GIGA_MAC_VER_22,
 109        RTL_GIGA_MAC_VER_23,
 110        RTL_GIGA_MAC_VER_24,
 111        RTL_GIGA_MAC_VER_25,
 112        RTL_GIGA_MAC_VER_26,
 113        RTL_GIGA_MAC_VER_27,
 114        RTL_GIGA_MAC_VER_28,
 115        RTL_GIGA_MAC_VER_29,
 116        RTL_GIGA_MAC_VER_30,
 117        RTL_GIGA_MAC_VER_31,
 118        RTL_GIGA_MAC_VER_32,
 119        RTL_GIGA_MAC_VER_33,
 120        RTL_GIGA_MAC_VER_34,
 121        RTL_GIGA_MAC_VER_35,
 122        RTL_GIGA_MAC_VER_36,
 123        RTL_GIGA_MAC_VER_37,
 124        RTL_GIGA_MAC_VER_38,
 125        RTL_GIGA_MAC_VER_39,
 126        RTL_GIGA_MAC_VER_40,
 127        RTL_GIGA_MAC_VER_41,
 128        RTL_GIGA_MAC_VER_42,
 129        RTL_GIGA_MAC_VER_43,
 130        RTL_GIGA_MAC_VER_44,
 131        RTL_GIGA_MAC_VER_45,
 132        RTL_GIGA_MAC_VER_46,
 133        RTL_GIGA_MAC_VER_47,
 134        RTL_GIGA_MAC_VER_48,
 135        RTL_GIGA_MAC_VER_49,
 136        RTL_GIGA_MAC_VER_50,
 137        RTL_GIGA_MAC_VER_51,
 138        RTL_GIGA_MAC_VER_60,
 139        RTL_GIGA_MAC_VER_61,
 140        RTL_GIGA_MAC_NONE
 141};
 142
 143#define JUMBO_1K        ETH_DATA_LEN
 144#define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 145#define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 146#define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 147#define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 148
 149static const struct {
 150        const char *name;
 151        const char *fw_name;
 152} rtl_chip_infos[] = {
 153        /* PCI devices. */
 154        [RTL_GIGA_MAC_VER_02] = {"RTL8169s"                             },
 155        [RTL_GIGA_MAC_VER_03] = {"RTL8110s"                             },
 156        [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"                     },
 157        [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"                     },
 158        [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"                     },
 159        /* PCI-E devices. */
 160        [RTL_GIGA_MAC_VER_07] = {"RTL8102e"                             },
 161        [RTL_GIGA_MAC_VER_08] = {"RTL8102e"                             },
 162        [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"                    },
 163        [RTL_GIGA_MAC_VER_10] = {"RTL8101e"                             },
 164        [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b"                       },
 165        [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b"                       },
 166        [RTL_GIGA_MAC_VER_13] = {"RTL8101e"                             },
 167        [RTL_GIGA_MAC_VER_14] = {"RTL8100e"                             },
 168        [RTL_GIGA_MAC_VER_15] = {"RTL8100e"                             },
 169        [RTL_GIGA_MAC_VER_16] = {"RTL8101e"                             },
 170        [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"                       },
 171        [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"                     },
 172        [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"                       },
 173        [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"                       },
 174        [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"                       },
 175        [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"                       },
 176        [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"                     },
 177        [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"                     },
 178        [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",      FIRMWARE_8168D_1},
 179        [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",      FIRMWARE_8168D_2},
 180        [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp"                     },
 181        [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"                     },
 182        [RTL_GIGA_MAC_VER_29] = {"RTL8105e",            FIRMWARE_8105E_1},
 183        [RTL_GIGA_MAC_VER_30] = {"RTL8105e",            FIRMWARE_8105E_1},
 184        [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"                     },
 185        [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",      FIRMWARE_8168E_1},
 186        [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",      FIRMWARE_8168E_2},
 187        [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",  FIRMWARE_8168E_3},
 188        [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",      FIRMWARE_8168F_1},
 189        [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",      FIRMWARE_8168F_2},
 190        [RTL_GIGA_MAC_VER_37] = {"RTL8402",             FIRMWARE_8402_1 },
 191        [RTL_GIGA_MAC_VER_38] = {"RTL8411",             FIRMWARE_8411_1 },
 192        [RTL_GIGA_MAC_VER_39] = {"RTL8106e",            FIRMWARE_8106E_1},
 193        [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",      FIRMWARE_8168G_2},
 194        [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g"                       },
 195        [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",    FIRMWARE_8168G_3},
 196        [RTL_GIGA_MAC_VER_43] = {"RTL8106eus",          FIRMWARE_8106E_2},
 197        [RTL_GIGA_MAC_VER_44] = {"RTL8411b",            FIRMWARE_8411_2 },
 198        [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h",      FIRMWARE_8168H_1},
 199        [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",      FIRMWARE_8168H_2},
 200        [RTL_GIGA_MAC_VER_47] = {"RTL8107e",            FIRMWARE_8107E_1},
 201        [RTL_GIGA_MAC_VER_48] = {"RTL8107e",            FIRMWARE_8107E_2},
 202        [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep"                     },
 203        [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep"                     },
 204        [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"                     },
 205        [RTL_GIGA_MAC_VER_60] = {"RTL8125"                              },
 206        [RTL_GIGA_MAC_VER_61] = {"RTL8125",             FIRMWARE_8125A_3},
 207};
 208
 209static const struct pci_device_id rtl8169_pci_tbl[] = {
 210        { PCI_VDEVICE(REALTEK,  0x2502) },
 211        { PCI_VDEVICE(REALTEK,  0x2600) },
 212        { PCI_VDEVICE(REALTEK,  0x8129) },
 213        { PCI_VDEVICE(REALTEK,  0x8136), RTL_CFG_NO_GBIT },
 214        { PCI_VDEVICE(REALTEK,  0x8161) },
 215        { PCI_VDEVICE(REALTEK,  0x8167) },
 216        { PCI_VDEVICE(REALTEK,  0x8168) },
 217        { PCI_VDEVICE(NCUBE,    0x8168) },
 218        { PCI_VDEVICE(REALTEK,  0x8169) },
 219        { PCI_VENDOR_ID_DLINK,  0x4300,
 220                PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
 221        { PCI_VDEVICE(DLINK,    0x4300) },
 222        { PCI_VDEVICE(DLINK,    0x4302) },
 223        { PCI_VDEVICE(AT,       0xc107) },
 224        { PCI_VDEVICE(USR,      0x0116) },
 225        { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
 226        { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
 227        { PCI_VDEVICE(REALTEK,  0x8125) },
 228        { PCI_VDEVICE(REALTEK,  0x3000) },
 229        {}
 230};
 231
 232MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 233
 234static struct {
 235        u32 msg_enable;
 236} debug = { -1 };
 237
 238enum rtl_registers {
 239        MAC0            = 0,    /* Ethernet hardware address. */
 240        MAC4            = 4,
 241        MAR0            = 8,    /* Multicast filter. */
 242        CounterAddrLow          = 0x10,
 243        CounterAddrHigh         = 0x14,
 244        TxDescStartAddrLow      = 0x20,
 245        TxDescStartAddrHigh     = 0x24,
 246        TxHDescStartAddrLow     = 0x28,
 247        TxHDescStartAddrHigh    = 0x2c,
 248        FLASH           = 0x30,
 249        ERSR            = 0x36,
 250        ChipCmd         = 0x37,
 251        TxPoll          = 0x38,
 252        IntrMask        = 0x3c,
 253        IntrStatus      = 0x3e,
 254
 255        TxConfig        = 0x40,
 256#define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 257#define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 258
 259        RxConfig        = 0x44,
 260#define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 261#define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 262#define RXCFG_FIFO_SHIFT                13
 263                                        /* No threshold before first PCI xfer */
 264#define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 265#define RX_EARLY_OFF                    (1 << 11)
 266#define RXCFG_DMA_SHIFT                 8
 267                                        /* Unlimited maximum PCI burst. */
 268#define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 269
 270        RxMissed        = 0x4c,
 271        Cfg9346         = 0x50,
 272        Config0         = 0x51,
 273        Config1         = 0x52,
 274        Config2         = 0x53,
 275#define PME_SIGNAL                      (1 << 5)        /* 8168c and later */
 276
 277        Config3         = 0x54,
 278        Config4         = 0x55,
 279        Config5         = 0x56,
 280        PHYAR           = 0x60,
 281        PHYstatus       = 0x6c,
 282        RxMaxSize       = 0xda,
 283        CPlusCmd        = 0xe0,
 284        IntrMitigate    = 0xe2,
 285
 286#define RTL_COALESCE_MASK       0x0f
 287#define RTL_COALESCE_SHIFT      4
 288#define RTL_COALESCE_T_MAX      (RTL_COALESCE_MASK)
 289#define RTL_COALESCE_FRAME_MAX  (RTL_COALESCE_MASK << 2)
 290
 291        RxDescAddrLow   = 0xe4,
 292        RxDescAddrHigh  = 0xe8,
 293        EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295#define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297        MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299#define TxPacketMax     (8064 >> 7)
 300#define EarlySize       0x27
 301
 302        FuncEvent       = 0xf0,
 303        FuncEventMask   = 0xf4,
 304        FuncPresetState = 0xf8,
 305        IBCR0           = 0xf8,
 306        IBCR2           = 0xf9,
 307        IBIMR0          = 0xfa,
 308        IBISR0          = 0xfb,
 309        FuncForceEvent  = 0xfc,
 310};
 311
 312enum rtl8168_8101_registers {
 313        CSIDR                   = 0x64,
 314        CSIAR                   = 0x68,
 315#define CSIAR_FLAG                      0x80000000
 316#define CSIAR_WRITE_CMD                 0x80000000
 317#define CSIAR_BYTE_ENABLE               0x0000f000
 318#define CSIAR_ADDR_MASK                 0x00000fff
 319        PMCH                    = 0x6f,
 320        EPHYAR                  = 0x80,
 321#define EPHYAR_FLAG                     0x80000000
 322#define EPHYAR_WRITE_CMD                0x80000000
 323#define EPHYAR_REG_MASK                 0x1f
 324#define EPHYAR_REG_SHIFT                16
 325#define EPHYAR_DATA_MASK                0xffff
 326        DLLPR                   = 0xd0,
 327#define PFM_EN                          (1 << 6)
 328#define TX_10M_PS_EN                    (1 << 7)
 329        DBG_REG                 = 0xd1,
 330#define FIX_NAK_1                       (1 << 4)
 331#define FIX_NAK_2                       (1 << 3)
 332        TWSI                    = 0xd2,
 333        MCU                     = 0xd3,
 334#define NOW_IS_OOB                      (1 << 7)
 335#define TX_EMPTY                        (1 << 5)
 336#define RX_EMPTY                        (1 << 4)
 337#define RXTX_EMPTY                      (TX_EMPTY | RX_EMPTY)
 338#define EN_NDP                          (1 << 3)
 339#define EN_OOB_RESET                    (1 << 2)
 340#define LINK_LIST_RDY                   (1 << 1)
 341        EFUSEAR                 = 0xdc,
 342#define EFUSEAR_FLAG                    0x80000000
 343#define EFUSEAR_WRITE_CMD               0x80000000
 344#define EFUSEAR_READ_CMD                0x00000000
 345#define EFUSEAR_REG_MASK                0x03ff
 346#define EFUSEAR_REG_SHIFT               8
 347#define EFUSEAR_DATA_MASK               0xff
 348        MISC_1                  = 0xf2,
 349#define PFM_D3COLD_EN                   (1 << 6)
 350};
 351
 352enum rtl8168_registers {
 353        LED_FREQ                = 0x1a,
 354        EEE_LED                 = 0x1b,
 355        ERIDR                   = 0x70,
 356        ERIAR                   = 0x74,
 357#define ERIAR_FLAG                      0x80000000
 358#define ERIAR_WRITE_CMD                 0x80000000
 359#define ERIAR_READ_CMD                  0x00000000
 360#define ERIAR_ADDR_BYTE_ALIGN           4
 361#define ERIAR_TYPE_SHIFT                16
 362#define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 363#define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 364#define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 365#define ERIAR_OOB                       (0x02 << ERIAR_TYPE_SHIFT)
 366#define ERIAR_MASK_SHIFT                12
 367#define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 368#define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 369#define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 370#define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 371#define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 372        EPHY_RXER_NUM           = 0x7c,
 373        OCPDR                   = 0xb0, /* OCP GPHY access */
 374#define OCPDR_WRITE_CMD                 0x80000000
 375#define OCPDR_READ_CMD                  0x00000000
 376#define OCPDR_REG_MASK                  0x7f
 377#define OCPDR_GPHY_REG_SHIFT            16
 378#define OCPDR_DATA_MASK                 0xffff
 379        OCPAR                   = 0xb4,
 380#define OCPAR_FLAG                      0x80000000
 381#define OCPAR_GPHY_WRITE_CMD            0x8000f060
 382#define OCPAR_GPHY_READ_CMD             0x0000f060
 383        GPHY_OCP                = 0xb8,
 384        RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 385        MISC                    = 0xf0, /* 8168e only. */
 386#define TXPLA_RST                       (1 << 29)
 387#define DISABLE_LAN_EN                  (1 << 23) /* Enable GPIO pin */
 388#define PWM_EN                          (1 << 22)
 389#define RXDV_GATED_EN                   (1 << 19)
 390#define EARLY_TALLY_EN                  (1 << 16)
 391};
 392
 393enum rtl8125_registers {
 394        IntrMask_8125           = 0x38,
 395        IntrStatus_8125         = 0x3c,
 396        TxPoll_8125             = 0x90,
 397        MAC0_BKP                = 0x19e0,
 398};
 399
 400#define RX_VLAN_INNER_8125      BIT(22)
 401#define RX_VLAN_OUTER_8125      BIT(23)
 402#define RX_VLAN_8125            (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
 403
 404#define RX_FETCH_DFLT_8125      (8 << 27)
 405
 406enum rtl_register_content {
 407        /* InterruptStatusBits */
 408        SYSErr          = 0x8000,
 409        PCSTimeout      = 0x4000,
 410        SWInt           = 0x0100,
 411        TxDescUnavail   = 0x0080,
 412        RxFIFOOver      = 0x0040,
 413        LinkChg         = 0x0020,
 414        RxOverflow      = 0x0010,
 415        TxErr           = 0x0008,
 416        TxOK            = 0x0004,
 417        RxErr           = 0x0002,
 418        RxOK            = 0x0001,
 419
 420        /* RxStatusDesc */
 421        RxRWT   = (1 << 22),
 422        RxRES   = (1 << 21),
 423        RxRUNT  = (1 << 20),
 424        RxCRC   = (1 << 19),
 425
 426        /* ChipCmdBits */
 427        StopReq         = 0x80,
 428        CmdReset        = 0x10,
 429        CmdRxEnb        = 0x08,
 430        CmdTxEnb        = 0x04,
 431        RxBufEmpty      = 0x01,
 432
 433        /* TXPoll register p.5 */
 434        HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 435        NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 436        FSWInt          = 0x01,         /* Forced software interrupt */
 437
 438        /* Cfg9346Bits */
 439        Cfg9346_Lock    = 0x00,
 440        Cfg9346_Unlock  = 0xc0,
 441
 442        /* rx_mode_bits */
 443        AcceptErr       = 0x20,
 444        AcceptRunt      = 0x10,
 445        AcceptBroadcast = 0x08,
 446        AcceptMulticast = 0x04,
 447        AcceptMyPhys    = 0x02,
 448        AcceptAllPhys   = 0x01,
 449#define RX_CONFIG_ACCEPT_MASK           0x3f
 450
 451        /* TxConfigBits */
 452        TxInterFrameGapShift = 24,
 453        TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 454
 455        /* Config1 register p.24 */
 456        LEDS1           = (1 << 7),
 457        LEDS0           = (1 << 6),
 458        Speed_down      = (1 << 4),
 459        MEMMAP          = (1 << 3),
 460        IOMAP           = (1 << 2),
 461        VPD             = (1 << 1),
 462        PMEnable        = (1 << 0),     /* Power Management Enable */
 463
 464        /* Config2 register p. 25 */
 465        ClkReqEn        = (1 << 7),     /* Clock Request Enable */
 466        MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
 467        PCI_Clock_66MHz = 0x01,
 468        PCI_Clock_33MHz = 0x00,
 469
 470        /* Config3 register p.25 */
 471        MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 472        LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 473        Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 474        Rdy_to_L23      = (1 << 1),     /* L23 Enable */
 475        Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 476
 477        /* Config4 register */
 478        Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 479
 480        /* Config5 register p.27 */
 481        BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 482        MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 483        UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 484        Spi_en          = (1 << 3),
 485        LanWake         = (1 << 1),     /* LanWake enable/disable */
 486        PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 487        ASPM_en         = (1 << 0),     /* ASPM enable */
 488
 489        /* CPlusCmd p.31 */
 490        EnableBist      = (1 << 15),    // 8168 8101
 491        Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 492        Normal_mode     = (1 << 13),    // unused
 493        Force_half_dup  = (1 << 12),    // 8168 8101
 494        Force_rxflow_en = (1 << 11),    // 8168 8101
 495        Force_txflow_en = (1 << 10),    // 8168 8101
 496        Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 497        ASF             = (1 << 8),     // 8168 8101
 498        PktCntrDisable  = (1 << 7),     // 8168 8101
 499        Mac_dbgo_sel    = 0x001c,       // 8168
 500        RxVlan          = (1 << 6),
 501        RxChkSum        = (1 << 5),
 502        PCIDAC          = (1 << 4),
 503        PCIMulRW        = (1 << 3),
 504#define INTT_MASK       GENMASK(1, 0)
 505#define CPCMD_MASK      (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
 506
 507        /* rtl8169_PHYstatus */
 508        TBI_Enable      = 0x80,
 509        TxFlowCtrl      = 0x40,
 510        RxFlowCtrl      = 0x20,
 511        _1000bpsF       = 0x10,
 512        _100bps         = 0x08,
 513        _10bps          = 0x04,
 514        LinkStatus      = 0x02,
 515        FullDup         = 0x01,
 516
 517        /* ResetCounterCommand */
 518        CounterReset    = 0x1,
 519
 520        /* DumpCounterCommand */
 521        CounterDump     = 0x8,
 522
 523        /* magic enable v2 */
 524        MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 525};
 526
 527enum rtl_desc_bit {
 528        /* First doubleword. */
 529        DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 530        RingEnd         = (1 << 30), /* End of descriptor ring */
 531        FirstFrag       = (1 << 29), /* First segment of a packet */
 532        LastFrag        = (1 << 28), /* Final segment of a packet */
 533};
 534
 535/* Generic case. */
 536enum rtl_tx_desc_bit {
 537        /* First doubleword. */
 538        TD_LSO          = (1 << 27),            /* Large Send Offload */
 539#define TD_MSS_MAX                      0x07ffu /* MSS value */
 540
 541        /* Second doubleword. */
 542        TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 543};
 544
 545/* 8169, 8168b and 810x except 8102e. */
 546enum rtl_tx_desc_bit_0 {
 547        /* First doubleword. */
 548#define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 549        TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 550        TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 551        TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 552};
 553
 554/* 8102e, 8168c and beyond. */
 555enum rtl_tx_desc_bit_1 {
 556        /* First doubleword. */
 557        TD1_GTSENV4     = (1 << 26),            /* Giant Send for IPv4 */
 558        TD1_GTSENV6     = (1 << 25),            /* Giant Send for IPv6 */
 559#define GTTCPHO_SHIFT                   18
 560#define GTTCPHO_MAX                     0x7f
 561
 562        /* Second doubleword. */
 563#define TCPHO_SHIFT                     18
 564#define TCPHO_MAX                       0x3ff
 565#define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 566        TD1_IPv6_CS     = (1 << 28),            /* Calculate IPv6 checksum */
 567        TD1_IPv4_CS     = (1 << 29),            /* Calculate IPv4 checksum */
 568        TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 569        TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 570};
 571
 572enum rtl_rx_desc_bit {
 573        /* Rx private */
 574        PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 575        PID0            = (1 << 17), /* Protocol ID bit 0/2 */
 576
 577#define RxProtoUDP      (PID1)
 578#define RxProtoTCP      (PID0)
 579#define RxProtoIP       (PID1 | PID0)
 580#define RxProtoMask     RxProtoIP
 581
 582        IPFail          = (1 << 16), /* IP checksum failed */
 583        UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 584        TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 585        RxVlanTag       = (1 << 16), /* VLAN tag available */
 586};
 587
 588#define RsvdMask        0x3fffc000
 589
 590#define RTL_GSO_MAX_SIZE_V1     32000
 591#define RTL_GSO_MAX_SEGS_V1     24
 592#define RTL_GSO_MAX_SIZE_V2     64000
 593#define RTL_GSO_MAX_SEGS_V2     64
 594
 595struct TxDesc {
 596        __le32 opts1;
 597        __le32 opts2;
 598        __le64 addr;
 599};
 600
 601struct RxDesc {
 602        __le32 opts1;
 603        __le32 opts2;
 604        __le64 addr;
 605};
 606
 607struct ring_info {
 608        struct sk_buff  *skb;
 609        u32             len;
 610};
 611
 612struct rtl8169_counters {
 613        __le64  tx_packets;
 614        __le64  rx_packets;
 615        __le64  tx_errors;
 616        __le32  rx_errors;
 617        __le16  rx_missed;
 618        __le16  align_errors;
 619        __le32  tx_one_collision;
 620        __le32  tx_multi_collision;
 621        __le64  rx_unicast;
 622        __le64  rx_broadcast;
 623        __le32  rx_multicast;
 624        __le16  tx_aborted;
 625        __le16  tx_underun;
 626};
 627
 628struct rtl8169_tc_offsets {
 629        bool    inited;
 630        __le64  tx_errors;
 631        __le32  tx_multi_collision;
 632        __le16  tx_aborted;
 633};
 634
 635enum rtl_flag {
 636        RTL_FLAG_TASK_ENABLED = 0,
 637        RTL_FLAG_TASK_RESET_PENDING,
 638        RTL_FLAG_MAX
 639};
 640
 641struct rtl8169_stats {
 642        u64                     packets;
 643        u64                     bytes;
 644        struct u64_stats_sync   syncp;
 645};
 646
 647struct rtl8169_private {
 648        void __iomem *mmio_addr;        /* memory map physical address */
 649        struct pci_dev *pci_dev;
 650        struct net_device *dev;
 651        struct phy_device *phydev;
 652        struct napi_struct napi;
 653        u32 msg_enable;
 654        enum mac_version mac_version;
 655        u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 656        u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 657        u32 dirty_tx;
 658        struct rtl8169_stats rx_stats;
 659        struct rtl8169_stats tx_stats;
 660        struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 661        struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 662        dma_addr_t TxPhyAddr;
 663        dma_addr_t RxPhyAddr;
 664        struct page *Rx_databuff[NUM_RX_DESC];  /* Rx data buffers */
 665        struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 666        u16 cp_cmd;
 667        u32 irq_mask;
 668        struct clk *clk;
 669
 670        struct {
 671                DECLARE_BITMAP(flags, RTL_FLAG_MAX);
 672                struct mutex mutex;
 673                struct work_struct work;
 674        } wk;
 675
 676        unsigned irq_enabled:1;
 677        unsigned supports_gmii:1;
 678        unsigned aspm_manageable:1;
 679        dma_addr_t counters_phys_addr;
 680        struct rtl8169_counters *counters;
 681        struct rtl8169_tc_offsets tc_offset;
 682        u32 saved_wolopts;
 683
 684        const char *fw_name;
 685        struct rtl_fw *rtl_fw;
 686
 687        u32 ocp_base;
 688};
 689
 690typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
 691
 692MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 693MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 694module_param_named(debug, debug.msg_enable, int, 0);
 695MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 696MODULE_SOFTDEP("pre: realtek");
 697MODULE_LICENSE("GPL");
 698MODULE_FIRMWARE(FIRMWARE_8168D_1);
 699MODULE_FIRMWARE(FIRMWARE_8168D_2);
 700MODULE_FIRMWARE(FIRMWARE_8168E_1);
 701MODULE_FIRMWARE(FIRMWARE_8168E_2);
 702MODULE_FIRMWARE(FIRMWARE_8168E_3);
 703MODULE_FIRMWARE(FIRMWARE_8105E_1);
 704MODULE_FIRMWARE(FIRMWARE_8168F_1);
 705MODULE_FIRMWARE(FIRMWARE_8168F_2);
 706MODULE_FIRMWARE(FIRMWARE_8402_1);
 707MODULE_FIRMWARE(FIRMWARE_8411_1);
 708MODULE_FIRMWARE(FIRMWARE_8411_2);
 709MODULE_FIRMWARE(FIRMWARE_8106E_1);
 710MODULE_FIRMWARE(FIRMWARE_8106E_2);
 711MODULE_FIRMWARE(FIRMWARE_8168G_2);
 712MODULE_FIRMWARE(FIRMWARE_8168G_3);
 713MODULE_FIRMWARE(FIRMWARE_8168H_1);
 714MODULE_FIRMWARE(FIRMWARE_8168H_2);
 715MODULE_FIRMWARE(FIRMWARE_8107E_1);
 716MODULE_FIRMWARE(FIRMWARE_8107E_2);
 717MODULE_FIRMWARE(FIRMWARE_8125A_3);
 718
 719static inline struct device *tp_to_dev(struct rtl8169_private *tp)
 720{
 721        return &tp->pci_dev->dev;
 722}
 723
 724static void rtl_lock_work(struct rtl8169_private *tp)
 725{
 726        mutex_lock(&tp->wk.mutex);
 727}
 728
 729static void rtl_unlock_work(struct rtl8169_private *tp)
 730{
 731        mutex_unlock(&tp->wk.mutex);
 732}
 733
 734static void rtl_lock_config_regs(struct rtl8169_private *tp)
 735{
 736        RTL_W8(tp, Cfg9346, Cfg9346_Lock);
 737}
 738
 739static void rtl_unlock_config_regs(struct rtl8169_private *tp)
 740{
 741        RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
 742}
 743
 744static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
 745{
 746        pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
 747                                           PCI_EXP_DEVCTL_READRQ, force);
 748}
 749
 750static bool rtl_is_8125(struct rtl8169_private *tp)
 751{
 752        return tp->mac_version >= RTL_GIGA_MAC_VER_60;
 753}
 754
 755static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
 756{
 757        return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 758               tp->mac_version != RTL_GIGA_MAC_VER_39 &&
 759               tp->mac_version <= RTL_GIGA_MAC_VER_51;
 760}
 761
 762static bool rtl_supports_eee(struct rtl8169_private *tp)
 763{
 764        return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
 765               tp->mac_version != RTL_GIGA_MAC_VER_37 &&
 766               tp->mac_version != RTL_GIGA_MAC_VER_39;
 767}
 768
 769static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
 770{
 771        int i;
 772
 773        for (i = 0; i < ETH_ALEN; i++)
 774                mac[i] = RTL_R8(tp, reg + i);
 775}
 776
 777struct rtl_cond {
 778        bool (*check)(struct rtl8169_private *);
 779        const char *msg;
 780};
 781
 782static void rtl_udelay(unsigned int d)
 783{
 784        udelay(d);
 785}
 786
 787static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
 788                          void (*delay)(unsigned int), unsigned int d, int n,
 789                          bool high)
 790{
 791        int i;
 792
 793        for (i = 0; i < n; i++) {
 794                if (c->check(tp) == high)
 795                        return true;
 796                delay(d);
 797        }
 798        netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
 799                  c->msg, !high, n, d);
 800        return false;
 801}
 802
 803static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
 804                                      const struct rtl_cond *c,
 805                                      unsigned int d, int n)
 806{
 807        return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
 808}
 809
 810static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
 811                                     const struct rtl_cond *c,
 812                                     unsigned int d, int n)
 813{
 814        return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
 815}
 816
 817static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
 818                                      const struct rtl_cond *c,
 819                                      unsigned int d, int n)
 820{
 821        return rtl_loop_wait(tp, c, msleep, d, n, true);
 822}
 823
 824static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
 825                                     const struct rtl_cond *c,
 826                                     unsigned int d, int n)
 827{
 828        return rtl_loop_wait(tp, c, msleep, d, n, false);
 829}
 830
 831#define DECLARE_RTL_COND(name)                          \
 832static bool name ## _check(struct rtl8169_private *);   \
 833                                                        \
 834static const struct rtl_cond name = {                   \
 835        .check  = name ## _check,                       \
 836        .msg    = #name                                 \
 837};                                                      \
 838                                                        \
 839static bool name ## _check(struct rtl8169_private *tp)
 840
 841static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
 842{
 843        if (reg & 0xffff0001) {
 844                netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
 845                return true;
 846        }
 847        return false;
 848}
 849
 850DECLARE_RTL_COND(rtl_ocp_gphy_cond)
 851{
 852        return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
 853}
 854
 855static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 856{
 857        if (rtl_ocp_reg_failure(tp, reg))
 858                return;
 859
 860        RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
 861
 862        rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
 863}
 864
 865static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
 866{
 867        if (rtl_ocp_reg_failure(tp, reg))
 868                return 0;
 869
 870        RTL_W32(tp, GPHY_OCP, reg << 15);
 871
 872        return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
 873                (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
 874}
 875
 876static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 877{
 878        if (rtl_ocp_reg_failure(tp, reg))
 879                return;
 880
 881        RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
 882}
 883
 884static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
 885{
 886        if (rtl_ocp_reg_failure(tp, reg))
 887                return 0;
 888
 889        RTL_W32(tp, OCPDR, reg << 15);
 890
 891        return RTL_R32(tp, OCPDR);
 892}
 893
 894static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
 895                                 u16 set)
 896{
 897        u16 data = r8168_mac_ocp_read(tp, reg);
 898
 899        r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
 900}
 901
 902#define OCP_STD_PHY_BASE        0xa400
 903
 904static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
 905{
 906        if (reg == 0x1f) {
 907                tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
 908                return;
 909        }
 910
 911        if (tp->ocp_base != OCP_STD_PHY_BASE)
 912                reg -= 0x10;
 913
 914        r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
 915}
 916
 917static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
 918{
 919        if (reg == 0x1f)
 920                return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
 921
 922        if (tp->ocp_base != OCP_STD_PHY_BASE)
 923                reg -= 0x10;
 924
 925        return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 926}
 927
 928static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
 929{
 930        if (reg == 0x1f) {
 931                tp->ocp_base = value << 4;
 932                return;
 933        }
 934
 935        r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
 936}
 937
 938static int mac_mcu_read(struct rtl8169_private *tp, int reg)
 939{
 940        return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
 941}
 942
 943DECLARE_RTL_COND(rtl_phyar_cond)
 944{
 945        return RTL_R32(tp, PHYAR) & 0x80000000;
 946}
 947
 948static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
 949{
 950        RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
 951
 952        rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
 953        /*
 954         * According to hardware specs a 20us delay is required after write
 955         * complete indication, but before sending next command.
 956         */
 957        udelay(20);
 958}
 959
 960static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
 961{
 962        int value;
 963
 964        RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
 965
 966        value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
 967                RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
 968
 969        /*
 970         * According to hardware specs a 20us delay is required after read
 971         * complete indication, but before sending next command.
 972         */
 973        udelay(20);
 974
 975        return value;
 976}
 977
 978DECLARE_RTL_COND(rtl_ocpar_cond)
 979{
 980        return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
 981}
 982
 983static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
 984{
 985        RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 986        RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
 987        RTL_W32(tp, EPHY_RXER_NUM, 0);
 988
 989        rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
 990}
 991
 992static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
 993{
 994        r8168dp_1_mdio_access(tp, reg,
 995                              OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
 996}
 997
 998static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
 999{
1000        r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1001
1002        mdelay(1);
1003        RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1004        RTL_W32(tp, EPHY_RXER_NUM, 0);
1005
1006        return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1007                RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1008}
1009
1010#define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
1011
1012static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1013{
1014        RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1015}
1016
1017static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1018{
1019        RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1020}
1021
1022static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1023{
1024        r8168dp_2_mdio_start(tp);
1025
1026        r8169_mdio_write(tp, reg, value);
1027
1028        r8168dp_2_mdio_stop(tp);
1029}
1030
1031static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1032{
1033        int value;
1034
1035        /* Work around issue with chip reporting wrong PHY ID */
1036        if (reg == MII_PHYSID2)
1037                return 0xc912;
1038
1039        r8168dp_2_mdio_start(tp);
1040
1041        value = r8169_mdio_read(tp, reg);
1042
1043        r8168dp_2_mdio_stop(tp);
1044
1045        return value;
1046}
1047
1048static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1049{
1050        switch (tp->mac_version) {
1051        case RTL_GIGA_MAC_VER_27:
1052                r8168dp_1_mdio_write(tp, location, val);
1053                break;
1054        case RTL_GIGA_MAC_VER_28:
1055        case RTL_GIGA_MAC_VER_31:
1056                r8168dp_2_mdio_write(tp, location, val);
1057                break;
1058        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1059                r8168g_mdio_write(tp, location, val);
1060                break;
1061        default:
1062                r8169_mdio_write(tp, location, val);
1063                break;
1064        }
1065}
1066
1067static int rtl_readphy(struct rtl8169_private *tp, int location)
1068{
1069        switch (tp->mac_version) {
1070        case RTL_GIGA_MAC_VER_27:
1071                return r8168dp_1_mdio_read(tp, location);
1072        case RTL_GIGA_MAC_VER_28:
1073        case RTL_GIGA_MAC_VER_31:
1074                return r8168dp_2_mdio_read(tp, location);
1075        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1076                return r8168g_mdio_read(tp, location);
1077        default:
1078                return r8169_mdio_read(tp, location);
1079        }
1080}
1081
1082static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1083{
1084        rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1085}
1086
1087static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1088{
1089        int val;
1090
1091        val = rtl_readphy(tp, reg_addr);
1092        rtl_writephy(tp, reg_addr, (val & ~m) | p);
1093}
1094
1095DECLARE_RTL_COND(rtl_ephyar_cond)
1096{
1097        return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1098}
1099
1100static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1101{
1102        RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1103                (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1104
1105        rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1106
1107        udelay(10);
1108}
1109
1110static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1111{
1112        RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1113
1114        return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1115                RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1116}
1117
1118DECLARE_RTL_COND(rtl_eriar_cond)
1119{
1120        return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1121}
1122
1123static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1124                           u32 val, int type)
1125{
1126        BUG_ON((addr & 3) || (mask == 0));
1127        RTL_W32(tp, ERIDR, val);
1128        RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1129
1130        rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1131}
1132
1133static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1134                          u32 val)
1135{
1136        _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1137}
1138
1139static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1140{
1141        RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1142
1143        return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1144                RTL_R32(tp, ERIDR) : ~0;
1145}
1146
1147static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1148{
1149        return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1150}
1151
1152static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1153                         u32 m)
1154{
1155        u32 val;
1156
1157        val = rtl_eri_read(tp, addr);
1158        rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1159}
1160
1161static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1162                             u32 p)
1163{
1164        rtl_w0w1_eri(tp, addr, mask, p, 0);
1165}
1166
1167static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1168                               u32 m)
1169{
1170        rtl_w0w1_eri(tp, addr, mask, 0, m);
1171}
1172
1173static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1174{
1175        RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1176        return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1177                RTL_R32(tp, OCPDR) : ~0;
1178}
1179
1180static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1181{
1182        return _rtl_eri_read(tp, reg, ERIAR_OOB);
1183}
1184
1185static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1186                              u32 data)
1187{
1188        RTL_W32(tp, OCPDR, data);
1189        RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1190        rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1191}
1192
1193static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1194                              u32 data)
1195{
1196        _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1197                       data, ERIAR_OOB);
1198}
1199
1200static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1201{
1202        rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1203
1204        r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1205}
1206
1207#define OOB_CMD_RESET           0x00
1208#define OOB_CMD_DRIVER_START    0x05
1209#define OOB_CMD_DRIVER_STOP     0x06
1210
1211static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1212{
1213        return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1214}
1215
1216DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1217{
1218        u16 reg;
1219
1220        reg = rtl8168_get_ocp_reg(tp);
1221
1222        return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1223}
1224
1225DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1226{
1227        return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1228}
1229
1230DECLARE_RTL_COND(rtl_ocp_tx_cond)
1231{
1232        return RTL_R8(tp, IBISR0) & 0x20;
1233}
1234
1235static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1236{
1237        RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1238        rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1239        RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1240        RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1241}
1242
1243static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1244{
1245        r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1246        rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1247}
1248
1249static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1250{
1251        r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1252        r8168ep_ocp_write(tp, 0x01, 0x30,
1253                          r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1254        rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1255}
1256
1257static void rtl8168_driver_start(struct rtl8169_private *tp)
1258{
1259        switch (tp->mac_version) {
1260        case RTL_GIGA_MAC_VER_27:
1261        case RTL_GIGA_MAC_VER_28:
1262        case RTL_GIGA_MAC_VER_31:
1263                rtl8168dp_driver_start(tp);
1264                break;
1265        case RTL_GIGA_MAC_VER_49:
1266        case RTL_GIGA_MAC_VER_50:
1267        case RTL_GIGA_MAC_VER_51:
1268                rtl8168ep_driver_start(tp);
1269                break;
1270        default:
1271                BUG();
1272                break;
1273        }
1274}
1275
1276static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1277{
1278        r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1279        rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1280}
1281
1282static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1283{
1284        rtl8168ep_stop_cmac(tp);
1285        r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1286        r8168ep_ocp_write(tp, 0x01, 0x30,
1287                          r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1288        rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1289}
1290
1291static void rtl8168_driver_stop(struct rtl8169_private *tp)
1292{
1293        switch (tp->mac_version) {
1294        case RTL_GIGA_MAC_VER_27:
1295        case RTL_GIGA_MAC_VER_28:
1296        case RTL_GIGA_MAC_VER_31:
1297                rtl8168dp_driver_stop(tp);
1298                break;
1299        case RTL_GIGA_MAC_VER_49:
1300        case RTL_GIGA_MAC_VER_50:
1301        case RTL_GIGA_MAC_VER_51:
1302                rtl8168ep_driver_stop(tp);
1303                break;
1304        default:
1305                BUG();
1306                break;
1307        }
1308}
1309
1310static bool r8168dp_check_dash(struct rtl8169_private *tp)
1311{
1312        u16 reg = rtl8168_get_ocp_reg(tp);
1313
1314        return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1315}
1316
1317static bool r8168ep_check_dash(struct rtl8169_private *tp)
1318{
1319        return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1320}
1321
1322static bool r8168_check_dash(struct rtl8169_private *tp)
1323{
1324        switch (tp->mac_version) {
1325        case RTL_GIGA_MAC_VER_27:
1326        case RTL_GIGA_MAC_VER_28:
1327        case RTL_GIGA_MAC_VER_31:
1328                return r8168dp_check_dash(tp);
1329        case RTL_GIGA_MAC_VER_49:
1330        case RTL_GIGA_MAC_VER_50:
1331        case RTL_GIGA_MAC_VER_51:
1332                return r8168ep_check_dash(tp);
1333        default:
1334                return false;
1335        }
1336}
1337
1338static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1339{
1340        rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1341        rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1342}
1343
1344DECLARE_RTL_COND(rtl_efusear_cond)
1345{
1346        return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1347}
1348
1349static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1350{
1351        RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1352
1353        return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1354                RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1355}
1356
1357static u32 rtl_get_events(struct rtl8169_private *tp)
1358{
1359        if (rtl_is_8125(tp))
1360                return RTL_R32(tp, IntrStatus_8125);
1361        else
1362                return RTL_R16(tp, IntrStatus);
1363}
1364
1365static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1366{
1367        if (rtl_is_8125(tp))
1368                RTL_W32(tp, IntrStatus_8125, bits);
1369        else
1370                RTL_W16(tp, IntrStatus, bits);
1371}
1372
1373static void rtl_irq_disable(struct rtl8169_private *tp)
1374{
1375        if (rtl_is_8125(tp))
1376                RTL_W32(tp, IntrMask_8125, 0);
1377        else
1378                RTL_W16(tp, IntrMask, 0);
1379        tp->irq_enabled = 0;
1380}
1381
1382#define RTL_EVENT_NAPI_RX       (RxOK | RxErr)
1383#define RTL_EVENT_NAPI_TX       (TxOK | TxErr)
1384#define RTL_EVENT_NAPI          (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1385
1386static void rtl_irq_enable(struct rtl8169_private *tp)
1387{
1388        tp->irq_enabled = 1;
1389        if (rtl_is_8125(tp))
1390                RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1391        else
1392                RTL_W16(tp, IntrMask, tp->irq_mask);
1393}
1394
1395static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1396{
1397        rtl_irq_disable(tp);
1398        rtl_ack_events(tp, 0xffffffff);
1399        /* PCI commit */
1400        RTL_R8(tp, ChipCmd);
1401}
1402
1403static void rtl_link_chg_patch(struct rtl8169_private *tp)
1404{
1405        struct net_device *dev = tp->dev;
1406        struct phy_device *phydev = tp->phydev;
1407
1408        if (!netif_running(dev))
1409                return;
1410
1411        if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1412            tp->mac_version == RTL_GIGA_MAC_VER_38) {
1413                if (phydev->speed == SPEED_1000) {
1414                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1415                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1416                } else if (phydev->speed == SPEED_100) {
1417                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1418                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1419                } else {
1420                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1421                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1422                }
1423                rtl_reset_packet_filter(tp);
1424        } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1425                   tp->mac_version == RTL_GIGA_MAC_VER_36) {
1426                if (phydev->speed == SPEED_1000) {
1427                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1428                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1429                } else {
1430                        rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1431                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1432                }
1433        } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1434                if (phydev->speed == SPEED_10) {
1435                        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1436                        rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1437                } else {
1438                        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1439                }
1440        }
1441}
1442
1443#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1444
1445static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1446{
1447        struct rtl8169_private *tp = netdev_priv(dev);
1448
1449        rtl_lock_work(tp);
1450        wol->supported = WAKE_ANY;
1451        wol->wolopts = tp->saved_wolopts;
1452        rtl_unlock_work(tp);
1453}
1454
1455static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1456{
1457        static const struct {
1458                u32 opt;
1459                u16 reg;
1460                u8  mask;
1461        } cfg[] = {
1462                { WAKE_PHY,   Config3, LinkUp },
1463                { WAKE_UCAST, Config5, UWF },
1464                { WAKE_BCAST, Config5, BWF },
1465                { WAKE_MCAST, Config5, MWF },
1466                { WAKE_ANY,   Config5, LanWake },
1467                { WAKE_MAGIC, Config3, MagicPacket }
1468        };
1469        unsigned int i, tmp = ARRAY_SIZE(cfg);
1470        u8 options;
1471
1472        rtl_unlock_config_regs(tp);
1473
1474        if (rtl_is_8168evl_up(tp)) {
1475                tmp--;
1476                if (wolopts & WAKE_MAGIC)
1477                        rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1478                                         MagicPacket_v2);
1479                else
1480                        rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1481                                           MagicPacket_v2);
1482        } else if (rtl_is_8125(tp)) {
1483                tmp--;
1484                if (wolopts & WAKE_MAGIC)
1485                        r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1486                else
1487                        r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1488        }
1489
1490        for (i = 0; i < tmp; i++) {
1491                options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1492                if (wolopts & cfg[i].opt)
1493                        options |= cfg[i].mask;
1494                RTL_W8(tp, cfg[i].reg, options);
1495        }
1496
1497        switch (tp->mac_version) {
1498        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1499                options = RTL_R8(tp, Config1) & ~PMEnable;
1500                if (wolopts)
1501                        options |= PMEnable;
1502                RTL_W8(tp, Config1, options);
1503                break;
1504        case RTL_GIGA_MAC_VER_34:
1505        case RTL_GIGA_MAC_VER_37:
1506        case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_51:
1507                options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1508                if (wolopts)
1509                        options |= PME_SIGNAL;
1510                RTL_W8(tp, Config2, options);
1511                break;
1512        default:
1513                break;
1514        }
1515
1516        rtl_lock_config_regs(tp);
1517
1518        device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1519}
1520
1521static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1522{
1523        struct rtl8169_private *tp = netdev_priv(dev);
1524        struct device *d = tp_to_dev(tp);
1525
1526        if (wol->wolopts & ~WAKE_ANY)
1527                return -EINVAL;
1528
1529        pm_runtime_get_noresume(d);
1530
1531        rtl_lock_work(tp);
1532
1533        tp->saved_wolopts = wol->wolopts;
1534
1535        if (pm_runtime_active(d))
1536                __rtl8169_set_wol(tp, tp->saved_wolopts);
1537
1538        rtl_unlock_work(tp);
1539
1540        pm_runtime_put_noidle(d);
1541
1542        return 0;
1543}
1544
1545static void rtl8169_get_drvinfo(struct net_device *dev,
1546                                struct ethtool_drvinfo *info)
1547{
1548        struct rtl8169_private *tp = netdev_priv(dev);
1549        struct rtl_fw *rtl_fw = tp->rtl_fw;
1550
1551        strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1552        strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1553        BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1554        if (rtl_fw)
1555                strlcpy(info->fw_version, rtl_fw->version,
1556                        sizeof(info->fw_version));
1557}
1558
1559static int rtl8169_get_regs_len(struct net_device *dev)
1560{
1561        return R8169_REGS_SIZE;
1562}
1563
1564static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1565        netdev_features_t features)
1566{
1567        struct rtl8169_private *tp = netdev_priv(dev);
1568
1569        if (dev->mtu > TD_MSS_MAX)
1570                features &= ~NETIF_F_ALL_TSO;
1571
1572        if (dev->mtu > JUMBO_1K &&
1573            tp->mac_version > RTL_GIGA_MAC_VER_06)
1574                features &= ~NETIF_F_IP_CSUM;
1575
1576        return features;
1577}
1578
1579static int rtl8169_set_features(struct net_device *dev,
1580                                netdev_features_t features)
1581{
1582        struct rtl8169_private *tp = netdev_priv(dev);
1583        u32 rx_config;
1584
1585        rtl_lock_work(tp);
1586
1587        rx_config = RTL_R32(tp, RxConfig);
1588        if (features & NETIF_F_RXALL)
1589                rx_config |= (AcceptErr | AcceptRunt);
1590        else
1591                rx_config &= ~(AcceptErr | AcceptRunt);
1592
1593        if (rtl_is_8125(tp)) {
1594                if (features & NETIF_F_HW_VLAN_CTAG_RX)
1595                        rx_config |= RX_VLAN_8125;
1596                else
1597                        rx_config &= ~RX_VLAN_8125;
1598        }
1599
1600        RTL_W32(tp, RxConfig, rx_config);
1601
1602        if (features & NETIF_F_RXCSUM)
1603                tp->cp_cmd |= RxChkSum;
1604        else
1605                tp->cp_cmd &= ~RxChkSum;
1606
1607        if (!rtl_is_8125(tp)) {
1608                if (features & NETIF_F_HW_VLAN_CTAG_RX)
1609                        tp->cp_cmd |= RxVlan;
1610                else
1611                        tp->cp_cmd &= ~RxVlan;
1612        }
1613
1614        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1615        RTL_R16(tp, CPlusCmd);
1616
1617        rtl_unlock_work(tp);
1618
1619        return 0;
1620}
1621
1622static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1623{
1624        return (skb_vlan_tag_present(skb)) ?
1625                TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1626}
1627
1628static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1629{
1630        u32 opts2 = le32_to_cpu(desc->opts2);
1631
1632        if (opts2 & RxVlanTag)
1633                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1634}
1635
1636static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1637                             void *p)
1638{
1639        struct rtl8169_private *tp = netdev_priv(dev);
1640        u32 __iomem *data = tp->mmio_addr;
1641        u32 *dw = p;
1642        int i;
1643
1644        rtl_lock_work(tp);
1645        for (i = 0; i < R8169_REGS_SIZE; i += 4)
1646                memcpy_fromio(dw++, data++, 4);
1647        rtl_unlock_work(tp);
1648}
1649
1650static u32 rtl8169_get_msglevel(struct net_device *dev)
1651{
1652        struct rtl8169_private *tp = netdev_priv(dev);
1653
1654        return tp->msg_enable;
1655}
1656
1657static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1658{
1659        struct rtl8169_private *tp = netdev_priv(dev);
1660
1661        tp->msg_enable = value;
1662}
1663
1664static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1665        "tx_packets",
1666        "rx_packets",
1667        "tx_errors",
1668        "rx_errors",
1669        "rx_missed",
1670        "align_errors",
1671        "tx_single_collisions",
1672        "tx_multi_collisions",
1673        "unicast",
1674        "broadcast",
1675        "multicast",
1676        "tx_aborted",
1677        "tx_underrun",
1678};
1679
1680static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1681{
1682        switch (sset) {
1683        case ETH_SS_STATS:
1684                return ARRAY_SIZE(rtl8169_gstrings);
1685        default:
1686                return -EOPNOTSUPP;
1687        }
1688}
1689
1690DECLARE_RTL_COND(rtl_counters_cond)
1691{
1692        return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1693}
1694
1695static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1696{
1697        dma_addr_t paddr = tp->counters_phys_addr;
1698        u32 cmd;
1699
1700        RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1701        RTL_R32(tp, CounterAddrHigh);
1702        cmd = (u64)paddr & DMA_BIT_MASK(32);
1703        RTL_W32(tp, CounterAddrLow, cmd);
1704        RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1705
1706        return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1707}
1708
1709static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1710{
1711        /*
1712         * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1713         * tally counters.
1714         */
1715        if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1716                return true;
1717
1718        return rtl8169_do_counters(tp, CounterReset);
1719}
1720
1721static bool rtl8169_update_counters(struct rtl8169_private *tp)
1722{
1723        u8 val = RTL_R8(tp, ChipCmd);
1724
1725        /*
1726         * Some chips are unable to dump tally counters when the receiver
1727         * is disabled. If 0xff chip may be in a PCI power-save state.
1728         */
1729        if (!(val & CmdRxEnb) || val == 0xff)
1730                return true;
1731
1732        return rtl8169_do_counters(tp, CounterDump);
1733}
1734
1735static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1736{
1737        struct rtl8169_counters *counters = tp->counters;
1738        bool ret = false;
1739
1740        /*
1741         * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1742         * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1743         * reset by a power cycle, while the counter values collected by the
1744         * driver are reset at every driver unload/load cycle.
1745         *
1746         * To make sure the HW values returned by @get_stats64 match the SW
1747         * values, we collect the initial values at first open(*) and use them
1748         * as offsets to normalize the values returned by @get_stats64.
1749         *
1750         * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1751         * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1752         * set at open time by rtl_hw_start.
1753         */
1754
1755        if (tp->tc_offset.inited)
1756                return true;
1757
1758        /* If both, reset and update fail, propagate to caller. */
1759        if (rtl8169_reset_counters(tp))
1760                ret = true;
1761
1762        if (rtl8169_update_counters(tp))
1763                ret = true;
1764
1765        tp->tc_offset.tx_errors = counters->tx_errors;
1766        tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1767        tp->tc_offset.tx_aborted = counters->tx_aborted;
1768        tp->tc_offset.inited = true;
1769
1770        return ret;
1771}
1772
1773static void rtl8169_get_ethtool_stats(struct net_device *dev,
1774                                      struct ethtool_stats *stats, u64 *data)
1775{
1776        struct rtl8169_private *tp = netdev_priv(dev);
1777        struct device *d = tp_to_dev(tp);
1778        struct rtl8169_counters *counters = tp->counters;
1779
1780        ASSERT_RTNL();
1781
1782        pm_runtime_get_noresume(d);
1783
1784        if (pm_runtime_active(d))
1785                rtl8169_update_counters(tp);
1786
1787        pm_runtime_put_noidle(d);
1788
1789        data[0] = le64_to_cpu(counters->tx_packets);
1790        data[1] = le64_to_cpu(counters->rx_packets);
1791        data[2] = le64_to_cpu(counters->tx_errors);
1792        data[3] = le32_to_cpu(counters->rx_errors);
1793        data[4] = le16_to_cpu(counters->rx_missed);
1794        data[5] = le16_to_cpu(counters->align_errors);
1795        data[6] = le32_to_cpu(counters->tx_one_collision);
1796        data[7] = le32_to_cpu(counters->tx_multi_collision);
1797        data[8] = le64_to_cpu(counters->rx_unicast);
1798        data[9] = le64_to_cpu(counters->rx_broadcast);
1799        data[10] = le32_to_cpu(counters->rx_multicast);
1800        data[11] = le16_to_cpu(counters->tx_aborted);
1801        data[12] = le16_to_cpu(counters->tx_underun);
1802}
1803
1804static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1805{
1806        switch(stringset) {
1807        case ETH_SS_STATS:
1808                memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1809                break;
1810        }
1811}
1812
1813/*
1814 * Interrupt coalescing
1815 *
1816 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1817 * >     8169, 8168 and 810x line of chipsets
1818 *
1819 * 8169, 8168, and 8136(810x) serial chipsets support it.
1820 *
1821 * > 2 - the Tx timer unit at gigabit speed
1822 *
1823 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1824 * (0xe0) bit 1 and bit 0.
1825 *
1826 * For 8169
1827 * bit[1:0] \ speed        1000M           100M            10M
1828 * 0 0                     320ns           2.56us          40.96us
1829 * 0 1                     2.56us          20.48us         327.7us
1830 * 1 0                     5.12us          40.96us         655.4us
1831 * 1 1                     10.24us         81.92us         1.31ms
1832 *
1833 * For the other
1834 * bit[1:0] \ speed        1000M           100M            10M
1835 * 0 0                     5us             2.56us          40.96us
1836 * 0 1                     40us            20.48us         327.7us
1837 * 1 0                     80us            40.96us         655.4us
1838 * 1 1                     160us           81.92us         1.31ms
1839 */
1840
1841/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1842struct rtl_coalesce_scale {
1843        /* Rx / Tx */
1844        u32 nsecs[2];
1845};
1846
1847/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1848struct rtl_coalesce_info {
1849        u32 speed;
1850        struct rtl_coalesce_scale scalev[4];    /* each CPlusCmd[0:1] case */
1851};
1852
1853/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1854#define rxtx_x1822(r, t) {              \
1855        {{(r),          (t)}},          \
1856        {{(r)*8,        (t)*8}},        \
1857        {{(r)*8*2,      (t)*8*2}},      \
1858        {{(r)*8*2*2,    (t)*8*2*2}},    \
1859}
1860static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1861        /* speed        delays:     rx00   tx00 */
1862        { SPEED_10,     rxtx_x1822(40960, 40960)        },
1863        { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1864        { SPEED_1000,   rxtx_x1822(  320,   320)        },
1865        { 0 },
1866};
1867
1868static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1869        /* speed        delays:     rx00   tx00 */
1870        { SPEED_10,     rxtx_x1822(40960, 40960)        },
1871        { SPEED_100,    rxtx_x1822( 2560,  2560)        },
1872        { SPEED_1000,   rxtx_x1822( 5000,  5000)        },
1873        { 0 },
1874};
1875#undef rxtx_x1822
1876
1877/* get rx/tx scale vector corresponding to current speed */
1878static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1879{
1880        struct rtl8169_private *tp = netdev_priv(dev);
1881        const struct rtl_coalesce_info *ci;
1882
1883        if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1884                ci = rtl_coalesce_info_8169;
1885        else
1886                ci = rtl_coalesce_info_8168_8136;
1887
1888        for (; ci->speed; ci++) {
1889                if (tp->phydev->speed == ci->speed)
1890                        return ci;
1891        }
1892
1893        return ERR_PTR(-ELNRNG);
1894}
1895
1896static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1897{
1898        struct rtl8169_private *tp = netdev_priv(dev);
1899        const struct rtl_coalesce_info *ci;
1900        const struct rtl_coalesce_scale *scale;
1901        struct {
1902                u32 *max_frames;
1903                u32 *usecs;
1904        } coal_settings [] = {
1905                { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1906                { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1907        }, *p = coal_settings;
1908        int i;
1909        u16 w;
1910
1911        if (rtl_is_8125(tp))
1912                return -EOPNOTSUPP;
1913
1914        memset(ec, 0, sizeof(*ec));
1915
1916        /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1917        ci = rtl_coalesce_info(dev);
1918        if (IS_ERR(ci))
1919                return PTR_ERR(ci);
1920
1921        scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1922
1923        /* read IntrMitigate and adjust according to scale */
1924        for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1925                *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1926                w >>= RTL_COALESCE_SHIFT;
1927                *p->usecs = w & RTL_COALESCE_MASK;
1928        }
1929
1930        for (i = 0; i < 2; i++) {
1931                p = coal_settings + i;
1932                *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1933
1934                /*
1935                 * ethtool_coalesce says it is illegal to set both usecs and
1936                 * max_frames to 0.
1937                 */
1938                if (!*p->usecs && !*p->max_frames)
1939                        *p->max_frames = 1;
1940        }
1941
1942        return 0;
1943}
1944
1945/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1946static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1947                        struct net_device *dev, u32 nsec, u16 *cp01)
1948{
1949        const struct rtl_coalesce_info *ci;
1950        u16 i;
1951
1952        ci = rtl_coalesce_info(dev);
1953        if (IS_ERR(ci))
1954                return ERR_CAST(ci);
1955
1956        for (i = 0; i < 4; i++) {
1957                u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1958                                        ci->scalev[i].nsecs[1]);
1959                if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1960                        *cp01 = i;
1961                        return &ci->scalev[i];
1962                }
1963        }
1964
1965        return ERR_PTR(-EINVAL);
1966}
1967
1968static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1969{
1970        struct rtl8169_private *tp = netdev_priv(dev);
1971        const struct rtl_coalesce_scale *scale;
1972        struct {
1973                u32 frames;
1974                u32 usecs;
1975        } coal_settings [] = {
1976                { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1977                { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1978        }, *p = coal_settings;
1979        u16 w = 0, cp01;
1980        int i;
1981
1982        if (rtl_is_8125(tp))
1983                return -EOPNOTSUPP;
1984
1985        scale = rtl_coalesce_choose_scale(dev,
1986                        max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1987        if (IS_ERR(scale))
1988                return PTR_ERR(scale);
1989
1990        for (i = 0; i < 2; i++, p++) {
1991                u32 units;
1992
1993                /*
1994                 * accept max_frames=1 we returned in rtl_get_coalesce.
1995                 * accept it not only when usecs=0 because of e.g. the following scenario:
1996                 *
1997                 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1998                 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1999                 * - then user does `ethtool -C eth0 rx-usecs 100`
2000                 *
2001                 * since ethtool sends to kernel whole ethtool_coalesce
2002                 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2003                 * we'll reject it below in `frames % 4 != 0`.
2004                 */
2005                if (p->frames == 1) {
2006                        p->frames = 0;
2007                }
2008
2009                units = p->usecs * 1000 / scale->nsecs[i];
2010                if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2011                        return -EINVAL;
2012
2013                w <<= RTL_COALESCE_SHIFT;
2014                w |= units;
2015                w <<= RTL_COALESCE_SHIFT;
2016                w |= p->frames >> 2;
2017        }
2018
2019        rtl_lock_work(tp);
2020
2021        RTL_W16(tp, IntrMitigate, swab16(w));
2022
2023        tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2024        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2025        RTL_R16(tp, CPlusCmd);
2026
2027        rtl_unlock_work(tp);
2028
2029        return 0;
2030}
2031
2032static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
2033{
2034        struct rtl8169_private *tp = netdev_priv(dev);
2035        struct device *d = tp_to_dev(tp);
2036        int ret;
2037
2038        if (!rtl_supports_eee(tp))
2039                return -EOPNOTSUPP;
2040
2041        pm_runtime_get_noresume(d);
2042
2043        if (!pm_runtime_active(d)) {
2044                ret = -EOPNOTSUPP;
2045        } else {
2046                ret = phy_ethtool_get_eee(tp->phydev, data);
2047        }
2048
2049        pm_runtime_put_noidle(d);
2050
2051        return ret;
2052}
2053
2054static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
2055{
2056        struct rtl8169_private *tp = netdev_priv(dev);
2057        struct device *d = tp_to_dev(tp);
2058        int ret;
2059
2060        if (!rtl_supports_eee(tp))
2061                return -EOPNOTSUPP;
2062
2063        pm_runtime_get_noresume(d);
2064
2065        if (!pm_runtime_active(d)) {
2066                ret = -EOPNOTSUPP;
2067                goto out;
2068        }
2069
2070        if (dev->phydev->autoneg == AUTONEG_DISABLE ||
2071            dev->phydev->duplex != DUPLEX_FULL) {
2072                ret = -EPROTONOSUPPORT;
2073                goto out;
2074        }
2075
2076        ret = phy_ethtool_set_eee(tp->phydev, data);
2077out:
2078        pm_runtime_put_noidle(d);
2079        return ret;
2080}
2081
2082static const struct ethtool_ops rtl8169_ethtool_ops = {
2083        .get_drvinfo            = rtl8169_get_drvinfo,
2084        .get_regs_len           = rtl8169_get_regs_len,
2085        .get_link               = ethtool_op_get_link,
2086        .get_coalesce           = rtl_get_coalesce,
2087        .set_coalesce           = rtl_set_coalesce,
2088        .get_msglevel           = rtl8169_get_msglevel,
2089        .set_msglevel           = rtl8169_set_msglevel,
2090        .get_regs               = rtl8169_get_regs,
2091        .get_wol                = rtl8169_get_wol,
2092        .set_wol                = rtl8169_set_wol,
2093        .get_strings            = rtl8169_get_strings,
2094        .get_sset_count         = rtl8169_get_sset_count,
2095        .get_ethtool_stats      = rtl8169_get_ethtool_stats,
2096        .get_ts_info            = ethtool_op_get_ts_info,
2097        .nway_reset             = phy_ethtool_nway_reset,
2098        .get_eee                = rtl8169_get_eee,
2099        .set_eee                = rtl8169_set_eee,
2100        .get_link_ksettings     = phy_ethtool_get_link_ksettings,
2101        .set_link_ksettings     = phy_ethtool_set_link_ksettings,
2102};
2103
2104static void rtl_enable_eee(struct rtl8169_private *tp)
2105{
2106        struct phy_device *phydev = tp->phydev;
2107        int supported = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2108
2109        if (supported > 0)
2110                phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, supported);
2111}
2112
2113static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2114{
2115        /*
2116         * The driver currently handles the 8168Bf and the 8168Be identically
2117         * but they can be identified more specifically through the test below
2118         * if needed:
2119         *
2120         * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2121         *
2122         * Same thing for the 8101Eb and the 8101Ec:
2123         *
2124         * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2125         */
2126        static const struct rtl_mac_info {
2127                u16 mask;
2128                u16 val;
2129                u16 mac_version;
2130        } mac_info[] = {
2131                /* 8125 family. */
2132                { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2133                { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2134
2135                /* 8168EP family. */
2136                { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2137                { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2138                { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2139
2140                /* 8168H family. */
2141                { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2142                { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2143
2144                /* 8168G family. */
2145                { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2146                { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2147                { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2148                { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2149
2150                /* 8168F family. */
2151                { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2152                { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2153                { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2154
2155                /* 8168E family. */
2156                { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2157                { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2158                { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2159
2160                /* 8168D family. */
2161                { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2162                { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2163
2164                /* 8168DP family. */
2165                { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2166                { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2167                { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2168
2169                /* 8168C family. */
2170                { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2171                { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2172                { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2173                { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2174                { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2175                { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2176                { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2177
2178                /* 8168B family. */
2179                { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2180                { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2181                { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2182
2183                /* 8101 family. */
2184                { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2185                { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2186                { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2187                { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2188                { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2189                { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2190                { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2191                { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2192                { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2193                { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2194                { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2195                { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2196                { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2197                { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2198                /* FIXME: where did these entries come from ? -- FR */
2199                { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2200                { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2201
2202                /* 8110 family. */
2203                { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2204                { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2205                { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2206                { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2207                { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2208
2209                /* Catch-all */
2210                { 0x000, 0x000, RTL_GIGA_MAC_NONE   }
2211        };
2212        const struct rtl_mac_info *p = mac_info;
2213        u16 reg = RTL_R32(tp, TxConfig) >> 20;
2214
2215        while ((reg & p->mask) != p->val)
2216                p++;
2217        tp->mac_version = p->mac_version;
2218
2219        if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2220                dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2221        } else if (!tp->supports_gmii) {
2222                if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2223                        tp->mac_version = RTL_GIGA_MAC_VER_43;
2224                else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2225                        tp->mac_version = RTL_GIGA_MAC_VER_47;
2226                else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2227                        tp->mac_version = RTL_GIGA_MAC_VER_48;
2228        }
2229}
2230
2231struct phy_reg {
2232        u16 reg;
2233        u16 val;
2234};
2235
2236static void __rtl_writephy_batch(struct rtl8169_private *tp,
2237                                 const struct phy_reg *regs, int len)
2238{
2239        while (len-- > 0) {
2240                rtl_writephy(tp, regs->reg, regs->val);
2241                regs++;
2242        }
2243}
2244
2245#define rtl_writephy_batch(tp, a) __rtl_writephy_batch(tp, a, ARRAY_SIZE(a))
2246
2247static void rtl_release_firmware(struct rtl8169_private *tp)
2248{
2249        if (tp->rtl_fw) {
2250                rtl_fw_release_firmware(tp->rtl_fw);
2251                kfree(tp->rtl_fw);
2252                tp->rtl_fw = NULL;
2253        }
2254}
2255
2256static void rtl_apply_firmware(struct rtl8169_private *tp)
2257{
2258        /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2259        if (tp->rtl_fw)
2260                rtl_fw_write_firmware(tp, tp->rtl_fw);
2261}
2262
2263static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2264{
2265        if (rtl_readphy(tp, reg) != val)
2266                netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2267        else
2268                rtl_apply_firmware(tp);
2269}
2270
2271static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2272{
2273        /* Adjust EEE LED frequency */
2274        if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2275                RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2276
2277        rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2278}
2279
2280static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2281{
2282        r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2283        r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2284}
2285
2286static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
2287{
2288        struct phy_device *phydev = tp->phydev;
2289
2290        phy_write(phydev, 0x1f, 0x0007);
2291        phy_write(phydev, 0x1e, 0x0020);
2292        phy_set_bits(phydev, 0x15, BIT(8));
2293
2294        phy_write(phydev, 0x1f, 0x0005);
2295        phy_write(phydev, 0x05, 0x8b85);
2296        phy_set_bits(phydev, 0x06, BIT(13));
2297
2298        phy_write(phydev, 0x1f, 0x0000);
2299}
2300
2301static void rtl8168g_config_eee_phy(struct rtl8169_private *tp)
2302{
2303        phy_modify_paged(tp->phydev, 0x0a43, 0x11, 0, BIT(4));
2304}
2305
2306static void rtl8168h_config_eee_phy(struct rtl8169_private *tp)
2307{
2308        struct phy_device *phydev = tp->phydev;
2309
2310        rtl8168g_config_eee_phy(tp);
2311
2312        phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
2313        phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
2314}
2315
2316static void rtl8125_config_eee_phy(struct rtl8169_private *tp)
2317{
2318        struct phy_device *phydev = tp->phydev;
2319
2320        rtl8168h_config_eee_phy(tp);
2321
2322        phy_modify_paged(phydev, 0xa6d, 0x12, 0x0001, 0x0000);
2323        phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
2324}
2325
2326static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2327{
2328        static const struct phy_reg phy_reg_init[] = {
2329                { 0x1f, 0x0001 },
2330                { 0x06, 0x006e },
2331                { 0x08, 0x0708 },
2332                { 0x15, 0x4000 },
2333                { 0x18, 0x65c7 },
2334
2335                { 0x1f, 0x0001 },
2336                { 0x03, 0x00a1 },
2337                { 0x02, 0x0008 },
2338                { 0x01, 0x0120 },
2339                { 0x00, 0x1000 },
2340                { 0x04, 0x0800 },
2341                { 0x04, 0x0000 },
2342
2343                { 0x03, 0xff41 },
2344                { 0x02, 0xdf60 },
2345                { 0x01, 0x0140 },
2346                { 0x00, 0x0077 },
2347                { 0x04, 0x7800 },
2348                { 0x04, 0x7000 },
2349
2350                { 0x03, 0x802f },
2351                { 0x02, 0x4f02 },
2352                { 0x01, 0x0409 },
2353                { 0x00, 0xf0f9 },
2354                { 0x04, 0x9800 },
2355                { 0x04, 0x9000 },
2356
2357                { 0x03, 0xdf01 },
2358                { 0x02, 0xdf20 },
2359                { 0x01, 0xff95 },
2360                { 0x00, 0xba00 },
2361                { 0x04, 0xa800 },
2362                { 0x04, 0xa000 },
2363
2364                { 0x03, 0xff41 },
2365                { 0x02, 0xdf20 },
2366                { 0x01, 0x0140 },
2367                { 0x00, 0x00bb },
2368                { 0x04, 0xb800 },
2369                { 0x04, 0xb000 },
2370
2371                { 0x03, 0xdf41 },
2372                { 0x02, 0xdc60 },
2373                { 0x01, 0x6340 },
2374                { 0x00, 0x007d },
2375                { 0x04, 0xd800 },
2376                { 0x04, 0xd000 },
2377
2378                { 0x03, 0xdf01 },
2379                { 0x02, 0xdf20 },
2380                { 0x01, 0x100a },
2381                { 0x00, 0xa0ff },
2382                { 0x04, 0xf800 },
2383                { 0x04, 0xf000 },
2384
2385                { 0x1f, 0x0000 },
2386                { 0x0b, 0x0000 },
2387                { 0x00, 0x9200 }
2388        };
2389
2390        rtl_writephy_batch(tp, phy_reg_init);
2391}
2392
2393static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2394{
2395        static const struct phy_reg phy_reg_init[] = {
2396                { 0x1f, 0x0002 },
2397                { 0x01, 0x90d0 },
2398                { 0x1f, 0x0000 }
2399        };
2400
2401        rtl_writephy_batch(tp, phy_reg_init);
2402}
2403
2404static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2405{
2406        struct pci_dev *pdev = tp->pci_dev;
2407
2408        if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2409            (pdev->subsystem_device != 0xe000))
2410                return;
2411
2412        rtl_writephy(tp, 0x1f, 0x0001);
2413        rtl_writephy(tp, 0x10, 0xf01b);
2414        rtl_writephy(tp, 0x1f, 0x0000);
2415}
2416
2417static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2418{
2419        static const struct phy_reg phy_reg_init[] = {
2420                { 0x1f, 0x0001 },
2421                { 0x04, 0x0000 },
2422                { 0x03, 0x00a1 },
2423                { 0x02, 0x0008 },
2424                { 0x01, 0x0120 },
2425                { 0x00, 0x1000 },
2426                { 0x04, 0x0800 },
2427                { 0x04, 0x9000 },
2428                { 0x03, 0x802f },
2429                { 0x02, 0x4f02 },
2430                { 0x01, 0x0409 },
2431                { 0x00, 0xf099 },
2432                { 0x04, 0x9800 },
2433                { 0x04, 0xa000 },
2434                { 0x03, 0xdf01 },
2435                { 0x02, 0xdf20 },
2436                { 0x01, 0xff95 },
2437                { 0x00, 0xba00 },
2438                { 0x04, 0xa800 },
2439                { 0x04, 0xf000 },
2440                { 0x03, 0xdf01 },
2441                { 0x02, 0xdf20 },
2442                { 0x01, 0x101a },
2443                { 0x00, 0xa0ff },
2444                { 0x04, 0xf800 },
2445                { 0x04, 0x0000 },
2446                { 0x1f, 0x0000 },
2447
2448                { 0x1f, 0x0001 },
2449                { 0x10, 0xf41b },
2450                { 0x14, 0xfb54 },
2451                { 0x18, 0xf5c7 },
2452                { 0x1f, 0x0000 },
2453
2454                { 0x1f, 0x0001 },
2455                { 0x17, 0x0cc0 },
2456                { 0x1f, 0x0000 }
2457        };
2458
2459        rtl_writephy_batch(tp, phy_reg_init);
2460
2461        rtl8169scd_hw_phy_config_quirk(tp);
2462}
2463
2464static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2465{
2466        static const struct phy_reg phy_reg_init[] = {
2467                { 0x1f, 0x0001 },
2468                { 0x04, 0x0000 },
2469                { 0x03, 0x00a1 },
2470                { 0x02, 0x0008 },
2471                { 0x01, 0x0120 },
2472                { 0x00, 0x1000 },
2473                { 0x04, 0x0800 },
2474                { 0x04, 0x9000 },
2475                { 0x03, 0x802f },
2476                { 0x02, 0x4f02 },
2477                { 0x01, 0x0409 },
2478                { 0x00, 0xf099 },
2479                { 0x04, 0x9800 },
2480                { 0x04, 0xa000 },
2481                { 0x03, 0xdf01 },
2482                { 0x02, 0xdf20 },
2483                { 0x01, 0xff95 },
2484                { 0x00, 0xba00 },
2485                { 0x04, 0xa800 },
2486                { 0x04, 0xf000 },
2487                { 0x03, 0xdf01 },
2488                { 0x02, 0xdf20 },
2489                { 0x01, 0x101a },
2490                { 0x00, 0xa0ff },
2491                { 0x04, 0xf800 },
2492                { 0x04, 0x0000 },
2493                { 0x1f, 0x0000 },
2494
2495                { 0x1f, 0x0001 },
2496                { 0x0b, 0x8480 },
2497                { 0x1f, 0x0000 },
2498
2499                { 0x1f, 0x0001 },
2500                { 0x18, 0x67c7 },
2501                { 0x04, 0x2000 },
2502                { 0x03, 0x002f },
2503                { 0x02, 0x4360 },
2504                { 0x01, 0x0109 },
2505                { 0x00, 0x3022 },
2506                { 0x04, 0x2800 },
2507                { 0x1f, 0x0000 },
2508
2509                { 0x1f, 0x0001 },
2510                { 0x17, 0x0cc0 },
2511                { 0x1f, 0x0000 }
2512        };
2513
2514        rtl_writephy_batch(tp, phy_reg_init);
2515}
2516
2517static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2518{
2519        static const struct phy_reg phy_reg_init[] = {
2520                { 0x10, 0xf41b },
2521                { 0x1f, 0x0000 }
2522        };
2523
2524        rtl_writephy(tp, 0x1f, 0x0001);
2525        rtl_patchphy(tp, 0x16, 1 << 0);
2526
2527        rtl_writephy_batch(tp, phy_reg_init);
2528}
2529
2530static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2531{
2532        static const struct phy_reg phy_reg_init[] = {
2533                { 0x1f, 0x0001 },
2534                { 0x10, 0xf41b },
2535                { 0x1f, 0x0000 }
2536        };
2537
2538        rtl_writephy_batch(tp, phy_reg_init);
2539}
2540
2541static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2542{
2543        static const struct phy_reg phy_reg_init[] = {
2544                { 0x1f, 0x0000 },
2545                { 0x1d, 0x0f00 },
2546                { 0x1f, 0x0002 },
2547                { 0x0c, 0x1ec8 },
2548                { 0x1f, 0x0000 }
2549        };
2550
2551        rtl_writephy_batch(tp, phy_reg_init);
2552}
2553
2554static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2555{
2556        static const struct phy_reg phy_reg_init[] = {
2557                { 0x1f, 0x0001 },
2558                { 0x1d, 0x3d98 },
2559                { 0x1f, 0x0000 }
2560        };
2561
2562        rtl_writephy(tp, 0x1f, 0x0000);
2563        rtl_patchphy(tp, 0x14, 1 << 5);
2564        rtl_patchphy(tp, 0x0d, 1 << 5);
2565
2566        rtl_writephy_batch(tp, phy_reg_init);
2567}
2568
2569static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2570{
2571        static const struct phy_reg phy_reg_init[] = {
2572                { 0x1f, 0x0001 },
2573                { 0x12, 0x2300 },
2574                { 0x1f, 0x0002 },
2575                { 0x00, 0x88d4 },
2576                { 0x01, 0x82b1 },
2577                { 0x03, 0x7002 },
2578                { 0x08, 0x9e30 },
2579                { 0x09, 0x01f0 },
2580                { 0x0a, 0x5500 },
2581                { 0x0c, 0x00c8 },
2582                { 0x1f, 0x0003 },
2583                { 0x12, 0xc096 },
2584                { 0x16, 0x000a },
2585                { 0x1f, 0x0000 },
2586                { 0x1f, 0x0000 },
2587                { 0x09, 0x2000 },
2588                { 0x09, 0x0000 }
2589        };
2590
2591        rtl_writephy_batch(tp, phy_reg_init);
2592
2593        rtl_patchphy(tp, 0x14, 1 << 5);
2594        rtl_patchphy(tp, 0x0d, 1 << 5);
2595        rtl_writephy(tp, 0x1f, 0x0000);
2596}
2597
2598static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2599{
2600        static const struct phy_reg phy_reg_init[] = {
2601                { 0x1f, 0x0001 },
2602                { 0x12, 0x2300 },
2603                { 0x03, 0x802f },
2604                { 0x02, 0x4f02 },
2605                { 0x01, 0x0409 },
2606                { 0x00, 0xf099 },
2607                { 0x04, 0x9800 },
2608                { 0x04, 0x9000 },
2609                { 0x1d, 0x3d98 },
2610                { 0x1f, 0x0002 },
2611                { 0x0c, 0x7eb8 },
2612                { 0x06, 0x0761 },
2613                { 0x1f, 0x0003 },
2614                { 0x16, 0x0f0a },
2615                { 0x1f, 0x0000 }
2616        };
2617
2618        rtl_writephy_batch(tp, phy_reg_init);
2619
2620        rtl_patchphy(tp, 0x16, 1 << 0);
2621        rtl_patchphy(tp, 0x14, 1 << 5);
2622        rtl_patchphy(tp, 0x0d, 1 << 5);
2623        rtl_writephy(tp, 0x1f, 0x0000);
2624}
2625
2626static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2627{
2628        static const struct phy_reg phy_reg_init[] = {
2629                { 0x1f, 0x0001 },
2630                { 0x12, 0x2300 },
2631                { 0x1d, 0x3d98 },
2632                { 0x1f, 0x0002 },
2633                { 0x0c, 0x7eb8 },
2634                { 0x06, 0x5461 },
2635                { 0x1f, 0x0003 },
2636                { 0x16, 0x0f0a },
2637                { 0x1f, 0x0000 }
2638        };
2639
2640        rtl_writephy_batch(tp, phy_reg_init);
2641
2642        rtl_patchphy(tp, 0x16, 1 << 0);
2643        rtl_patchphy(tp, 0x14, 1 << 5);
2644        rtl_patchphy(tp, 0x0d, 1 << 5);
2645        rtl_writephy(tp, 0x1f, 0x0000);
2646}
2647
2648static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2649{
2650        rtl8168c_3_hw_phy_config(tp);
2651}
2652
2653static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
2654        /* Channel Estimation */
2655        { 0x1f, 0x0001 },
2656        { 0x06, 0x4064 },
2657        { 0x07, 0x2863 },
2658        { 0x08, 0x059c },
2659        { 0x09, 0x26b4 },
2660        { 0x0a, 0x6a19 },
2661        { 0x0b, 0xdcc8 },
2662        { 0x10, 0xf06d },
2663        { 0x14, 0x7f68 },
2664        { 0x18, 0x7fd9 },
2665        { 0x1c, 0xf0ff },
2666        { 0x1d, 0x3d9c },
2667        { 0x1f, 0x0003 },
2668        { 0x12, 0xf49f },
2669        { 0x13, 0x070b },
2670        { 0x1a, 0x05ad },
2671        { 0x14, 0x94c0 },
2672
2673        /*
2674         * Tx Error Issue
2675         * Enhance line driver power
2676         */
2677        { 0x1f, 0x0002 },
2678        { 0x06, 0x5561 },
2679        { 0x1f, 0x0005 },
2680        { 0x05, 0x8332 },
2681        { 0x06, 0x5561 },
2682
2683        /*
2684         * Can not link to 1Gbps with bad cable
2685         * Decrease SNR threshold form 21.07dB to 19.04dB
2686         */
2687        { 0x1f, 0x0001 },
2688        { 0x17, 0x0cc0 },
2689
2690        { 0x1f, 0x0000 },
2691        { 0x0d, 0xf880 }
2692};
2693
2694static const struct phy_reg rtl8168d_1_phy_reg_init_1[] = {
2695        { 0x1f, 0x0002 },
2696        { 0x05, 0x669a },
2697        { 0x1f, 0x0005 },
2698        { 0x05, 0x8330 },
2699        { 0x06, 0x669a },
2700        { 0x1f, 0x0002 }
2701};
2702
2703static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2704{
2705        rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2706
2707        /*
2708         * Rx Error Issue
2709         * Fine Tune Switching regulator parameter
2710         */
2711        rtl_writephy(tp, 0x1f, 0x0002);
2712        rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2713        rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2714
2715        if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2716                int val;
2717
2718                rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2719
2720                val = rtl_readphy(tp, 0x0d);
2721
2722                if ((val & 0x00ff) != 0x006c) {
2723                        static const u32 set[] = {
2724                                0x0065, 0x0066, 0x0067, 0x0068,
2725                                0x0069, 0x006a, 0x006b, 0x006c
2726                        };
2727                        int i;
2728
2729                        rtl_writephy(tp, 0x1f, 0x0002);
2730
2731                        val &= 0xff00;
2732                        for (i = 0; i < ARRAY_SIZE(set); i++)
2733                                rtl_writephy(tp, 0x0d, val | set[i]);
2734                }
2735        } else {
2736                static const struct phy_reg phy_reg_init[] = {
2737                        { 0x1f, 0x0002 },
2738                        { 0x05, 0x6662 },
2739                        { 0x1f, 0x0005 },
2740                        { 0x05, 0x8330 },
2741                        { 0x06, 0x6662 }
2742                };
2743
2744                rtl_writephy_batch(tp, phy_reg_init);
2745        }
2746
2747        /* RSET couple improve */
2748        rtl_writephy(tp, 0x1f, 0x0002);
2749        rtl_patchphy(tp, 0x0d, 0x0300);
2750        rtl_patchphy(tp, 0x0f, 0x0010);
2751
2752        /* Fine tune PLL performance */
2753        rtl_writephy(tp, 0x1f, 0x0002);
2754        rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2755        rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2756
2757        rtl_writephy(tp, 0x1f, 0x0005);
2758        rtl_writephy(tp, 0x05, 0x001b);
2759
2760        rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2761
2762        rtl_writephy(tp, 0x1f, 0x0000);
2763}
2764
2765static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2766{
2767        rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_0);
2768
2769        if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2770                int val;
2771
2772                rtl_writephy_batch(tp, rtl8168d_1_phy_reg_init_1);
2773
2774                val = rtl_readphy(tp, 0x0d);
2775                if ((val & 0x00ff) != 0x006c) {
2776                        static const u32 set[] = {
2777                                0x0065, 0x0066, 0x0067, 0x0068,
2778                                0x0069, 0x006a, 0x006b, 0x006c
2779                        };
2780                        int i;
2781
2782                        rtl_writephy(tp, 0x1f, 0x0002);
2783
2784                        val &= 0xff00;
2785                        for (i = 0; i < ARRAY_SIZE(set); i++)
2786                                rtl_writephy(tp, 0x0d, val | set[i]);
2787                }
2788        } else {
2789                static const struct phy_reg phy_reg_init[] = {
2790                        { 0x1f, 0x0002 },
2791                        { 0x05, 0x2642 },
2792                        { 0x1f, 0x0005 },
2793                        { 0x05, 0x8330 },
2794                        { 0x06, 0x2642 }
2795                };
2796
2797                rtl_writephy_batch(tp, phy_reg_init);
2798        }
2799
2800        /* Fine tune PLL performance */
2801        rtl_writephy(tp, 0x1f, 0x0002);
2802        rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2803        rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2804
2805        /* Switching regulator Slew rate */
2806        rtl_writephy(tp, 0x1f, 0x0002);
2807        rtl_patchphy(tp, 0x0f, 0x0017);
2808
2809        rtl_writephy(tp, 0x1f, 0x0005);
2810        rtl_writephy(tp, 0x05, 0x001b);
2811
2812        rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2813
2814        rtl_writephy(tp, 0x1f, 0x0000);
2815}
2816
2817static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2818{
2819        static const struct phy_reg phy_reg_init[] = {
2820                { 0x1f, 0x0002 },
2821                { 0x10, 0x0008 },
2822                { 0x0d, 0x006c },
2823
2824                { 0x1f, 0x0000 },
2825                { 0x0d, 0xf880 },
2826
2827                { 0x1f, 0x0001 },
2828                { 0x17, 0x0cc0 },
2829
2830                { 0x1f, 0x0001 },
2831                { 0x0b, 0xa4d8 },
2832                { 0x09, 0x281c },
2833                { 0x07, 0x2883 },
2834                { 0x0a, 0x6b35 },
2835                { 0x1d, 0x3da4 },
2836                { 0x1c, 0xeffd },
2837                { 0x14, 0x7f52 },
2838                { 0x18, 0x7fc6 },
2839                { 0x08, 0x0601 },
2840                { 0x06, 0x4063 },
2841                { 0x10, 0xf074 },
2842                { 0x1f, 0x0003 },
2843                { 0x13, 0x0789 },
2844                { 0x12, 0xf4bd },
2845                { 0x1a, 0x04fd },
2846                { 0x14, 0x84b0 },
2847                { 0x1f, 0x0000 },
2848                { 0x00, 0x9200 },
2849
2850                { 0x1f, 0x0005 },
2851                { 0x01, 0x0340 },
2852                { 0x1f, 0x0001 },
2853                { 0x04, 0x4000 },
2854                { 0x03, 0x1d21 },
2855                { 0x02, 0x0c32 },
2856                { 0x01, 0x0200 },
2857                { 0x00, 0x5554 },
2858                { 0x04, 0x4800 },
2859                { 0x04, 0x4000 },
2860                { 0x04, 0xf000 },
2861                { 0x03, 0xdf01 },
2862                { 0x02, 0xdf20 },
2863                { 0x01, 0x101a },
2864                { 0x00, 0xa0ff },
2865                { 0x04, 0xf800 },
2866                { 0x04, 0xf000 },
2867                { 0x1f, 0x0000 },
2868
2869                { 0x1f, 0x0007 },
2870                { 0x1e, 0x0023 },
2871                { 0x16, 0x0000 },
2872                { 0x1f, 0x0000 }
2873        };
2874
2875        rtl_writephy_batch(tp, phy_reg_init);
2876}
2877
2878static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2879{
2880        static const struct phy_reg phy_reg_init[] = {
2881                { 0x1f, 0x0001 },
2882                { 0x17, 0x0cc0 },
2883
2884                { 0x1f, 0x0007 },
2885                { 0x1e, 0x002d },
2886                { 0x18, 0x0040 },
2887                { 0x1f, 0x0000 }
2888        };
2889
2890        rtl_writephy_batch(tp, phy_reg_init);
2891        rtl_patchphy(tp, 0x0d, 1 << 5);
2892}
2893
2894static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2895{
2896        static const struct phy_reg phy_reg_init[] = {
2897                /* Enable Delay cap */
2898                { 0x1f, 0x0005 },
2899                { 0x05, 0x8b80 },
2900                { 0x06, 0xc896 },
2901                { 0x1f, 0x0000 },
2902
2903                /* Channel estimation fine tune */
2904                { 0x1f, 0x0001 },
2905                { 0x0b, 0x6c20 },
2906                { 0x07, 0x2872 },
2907                { 0x1c, 0xefff },
2908                { 0x1f, 0x0003 },
2909                { 0x14, 0x6420 },
2910                { 0x1f, 0x0000 },
2911
2912                /* Update PFM & 10M TX idle timer */
2913                { 0x1f, 0x0007 },
2914                { 0x1e, 0x002f },
2915                { 0x15, 0x1919 },
2916                { 0x1f, 0x0000 },
2917
2918                { 0x1f, 0x0007 },
2919                { 0x1e, 0x00ac },
2920                { 0x18, 0x0006 },
2921                { 0x1f, 0x0000 }
2922        };
2923
2924        rtl_apply_firmware(tp);
2925
2926        rtl_writephy_batch(tp, phy_reg_init);
2927
2928        /* DCO enable for 10M IDLE Power */
2929        rtl_writephy(tp, 0x1f, 0x0007);
2930        rtl_writephy(tp, 0x1e, 0x0023);
2931        rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
2932        rtl_writephy(tp, 0x1f, 0x0000);
2933
2934        /* For impedance matching */
2935        rtl_writephy(tp, 0x1f, 0x0002);
2936        rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
2937        rtl_writephy(tp, 0x1f, 0x0000);
2938
2939        /* PHY auto speed down */
2940        rtl_writephy(tp, 0x1f, 0x0007);
2941        rtl_writephy(tp, 0x1e, 0x002d);
2942        rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
2943        rtl_writephy(tp, 0x1f, 0x0000);
2944        rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
2945
2946        rtl_writephy(tp, 0x1f, 0x0005);
2947        rtl_writephy(tp, 0x05, 0x8b86);
2948        rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
2949        rtl_writephy(tp, 0x1f, 0x0000);
2950
2951        rtl_writephy(tp, 0x1f, 0x0005);
2952        rtl_writephy(tp, 0x05, 0x8b85);
2953        rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
2954        rtl_writephy(tp, 0x1f, 0x0007);
2955        rtl_writephy(tp, 0x1e, 0x0020);
2956        rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
2957        rtl_writephy(tp, 0x1f, 0x0006);
2958        rtl_writephy(tp, 0x00, 0x5a00);
2959        rtl_writephy(tp, 0x1f, 0x0000);
2960        rtl_writephy(tp, 0x0d, 0x0007);
2961        rtl_writephy(tp, 0x0e, 0x003c);
2962        rtl_writephy(tp, 0x0d, 0x4007);
2963        rtl_writephy(tp, 0x0e, 0x0000);
2964        rtl_writephy(tp, 0x0d, 0x0000);
2965}
2966
2967static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2968{
2969        const u16 w[] = {
2970                addr[0] | (addr[1] << 8),
2971                addr[2] | (addr[3] << 8),
2972                addr[4] | (addr[5] << 8)
2973        };
2974
2975        rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2976        rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2977        rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2978        rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2979}
2980
2981static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2982{
2983        static const struct phy_reg phy_reg_init[] = {
2984                /* Enable Delay cap */
2985                { 0x1f, 0x0004 },
2986                { 0x1f, 0x0007 },
2987                { 0x1e, 0x00ac },
2988                { 0x18, 0x0006 },
2989                { 0x1f, 0x0002 },
2990                { 0x1f, 0x0000 },
2991                { 0x1f, 0x0000 },
2992
2993                /* Channel estimation fine tune */
2994                { 0x1f, 0x0003 },
2995                { 0x09, 0xa20f },
2996                { 0x1f, 0x0000 },
2997                { 0x1f, 0x0000 },
2998
2999                /* Green Setting */
3000                { 0x1f, 0x0005 },
3001                { 0x05, 0x8b5b },
3002                { 0x06, 0x9222 },
3003                { 0x05, 0x8b6d },
3004                { 0x06, 0x8000 },
3005                { 0x05, 0x8b76 },
3006                { 0x06, 0x8000 },
3007                { 0x1f, 0x0000 }
3008        };
3009
3010        rtl_apply_firmware(tp);
3011
3012        rtl_writephy_batch(tp, phy_reg_init);
3013
3014        /* For 4-corner performance improve */
3015        rtl_writephy(tp, 0x1f, 0x0005);
3016        rtl_writephy(tp, 0x05, 0x8b80);
3017        rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3018        rtl_writephy(tp, 0x1f, 0x0000);
3019
3020        /* PHY auto speed down */
3021        rtl_writephy(tp, 0x1f, 0x0004);
3022        rtl_writephy(tp, 0x1f, 0x0007);
3023        rtl_writephy(tp, 0x1e, 0x002d);
3024        rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3025        rtl_writephy(tp, 0x1f, 0x0002);
3026        rtl_writephy(tp, 0x1f, 0x0000);
3027        rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3028
3029        /* improve 10M EEE waveform */
3030        rtl_writephy(tp, 0x1f, 0x0005);
3031        rtl_writephy(tp, 0x05, 0x8b86);
3032        rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3033        rtl_writephy(tp, 0x1f, 0x0000);
3034
3035        /* Improve 2-pair detection performance */
3036        rtl_writephy(tp, 0x1f, 0x0005);
3037        rtl_writephy(tp, 0x05, 0x8b85);
3038        rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3039        rtl_writephy(tp, 0x1f, 0x0000);
3040
3041        rtl8168f_config_eee_phy(tp);
3042        rtl_enable_eee(tp);
3043
3044        /* Green feature */
3045        rtl_writephy(tp, 0x1f, 0x0003);
3046        rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3047        rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3048        rtl_writephy(tp, 0x1f, 0x0000);
3049        rtl_writephy(tp, 0x1f, 0x0005);
3050        rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3051        rtl_writephy(tp, 0x1f, 0x0000);
3052
3053        /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3054        rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3055}
3056
3057static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3058{
3059        /* For 4-corner performance improve */
3060        rtl_writephy(tp, 0x1f, 0x0005);
3061        rtl_writephy(tp, 0x05, 0x8b80);
3062        rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3063        rtl_writephy(tp, 0x1f, 0x0000);
3064
3065        /* PHY auto speed down */
3066        rtl_writephy(tp, 0x1f, 0x0007);
3067        rtl_writephy(tp, 0x1e, 0x002d);
3068        rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3069        rtl_writephy(tp, 0x1f, 0x0000);
3070        rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3071
3072        /* Improve 10M EEE waveform */
3073        rtl_writephy(tp, 0x1f, 0x0005);
3074        rtl_writephy(tp, 0x05, 0x8b86);
3075        rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3076        rtl_writephy(tp, 0x1f, 0x0000);
3077
3078        rtl8168f_config_eee_phy(tp);
3079        rtl_enable_eee(tp);
3080}
3081
3082static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3083{
3084        static const struct phy_reg phy_reg_init[] = {
3085                /* Channel estimation fine tune */
3086                { 0x1f, 0x0003 },
3087                { 0x09, 0xa20f },
3088                { 0x1f, 0x0000 },
3089
3090                /* Modify green table for giga & fnet */
3091                { 0x1f, 0x0005 },
3092                { 0x05, 0x8b55 },
3093                { 0x06, 0x0000 },
3094                { 0x05, 0x8b5e },
3095                { 0x06, 0x0000 },
3096                { 0x05, 0x8b67 },
3097                { 0x06, 0x0000 },
3098                { 0x05, 0x8b70 },
3099                { 0x06, 0x0000 },
3100                { 0x1f, 0x0000 },
3101                { 0x1f, 0x0007 },
3102                { 0x1e, 0x0078 },
3103                { 0x17, 0x0000 },
3104                { 0x19, 0x00fb },
3105                { 0x1f, 0x0000 },
3106
3107                /* Modify green table for 10M */
3108                { 0x1f, 0x0005 },
3109                { 0x05, 0x8b79 },
3110                { 0x06, 0xaa00 },
3111                { 0x1f, 0x0000 },
3112
3113                /* Disable hiimpedance detection (RTCT) */
3114                { 0x1f, 0x0003 },
3115                { 0x01, 0x328a },
3116                { 0x1f, 0x0000 }
3117        };
3118
3119        rtl_apply_firmware(tp);
3120
3121        rtl_writephy_batch(tp, phy_reg_init);
3122
3123        rtl8168f_hw_phy_config(tp);
3124
3125        /* Improve 2-pair detection performance */
3126        rtl_writephy(tp, 0x1f, 0x0005);
3127        rtl_writephy(tp, 0x05, 0x8b85);
3128        rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3129        rtl_writephy(tp, 0x1f, 0x0000);
3130}
3131
3132static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3133{
3134        rtl_apply_firmware(tp);
3135
3136        rtl8168f_hw_phy_config(tp);
3137}
3138
3139static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3140{
3141        static const struct phy_reg phy_reg_init[] = {
3142                /* Channel estimation fine tune */
3143                { 0x1f, 0x0003 },
3144                { 0x09, 0xa20f },
3145                { 0x1f, 0x0000 },
3146
3147                /* Modify green table for giga & fnet */
3148                { 0x1f, 0x0005 },
3149                { 0x05, 0x8b55 },
3150                { 0x06, 0x0000 },
3151                { 0x05, 0x8b5e },
3152                { 0x06, 0x0000 },
3153                { 0x05, 0x8b67 },
3154                { 0x06, 0x0000 },
3155                { 0x05, 0x8b70 },
3156                { 0x06, 0x0000 },
3157                { 0x1f, 0x0000 },
3158                { 0x1f, 0x0007 },
3159                { 0x1e, 0x0078 },
3160                { 0x17, 0x0000 },
3161                { 0x19, 0x00aa },
3162                { 0x1f, 0x0000 },
3163
3164                /* Modify green table for 10M */
3165                { 0x1f, 0x0005 },
3166                { 0x05, 0x8b79 },
3167                { 0x06, 0xaa00 },
3168                { 0x1f, 0x0000 },
3169
3170                /* Disable hiimpedance detection (RTCT) */
3171                { 0x1f, 0x0003 },
3172                { 0x01, 0x328a },
3173                { 0x1f, 0x0000 }
3174        };
3175
3176
3177        rtl_apply_firmware(tp);
3178
3179        rtl8168f_hw_phy_config(tp);
3180
3181        /* Improve 2-pair detection performance */
3182        rtl_writephy(tp, 0x1f, 0x0005);
3183        rtl_writephy(tp, 0x05, 0x8b85);
3184        rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3185        rtl_writephy(tp, 0x1f, 0x0000);
3186
3187        rtl_writephy_batch(tp, phy_reg_init);
3188
3189        /* Modify green table for giga */
3190        rtl_writephy(tp, 0x1f, 0x0005);
3191        rtl_writephy(tp, 0x05, 0x8b54);
3192        rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3193        rtl_writephy(tp, 0x05, 0x8b5d);
3194        rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3195        rtl_writephy(tp, 0x05, 0x8a7c);
3196        rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3197        rtl_writephy(tp, 0x05, 0x8a7f);
3198        rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3199        rtl_writephy(tp, 0x05, 0x8a82);
3200        rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3201        rtl_writephy(tp, 0x05, 0x8a85);
3202        rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3203        rtl_writephy(tp, 0x05, 0x8a88);
3204        rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3205        rtl_writephy(tp, 0x1f, 0x0000);
3206
3207        /* uc same-seed solution */
3208        rtl_writephy(tp, 0x1f, 0x0005);
3209        rtl_writephy(tp, 0x05, 0x8b85);
3210        rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3211        rtl_writephy(tp, 0x1f, 0x0000);
3212
3213        /* Green feature */
3214        rtl_writephy(tp, 0x1f, 0x0003);
3215        rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3216        rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3217        rtl_writephy(tp, 0x1f, 0x0000);
3218}
3219
3220static void rtl8168g_disable_aldps(struct rtl8169_private *tp)
3221{
3222        phy_modify_paged(tp->phydev, 0x0a43, 0x10, BIT(2), 0);
3223}
3224
3225static void rtl8168g_phy_adjust_10m_aldps(struct rtl8169_private *tp)
3226{
3227        struct phy_device *phydev = tp->phydev;
3228
3229        phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
3230        phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
3231        phy_write(phydev, 0x1f, 0x0a43);
3232        phy_write(phydev, 0x13, 0x8084);
3233        phy_clear_bits(phydev, 0x14, BIT(14) | BIT(13));
3234        phy_set_bits(phydev, 0x10, BIT(12) | BIT(1) | BIT(0));
3235
3236        phy_write(phydev, 0x1f, 0x0000);
3237}
3238
3239static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3240{
3241        int ret;
3242
3243        rtl_apply_firmware(tp);
3244
3245        ret = phy_read_paged(tp->phydev, 0x0a46, 0x10);
3246        if (ret & BIT(8))
3247                phy_modify_paged(tp->phydev, 0x0bcc, 0x12, BIT(15), 0);
3248        else
3249                phy_modify_paged(tp->phydev, 0x0bcc, 0x12, 0, BIT(15));
3250
3251        ret = phy_read_paged(tp->phydev, 0x0a46, 0x13);
3252        if (ret & BIT(8))
3253                phy_modify_paged(tp->phydev, 0x0c41, 0x15, 0, BIT(1));
3254        else
3255                phy_modify_paged(tp->phydev, 0x0c41, 0x15, BIT(1), 0);
3256
3257        /* Enable PHY auto speed down */
3258        phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3259
3260        rtl8168g_phy_adjust_10m_aldps(tp);
3261
3262        /* EEE auto-fallback function */
3263        phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3264
3265        /* Enable UC LPF tune function */
3266        rtl_writephy(tp, 0x1f, 0x0a43);
3267        rtl_writephy(tp, 0x13, 0x8012);
3268        rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3269
3270        phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3271
3272        /* Improve SWR Efficiency */
3273        rtl_writephy(tp, 0x1f, 0x0bcd);
3274        rtl_writephy(tp, 0x14, 0x5065);
3275        rtl_writephy(tp, 0x14, 0xd065);
3276        rtl_writephy(tp, 0x1f, 0x0bc8);
3277        rtl_writephy(tp, 0x11, 0x5655);
3278        rtl_writephy(tp, 0x1f, 0x0bcd);
3279        rtl_writephy(tp, 0x14, 0x1065);
3280        rtl_writephy(tp, 0x14, 0x9065);
3281        rtl_writephy(tp, 0x14, 0x1065);
3282        rtl_writephy(tp, 0x1f, 0x0000);
3283
3284        rtl8168g_disable_aldps(tp);
3285        rtl8168g_config_eee_phy(tp);
3286        rtl_enable_eee(tp);
3287}
3288
3289static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3290{
3291        rtl_apply_firmware(tp);
3292        rtl8168g_config_eee_phy(tp);
3293        rtl_enable_eee(tp);
3294}
3295
3296static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3297{
3298        u16 dout_tapbin;
3299        u32 data;
3300
3301        rtl_apply_firmware(tp);
3302
3303        /* CHN EST parameters adjust - giga master */
3304        rtl_writephy(tp, 0x1f, 0x0a43);
3305        rtl_writephy(tp, 0x13, 0x809b);
3306        rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3307        rtl_writephy(tp, 0x13, 0x80a2);
3308        rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3309        rtl_writephy(tp, 0x13, 0x80a4);
3310        rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3311        rtl_writephy(tp, 0x13, 0x809c);
3312        rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3313        rtl_writephy(tp, 0x1f, 0x0000);
3314
3315        /* CHN EST parameters adjust - giga slave */
3316        rtl_writephy(tp, 0x1f, 0x0a43);
3317        rtl_writephy(tp, 0x13, 0x80ad);
3318        rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3319        rtl_writephy(tp, 0x13, 0x80b4);
3320        rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3321        rtl_writephy(tp, 0x13, 0x80ac);
3322        rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3323        rtl_writephy(tp, 0x1f, 0x0000);
3324
3325        /* CHN EST parameters adjust - fnet */
3326        rtl_writephy(tp, 0x1f, 0x0a43);
3327        rtl_writephy(tp, 0x13, 0x808e);
3328        rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3329        rtl_writephy(tp, 0x13, 0x8090);
3330        rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3331        rtl_writephy(tp, 0x13, 0x8092);
3332        rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3333        rtl_writephy(tp, 0x1f, 0x0000);
3334
3335        /* enable R-tune & PGA-retune function */
3336        dout_tapbin = 0;
3337        rtl_writephy(tp, 0x1f, 0x0a46);
3338        data = rtl_readphy(tp, 0x13);
3339        data &= 3;
3340        data <<= 2;
3341        dout_tapbin |= data;
3342        data = rtl_readphy(tp, 0x12);
3343        data &= 0xc000;
3344        data >>= 14;
3345        dout_tapbin |= data;
3346        dout_tapbin = ~(dout_tapbin^0x08);
3347        dout_tapbin <<= 12;
3348        dout_tapbin &= 0xf000;
3349        rtl_writephy(tp, 0x1f, 0x0a43);
3350        rtl_writephy(tp, 0x13, 0x827a);
3351        rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3352        rtl_writephy(tp, 0x13, 0x827b);
3353        rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3354        rtl_writephy(tp, 0x13, 0x827c);
3355        rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3356        rtl_writephy(tp, 0x13, 0x827d);
3357        rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3358
3359        rtl_writephy(tp, 0x1f, 0x0a43);
3360        rtl_writephy(tp, 0x13, 0x0811);
3361        rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3362        rtl_writephy(tp, 0x1f, 0x0a42);
3363        rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3364        rtl_writephy(tp, 0x1f, 0x0000);
3365
3366        /* enable GPHY 10M */
3367        phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3368
3369        /* SAR ADC performance */
3370        phy_modify_paged(tp->phydev, 0x0bca, 0x17, BIT(12) | BIT(13), BIT(14));
3371
3372        rtl_writephy(tp, 0x1f, 0x0a43);
3373        rtl_writephy(tp, 0x13, 0x803f);
3374        rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3375        rtl_writephy(tp, 0x13, 0x8047);
3376        rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3377        rtl_writephy(tp, 0x13, 0x804f);
3378        rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3379        rtl_writephy(tp, 0x13, 0x8057);
3380        rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3381        rtl_writephy(tp, 0x13, 0x805f);
3382        rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3383        rtl_writephy(tp, 0x13, 0x8067);
3384        rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3385        rtl_writephy(tp, 0x13, 0x806f);
3386        rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3387        rtl_writephy(tp, 0x1f, 0x0000);
3388
3389        /* disable phy pfm mode */
3390        phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3391
3392        rtl8168g_disable_aldps(tp);
3393        rtl8168h_config_eee_phy(tp);
3394        rtl_enable_eee(tp);
3395}
3396
3397static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3398{
3399        u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3400        u16 rlen;
3401        u32 data;
3402
3403        rtl_apply_firmware(tp);
3404
3405        /* CHIN EST parameter update */
3406        rtl_writephy(tp, 0x1f, 0x0a43);
3407        rtl_writephy(tp, 0x13, 0x808a);
3408        rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3409        rtl_writephy(tp, 0x1f, 0x0000);
3410
3411        /* enable R-tune & PGA-retune function */
3412        rtl_writephy(tp, 0x1f, 0x0a43);
3413        rtl_writephy(tp, 0x13, 0x0811);
3414        rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3415        rtl_writephy(tp, 0x1f, 0x0a42);
3416        rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3417        rtl_writephy(tp, 0x1f, 0x0000);
3418
3419        /* enable GPHY 10M */
3420        phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(11));
3421
3422        r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3423        data = r8168_mac_ocp_read(tp, 0xdd02);
3424        ioffset_p3 = ((data & 0x80)>>7);
3425        ioffset_p3 <<= 3;
3426
3427        data = r8168_mac_ocp_read(tp, 0xdd00);
3428        ioffset_p3 |= ((data & (0xe000))>>13);
3429        ioffset_p2 = ((data & (0x1e00))>>9);
3430        ioffset_p1 = ((data & (0x01e0))>>5);
3431        ioffset_p0 = ((data & 0x0010)>>4);
3432        ioffset_p0 <<= 3;
3433        ioffset_p0 |= (data & (0x07));
3434        data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3435
3436        if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3437            (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3438                rtl_writephy(tp, 0x1f, 0x0bcf);
3439                rtl_writephy(tp, 0x16, data);
3440                rtl_writephy(tp, 0x1f, 0x0000);
3441        }
3442
3443        /* Modify rlen (TX LPF corner frequency) level */
3444        rtl_writephy(tp, 0x1f, 0x0bcd);
3445        data = rtl_readphy(tp, 0x16);
3446        data &= 0x000f;
3447        rlen = 0;
3448        if (data > 3)
3449                rlen = data - 3;
3450        data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3451        rtl_writephy(tp, 0x17, data);
3452        rtl_writephy(tp, 0x1f, 0x0bcd);
3453        rtl_writephy(tp, 0x1f, 0x0000);
3454
3455        /* disable phy pfm mode */
3456        phy_modify_paged(tp->phydev, 0x0a44, 0x11, BIT(7), 0);
3457
3458        rtl8168g_disable_aldps(tp);
3459        rtl8168g_config_eee_phy(tp);
3460        rtl_enable_eee(tp);
3461}
3462
3463static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3464{
3465        /* Enable PHY auto speed down */
3466        phy_modify_paged(tp->phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
3467
3468        rtl8168g_phy_adjust_10m_aldps(tp);
3469
3470        /* Enable EEE auto-fallback function */
3471        phy_modify_paged(tp->phydev, 0x0a4b, 0x11, 0, BIT(2));
3472
3473        /* Enable UC LPF tune function */
3474        rtl_writephy(tp, 0x1f, 0x0a43);
3475        rtl_writephy(tp, 0x13, 0x8012);
3476        rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3477        rtl_writephy(tp, 0x1f, 0x0000);
3478
3479        /* set rg_sel_sdm_rate */
3480        phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3481
3482        rtl8168g_disable_aldps(tp);
3483        rtl8168g_config_eee_phy(tp);
3484        rtl_enable_eee(tp);
3485}
3486
3487static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3488{
3489        rtl8168g_phy_adjust_10m_aldps(tp);
3490
3491        /* Enable UC LPF tune function */
3492        rtl_writephy(tp, 0x1f, 0x0a43);
3493        rtl_writephy(tp, 0x13, 0x8012);
3494        rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3495        rtl_writephy(tp, 0x1f, 0x0000);
3496
3497        /* Set rg_sel_sdm_rate */
3498        phy_modify_paged(tp->phydev, 0x0c42, 0x11, BIT(13), BIT(14));
3499
3500        /* Channel estimation parameters */
3501        rtl_writephy(tp, 0x1f, 0x0a43);
3502        rtl_writephy(tp, 0x13, 0x80f3);
3503        rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3504        rtl_writephy(tp, 0x13, 0x80f0);
3505        rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3506        rtl_writephy(tp, 0x13, 0x80ef);
3507        rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3508        rtl_writephy(tp, 0x13, 0x80f6);
3509        rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3510        rtl_writephy(tp, 0x13, 0x80ec);
3511        rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3512        rtl_writephy(tp, 0x13, 0x80ed);
3513        rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3514        rtl_writephy(tp, 0x13, 0x80f2);
3515        rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3516        rtl_writephy(tp, 0x13, 0x80f4);
3517        rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3518        rtl_writephy(tp, 0x1f, 0x0a43);
3519        rtl_writephy(tp, 0x13, 0x8110);
3520        rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3521        rtl_writephy(tp, 0x13, 0x810f);
3522        rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3523        rtl_writephy(tp, 0x13, 0x8111);
3524        rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3525        rtl_writephy(tp, 0x13, 0x8113);
3526        rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3527        rtl_writephy(tp, 0x13, 0x8115);
3528        rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3529        rtl_writephy(tp, 0x13, 0x810e);
3530        rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3531        rtl_writephy(tp, 0x13, 0x810c);
3532        rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3533        rtl_writephy(tp, 0x13, 0x810b);
3534        rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3535        rtl_writephy(tp, 0x1f, 0x0a43);
3536        rtl_writephy(tp, 0x13, 0x80d1);
3537        rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3538        rtl_writephy(tp, 0x13, 0x80cd);
3539        rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3540        rtl_writephy(tp, 0x13, 0x80d3);
3541        rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3542        rtl_writephy(tp, 0x13, 0x80d5);
3543        rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3544        rtl_writephy(tp, 0x13, 0x80d7);
3545        rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3546
3547        /* Force PWM-mode */
3548        rtl_writephy(tp, 0x1f, 0x0bcd);
3549        rtl_writephy(tp, 0x14, 0x5065);
3550        rtl_writephy(tp, 0x14, 0xd065);
3551        rtl_writephy(tp, 0x1f, 0x0bc8);
3552        rtl_writephy(tp, 0x12, 0x00ed);
3553        rtl_writephy(tp, 0x1f, 0x0bcd);
3554        rtl_writephy(tp, 0x14, 0x1065);
3555        rtl_writephy(tp, 0x14, 0x9065);
3556        rtl_writephy(tp, 0x14, 0x1065);
3557        rtl_writephy(tp, 0x1f, 0x0000);
3558
3559        rtl8168g_disable_aldps(tp);
3560        rtl8168g_config_eee_phy(tp);
3561        rtl_enable_eee(tp);
3562}
3563
3564static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3565{
3566        static const struct phy_reg phy_reg_init[] = {
3567                { 0x1f, 0x0003 },
3568                { 0x08, 0x441d },
3569                { 0x01, 0x9100 },
3570                { 0x1f, 0x0000 }
3571        };
3572
3573        rtl_writephy(tp, 0x1f, 0x0000);
3574        rtl_patchphy(tp, 0x11, 1 << 12);
3575        rtl_patchphy(tp, 0x19, 1 << 13);
3576        rtl_patchphy(tp, 0x10, 1 << 15);
3577
3578        rtl_writephy_batch(tp, phy_reg_init);
3579}
3580
3581static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3582{
3583        static const struct phy_reg phy_reg_init[] = {
3584                { 0x1f, 0x0005 },
3585                { 0x1a, 0x0000 },
3586                { 0x1f, 0x0000 },
3587
3588                { 0x1f, 0x0004 },
3589                { 0x1c, 0x0000 },
3590                { 0x1f, 0x0000 },
3591
3592                { 0x1f, 0x0001 },
3593                { 0x15, 0x7701 },
3594                { 0x1f, 0x0000 }
3595        };
3596
3597        /* Disable ALDPS before ram code */
3598        rtl_writephy(tp, 0x1f, 0x0000);
3599        rtl_writephy(tp, 0x18, 0x0310);
3600        msleep(100);
3601
3602        rtl_apply_firmware(tp);
3603
3604        rtl_writephy_batch(tp, phy_reg_init);
3605}
3606
3607static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3608{
3609        /* Disable ALDPS before setting firmware */
3610        rtl_writephy(tp, 0x1f, 0x0000);
3611        rtl_writephy(tp, 0x18, 0x0310);
3612        msleep(20);
3613
3614        rtl_apply_firmware(tp);
3615
3616        /* EEE setting */
3617        rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3618        rtl_writephy(tp, 0x1f, 0x0004);
3619        rtl_writephy(tp, 0x10, 0x401f);
3620        rtl_writephy(tp, 0x19, 0x7030);
3621        rtl_writephy(tp, 0x1f, 0x0000);
3622}
3623
3624static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3625{
3626        static const struct phy_reg phy_reg_init[] = {
3627                { 0x1f, 0x0004 },
3628                { 0x10, 0xc07f },
3629                { 0x19, 0x7030 },
3630                { 0x1f, 0x0000 }
3631        };
3632
3633        /* Disable ALDPS before ram code */
3634        rtl_writephy(tp, 0x1f, 0x0000);
3635        rtl_writephy(tp, 0x18, 0x0310);
3636        msleep(100);
3637
3638        rtl_apply_firmware(tp);
3639
3640        rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3641        rtl_writephy_batch(tp, phy_reg_init);
3642
3643        rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3644}
3645
3646static void rtl8125_1_hw_phy_config(struct rtl8169_private *tp)
3647{
3648        struct phy_device *phydev = tp->phydev;
3649
3650        phy_modify_paged(phydev, 0xad4, 0x10, 0x03ff, 0x0084);
3651        phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3652        phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x0006);
3653        phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3654        phy_modify_paged(phydev, 0xac0, 0x14, 0x0000, 0x1100);
3655        phy_modify_paged(phydev, 0xac8, 0x15, 0xf000, 0x7000);
3656        phy_modify_paged(phydev, 0xad1, 0x14, 0x0000, 0x0400);
3657        phy_modify_paged(phydev, 0xad1, 0x15, 0x0000, 0x03ff);
3658        phy_modify_paged(phydev, 0xad1, 0x16, 0x0000, 0x03ff);
3659
3660        phy_write(phydev, 0x1f, 0x0a43);
3661        phy_write(phydev, 0x13, 0x80ea);
3662        phy_modify(phydev, 0x14, 0xff00, 0xc400);
3663        phy_write(phydev, 0x13, 0x80eb);
3664        phy_modify(phydev, 0x14, 0x0700, 0x0300);
3665        phy_write(phydev, 0x13, 0x80f8);
3666        phy_modify(phydev, 0x14, 0xff00, 0x1c00);
3667        phy_write(phydev, 0x13, 0x80f1);
3668        phy_modify(phydev, 0x14, 0xff00, 0x3000);
3669        phy_write(phydev, 0x13, 0x80fe);
3670        phy_modify(phydev, 0x14, 0xff00, 0xa500);
3671        phy_write(phydev, 0x13, 0x8102);
3672        phy_modify(phydev, 0x14, 0xff00, 0x5000);
3673        phy_write(phydev, 0x13, 0x8105);
3674        phy_modify(phydev, 0x14, 0xff00, 0x3300);
3675        phy_write(phydev, 0x13, 0x8100);
3676        phy_modify(phydev, 0x14, 0xff00, 0x7000);
3677        phy_write(phydev, 0x13, 0x8104);
3678        phy_modify(phydev, 0x14, 0xff00, 0xf000);
3679        phy_write(phydev, 0x13, 0x8106);
3680        phy_modify(phydev, 0x14, 0xff00, 0x6500);
3681        phy_write(phydev, 0x13, 0x80dc);
3682        phy_modify(phydev, 0x14, 0xff00, 0xed00);
3683        phy_write(phydev, 0x13, 0x80df);
3684        phy_set_bits(phydev, 0x14, BIT(8));
3685        phy_write(phydev, 0x13, 0x80e1);
3686        phy_clear_bits(phydev, 0x14, BIT(8));
3687        phy_write(phydev, 0x1f, 0x0000);
3688
3689        phy_modify_paged(phydev, 0xbf0, 0x13, 0x003f, 0x0038);
3690        phy_write_paged(phydev, 0xa43, 0x13, 0x819f);
3691        phy_write_paged(phydev, 0xa43, 0x14, 0xd0b6);
3692
3693        phy_write_paged(phydev, 0xbc3, 0x12, 0x5555);
3694        phy_modify_paged(phydev, 0xbf0, 0x15, 0x0e00, 0x0a00);
3695        phy_modify_paged(phydev, 0xa5c, 0x10, 0x0400, 0x0000);
3696        phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3697
3698        rtl8125_config_eee_phy(tp);
3699        rtl_enable_eee(tp);
3700}
3701
3702static void rtl8125_2_hw_phy_config(struct rtl8169_private *tp)
3703{
3704        struct phy_device *phydev = tp->phydev;
3705        int i;
3706
3707        phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
3708        phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
3709        phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
3710        phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
3711        phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
3712        phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
3713        phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
3714        phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
3715        phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
3716        phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
3717        phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
3718        phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
3719
3720        phy_write(phydev, 0x1f, 0x0b87);
3721        phy_write(phydev, 0x16, 0x80a2);
3722        phy_write(phydev, 0x17, 0x0153);
3723        phy_write(phydev, 0x16, 0x809c);
3724        phy_write(phydev, 0x17, 0x0153);
3725        phy_write(phydev, 0x1f, 0x0000);
3726
3727        phy_write(phydev, 0x1f, 0x0a43);
3728        phy_write(phydev, 0x13, 0x81B3);
3729        phy_write(phydev, 0x14, 0x0043);
3730        phy_write(phydev, 0x14, 0x00A7);
3731        phy_write(phydev, 0x14, 0x00D6);
3732        phy_write(phydev, 0x14, 0x00EC);
3733        phy_write(phydev, 0x14, 0x00F6);
3734        phy_write(phydev, 0x14, 0x00FB);
3735        phy_write(phydev, 0x14, 0x00FD);
3736        phy_write(phydev, 0x14, 0x00FF);
3737        phy_write(phydev, 0x14, 0x00BB);
3738        phy_write(phydev, 0x14, 0x0058);
3739        phy_write(phydev, 0x14, 0x0029);
3740        phy_write(phydev, 0x14, 0x0013);
3741        phy_write(phydev, 0x14, 0x0009);
3742        phy_write(phydev, 0x14, 0x0004);
3743        phy_write(phydev, 0x14, 0x0002);
3744        for (i = 0; i < 25; i++)
3745                phy_write(phydev, 0x14, 0x0000);
3746
3747        phy_write(phydev, 0x13, 0x8257);
3748        phy_write(phydev, 0x14, 0x020F);
3749
3750        phy_write(phydev, 0x13, 0x80EA);
3751        phy_write(phydev, 0x14, 0x7843);
3752        phy_write(phydev, 0x1f, 0x0000);
3753
3754        rtl_apply_firmware(tp);
3755
3756        phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
3757
3758        phy_write(phydev, 0x1f, 0x0a43);
3759        phy_write(phydev, 0x13, 0x81a2);
3760        phy_set_bits(phydev, 0x14, BIT(8));
3761        phy_write(phydev, 0x1f, 0x0000);
3762
3763        phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
3764        phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
3765        phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
3766        phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
3767        phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
3768        phy_modify_paged(phydev, 0xa44, 0x11, 0x0000, 0x0800);
3769
3770        rtl8125_config_eee_phy(tp);
3771        rtl_enable_eee(tp);
3772}
3773
3774static void rtl_hw_phy_config(struct net_device *dev)
3775{
3776        static const rtl_generic_fct phy_configs[] = {
3777                /* PCI devices. */
3778                [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
3779                [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
3780                [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
3781                [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
3782                [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
3783                /* PCI-E devices. */
3784                [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
3785                [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
3786                [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
3787                [RTL_GIGA_MAC_VER_10] = NULL,
3788                [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
3789                [RTL_GIGA_MAC_VER_12] = rtl8168bef_hw_phy_config,
3790                [RTL_GIGA_MAC_VER_13] = NULL,
3791                [RTL_GIGA_MAC_VER_14] = NULL,
3792                [RTL_GIGA_MAC_VER_15] = NULL,
3793                [RTL_GIGA_MAC_VER_16] = NULL,
3794                [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
3795                [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
3796                [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
3797                [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
3798                [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
3799                [RTL_GIGA_MAC_VER_22] = rtl8168c_4_hw_phy_config,
3800                [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
3801                [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
3802                [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
3803                [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
3804                [RTL_GIGA_MAC_VER_27] = rtl8168d_3_hw_phy_config,
3805                [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
3806                [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
3807                [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
3808                [RTL_GIGA_MAC_VER_31] = NULL,
3809                [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
3810                [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
3811                [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
3812                [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
3813                [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
3814                [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
3815                [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
3816                [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
3817                [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
3818                [RTL_GIGA_MAC_VER_41] = NULL,
3819                [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
3820                [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
3821                [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
3822                [RTL_GIGA_MAC_VER_45] = rtl8168h_1_hw_phy_config,
3823                [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
3824                [RTL_GIGA_MAC_VER_47] = rtl8168h_1_hw_phy_config,
3825                [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
3826                [RTL_GIGA_MAC_VER_49] = rtl8168ep_1_hw_phy_config,
3827                [RTL_GIGA_MAC_VER_50] = rtl8168ep_2_hw_phy_config,
3828                [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
3829                [RTL_GIGA_MAC_VER_60] = rtl8125_1_hw_phy_config,
3830                [RTL_GIGA_MAC_VER_61] = rtl8125_2_hw_phy_config,
3831        };
3832        struct rtl8169_private *tp = netdev_priv(dev);
3833
3834        if (phy_configs[tp->mac_version])
3835                phy_configs[tp->mac_version](tp);
3836}
3837
3838static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
3839{
3840        if (!test_and_set_bit(flag, tp->wk.flags))
3841                schedule_work(&tp->wk.work);
3842}
3843
3844static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3845{
3846        rtl_hw_phy_config(dev);
3847
3848        if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3849                pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3850                pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3851                netif_dbg(tp, drv, dev,
3852                          "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3853                RTL_W8(tp, 0x82, 0x01);
3854        }
3855
3856        /* We may have called phy_speed_down before */
3857        phy_speed_up(tp->phydev);
3858
3859        genphy_soft_reset(tp->phydev);
3860}
3861
3862static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3863{
3864        rtl_lock_work(tp);
3865
3866        rtl_unlock_config_regs(tp);
3867
3868        RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
3869        RTL_R32(tp, MAC4);
3870
3871        RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3872        RTL_R32(tp, MAC0);
3873
3874        if (tp->mac_version == RTL_GIGA_MAC_VER_34)
3875                rtl_rar_exgmac_set(tp, addr);
3876
3877        rtl_lock_config_regs(tp);
3878
3879        rtl_unlock_work(tp);
3880}
3881
3882static int rtl_set_mac_address(struct net_device *dev, void *p)
3883{
3884        struct rtl8169_private *tp = netdev_priv(dev);
3885        struct device *d = tp_to_dev(tp);
3886        int ret;
3887
3888        ret = eth_mac_addr(dev, p);
3889        if (ret)
3890                return ret;
3891
3892        pm_runtime_get_noresume(d);
3893
3894        if (pm_runtime_active(d))
3895                rtl_rar_set(tp, dev->dev_addr);
3896
3897        pm_runtime_put_noidle(d);
3898
3899        return 0;
3900}
3901
3902static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3903{
3904        struct rtl8169_private *tp = netdev_priv(dev);
3905
3906        if (!netif_running(dev))
3907                return -ENODEV;
3908
3909        return phy_mii_ioctl(tp->phydev, ifr, cmd);
3910}
3911
3912static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3913{
3914        switch (tp->mac_version) {
3915        case RTL_GIGA_MAC_VER_25:
3916        case RTL_GIGA_MAC_VER_26:
3917        case RTL_GIGA_MAC_VER_29:
3918        case RTL_GIGA_MAC_VER_30:
3919        case RTL_GIGA_MAC_VER_32:
3920        case RTL_GIGA_MAC_VER_33:
3921        case RTL_GIGA_MAC_VER_34:
3922        case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
3923                RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
3924                        AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3925                break;
3926        default:
3927                break;
3928        }
3929}
3930
3931static void rtl_pll_power_down(struct rtl8169_private *tp)
3932{
3933        if (r8168_check_dash(tp))
3934                return;
3935
3936        if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3937            tp->mac_version == RTL_GIGA_MAC_VER_33)
3938                rtl_ephy_write(tp, 0x19, 0xff64);
3939
3940        if (device_may_wakeup(tp_to_dev(tp))) {
3941                phy_speed_down(tp->phydev, false);
3942                rtl_wol_suspend_quirk(tp);
3943                return;
3944        }
3945
3946        switch (tp->mac_version) {
3947        case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3948        case RTL_GIGA_MAC_VER_37:
3949        case RTL_GIGA_MAC_VER_39:
3950        case RTL_GIGA_MAC_VER_43:
3951        case RTL_GIGA_MAC_VER_44:
3952        case RTL_GIGA_MAC_VER_45:
3953        case RTL_GIGA_MAC_VER_46:
3954        case RTL_GIGA_MAC_VER_47:
3955        case RTL_GIGA_MAC_VER_48:
3956        case RTL_GIGA_MAC_VER_50:
3957        case RTL_GIGA_MAC_VER_51:
3958        case RTL_GIGA_MAC_VER_60:
3959        case RTL_GIGA_MAC_VER_61:
3960                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3961                break;
3962        case RTL_GIGA_MAC_VER_40:
3963        case RTL_GIGA_MAC_VER_41:
3964        case RTL_GIGA_MAC_VER_49:
3965                rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3966                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
3967                break;
3968        default:
3969                break;
3970        }
3971}
3972
3973static void rtl_pll_power_up(struct rtl8169_private *tp)
3974{
3975        switch (tp->mac_version) {
3976        case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
3977        case RTL_GIGA_MAC_VER_37:
3978        case RTL_GIGA_MAC_VER_39:
3979        case RTL_GIGA_MAC_VER_43:
3980                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
3981                break;
3982        case RTL_GIGA_MAC_VER_44:
3983        case RTL_GIGA_MAC_VER_45:
3984        case RTL_GIGA_MAC_VER_46:
3985        case RTL_GIGA_MAC_VER_47:
3986        case RTL_GIGA_MAC_VER_48:
3987        case RTL_GIGA_MAC_VER_50:
3988        case RTL_GIGA_MAC_VER_51:
3989        case RTL_GIGA_MAC_VER_60:
3990        case RTL_GIGA_MAC_VER_61:
3991                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3992                break;
3993        case RTL_GIGA_MAC_VER_40:
3994        case RTL_GIGA_MAC_VER_41:
3995        case RTL_GIGA_MAC_VER_49:
3996                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
3997                rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
3998                break;
3999        default:
4000                break;
4001        }
4002
4003        phy_resume(tp->phydev);
4004        /* give MAC/PHY some time to resume */
4005        msleep(20);
4006}
4007
4008static void rtl_init_rxcfg(struct rtl8169_private *tp)
4009{
4010        switch (tp->mac_version) {
4011        case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4012        case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4013                RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4014                break;
4015        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4016        case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4017        case RTL_GIGA_MAC_VER_38:
4018                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4019                break;
4020        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4021                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4022                break;
4023        case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
4024                RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
4025                                      RX_DMA_BURST);
4026                break;
4027        default:
4028                RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4029                break;
4030        }
4031}
4032
4033static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4034{
4035        tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4036}
4037
4038static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4039{
4040        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4041        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4042        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4043}
4044
4045static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4046{
4047        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4048        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4049        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4050}
4051
4052static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4053{
4054        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4055}
4056
4057static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4058{
4059        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4060}
4061
4062static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4063{
4064        RTL_W8(tp, MaxTxPacketSize, 0x3f);
4065        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4066        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4067        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4068}
4069
4070static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4071{
4072        RTL_W8(tp, MaxTxPacketSize, 0x0c);
4073        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4074        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4075        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4076}
4077
4078static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4079{
4080        rtl_tx_performance_tweak(tp,
4081                PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4082}
4083
4084static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4085{
4086        rtl_tx_performance_tweak(tp,
4087                PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4088}
4089
4090static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4091{
4092        r8168b_0_hw_jumbo_enable(tp);
4093
4094        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4095}
4096
4097static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4098{
4099        r8168b_0_hw_jumbo_disable(tp);
4100
4101        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4102}
4103
4104static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4105{
4106        rtl_unlock_config_regs(tp);
4107        switch (tp->mac_version) {
4108        case RTL_GIGA_MAC_VER_11:
4109                r8168b_0_hw_jumbo_enable(tp);
4110                break;
4111        case RTL_GIGA_MAC_VER_12:
4112        case RTL_GIGA_MAC_VER_17:
4113                r8168b_1_hw_jumbo_enable(tp);
4114                break;
4115        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4116                r8168c_hw_jumbo_enable(tp);
4117                break;
4118        case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4119                r8168dp_hw_jumbo_enable(tp);
4120                break;
4121        case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4122                r8168e_hw_jumbo_enable(tp);
4123                break;
4124        default:
4125                break;
4126        }
4127        rtl_lock_config_regs(tp);
4128}
4129
4130static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4131{
4132        rtl_unlock_config_regs(tp);
4133        switch (tp->mac_version) {
4134        case RTL_GIGA_MAC_VER_11:
4135                r8168b_0_hw_jumbo_disable(tp);
4136                break;
4137        case RTL_GIGA_MAC_VER_12:
4138        case RTL_GIGA_MAC_VER_17:
4139                r8168b_1_hw_jumbo_disable(tp);
4140                break;
4141        case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
4142                r8168c_hw_jumbo_disable(tp);
4143                break;
4144        case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
4145                r8168dp_hw_jumbo_disable(tp);
4146                break;
4147        case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_34:
4148                r8168e_hw_jumbo_disable(tp);
4149                break;
4150        default:
4151                break;
4152        }
4153        rtl_lock_config_regs(tp);
4154}
4155
4156static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
4157{
4158        if (mtu > ETH_DATA_LEN)
4159                rtl_hw_jumbo_enable(tp);
4160        else
4161                rtl_hw_jumbo_disable(tp);
4162}
4163
4164DECLARE_RTL_COND(rtl_chipcmd_cond)
4165{
4166        return RTL_R8(tp, ChipCmd) & CmdReset;
4167}
4168
4169static void rtl_hw_reset(struct rtl8169_private *tp)
4170{
4171        RTL_W8(tp, ChipCmd, CmdReset);
4172
4173        rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4174}
4175
4176static void rtl_request_firmware(struct rtl8169_private *tp)
4177{
4178        struct rtl_fw *rtl_fw;
4179
4180        /* firmware loaded already or no firmware available */
4181        if (tp->rtl_fw || !tp->fw_name)
4182                return;
4183
4184        rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4185        if (!rtl_fw) {
4186                netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
4187                return;
4188        }
4189
4190        rtl_fw->phy_write = rtl_writephy;
4191        rtl_fw->phy_read = rtl_readphy;
4192        rtl_fw->mac_mcu_write = mac_mcu_write;
4193        rtl_fw->mac_mcu_read = mac_mcu_read;
4194        rtl_fw->fw_name = tp->fw_name;
4195        rtl_fw->dev = tp_to_dev(tp);
4196
4197        if (rtl_fw_request_firmware(rtl_fw))
4198                kfree(rtl_fw);
4199        else
4200                tp->rtl_fw = rtl_fw;
4201}
4202
4203static void rtl_rx_close(struct rtl8169_private *tp)
4204{
4205        RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4206}
4207
4208DECLARE_RTL_COND(rtl_npq_cond)
4209{
4210        return RTL_R8(tp, TxPoll) & NPQ;
4211}
4212
4213DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4214{
4215        return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4216}
4217
4218static void rtl8169_hw_reset(struct rtl8169_private *tp)
4219{
4220        /* Disable interrupts */
4221        rtl8169_irq_mask_and_ack(tp);
4222
4223        rtl_rx_close(tp);
4224
4225        switch (tp->mac_version) {
4226        case RTL_GIGA_MAC_VER_27:
4227        case RTL_GIGA_MAC_VER_28:
4228        case RTL_GIGA_MAC_VER_31:
4229                rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4230                break;
4231        case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4232        case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4233                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4234                rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4235                break;
4236        default:
4237                RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4238                udelay(100);
4239                break;
4240        }
4241
4242        rtl_hw_reset(tp);
4243}
4244
4245static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4246{
4247        u32 val = TX_DMA_BURST << TxDMAShift |
4248                  InterFrameGap << TxInterFrameGapShift;
4249
4250        if (rtl_is_8168evl_up(tp))
4251                val |= TXCFG_AUTO_FIFO;
4252
4253        RTL_W32(tp, TxConfig, val);
4254}
4255
4256static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4257{
4258        /* Low hurts. Let's disable the filtering. */
4259        RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4260}
4261
4262static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4263{
4264        /*
4265         * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4266         * register to be written before TxDescAddrLow to work.
4267         * Switching from MMIO to I/O access fixes the issue as well.
4268         */
4269        RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4270        RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4271        RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4272        RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4273}
4274
4275static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4276{
4277        u32 val;
4278
4279        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4280                val = 0x000fff00;
4281        else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
4282                val = 0x00ffff00;
4283        else
4284                return;
4285
4286        if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
4287                val |= 0xff;
4288
4289        RTL_W32(tp, 0x7c, val);
4290}
4291
4292static void rtl_set_rx_mode(struct net_device *dev)
4293{
4294        u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
4295        /* Multicast hash filter */
4296        u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
4297        struct rtl8169_private *tp = netdev_priv(dev);
4298        u32 tmp;
4299
4300        if (dev->flags & IFF_PROMISC) {
4301                /* Unconditionally log net taps. */
4302                netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4303                rx_mode |= AcceptAllPhys;
4304        } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
4305                   dev->flags & IFF_ALLMULTI ||
4306                   tp->mac_version == RTL_GIGA_MAC_VER_35) {
4307                /* accept all multicasts */
4308        } else if (netdev_mc_empty(dev)) {
4309                rx_mode &= ~AcceptMulticast;
4310        } else {
4311                struct netdev_hw_addr *ha;
4312
4313                mc_filter[1] = mc_filter[0] = 0;
4314                netdev_for_each_mc_addr(ha, dev) {
4315                        u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4316                        mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
4317                }
4318
4319                if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4320                        tmp = mc_filter[0];
4321                        mc_filter[0] = swab32(mc_filter[1]);
4322                        mc_filter[1] = swab32(tmp);
4323                }
4324        }
4325
4326        if (dev->features & NETIF_F_RXALL)
4327                rx_mode |= (AcceptErr | AcceptRunt);
4328
4329        RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4330        RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4331
4332        tmp = RTL_R32(tp, RxConfig);
4333        RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
4334}
4335
4336DECLARE_RTL_COND(rtl_csiar_cond)
4337{
4338        return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4339}
4340
4341static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4342{
4343        u32 func = PCI_FUNC(tp->pci_dev->devfn);
4344
4345        RTL_W32(tp, CSIDR, value);
4346        RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4347                CSIAR_BYTE_ENABLE | func << 16);
4348
4349        rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4350}
4351
4352static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4353{
4354        u32 func = PCI_FUNC(tp->pci_dev->devfn);
4355
4356        RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4357                CSIAR_BYTE_ENABLE);
4358
4359        return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4360                RTL_R32(tp, CSIDR) : ~0;
4361}
4362
4363static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4364{
4365        struct pci_dev *pdev = tp->pci_dev;
4366        u32 csi;
4367
4368        /* According to Realtek the value at config space address 0x070f
4369         * controls the L0s/L1 entrance latency. We try standard ECAM access
4370         * first and if it fails fall back to CSI.
4371         */
4372        if (pdev->cfg_size > 0x070f &&
4373            pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4374                return;
4375
4376        netdev_notice_once(tp->dev,
4377                "No native access to PCI extended config space, falling back to CSI\n");
4378        csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4379        rtl_csi_write(tp, 0x070c, csi | val << 24);
4380}
4381
4382static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4383{
4384        rtl_csi_access_enable(tp, 0x27);
4385}
4386
4387struct ephy_info {
4388        unsigned int offset;
4389        u16 mask;
4390        u16 bits;
4391};
4392
4393static void __rtl_ephy_init(struct rtl8169_private *tp,
4394                            const struct ephy_info *e, int len)
4395{
4396        u16 w;
4397
4398        while (len-- > 0) {
4399                w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4400                rtl_ephy_write(tp, e->offset, w);
4401                e++;
4402        }
4403}
4404
4405#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
4406
4407static void rtl_disable_clock_request(struct rtl8169_private *tp)
4408{
4409        pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4410                                   PCI_EXP_LNKCTL_CLKREQ_EN);
4411}
4412
4413static void rtl_enable_clock_request(struct rtl8169_private *tp)
4414{
4415        pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4416                                 PCI_EXP_LNKCTL_CLKREQ_EN);
4417}
4418
4419static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
4420{
4421        /* work around an issue when PCI reset occurs during L2/L3 state */
4422        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
4423}
4424
4425static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4426{
4427        /* Don't enable ASPM in the chip if OS can't control ASPM */
4428        if (enable && tp->aspm_manageable) {
4429                RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4430                RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4431        } else {
4432                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4433                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4434        }
4435
4436        udelay(10);
4437}
4438
4439static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
4440                              u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
4441{
4442        /* Usage of dynamic vs. static FIFO is controlled by bit
4443         * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
4444         */
4445        rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
4446        rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
4447}
4448
4449static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
4450                                          u8 low, u8 high)
4451{
4452        /* FIFO thresholds for pause flow control */
4453        rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
4454        rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
4455}
4456
4457static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4458{
4459        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4460}
4461
4462static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4463{
4464        rtl_hw_start_8168bb(tp);
4465
4466        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4467}
4468
4469static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4470{
4471        RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4472
4473        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4474
4475        rtl_disable_clock_request(tp);
4476}
4477
4478static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4479{
4480        static const struct ephy_info e_info_8168cp[] = {
4481                { 0x01, 0,      0x0001 },
4482                { 0x02, 0x0800, 0x1000 },
4483                { 0x03, 0,      0x0042 },
4484                { 0x06, 0x0080, 0x0000 },
4485                { 0x07, 0,      0x2000 }
4486        };
4487
4488        rtl_set_def_aspm_entry_latency(tp);
4489
4490        rtl_ephy_init(tp, e_info_8168cp);
4491
4492        __rtl_hw_start_8168cp(tp);
4493}
4494
4495static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4496{
4497        rtl_set_def_aspm_entry_latency(tp);
4498
4499        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4500}
4501
4502static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4503{
4504        rtl_set_def_aspm_entry_latency(tp);
4505
4506        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4507
4508        /* Magic. */
4509        RTL_W8(tp, DBG_REG, 0x20);
4510}
4511
4512static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4513{
4514        static const struct ephy_info e_info_8168c_1[] = {
4515                { 0x02, 0x0800, 0x1000 },
4516                { 0x03, 0,      0x0002 },
4517                { 0x06, 0x0080, 0x0000 }
4518        };
4519
4520        rtl_set_def_aspm_entry_latency(tp);
4521
4522        RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4523
4524        rtl_ephy_init(tp, e_info_8168c_1);
4525
4526        __rtl_hw_start_8168cp(tp);
4527}
4528
4529static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4530{
4531        static const struct ephy_info e_info_8168c_2[] = {
4532                { 0x01, 0,      0x0001 },
4533                { 0x03, 0x0400, 0x0020 }
4534        };
4535
4536        rtl_set_def_aspm_entry_latency(tp);
4537
4538        rtl_ephy_init(tp, e_info_8168c_2);
4539
4540        __rtl_hw_start_8168cp(tp);
4541}
4542
4543static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4544{
4545        rtl_hw_start_8168c_2(tp);
4546}
4547
4548static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4549{
4550        rtl_set_def_aspm_entry_latency(tp);
4551
4552        __rtl_hw_start_8168cp(tp);
4553}
4554
4555static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4556{
4557        rtl_set_def_aspm_entry_latency(tp);
4558
4559        rtl_disable_clock_request(tp);
4560
4561        if (tp->dev->mtu <= ETH_DATA_LEN)
4562                rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4563}
4564
4565static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4566{
4567        rtl_set_def_aspm_entry_latency(tp);
4568
4569        if (tp->dev->mtu <= ETH_DATA_LEN)
4570                rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4571
4572        rtl_disable_clock_request(tp);
4573}
4574
4575static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4576{
4577        static const struct ephy_info e_info_8168d_4[] = {
4578                { 0x0b, 0x0000, 0x0048 },
4579                { 0x19, 0x0020, 0x0050 },
4580                { 0x0c, 0x0100, 0x0020 },
4581                { 0x10, 0x0004, 0x0000 },
4582        };
4583
4584        rtl_set_def_aspm_entry_latency(tp);
4585
4586        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4587
4588        rtl_ephy_init(tp, e_info_8168d_4);
4589
4590        rtl_enable_clock_request(tp);
4591}
4592
4593static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4594{
4595        static const struct ephy_info e_info_8168e_1[] = {
4596                { 0x00, 0x0200, 0x0100 },
4597                { 0x00, 0x0000, 0x0004 },
4598                { 0x06, 0x0002, 0x0001 },
4599                { 0x06, 0x0000, 0x0030 },
4600                { 0x07, 0x0000, 0x2000 },
4601                { 0x00, 0x0000, 0x0020 },
4602                { 0x03, 0x5800, 0x2000 },
4603                { 0x03, 0x0000, 0x0001 },
4604                { 0x01, 0x0800, 0x1000 },
4605                { 0x07, 0x0000, 0x4000 },
4606                { 0x1e, 0x0000, 0x2000 },
4607                { 0x19, 0xffff, 0xfe6c },
4608                { 0x0a, 0x0000, 0x0040 }
4609        };
4610
4611        rtl_set_def_aspm_entry_latency(tp);
4612
4613        rtl_ephy_init(tp, e_info_8168e_1);
4614
4615        rtl_disable_clock_request(tp);
4616
4617        /* Reset tx FIFO pointer */
4618        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
4619        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
4620
4621        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4622}
4623
4624static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
4625{
4626        static const struct ephy_info e_info_8168e_2[] = {
4627                { 0x09, 0x0000, 0x0080 },
4628                { 0x19, 0x0000, 0x0224 },
4629                { 0x00, 0x0000, 0x0004 },
4630                { 0x0c, 0x3df0, 0x0200 },
4631        };
4632
4633        rtl_set_def_aspm_entry_latency(tp);
4634
4635        rtl_ephy_init(tp, e_info_8168e_2);
4636
4637        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4638        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4639        rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4640        rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4641        rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
4642        rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4643        rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4644
4645        rtl_disable_clock_request(tp);
4646
4647        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4648
4649        rtl8168_config_eee_mac(tp);
4650
4651        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4652        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4653        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4654
4655        rtl_hw_aspm_clkreq_enable(tp, true);
4656}
4657
4658static void rtl_hw_start_8168f(struct rtl8169_private *tp)
4659{
4660        rtl_set_def_aspm_entry_latency(tp);
4661
4662        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4663
4664        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4665        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4666        rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
4667        rtl_reset_packet_filter(tp);
4668        rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
4669        rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
4670        rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
4671        rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
4672
4673        rtl_disable_clock_request(tp);
4674
4675        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
4676        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
4677        RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
4678        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
4679
4680        rtl8168_config_eee_mac(tp);
4681}
4682
4683static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
4684{
4685        static const struct ephy_info e_info_8168f_1[] = {
4686                { 0x06, 0x00c0, 0x0020 },
4687                { 0x08, 0x0001, 0x0002 },
4688                { 0x09, 0x0000, 0x0080 },
4689                { 0x19, 0x0000, 0x0224 },
4690                { 0x00, 0x0000, 0x0004 },
4691                { 0x0c, 0x3df0, 0x0200 },
4692        };
4693
4694        rtl_hw_start_8168f(tp);
4695
4696        rtl_ephy_init(tp, e_info_8168f_1);
4697
4698        rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
4699}
4700
4701static void rtl_hw_start_8411(struct rtl8169_private *tp)
4702{
4703        static const struct ephy_info e_info_8168f_1[] = {
4704                { 0x06, 0x00c0, 0x0020 },
4705                { 0x0f, 0xffff, 0x5200 },
4706                { 0x19, 0x0000, 0x0224 },
4707                { 0x00, 0x0000, 0x0004 },
4708                { 0x0c, 0x3df0, 0x0200 },
4709        };
4710
4711        rtl_hw_start_8168f(tp);
4712        rtl_pcie_state_l2l3_disable(tp);
4713
4714        rtl_ephy_init(tp, e_info_8168f_1);
4715
4716        rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
4717}
4718
4719static void rtl_hw_start_8168g(struct rtl8169_private *tp)
4720{
4721        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4722        rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4723
4724        rtl_set_def_aspm_entry_latency(tp);
4725
4726        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4727
4728        rtl_reset_packet_filter(tp);
4729        rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
4730
4731        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4732
4733        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4734        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4735
4736        rtl8168_config_eee_mac(tp);
4737
4738        rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
4739        rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4740
4741        rtl_pcie_state_l2l3_disable(tp);
4742}
4743
4744static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
4745{
4746        static const struct ephy_info e_info_8168g_1[] = {
4747                { 0x00, 0x0008, 0x0000 },
4748                { 0x0c, 0x3ff0, 0x0820 },
4749                { 0x1e, 0x0000, 0x0001 },
4750                { 0x19, 0x8000, 0x0000 }
4751        };
4752
4753        rtl_hw_start_8168g(tp);
4754
4755        /* disable aspm and clock request before access ephy */
4756        rtl_hw_aspm_clkreq_enable(tp, false);
4757        rtl_ephy_init(tp, e_info_8168g_1);
4758        rtl_hw_aspm_clkreq_enable(tp, true);
4759}
4760
4761static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
4762{
4763        static const struct ephy_info e_info_8168g_2[] = {
4764                { 0x00, 0x0008, 0x0000 },
4765                { 0x0c, 0x3ff0, 0x0820 },
4766                { 0x19, 0xffff, 0x7c00 },
4767                { 0x1e, 0xffff, 0x20eb },
4768                { 0x0d, 0xffff, 0x1666 },
4769                { 0x00, 0xffff, 0x10a3 },
4770                { 0x06, 0xffff, 0xf050 },
4771                { 0x04, 0x0000, 0x0010 },
4772                { 0x1d, 0x4000, 0x0000 },
4773        };
4774
4775        rtl_hw_start_8168g(tp);
4776
4777        /* disable aspm and clock request before access ephy */
4778        RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4779        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4780        rtl_ephy_init(tp, e_info_8168g_2);
4781}
4782
4783static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
4784{
4785        static const struct ephy_info e_info_8411_2[] = {
4786                { 0x00, 0x0008, 0x0000 },
4787                { 0x0c, 0x37d0, 0x0820 },
4788                { 0x1e, 0x0000, 0x0001 },
4789                { 0x19, 0x8021, 0x0000 },
4790                { 0x1e, 0x0000, 0x2000 },
4791                { 0x0d, 0x0100, 0x0200 },
4792                { 0x00, 0x0000, 0x0080 },
4793                { 0x06, 0x0000, 0x0010 },
4794                { 0x04, 0x0000, 0x0010 },
4795                { 0x1d, 0x0000, 0x4000 },
4796        };
4797
4798        rtl_hw_start_8168g(tp);
4799
4800        /* disable aspm and clock request before access ephy */
4801        rtl_hw_aspm_clkreq_enable(tp, false);
4802        rtl_ephy_init(tp, e_info_8411_2);
4803
4804        /* The following Realtek-provided magic fixes an issue with the RX unit
4805         * getting confused after the PHY having been powered-down.
4806         */
4807        r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
4808        r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
4809        r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
4810        r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
4811        r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
4812        r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
4813        r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
4814        r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
4815        mdelay(3);
4816        r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
4817
4818        r8168_mac_ocp_write(tp, 0xF800, 0xE008);
4819        r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
4820        r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
4821        r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
4822        r8168_mac_ocp_write(tp, 0xF808, 0xE027);
4823        r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
4824        r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
4825        r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
4826        r8168_mac_ocp_write(tp, 0xF810, 0xC602);
4827        r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
4828        r8168_mac_ocp_write(tp, 0xF814, 0x0000);
4829        r8168_mac_ocp_write(tp, 0xF816, 0xC502);
4830        r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
4831        r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
4832        r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
4833        r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
4834        r8168_mac_ocp_write(tp, 0xF820, 0x080A);
4835        r8168_mac_ocp_write(tp, 0xF822, 0x6420);
4836        r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
4837        r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
4838        r8168_mac_ocp_write(tp, 0xF828, 0xC516);
4839        r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
4840        r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
4841        r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
4842        r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
4843        r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
4844        r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
4845        r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
4846        r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
4847        r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
4848        r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
4849        r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
4850        r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
4851        r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
4852        r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
4853        r8168_mac_ocp_write(tp, 0xF846, 0xC404);
4854        r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
4855        r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
4856        r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
4857        r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
4858        r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
4859        r8168_mac_ocp_write(tp, 0xF852, 0xE434);
4860        r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
4861        r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
4862        r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
4863        r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
4864        r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
4865        r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
4866        r8168_mac_ocp_write(tp, 0xF860, 0xF007);
4867        r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
4868        r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
4869        r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
4870        r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
4871        r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
4872        r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
4873        r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
4874        r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
4875        r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
4876        r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
4877        r8168_mac_ocp_write(tp, 0xF876, 0xC516);
4878        r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
4879        r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
4880        r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
4881        r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
4882        r8168_mac_ocp_write(tp, 0xF880, 0xC512);
4883        r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
4884        r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
4885        r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
4886        r8168_mac_ocp_write(tp, 0xF888, 0x483F);
4887        r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
4888        r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
4889        r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
4890        r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
4891        r8168_mac_ocp_write(tp, 0xF892, 0xC505);
4892        r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
4893        r8168_mac_ocp_write(tp, 0xF896, 0xC502);
4894        r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
4895        r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
4896        r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
4897        r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
4898        r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
4899        r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
4900        r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
4901        r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
4902        r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
4903        r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
4904        r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
4905        r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
4906        r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
4907        r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
4908        r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
4909        r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
4910        r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
4911        r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
4912        r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
4913        r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
4914        r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
4915        r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
4916        r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
4917        r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
4918        r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
4919        r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
4920        r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
4921        r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
4922        r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
4923        r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
4924        r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
4925        r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
4926        r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
4927        r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
4928        r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
4929
4930        r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
4931
4932        r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
4933        r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
4934        r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
4935        r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
4936        r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
4937        r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
4938        r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
4939
4940        rtl_hw_aspm_clkreq_enable(tp, true);
4941}
4942
4943static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
4944{
4945        static const struct ephy_info e_info_8168h_1[] = {
4946                { 0x1e, 0x0800, 0x0001 },
4947                { 0x1d, 0x0000, 0x0800 },
4948                { 0x05, 0xffff, 0x2089 },
4949                { 0x06, 0xffff, 0x5881 },
4950                { 0x04, 0xffff, 0x854a },
4951                { 0x01, 0xffff, 0x068b }
4952        };
4953        int rg_saw_cnt;
4954
4955        /* disable aspm and clock request before access ephy */
4956        rtl_hw_aspm_clkreq_enable(tp, false);
4957        rtl_ephy_init(tp, e_info_8168h_1);
4958
4959        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
4960        rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
4961
4962        rtl_set_def_aspm_entry_latency(tp);
4963
4964        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4965
4966        rtl_reset_packet_filter(tp);
4967
4968        rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
4969
4970        rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
4971
4972        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
4973
4974        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
4975
4976        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
4977        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
4978
4979        rtl8168_config_eee_mac(tp);
4980
4981        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
4982        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
4983
4984        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
4985
4986        rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
4987
4988        rtl_pcie_state_l2l3_disable(tp);
4989
4990        rtl_writephy(tp, 0x1f, 0x0c42);
4991        rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
4992        rtl_writephy(tp, 0x1f, 0x0000);
4993        if (rg_saw_cnt > 0) {
4994                u16 sw_cnt_1ms_ini;
4995
4996                sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
4997                sw_cnt_1ms_ini &= 0x0fff;
4998                r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
4999        }
5000
5001        r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
5002        r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
5003        r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
5004        r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
5005
5006        r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5007        r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5008        r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5009        r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5010
5011        rtl_hw_aspm_clkreq_enable(tp, true);
5012}
5013
5014static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5015{
5016        rtl8168ep_stop_cmac(tp);
5017
5018        rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
5019        rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
5020
5021        rtl_set_def_aspm_entry_latency(tp);
5022
5023        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5024
5025        rtl_reset_packet_filter(tp);
5026
5027        rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
5028
5029        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
5030
5031        RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5032
5033        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5034        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5035
5036        rtl8168_config_eee_mac(tp);
5037
5038        rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
5039
5040        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5041
5042        rtl_pcie_state_l2l3_disable(tp);
5043}
5044
5045static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5046{
5047        static const struct ephy_info e_info_8168ep_1[] = {
5048                { 0x00, 0xffff, 0x10ab },
5049                { 0x06, 0xffff, 0xf030 },
5050                { 0x08, 0xffff, 0x2006 },
5051                { 0x0d, 0xffff, 0x1666 },
5052                { 0x0c, 0x3ff0, 0x0000 }
5053        };
5054
5055        /* disable aspm and clock request before access ephy */
5056        rtl_hw_aspm_clkreq_enable(tp, false);
5057        rtl_ephy_init(tp, e_info_8168ep_1);
5058
5059        rtl_hw_start_8168ep(tp);
5060
5061        rtl_hw_aspm_clkreq_enable(tp, true);
5062}
5063
5064static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5065{
5066        static const struct ephy_info e_info_8168ep_2[] = {
5067                { 0x00, 0xffff, 0x10a3 },
5068                { 0x19, 0xffff, 0xfc00 },
5069                { 0x1e, 0xffff, 0x20ea }
5070        };
5071
5072        /* disable aspm and clock request before access ephy */
5073        rtl_hw_aspm_clkreq_enable(tp, false);
5074        rtl_ephy_init(tp, e_info_8168ep_2);
5075
5076        rtl_hw_start_8168ep(tp);
5077
5078        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5079        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5080
5081        rtl_hw_aspm_clkreq_enable(tp, true);
5082}
5083
5084static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5085{
5086        static const struct ephy_info e_info_8168ep_3[] = {
5087                { 0x00, 0x0000, 0x0080 },
5088                { 0x0d, 0x0100, 0x0200 },
5089                { 0x19, 0x8021, 0x0000 },
5090                { 0x1e, 0x0000, 0x2000 },
5091        };
5092
5093        /* disable aspm and clock request before access ephy */
5094        rtl_hw_aspm_clkreq_enable(tp, false);
5095        rtl_ephy_init(tp, e_info_8168ep_3);
5096
5097        rtl_hw_start_8168ep(tp);
5098
5099        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5100        RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5101
5102        r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
5103        r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
5104        r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
5105
5106        rtl_hw_aspm_clkreq_enable(tp, true);
5107}
5108
5109static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5110{
5111        static const struct ephy_info e_info_8102e_1[] = {
5112                { 0x01, 0, 0x6e65 },
5113                { 0x02, 0, 0x091f },
5114                { 0x03, 0, 0xc2f9 },
5115                { 0x06, 0, 0xafb5 },
5116                { 0x07, 0, 0x0e00 },
5117                { 0x19, 0, 0xec80 },
5118                { 0x01, 0, 0x2e65 },
5119                { 0x01, 0, 0x6e65 }
5120        };
5121        u8 cfg1;
5122
5123        rtl_set_def_aspm_entry_latency(tp);
5124
5125        RTL_W8(tp, DBG_REG, FIX_NAK_1);
5126
5127        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5128
5129        RTL_W8(tp, Config1,
5130               LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5131        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5132
5133        cfg1 = RTL_R8(tp, Config1);
5134        if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5135                RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5136
5137        rtl_ephy_init(tp, e_info_8102e_1);
5138}
5139
5140static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5141{
5142        rtl_set_def_aspm_entry_latency(tp);
5143
5144        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5145
5146        RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5147        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5148}
5149
5150static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5151{
5152        rtl_hw_start_8102e_2(tp);
5153
5154        rtl_ephy_write(tp, 0x03, 0xc2f9);
5155}
5156
5157static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5158{
5159        static const struct ephy_info e_info_8105e_1[] = {
5160                { 0x07, 0, 0x4000 },
5161                { 0x19, 0, 0x0200 },
5162                { 0x19, 0, 0x0020 },
5163                { 0x1e, 0, 0x2000 },
5164                { 0x03, 0, 0x0001 },
5165                { 0x19, 0, 0x0100 },
5166                { 0x19, 0, 0x0004 },
5167                { 0x0a, 0, 0x0020 }
5168        };
5169
5170        /* Force LAN exit from ASPM if Rx/Tx are not idle */
5171        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5172
5173        /* Disable Early Tally Counter */
5174        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5175
5176        RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5177        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5178
5179        rtl_ephy_init(tp, e_info_8105e_1);
5180
5181        rtl_pcie_state_l2l3_disable(tp);
5182}
5183
5184static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5185{
5186        rtl_hw_start_8105e_1(tp);
5187        rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5188}
5189
5190static void rtl_hw_start_8402(struct rtl8169_private *tp)
5191{
5192        static const struct ephy_info e_info_8402[] = {
5193                { 0x19, 0xffff, 0xff64 },
5194                { 0x1e, 0, 0x4000 }
5195        };
5196
5197        rtl_set_def_aspm_entry_latency(tp);
5198
5199        /* Force LAN exit from ASPM if Rx/Tx are not idle */
5200        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5201
5202        RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5203
5204        rtl_ephy_init(tp, e_info_8402);
5205
5206        rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5207
5208        rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
5209        rtl_reset_packet_filter(tp);
5210        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
5211        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
5212        rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
5213
5214        rtl_pcie_state_l2l3_disable(tp);
5215}
5216
5217static void rtl_hw_start_8106(struct rtl8169_private *tp)
5218{
5219        rtl_hw_aspm_clkreq_enable(tp, false);
5220
5221        /* Force LAN exit from ASPM if Rx/Tx are not idle */
5222        RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5223
5224        RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5225        RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5226        RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5227
5228        rtl_pcie_state_l2l3_disable(tp);
5229        rtl_hw_aspm_clkreq_enable(tp, true);
5230}
5231
5232DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
5233{
5234        return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
5235}
5236
5237static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
5238{
5239        rtl_pcie_state_l2l3_disable(tp);
5240
5241        RTL_W16(tp, 0x382, 0x221b);
5242        RTL_W8(tp, 0x4500, 0);
5243        RTL_W16(tp, 0x4800, 0);
5244
5245        /* disable UPS */
5246        r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
5247
5248        RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
5249