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12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20#include <linux/if_vlan.h>
21#include <linux/in.h>
22#include <linux/io.h>
23#include <linux/ip.h>
24#include <linux/tcp.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/pm_runtime.h>
28#include <linux/bitfield.h>
29#include <linux/prefetch.h>
30#include <linux/ipv6.h>
31#include <asm/unaligned.h>
32#include <net/ip6_checksum.h>
33
34#include "r8169.h"
35#include "r8169_firmware.h"
36
37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
53#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
55#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
56#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
57#define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
58#define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw"
59
60
61
62#define MC_FILTER_LIMIT 32
63
64#define TX_DMA_BURST 7
65#define InterFrameGap 0x03
66
67#define R8169_REGS_SIZE 256
68#define R8169_RX_BUF_SIZE (SZ_16K - 1)
69#define NUM_TX_DESC 256
70#define NUM_RX_DESC 256
71#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
72#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
73
74#define OCP_STD_PHY_BASE 0xa400
75
76#define RTL_CFG_NO_GBIT 1
77
78
79#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
80#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
81#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
82#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
83#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
84#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
85
86#define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
87#define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
88#define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89#define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90
91static const struct {
92 const char *name;
93 const char *fw_name;
94} rtl_chip_infos[] = {
95
96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
101
102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e/RTL8100e" },
109 [RTL_GIGA_MAC_VER_14] = {"RTL8401" },
110 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
111 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
112 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
113 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
114 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
115 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
116 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
117 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
118 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
119 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
120 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
121 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
122 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
123 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
124 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
125 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
126 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
127 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
128 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
129 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
130 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
131 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
132 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
133 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
134 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
135 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
136 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
137 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
138 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
139 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
140 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
141 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
142 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
143 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
144 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
145 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
146 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
147 [RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117", },
148 [RTL_GIGA_MAC_VER_60] = {"RTL8125A" },
149 [RTL_GIGA_MAC_VER_61] = {"RTL8125A", FIRMWARE_8125A_3},
150
151 [RTL_GIGA_MAC_VER_63] = {"RTL8125B", FIRMWARE_8125B_2},
152};
153
154static const struct pci_device_id rtl8169_pci_tbl[] = {
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8162) },
161 { PCI_VDEVICE(REALTEK, 0x8167) },
162 { PCI_VDEVICE(REALTEK, 0x8168) },
163 { PCI_VDEVICE(NCUBE, 0x8168) },
164 { PCI_VDEVICE(REALTEK, 0x8169) },
165 { PCI_VENDOR_ID_DLINK, 0x4300,
166 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
167 { PCI_VDEVICE(DLINK, 0x4300) },
168 { PCI_VDEVICE(DLINK, 0x4302) },
169 { PCI_VDEVICE(AT, 0xc107) },
170 { PCI_VDEVICE(USR, 0x0116) },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
172 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
173 { PCI_VDEVICE(REALTEK, 0x8125) },
174 { PCI_VDEVICE(REALTEK, 0x3000) },
175 {}
176};
177
178MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
179
180enum rtl_registers {
181 MAC0 = 0,
182 MAC4 = 4,
183 MAR0 = 8,
184 CounterAddrLow = 0x10,
185 CounterAddrHigh = 0x14,
186 TxDescStartAddrLow = 0x20,
187 TxDescStartAddrHigh = 0x24,
188 TxHDescStartAddrLow = 0x28,
189 TxHDescStartAddrHigh = 0x2c,
190 FLASH = 0x30,
191 ERSR = 0x36,
192 ChipCmd = 0x37,
193 TxPoll = 0x38,
194 IntrMask = 0x3c,
195 IntrStatus = 0x3e,
196
197 TxConfig = 0x40,
198#define TXCFG_AUTO_FIFO (1 << 7)
199#define TXCFG_EMPTY (1 << 11)
200
201 RxConfig = 0x44,
202#define RX128_INT_EN (1 << 15)
203#define RX_MULTI_EN (1 << 14)
204#define RXCFG_FIFO_SHIFT 13
205
206#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
207#define RX_EARLY_OFF (1 << 11)
208#define RXCFG_DMA_SHIFT 8
209
210#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
211
212 Cfg9346 = 0x50,
213 Config0 = 0x51,
214 Config1 = 0x52,
215 Config2 = 0x53,
216#define PME_SIGNAL (1 << 5)
217
218 Config3 = 0x54,
219 Config4 = 0x55,
220 Config5 = 0x56,
221 PHYAR = 0x60,
222 PHYstatus = 0x6c,
223 RxMaxSize = 0xda,
224 CPlusCmd = 0xe0,
225 IntrMitigate = 0xe2,
226
227#define RTL_COALESCE_TX_USECS GENMASK(15, 12)
228#define RTL_COALESCE_TX_FRAMES GENMASK(11, 8)
229#define RTL_COALESCE_RX_USECS GENMASK(7, 4)
230#define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
231
232#define RTL_COALESCE_T_MAX 0x0fU
233#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4)
234
235 RxDescAddrLow = 0xe4,
236 RxDescAddrHigh = 0xe8,
237 EarlyTxThres = 0xec,
238
239#define NoEarlyTx 0x3f
240
241 MaxTxPacketSize = 0xec,
242
243#define TxPacketMax (8064 >> 7)
244#define EarlySize 0x27
245
246 FuncEvent = 0xf0,
247 FuncEventMask = 0xf4,
248 FuncPresetState = 0xf8,
249 IBCR0 = 0xf8,
250 IBCR2 = 0xf9,
251 IBIMR0 = 0xfa,
252 IBISR0 = 0xfb,
253 FuncForceEvent = 0xfc,
254};
255
256enum rtl8168_8101_registers {
257 CSIDR = 0x64,
258 CSIAR = 0x68,
259#define CSIAR_FLAG 0x80000000
260#define CSIAR_WRITE_CMD 0x80000000
261#define CSIAR_BYTE_ENABLE 0x0000f000
262#define CSIAR_ADDR_MASK 0x00000fff
263 PMCH = 0x6f,
264#define D3COLD_NO_PLL_DOWN BIT(7)
265#define D3HOT_NO_PLL_DOWN BIT(6)
266#define D3_NO_PLL_DOWN (BIT(7) | BIT(6))
267 EPHYAR = 0x80,
268#define EPHYAR_FLAG 0x80000000
269#define EPHYAR_WRITE_CMD 0x80000000
270#define EPHYAR_REG_MASK 0x1f
271#define EPHYAR_REG_SHIFT 16
272#define EPHYAR_DATA_MASK 0xffff
273 DLLPR = 0xd0,
274#define PFM_EN (1 << 6)
275#define TX_10M_PS_EN (1 << 7)
276 DBG_REG = 0xd1,
277#define FIX_NAK_1 (1 << 4)
278#define FIX_NAK_2 (1 << 3)
279 TWSI = 0xd2,
280 MCU = 0xd3,
281#define NOW_IS_OOB (1 << 7)
282#define TX_EMPTY (1 << 5)
283#define RX_EMPTY (1 << 4)
284#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
285#define EN_NDP (1 << 3)
286#define EN_OOB_RESET (1 << 2)
287#define LINK_LIST_RDY (1 << 1)
288 EFUSEAR = 0xdc,
289#define EFUSEAR_FLAG 0x80000000
290#define EFUSEAR_WRITE_CMD 0x80000000
291#define EFUSEAR_READ_CMD 0x00000000
292#define EFUSEAR_REG_MASK 0x03ff
293#define EFUSEAR_REG_SHIFT 8
294#define EFUSEAR_DATA_MASK 0xff
295 MISC_1 = 0xf2,
296#define PFM_D3COLD_EN (1 << 6)
297};
298
299enum rtl8168_registers {
300 LED_FREQ = 0x1a,
301 EEE_LED = 0x1b,
302 ERIDR = 0x70,
303 ERIAR = 0x74,
304#define ERIAR_FLAG 0x80000000
305#define ERIAR_WRITE_CMD 0x80000000
306#define ERIAR_READ_CMD 0x00000000
307#define ERIAR_ADDR_BYTE_ALIGN 4
308#define ERIAR_TYPE_SHIFT 16
309#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
310#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
311#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
312#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
313#define ERIAR_MASK_SHIFT 12
314#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
315#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
316#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
317#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
318#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
319 EPHY_RXER_NUM = 0x7c,
320 OCPDR = 0xb0,
321#define OCPDR_WRITE_CMD 0x80000000
322#define OCPDR_READ_CMD 0x00000000
323#define OCPDR_REG_MASK 0x7f
324#define OCPDR_GPHY_REG_SHIFT 16
325#define OCPDR_DATA_MASK 0xffff
326 OCPAR = 0xb4,
327#define OCPAR_FLAG 0x80000000
328#define OCPAR_GPHY_WRITE_CMD 0x8000f060
329#define OCPAR_GPHY_READ_CMD 0x0000f060
330 GPHY_OCP = 0xb8,
331 RDSAR1 = 0xd0,
332 MISC = 0xf0,
333#define TXPLA_RST (1 << 29)
334#define DISABLE_LAN_EN (1 << 23)
335#define PWM_EN (1 << 22)
336#define RXDV_GATED_EN (1 << 19)
337#define EARLY_TALLY_EN (1 << 16)
338};
339
340enum rtl8125_registers {
341 IntrMask_8125 = 0x38,
342 IntrStatus_8125 = 0x3c,
343 TxPoll_8125 = 0x90,
344 MAC0_BKP = 0x19e0,
345 EEE_TXIDLE_TIMER_8125 = 0x6048,
346};
347
348#define RX_VLAN_INNER_8125 BIT(22)
349#define RX_VLAN_OUTER_8125 BIT(23)
350#define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
351
352#define RX_FETCH_DFLT_8125 (8 << 27)
353
354enum rtl_register_content {
355
356 SYSErr = 0x8000,
357 PCSTimeout = 0x4000,
358 SWInt = 0x0100,
359 TxDescUnavail = 0x0080,
360 RxFIFOOver = 0x0040,
361 LinkChg = 0x0020,
362 RxOverflow = 0x0010,
363 TxErr = 0x0008,
364 TxOK = 0x0004,
365 RxErr = 0x0002,
366 RxOK = 0x0001,
367
368
369 RxRWT = (1 << 22),
370 RxRES = (1 << 21),
371 RxRUNT = (1 << 20),
372 RxCRC = (1 << 19),
373
374
375 StopReq = 0x80,
376 CmdReset = 0x10,
377 CmdRxEnb = 0x08,
378 CmdTxEnb = 0x04,
379 RxBufEmpty = 0x01,
380
381
382 HPQ = 0x80,
383 NPQ = 0x40,
384 FSWInt = 0x01,
385
386
387 Cfg9346_Lock = 0x00,
388 Cfg9346_Unlock = 0xc0,
389
390
391 AcceptErr = 0x20,
392 AcceptRunt = 0x10,
393#define RX_CONFIG_ACCEPT_ERR_MASK 0x30
394 AcceptBroadcast = 0x08,
395 AcceptMulticast = 0x04,
396 AcceptMyPhys = 0x02,
397 AcceptAllPhys = 0x01,
398#define RX_CONFIG_ACCEPT_OK_MASK 0x0f
399#define RX_CONFIG_ACCEPT_MASK 0x3f
400
401
402 TxInterFrameGapShift = 24,
403 TxDMAShift = 8,
404
405
406 LEDS1 = (1 << 7),
407 LEDS0 = (1 << 6),
408 Speed_down = (1 << 4),
409 MEMMAP = (1 << 3),
410 IOMAP = (1 << 2),
411 VPD = (1 << 1),
412 PMEnable = (1 << 0),
413
414
415 ClkReqEn = (1 << 7),
416 MSIEnable = (1 << 5),
417 PCI_Clock_66MHz = 0x01,
418 PCI_Clock_33MHz = 0x00,
419
420
421 MagicPacket = (1 << 5),
422 LinkUp = (1 << 4),
423 Jumbo_En0 = (1 << 2),
424 Rdy_to_L23 = (1 << 1),
425 Beacon_en = (1 << 0),
426
427
428 Jumbo_En1 = (1 << 1),
429
430
431 BWF = (1 << 6),
432 MWF = (1 << 5),
433 UWF = (1 << 4),
434 Spi_en = (1 << 3),
435 LanWake = (1 << 1),
436 PMEStatus = (1 << 0),
437 ASPM_en = (1 << 0),
438
439
440 EnableBist = (1 << 15),
441 Mac_dbgo_oe = (1 << 14),
442 EnAnaPLL = (1 << 14),
443 Normal_mode = (1 << 13),
444 Force_half_dup = (1 << 12),
445 Force_rxflow_en = (1 << 11),
446 Force_txflow_en = (1 << 10),
447 Cxpl_dbg_sel = (1 << 9),
448 ASF = (1 << 8),
449 PktCntrDisable = (1 << 7),
450 Mac_dbgo_sel = 0x001c,
451 RxVlan = (1 << 6),
452 RxChkSum = (1 << 5),
453 PCIDAC = (1 << 4),
454 PCIMulRW = (1 << 3),
455#define INTT_MASK GENMASK(1, 0)
456#define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
457
458
459 TBI_Enable = 0x80,
460 TxFlowCtrl = 0x40,
461 RxFlowCtrl = 0x20,
462 _1000bpsF = 0x10,
463 _100bps = 0x08,
464 _10bps = 0x04,
465 LinkStatus = 0x02,
466 FullDup = 0x01,
467
468
469 CounterReset = 0x1,
470
471
472 CounterDump = 0x8,
473
474
475 MagicPacket_v2 = (1 << 16),
476};
477
478enum rtl_desc_bit {
479
480 DescOwn = (1 << 31),
481 RingEnd = (1 << 30),
482 FirstFrag = (1 << 29),
483 LastFrag = (1 << 28),
484};
485
486
487enum rtl_tx_desc_bit {
488
489 TD_LSO = (1 << 27),
490#define TD_MSS_MAX 0x07ffu
491
492
493 TxVlanTag = (1 << 17),
494};
495
496
497enum rtl_tx_desc_bit_0 {
498
499#define TD0_MSS_SHIFT 16
500 TD0_TCP_CS = (1 << 16),
501 TD0_UDP_CS = (1 << 17),
502 TD0_IP_CS = (1 << 18),
503};
504
505
506enum rtl_tx_desc_bit_1 {
507
508 TD1_GTSENV4 = (1 << 26),
509 TD1_GTSENV6 = (1 << 25),
510#define GTTCPHO_SHIFT 18
511#define GTTCPHO_MAX 0x7f
512
513
514#define TCPHO_SHIFT 18
515#define TCPHO_MAX 0x3ff
516#define TD1_MSS_SHIFT 18
517 TD1_IPv6_CS = (1 << 28),
518 TD1_IPv4_CS = (1 << 29),
519 TD1_TCP_CS = (1 << 30),
520 TD1_UDP_CS = (1 << 31),
521};
522
523enum rtl_rx_desc_bit {
524
525 PID1 = (1 << 18),
526 PID0 = (1 << 17),
527
528#define RxProtoUDP (PID1)
529#define RxProtoTCP (PID0)
530#define RxProtoIP (PID1 | PID0)
531#define RxProtoMask RxProtoIP
532
533 IPFail = (1 << 16),
534 UDPFail = (1 << 15),
535 TCPFail = (1 << 14),
536
537#define RxCSFailMask (IPFail | UDPFail | TCPFail)
538
539 RxVlanTag = (1 << 16),
540};
541
542#define RTL_GSO_MAX_SIZE_V1 32000
543#define RTL_GSO_MAX_SEGS_V1 24
544#define RTL_GSO_MAX_SIZE_V2 64000
545#define RTL_GSO_MAX_SEGS_V2 64
546
547struct TxDesc {
548 __le32 opts1;
549 __le32 opts2;
550 __le64 addr;
551};
552
553struct RxDesc {
554 __le32 opts1;
555 __le32 opts2;
556 __le64 addr;
557};
558
559struct ring_info {
560 struct sk_buff *skb;
561 u32 len;
562};
563
564struct rtl8169_counters {
565 __le64 tx_packets;
566 __le64 rx_packets;
567 __le64 tx_errors;
568 __le32 rx_errors;
569 __le16 rx_missed;
570 __le16 align_errors;
571 __le32 tx_one_collision;
572 __le32 tx_multi_collision;
573 __le64 rx_unicast;
574 __le64 rx_broadcast;
575 __le32 rx_multicast;
576 __le16 tx_aborted;
577 __le16 tx_underun;
578};
579
580struct rtl8169_tc_offsets {
581 bool inited;
582 __le64 tx_errors;
583 __le32 tx_multi_collision;
584 __le16 tx_aborted;
585 __le16 rx_missed;
586};
587
588enum rtl_flag {
589 RTL_FLAG_TASK_ENABLED = 0,
590 RTL_FLAG_TASK_RESET_PENDING,
591 RTL_FLAG_MAX
592};
593
594enum rtl_dash_type {
595 RTL_DASH_NONE,
596 RTL_DASH_DP,
597 RTL_DASH_EP,
598};
599
600struct rtl8169_private {
601 void __iomem *mmio_addr;
602 struct pci_dev *pci_dev;
603 struct net_device *dev;
604 struct phy_device *phydev;
605 struct napi_struct napi;
606 enum mac_version mac_version;
607 enum rtl_dash_type dash_type;
608 u32 cur_rx;
609 u32 cur_tx;
610 u32 dirty_tx;
611 struct TxDesc *TxDescArray;
612 struct RxDesc *RxDescArray;
613 dma_addr_t TxPhyAddr;
614 dma_addr_t RxPhyAddr;
615 struct page *Rx_databuff[NUM_RX_DESC];
616 struct ring_info tx_skb[NUM_TX_DESC];
617 u16 cp_cmd;
618 u32 irq_mask;
619 struct clk *clk;
620
621 struct {
622 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
623 struct work_struct work;
624 } wk;
625
626 unsigned supports_gmii:1;
627 unsigned aspm_manageable:1;
628 dma_addr_t counters_phys_addr;
629 struct rtl8169_counters *counters;
630 struct rtl8169_tc_offsets tc_offset;
631 u32 saved_wolopts;
632 int eee_adv;
633
634 const char *fw_name;
635 struct rtl_fw *rtl_fw;
636
637 u32 ocp_base;
638};
639
640typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
641
642MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
643MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
644MODULE_SOFTDEP("pre: realtek");
645MODULE_LICENSE("GPL");
646MODULE_FIRMWARE(FIRMWARE_8168D_1);
647MODULE_FIRMWARE(FIRMWARE_8168D_2);
648MODULE_FIRMWARE(FIRMWARE_8168E_1);
649MODULE_FIRMWARE(FIRMWARE_8168E_2);
650MODULE_FIRMWARE(FIRMWARE_8168E_3);
651MODULE_FIRMWARE(FIRMWARE_8105E_1);
652MODULE_FIRMWARE(FIRMWARE_8168F_1);
653MODULE_FIRMWARE(FIRMWARE_8168F_2);
654MODULE_FIRMWARE(FIRMWARE_8402_1);
655MODULE_FIRMWARE(FIRMWARE_8411_1);
656MODULE_FIRMWARE(FIRMWARE_8411_2);
657MODULE_FIRMWARE(FIRMWARE_8106E_1);
658MODULE_FIRMWARE(FIRMWARE_8106E_2);
659MODULE_FIRMWARE(FIRMWARE_8168G_2);
660MODULE_FIRMWARE(FIRMWARE_8168G_3);
661MODULE_FIRMWARE(FIRMWARE_8168H_1);
662MODULE_FIRMWARE(FIRMWARE_8168H_2);
663MODULE_FIRMWARE(FIRMWARE_8168FP_3);
664MODULE_FIRMWARE(FIRMWARE_8107E_1);
665MODULE_FIRMWARE(FIRMWARE_8107E_2);
666MODULE_FIRMWARE(FIRMWARE_8125A_3);
667MODULE_FIRMWARE(FIRMWARE_8125B_2);
668
669static inline struct device *tp_to_dev(struct rtl8169_private *tp)
670{
671 return &tp->pci_dev->dev;
672}
673
674static void rtl_lock_config_regs(struct rtl8169_private *tp)
675{
676 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
677}
678
679static void rtl_unlock_config_regs(struct rtl8169_private *tp)
680{
681 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
682}
683
684static void rtl_pci_commit(struct rtl8169_private *tp)
685{
686
687 RTL_R8(tp, ChipCmd);
688}
689
690static bool rtl_is_8125(struct rtl8169_private *tp)
691{
692 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
693}
694
695static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
696{
697 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
698 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
699 tp->mac_version <= RTL_GIGA_MAC_VER_53;
700}
701
702static bool rtl_supports_eee(struct rtl8169_private *tp)
703{
704 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
705 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
706 tp->mac_version != RTL_GIGA_MAC_VER_39;
707}
708
709static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
710{
711 int i;
712
713 for (i = 0; i < ETH_ALEN; i++)
714 mac[i] = RTL_R8(tp, reg + i);
715}
716
717struct rtl_cond {
718 bool (*check)(struct rtl8169_private *);
719 const char *msg;
720};
721
722static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
723 unsigned long usecs, int n, bool high)
724{
725 int i;
726
727 for (i = 0; i < n; i++) {
728 if (c->check(tp) == high)
729 return true;
730 fsleep(usecs);
731 }
732
733 if (net_ratelimit())
734 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
735 c->msg, !high, n, usecs);
736 return false;
737}
738
739static bool rtl_loop_wait_high(struct rtl8169_private *tp,
740 const struct rtl_cond *c,
741 unsigned long d, int n)
742{
743 return rtl_loop_wait(tp, c, d, n, true);
744}
745
746static bool rtl_loop_wait_low(struct rtl8169_private *tp,
747 const struct rtl_cond *c,
748 unsigned long d, int n)
749{
750 return rtl_loop_wait(tp, c, d, n, false);
751}
752
753#define DECLARE_RTL_COND(name) \
754static bool name ## _check(struct rtl8169_private *); \
755 \
756static const struct rtl_cond name = { \
757 .check = name ## _check, \
758 .msg = #name \
759}; \
760 \
761static bool name ## _check(struct rtl8169_private *tp)
762
763static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
764{
765
766 if (type == ERIAR_OOB &&
767 (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
768 tp->mac_version == RTL_GIGA_MAC_VER_53))
769 *cmd |= 0xf70 << 18;
770}
771
772DECLARE_RTL_COND(rtl_eriar_cond)
773{
774 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
775}
776
777static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
778 u32 val, int type)
779{
780 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
781
782 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
783 return;
784
785 RTL_W32(tp, ERIDR, val);
786 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
787 RTL_W32(tp, ERIAR, cmd);
788
789 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
790}
791
792static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
793 u32 val)
794{
795 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
796}
797
798static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
799{
800 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
801
802 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
803 RTL_W32(tp, ERIAR, cmd);
804
805 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
806 RTL_R32(tp, ERIDR) : ~0;
807}
808
809static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
810{
811 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
812}
813
814static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
815{
816 u32 val = rtl_eri_read(tp, addr);
817
818 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
819}
820
821static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
822{
823 rtl_w0w1_eri(tp, addr, p, 0);
824}
825
826static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
827{
828 rtl_w0w1_eri(tp, addr, 0, m);
829}
830
831static bool rtl_ocp_reg_failure(u32 reg)
832{
833 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
834}
835
836DECLARE_RTL_COND(rtl_ocp_gphy_cond)
837{
838 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
839}
840
841static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
842{
843 if (rtl_ocp_reg_failure(reg))
844 return;
845
846 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
847
848 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
849}
850
851static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
852{
853 if (rtl_ocp_reg_failure(reg))
854 return 0;
855
856 RTL_W32(tp, GPHY_OCP, reg << 15);
857
858 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
859 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
860}
861
862static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
863{
864 if (rtl_ocp_reg_failure(reg))
865 return;
866
867 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
868}
869
870static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
871{
872 if (rtl_ocp_reg_failure(reg))
873 return 0;
874
875 RTL_W32(tp, OCPDR, reg << 15);
876
877 return RTL_R32(tp, OCPDR);
878}
879
880static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
881 u16 set)
882{
883 u16 data = r8168_mac_ocp_read(tp, reg);
884
885 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
886}
887
888
889
890
891static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
892{
893 switch (tp->mac_version) {
894 case RTL_GIGA_MAC_VER_40:
895 case RTL_GIGA_MAC_VER_41:
896 case RTL_GIGA_MAC_VER_49:
897 if (value & BMCR_RESET || !(value & BMCR_PDOWN))
898 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
899 else
900 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
901 break;
902 default:
903 break;
904 }
905};
906
907static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
908{
909 if (reg == 0x1f) {
910 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
911 return;
912 }
913
914 if (tp->ocp_base != OCP_STD_PHY_BASE)
915 reg -= 0x10;
916
917 if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
918 rtl8168g_phy_suspend_quirk(tp, value);
919
920 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
921}
922
923static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
924{
925 if (reg == 0x1f)
926 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
927
928 if (tp->ocp_base != OCP_STD_PHY_BASE)
929 reg -= 0x10;
930
931 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
932}
933
934static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
935{
936 if (reg == 0x1f) {
937 tp->ocp_base = value << 4;
938 return;
939 }
940
941 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
942}
943
944static int mac_mcu_read(struct rtl8169_private *tp, int reg)
945{
946 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
947}
948
949DECLARE_RTL_COND(rtl_phyar_cond)
950{
951 return RTL_R32(tp, PHYAR) & 0x80000000;
952}
953
954static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
955{
956 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
957
958 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
959
960
961
962
963 udelay(20);
964}
965
966static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
967{
968 int value;
969
970 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
971
972 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
973 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
974
975
976
977
978
979 udelay(20);
980
981 return value;
982}
983
984DECLARE_RTL_COND(rtl_ocpar_cond)
985{
986 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
987}
988
989static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
990{
991 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
992 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
993 RTL_W32(tp, EPHY_RXER_NUM, 0);
994
995 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
996}
997
998static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
999{
1000 r8168dp_1_mdio_access(tp, reg,
1001 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1002}
1003
1004static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1005{
1006 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1007
1008 mdelay(1);
1009 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
1010 RTL_W32(tp, EPHY_RXER_NUM, 0);
1011
1012 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1013 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
1014}
1015
1016#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1017
1018static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1019{
1020 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1021}
1022
1023static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1024{
1025 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1026}
1027
1028static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1029{
1030 r8168dp_2_mdio_start(tp);
1031
1032 r8169_mdio_write(tp, reg, value);
1033
1034 r8168dp_2_mdio_stop(tp);
1035}
1036
1037static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1038{
1039 int value;
1040
1041
1042 if (reg == MII_PHYSID2)
1043 return 0xc912;
1044
1045 r8168dp_2_mdio_start(tp);
1046
1047 value = r8169_mdio_read(tp, reg);
1048
1049 r8168dp_2_mdio_stop(tp);
1050
1051 return value;
1052}
1053
1054static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1055{
1056 switch (tp->mac_version) {
1057 case RTL_GIGA_MAC_VER_27:
1058 r8168dp_1_mdio_write(tp, location, val);
1059 break;
1060 case RTL_GIGA_MAC_VER_28:
1061 case RTL_GIGA_MAC_VER_31:
1062 r8168dp_2_mdio_write(tp, location, val);
1063 break;
1064 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1065 r8168g_mdio_write(tp, location, val);
1066 break;
1067 default:
1068 r8169_mdio_write(tp, location, val);
1069 break;
1070 }
1071}
1072
1073static int rtl_readphy(struct rtl8169_private *tp, int location)
1074{
1075 switch (tp->mac_version) {
1076 case RTL_GIGA_MAC_VER_27:
1077 return r8168dp_1_mdio_read(tp, location);
1078 case RTL_GIGA_MAC_VER_28:
1079 case RTL_GIGA_MAC_VER_31:
1080 return r8168dp_2_mdio_read(tp, location);
1081 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
1082 return r8168g_mdio_read(tp, location);
1083 default:
1084 return r8169_mdio_read(tp, location);
1085 }
1086}
1087
1088DECLARE_RTL_COND(rtl_ephyar_cond)
1089{
1090 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1091}
1092
1093static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1094{
1095 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1096 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1097
1098 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1099
1100 udelay(10);
1101}
1102
1103static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1104{
1105 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1106
1107 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1108 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1109}
1110
1111static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1112{
1113 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1114 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1115 RTL_R32(tp, OCPDR) : ~0;
1116}
1117
1118static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1119{
1120 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1121}
1122
1123static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1124 u32 data)
1125{
1126 RTL_W32(tp, OCPDR, data);
1127 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1128 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1129}
1130
1131static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1132 u32 data)
1133{
1134 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1135 data, ERIAR_OOB);
1136}
1137
1138static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1139{
1140 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1141
1142 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1143}
1144
1145#define OOB_CMD_RESET 0x00
1146#define OOB_CMD_DRIVER_START 0x05
1147#define OOB_CMD_DRIVER_STOP 0x06
1148
1149static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1150{
1151 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1152}
1153
1154DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1155{
1156 u16 reg;
1157
1158 reg = rtl8168_get_ocp_reg(tp);
1159
1160 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1161}
1162
1163DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1164{
1165 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1166}
1167
1168DECLARE_RTL_COND(rtl_ocp_tx_cond)
1169{
1170 return RTL_R8(tp, IBISR0) & 0x20;
1171}
1172
1173static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1174{
1175 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1176 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1177 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1178 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1179}
1180
1181static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1182{
1183 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1184 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1185}
1186
1187static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1188{
1189 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1190 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1191 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1192}
1193
1194static void rtl8168_driver_start(struct rtl8169_private *tp)
1195{
1196 if (tp->dash_type == RTL_DASH_DP)
1197 rtl8168dp_driver_start(tp);
1198 else
1199 rtl8168ep_driver_start(tp);
1200}
1201
1202static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1203{
1204 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1205 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1206}
1207
1208static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1209{
1210 rtl8168ep_stop_cmac(tp);
1211 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1212 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1213 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1214}
1215
1216static void rtl8168_driver_stop(struct rtl8169_private *tp)
1217{
1218 if (tp->dash_type == RTL_DASH_DP)
1219 rtl8168dp_driver_stop(tp);
1220 else
1221 rtl8168ep_driver_stop(tp);
1222}
1223
1224static bool r8168dp_check_dash(struct rtl8169_private *tp)
1225{
1226 u16 reg = rtl8168_get_ocp_reg(tp);
1227
1228 return r8168dp_ocp_read(tp, reg) & BIT(15);
1229}
1230
1231static bool r8168ep_check_dash(struct rtl8169_private *tp)
1232{
1233 return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1234}
1235
1236static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)
1237{
1238 switch (tp->mac_version) {
1239 case RTL_GIGA_MAC_VER_27:
1240 case RTL_GIGA_MAC_VER_28:
1241 case RTL_GIGA_MAC_VER_31:
1242 return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;
1243 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
1244 return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;
1245 default:
1246 return RTL_DASH_NONE;
1247 }
1248}
1249
1250static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1251{
1252 switch (tp->mac_version) {
1253 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_26:
1254 case RTL_GIGA_MAC_VER_29 ... RTL_GIGA_MAC_VER_30:
1255 case RTL_GIGA_MAC_VER_32 ... RTL_GIGA_MAC_VER_37:
1256 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1257 if (enable)
1258 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);
1259 else
1260 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);
1261 break;
1262 default:
1263 break;
1264 }
1265}
1266
1267static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1268{
1269 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1270 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1271}
1272
1273DECLARE_RTL_COND(rtl_efusear_cond)
1274{
1275 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1276}
1277
1278u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1279{
1280 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1281
1282 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1283 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1284}
1285
1286static u32 rtl_get_events(struct rtl8169_private *tp)
1287{
1288 if (rtl_is_8125(tp))
1289 return RTL_R32(tp, IntrStatus_8125);
1290 else
1291 return RTL_R16(tp, IntrStatus);
1292}
1293
1294static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1295{
1296 if (rtl_is_8125(tp))
1297 RTL_W32(tp, IntrStatus_8125, bits);
1298 else
1299 RTL_W16(tp, IntrStatus, bits);
1300}
1301
1302static void rtl_irq_disable(struct rtl8169_private *tp)
1303{
1304 if (rtl_is_8125(tp))
1305 RTL_W32(tp, IntrMask_8125, 0);
1306 else
1307 RTL_W16(tp, IntrMask, 0);
1308}
1309
1310static void rtl_irq_enable(struct rtl8169_private *tp)
1311{
1312 if (rtl_is_8125(tp))
1313 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1314 else
1315 RTL_W16(tp, IntrMask, tp->irq_mask);
1316}
1317
1318static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1319{
1320 rtl_irq_disable(tp);
1321 rtl_ack_events(tp, 0xffffffff);
1322 rtl_pci_commit(tp);
1323}
1324
1325static void rtl_link_chg_patch(struct rtl8169_private *tp)
1326{
1327 struct phy_device *phydev = tp->phydev;
1328
1329 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1330 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1331 if (phydev->speed == SPEED_1000) {
1332 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1333 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1334 } else if (phydev->speed == SPEED_100) {
1335 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1336 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1337 } else {
1338 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1339 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1340 }
1341 rtl_reset_packet_filter(tp);
1342 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1343 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1344 if (phydev->speed == SPEED_1000) {
1345 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1346 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1347 } else {
1348 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1349 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1350 }
1351 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1352 if (phydev->speed == SPEED_10) {
1353 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1355 } else {
1356 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1357 }
1358 }
1359}
1360
1361#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1362
1363static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1364{
1365 struct rtl8169_private *tp = netdev_priv(dev);
1366
1367 wol->supported = WAKE_ANY;
1368 wol->wolopts = tp->saved_wolopts;
1369}
1370
1371static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1372{
1373 static const struct {
1374 u32 opt;
1375 u16 reg;
1376 u8 mask;
1377 } cfg[] = {
1378 { WAKE_PHY, Config3, LinkUp },
1379 { WAKE_UCAST, Config5, UWF },
1380 { WAKE_BCAST, Config5, BWF },
1381 { WAKE_MCAST, Config5, MWF },
1382 { WAKE_ANY, Config5, LanWake },
1383 { WAKE_MAGIC, Config3, MagicPacket }
1384 };
1385 unsigned int i, tmp = ARRAY_SIZE(cfg);
1386 u8 options;
1387
1388 rtl_unlock_config_regs(tp);
1389
1390 if (rtl_is_8168evl_up(tp)) {
1391 tmp--;
1392 if (wolopts & WAKE_MAGIC)
1393 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1394 else
1395 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1396 } else if (rtl_is_8125(tp)) {
1397 tmp--;
1398 if (wolopts & WAKE_MAGIC)
1399 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1400 else
1401 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1402 }
1403
1404 for (i = 0; i < tmp; i++) {
1405 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1406 if (wolopts & cfg[i].opt)
1407 options |= cfg[i].mask;
1408 RTL_W8(tp, cfg[i].reg, options);
1409 }
1410
1411 switch (tp->mac_version) {
1412 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1413 options = RTL_R8(tp, Config1) & ~PMEnable;
1414 if (wolopts)
1415 options |= PMEnable;
1416 RTL_W8(tp, Config1, options);
1417 break;
1418 case RTL_GIGA_MAC_VER_34:
1419 case RTL_GIGA_MAC_VER_37:
1420 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_63:
1421 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1422 if (wolopts)
1423 options |= PME_SIGNAL;
1424 RTL_W8(tp, Config2, options);
1425 break;
1426 default:
1427 break;
1428 }
1429
1430 rtl_lock_config_regs(tp);
1431
1432 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1433 rtl_set_d3_pll_down(tp, !wolopts);
1434 tp->dev->wol_enabled = wolopts ? 1 : 0;
1435}
1436
1437static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1438{
1439 struct rtl8169_private *tp = netdev_priv(dev);
1440
1441 if (wol->wolopts & ~WAKE_ANY)
1442 return -EINVAL;
1443
1444 tp->saved_wolopts = wol->wolopts;
1445 __rtl8169_set_wol(tp, tp->saved_wolopts);
1446
1447 return 0;
1448}
1449
1450static void rtl8169_get_drvinfo(struct net_device *dev,
1451 struct ethtool_drvinfo *info)
1452{
1453 struct rtl8169_private *tp = netdev_priv(dev);
1454 struct rtl_fw *rtl_fw = tp->rtl_fw;
1455
1456 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1457 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1458 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1459 if (rtl_fw)
1460 strlcpy(info->fw_version, rtl_fw->version,
1461 sizeof(info->fw_version));
1462}
1463
1464static int rtl8169_get_regs_len(struct net_device *dev)
1465{
1466 return R8169_REGS_SIZE;
1467}
1468
1469static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1470 netdev_features_t features)
1471{
1472 struct rtl8169_private *tp = netdev_priv(dev);
1473
1474 if (dev->mtu > TD_MSS_MAX)
1475 features &= ~NETIF_F_ALL_TSO;
1476
1477 if (dev->mtu > ETH_DATA_LEN &&
1478 tp->mac_version > RTL_GIGA_MAC_VER_06)
1479 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1480
1481 return features;
1482}
1483
1484static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1485 netdev_features_t features)
1486{
1487 u32 rx_config = RTL_R32(tp, RxConfig);
1488
1489 if (features & NETIF_F_RXALL)
1490 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1491 else
1492 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1493
1494 if (rtl_is_8125(tp)) {
1495 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1496 rx_config |= RX_VLAN_8125;
1497 else
1498 rx_config &= ~RX_VLAN_8125;
1499 }
1500
1501 RTL_W32(tp, RxConfig, rx_config);
1502}
1503
1504static int rtl8169_set_features(struct net_device *dev,
1505 netdev_features_t features)
1506{
1507 struct rtl8169_private *tp = netdev_priv(dev);
1508
1509 rtl_set_rx_config_features(tp, features);
1510
1511 if (features & NETIF_F_RXCSUM)
1512 tp->cp_cmd |= RxChkSum;
1513 else
1514 tp->cp_cmd &= ~RxChkSum;
1515
1516 if (!rtl_is_8125(tp)) {
1517 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1518 tp->cp_cmd |= RxVlan;
1519 else
1520 tp->cp_cmd &= ~RxVlan;
1521 }
1522
1523 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1524 rtl_pci_commit(tp);
1525
1526 return 0;
1527}
1528
1529static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1530{
1531 return (skb_vlan_tag_present(skb)) ?
1532 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1533}
1534
1535static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1536{
1537 u32 opts2 = le32_to_cpu(desc->opts2);
1538
1539 if (opts2 & RxVlanTag)
1540 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1541}
1542
1543static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1544 void *p)
1545{
1546 struct rtl8169_private *tp = netdev_priv(dev);
1547 u32 __iomem *data = tp->mmio_addr;
1548 u32 *dw = p;
1549 int i;
1550
1551 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1552 memcpy_fromio(dw++, data++, 4);
1553}
1554
1555static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1556 "tx_packets",
1557 "rx_packets",
1558 "tx_errors",
1559 "rx_errors",
1560 "rx_missed",
1561 "align_errors",
1562 "tx_single_collisions",
1563 "tx_multi_collisions",
1564 "unicast",
1565 "broadcast",
1566 "multicast",
1567 "tx_aborted",
1568 "tx_underrun",
1569};
1570
1571static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1572{
1573 switch (sset) {
1574 case ETH_SS_STATS:
1575 return ARRAY_SIZE(rtl8169_gstrings);
1576 default:
1577 return -EOPNOTSUPP;
1578 }
1579}
1580
1581DECLARE_RTL_COND(rtl_counters_cond)
1582{
1583 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1584}
1585
1586static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1587{
1588 u32 cmd = lower_32_bits(tp->counters_phys_addr);
1589
1590 RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1591 rtl_pci_commit(tp);
1592 RTL_W32(tp, CounterAddrLow, cmd);
1593 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1594
1595 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1596}
1597
1598static void rtl8169_update_counters(struct rtl8169_private *tp)
1599{
1600 u8 val = RTL_R8(tp, ChipCmd);
1601
1602
1603
1604
1605
1606 if (val & CmdRxEnb && val != 0xff)
1607 rtl8169_do_counters(tp, CounterDump);
1608}
1609
1610static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1611{
1612 struct rtl8169_counters *counters = tp->counters;
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629 if (tp->tc_offset.inited)
1630 return;
1631
1632 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1633 rtl8169_do_counters(tp, CounterReset);
1634 } else {
1635 rtl8169_update_counters(tp);
1636 tp->tc_offset.tx_errors = counters->tx_errors;
1637 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1638 tp->tc_offset.tx_aborted = counters->tx_aborted;
1639 tp->tc_offset.rx_missed = counters->rx_missed;
1640 }
1641
1642 tp->tc_offset.inited = true;
1643}
1644
1645static void rtl8169_get_ethtool_stats(struct net_device *dev,
1646 struct ethtool_stats *stats, u64 *data)
1647{
1648 struct rtl8169_private *tp = netdev_priv(dev);
1649 struct rtl8169_counters *counters;
1650
1651 counters = tp->counters;
1652 rtl8169_update_counters(tp);
1653
1654 data[0] = le64_to_cpu(counters->tx_packets);
1655 data[1] = le64_to_cpu(counters->rx_packets);
1656 data[2] = le64_to_cpu(counters->tx_errors);
1657 data[3] = le32_to_cpu(counters->rx_errors);
1658 data[4] = le16_to_cpu(counters->rx_missed);
1659 data[5] = le16_to_cpu(counters->align_errors);
1660 data[6] = le32_to_cpu(counters->tx_one_collision);
1661 data[7] = le32_to_cpu(counters->tx_multi_collision);
1662 data[8] = le64_to_cpu(counters->rx_unicast);
1663 data[9] = le64_to_cpu(counters->rx_broadcast);
1664 data[10] = le32_to_cpu(counters->rx_multicast);
1665 data[11] = le16_to_cpu(counters->tx_aborted);
1666 data[12] = le16_to_cpu(counters->tx_underun);
1667}
1668
1669static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1670{
1671 switch(stringset) {
1672 case ETH_SS_STATS:
1673 memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1674 break;
1675 }
1676}
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707struct rtl_coalesce_info {
1708 u32 speed;
1709 u32 scale_nsecs[4];
1710};
1711
1712
1713#define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1714
1715static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1716 { SPEED_1000, COALESCE_DELAY(320) },
1717 { SPEED_100, COALESCE_DELAY(2560) },
1718 { SPEED_10, COALESCE_DELAY(40960) },
1719 { 0 },
1720};
1721
1722static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1723 { SPEED_1000, COALESCE_DELAY(5000) },
1724 { SPEED_100, COALESCE_DELAY(2560) },
1725 { SPEED_10, COALESCE_DELAY(40960) },
1726 { 0 },
1727};
1728#undef COALESCE_DELAY
1729
1730
1731static const struct rtl_coalesce_info *
1732rtl_coalesce_info(struct rtl8169_private *tp)
1733{
1734 const struct rtl_coalesce_info *ci;
1735
1736 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1737 ci = rtl_coalesce_info_8169;
1738 else
1739 ci = rtl_coalesce_info_8168_8136;
1740
1741
1742 if (tp->phydev->speed == SPEED_UNKNOWN)
1743 return ci;
1744
1745 for (; ci->speed; ci++) {
1746 if (tp->phydev->speed == ci->speed)
1747 return ci;
1748 }
1749
1750 return ERR_PTR(-ELNRNG);
1751}
1752
1753static int rtl_get_coalesce(struct net_device *dev,
1754 struct ethtool_coalesce *ec,
1755 struct kernel_ethtool_coalesce *kernel_coal,
1756 struct netlink_ext_ack *extack)
1757{
1758 struct rtl8169_private *tp = netdev_priv(dev);
1759 const struct rtl_coalesce_info *ci;
1760 u32 scale, c_us, c_fr;
1761 u16 intrmit;
1762
1763 if (rtl_is_8125(tp))
1764 return -EOPNOTSUPP;
1765
1766 memset(ec, 0, sizeof(*ec));
1767
1768
1769 ci = rtl_coalesce_info(tp);
1770 if (IS_ERR(ci))
1771 return PTR_ERR(ci);
1772
1773 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1774
1775 intrmit = RTL_R16(tp, IntrMitigate);
1776
1777 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1778 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1779
1780 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1781
1782 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1783
1784 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1785 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1786
1787 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1788 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1789
1790 return 0;
1791}
1792
1793
1794static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1795 u16 *cp01)
1796{
1797 const struct rtl_coalesce_info *ci;
1798 u16 i;
1799
1800 ci = rtl_coalesce_info(tp);
1801 if (IS_ERR(ci))
1802 return PTR_ERR(ci);
1803
1804 for (i = 0; i < 4; i++) {
1805 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1806 *cp01 = i;
1807 return ci->scale_nsecs[i];
1808 }
1809 }
1810
1811 return -ERANGE;
1812}
1813
1814static int rtl_set_coalesce(struct net_device *dev,
1815 struct ethtool_coalesce *ec,
1816 struct kernel_ethtool_coalesce *kernel_coal,
1817 struct netlink_ext_ack *extack)
1818{
1819 struct rtl8169_private *tp = netdev_priv(dev);
1820 u32 tx_fr = ec->tx_max_coalesced_frames;
1821 u32 rx_fr = ec->rx_max_coalesced_frames;
1822 u32 coal_usec_max, units;
1823 u16 w = 0, cp01 = 0;
1824 int scale;
1825
1826 if (rtl_is_8125(tp))
1827 return -EOPNOTSUPP;
1828
1829 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
1830 return -ERANGE;
1831
1832 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
1833 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1834 if (scale < 0)
1835 return scale;
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847 if (rx_fr == 1)
1848 rx_fr = 0;
1849 if (tx_fr == 1)
1850 tx_fr = 0;
1851
1852
1853 if ((tx_fr && !ec->tx_coalesce_usecs) ||
1854 (rx_fr && !ec->rx_coalesce_usecs))
1855 return -EINVAL;
1856
1857 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
1858 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
1859
1860 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
1861 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
1862 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
1863 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
1864
1865 RTL_W16(tp, IntrMitigate, w);
1866
1867
1868 if (rtl_is_8168evl_up(tp)) {
1869 if (!rx_fr && !tx_fr)
1870
1871 tp->cp_cmd |= PktCntrDisable;
1872 else
1873 tp->cp_cmd &= ~PktCntrDisable;
1874 }
1875
1876 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1877 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1878 rtl_pci_commit(tp);
1879
1880 return 0;
1881}
1882
1883static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1884{
1885 struct rtl8169_private *tp = netdev_priv(dev);
1886
1887 if (!rtl_supports_eee(tp))
1888 return -EOPNOTSUPP;
1889
1890 return phy_ethtool_get_eee(tp->phydev, data);
1891}
1892
1893static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1894{
1895 struct rtl8169_private *tp = netdev_priv(dev);
1896 int ret;
1897
1898 if (!rtl_supports_eee(tp))
1899 return -EOPNOTSUPP;
1900
1901 ret = phy_ethtool_set_eee(tp->phydev, data);
1902
1903 if (!ret)
1904 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1905 MDIO_AN_EEE_ADV);
1906 return ret;
1907}
1908
1909static void rtl8169_get_ringparam(struct net_device *dev,
1910 struct ethtool_ringparam *data)
1911{
1912 data->rx_max_pending = NUM_RX_DESC;
1913 data->rx_pending = NUM_RX_DESC;
1914 data->tx_max_pending = NUM_TX_DESC;
1915 data->tx_pending = NUM_TX_DESC;
1916}
1917
1918static void rtl8169_get_pauseparam(struct net_device *dev,
1919 struct ethtool_pauseparam *data)
1920{
1921 struct rtl8169_private *tp = netdev_priv(dev);
1922 bool tx_pause, rx_pause;
1923
1924 phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
1925
1926 data->autoneg = tp->phydev->autoneg;
1927 data->tx_pause = tx_pause ? 1 : 0;
1928 data->rx_pause = rx_pause ? 1 : 0;
1929}
1930
1931static int rtl8169_set_pauseparam(struct net_device *dev,
1932 struct ethtool_pauseparam *data)
1933{
1934 struct rtl8169_private *tp = netdev_priv(dev);
1935
1936 if (dev->mtu > ETH_DATA_LEN)
1937 return -EOPNOTSUPP;
1938
1939 phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
1940
1941 return 0;
1942}
1943
1944static const struct ethtool_ops rtl8169_ethtool_ops = {
1945 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1946 ETHTOOL_COALESCE_MAX_FRAMES,
1947 .get_drvinfo = rtl8169_get_drvinfo,
1948 .get_regs_len = rtl8169_get_regs_len,
1949 .get_link = ethtool_op_get_link,
1950 .get_coalesce = rtl_get_coalesce,
1951 .set_coalesce = rtl_set_coalesce,
1952 .get_regs = rtl8169_get_regs,
1953 .get_wol = rtl8169_get_wol,
1954 .set_wol = rtl8169_set_wol,
1955 .get_strings = rtl8169_get_strings,
1956 .get_sset_count = rtl8169_get_sset_count,
1957 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1958 .get_ts_info = ethtool_op_get_ts_info,
1959 .nway_reset = phy_ethtool_nway_reset,
1960 .get_eee = rtl8169_get_eee,
1961 .set_eee = rtl8169_set_eee,
1962 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1963 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1964 .get_ringparam = rtl8169_get_ringparam,
1965 .get_pauseparam = rtl8169_get_pauseparam,
1966 .set_pauseparam = rtl8169_set_pauseparam,
1967};
1968
1969static void rtl_enable_eee(struct rtl8169_private *tp)
1970{
1971 struct phy_device *phydev = tp->phydev;
1972 int adv;
1973
1974
1975 if (tp->eee_adv >= 0)
1976 adv = tp->eee_adv;
1977 else
1978 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
1979
1980 if (adv >= 0)
1981 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
1982}
1983
1984static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
1985{
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997 static const struct rtl_mac_info {
1998 u16 mask;
1999 u16 val;
2000 enum mac_version ver;
2001 } mac_info[] = {
2002
2003 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 },
2004
2005
2006 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2007 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2008
2009
2010 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 },
2011 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2012
2013
2014 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2015 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2016 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2017
2018
2019 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2020 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2021
2022
2023 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2024 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2025 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2026 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2027
2028
2029 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2030 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2031 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2032
2033
2034 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2035 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2036 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2037
2038
2039 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2040 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2041
2042
2043
2044
2045
2046
2047
2048 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2049 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2050
2051
2052 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2053 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2054 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2055 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2056 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2057 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2058 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2059
2060
2061 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2062 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2063 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2064
2065
2066 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2067 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2068 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2069 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2070 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2071 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2072 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2073 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2074 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2075 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 },
2076 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2077 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2078 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2079 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2080 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2081
2082
2083
2084
2085
2086
2087
2088
2089 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2090 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2091 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2092 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2093 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2094
2095
2096 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2097 };
2098 const struct rtl_mac_info *p = mac_info;
2099 enum mac_version ver;
2100
2101 while ((xid & p->mask) != p->val)
2102 p++;
2103 ver = p->ver;
2104
2105 if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2106 if (ver == RTL_GIGA_MAC_VER_42)
2107 ver = RTL_GIGA_MAC_VER_43;
2108 else if (ver == RTL_GIGA_MAC_VER_45)
2109 ver = RTL_GIGA_MAC_VER_47;
2110 else if (ver == RTL_GIGA_MAC_VER_46)
2111 ver = RTL_GIGA_MAC_VER_48;
2112 }
2113
2114 return ver;
2115}
2116
2117static void rtl_release_firmware(struct rtl8169_private *tp)
2118{
2119 if (tp->rtl_fw) {
2120 rtl_fw_release_firmware(tp->rtl_fw);
2121 kfree(tp->rtl_fw);
2122 tp->rtl_fw = NULL;
2123 }
2124}
2125
2126void r8169_apply_firmware(struct rtl8169_private *tp)
2127{
2128 int val;
2129
2130
2131 if (tp->rtl_fw) {
2132 rtl_fw_write_firmware(tp, tp->rtl_fw);
2133
2134 tp->ocp_base = OCP_STD_PHY_BASE;
2135
2136
2137 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2138 !(val & BMCR_RESET),
2139 50000, 600000, true);
2140 }
2141}
2142
2143static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2144{
2145
2146 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2147 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2148
2149 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2150}
2151
2152static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2153{
2154 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2155 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2156}
2157
2158static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2159{
2160 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2161}
2162
2163static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2164{
2165 rtl8125_set_eee_txidle_timer(tp);
2166 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2167}
2168
2169static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2170{
2171 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2172 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2173 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2174 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2175}
2176
2177u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2178{
2179 u16 data1, data2, ioffset;
2180
2181 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2182 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2183 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2184
2185 ioffset = (data2 >> 1) & 0x7ff8;
2186 ioffset |= data2 & 0x0007;
2187 if (data1 & BIT(7))
2188 ioffset |= BIT(15);
2189
2190 return ioffset;
2191}
2192
2193static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2194{
2195 set_bit(flag, tp->wk.flags);
2196 schedule_work(&tp->wk.work);
2197}
2198
2199static void rtl8169_init_phy(struct rtl8169_private *tp)
2200{
2201 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2202
2203 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2204 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2205 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2206
2207 RTL_W8(tp, 0x82, 0x01);
2208 }
2209
2210 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2211 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2212 tp->pci_dev->subsystem_device == 0xe000)
2213 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2214
2215
2216 phy_speed_up(tp->phydev);
2217
2218 if (rtl_supports_eee(tp))
2219 rtl_enable_eee(tp);
2220
2221 genphy_soft_reset(tp->phydev);
2222}
2223
2224static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2225{
2226 rtl_unlock_config_regs(tp);
2227
2228 RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2229 rtl_pci_commit(tp);
2230
2231 RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2232 rtl_pci_commit(tp);
2233
2234 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2235 rtl_rar_exgmac_set(tp, addr);
2236
2237 rtl_lock_config_regs(tp);
2238}
2239
2240static int rtl_set_mac_address(struct net_device *dev, void *p)
2241{
2242 struct rtl8169_private *tp = netdev_priv(dev);
2243 int ret;
2244
2245 ret = eth_mac_addr(dev, p);
2246 if (ret)
2247 return ret;
2248
2249 rtl_rar_set(tp, dev->dev_addr);
2250
2251 return 0;
2252}
2253
2254static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2255{
2256 if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2257 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2258 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2259}
2260
2261static void rtl_prepare_power_down(struct rtl8169_private *tp)
2262{
2263 if (tp->dash_type != RTL_DASH_NONE)
2264 return;
2265
2266 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2267 tp->mac_version == RTL_GIGA_MAC_VER_33)
2268 rtl_ephy_write(tp, 0x19, 0xff64);
2269
2270 if (device_may_wakeup(tp_to_dev(tp))) {
2271 phy_speed_down(tp->phydev, false);
2272 rtl_wol_enable_rx(tp);
2273 }
2274}
2275
2276static void rtl_init_rxcfg(struct rtl8169_private *tp)
2277{
2278 switch (tp->mac_version) {
2279 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2280 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2281 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2282 break;
2283 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2284 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2285 case RTL_GIGA_MAC_VER_38:
2286 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2287 break;
2288 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2289 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2290 break;
2291 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2292 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2293 break;
2294 default:
2295 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2296 break;
2297 }
2298}
2299
2300static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2301{
2302 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2303}
2304
2305static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2306{
2307 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2308 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2309}
2310
2311static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2312{
2313 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2314 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2315}
2316
2317static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2318{
2319 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2320}
2321
2322static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2323{
2324 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2325}
2326
2327static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2328{
2329 RTL_W8(tp, MaxTxPacketSize, 0x24);
2330 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2331 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2332}
2333
2334static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2335{
2336 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2337 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2338 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2339}
2340
2341static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2342{
2343 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2344}
2345
2346static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2347{
2348 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2349}
2350
2351static void rtl_jumbo_config(struct rtl8169_private *tp)
2352{
2353 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2354 int readrq = 4096;
2355
2356 rtl_unlock_config_regs(tp);
2357 switch (tp->mac_version) {
2358 case RTL_GIGA_MAC_VER_12:
2359 case RTL_GIGA_MAC_VER_17:
2360 if (jumbo) {
2361 readrq = 512;
2362 r8168b_1_hw_jumbo_enable(tp);
2363 } else {
2364 r8168b_1_hw_jumbo_disable(tp);
2365 }
2366 break;
2367 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2368 if (jumbo) {
2369 readrq = 512;
2370 r8168c_hw_jumbo_enable(tp);
2371 } else {
2372 r8168c_hw_jumbo_disable(tp);
2373 }
2374 break;
2375 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2376 if (jumbo)
2377 r8168dp_hw_jumbo_enable(tp);
2378 else
2379 r8168dp_hw_jumbo_disable(tp);
2380 break;
2381 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2382 if (jumbo)
2383 r8168e_hw_jumbo_enable(tp);
2384 else
2385 r8168e_hw_jumbo_disable(tp);
2386 break;
2387 default:
2388 break;
2389 }
2390 rtl_lock_config_regs(tp);
2391
2392 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2393 pcie_set_readrq(tp->pci_dev, readrq);
2394
2395
2396 if (jumbo) {
2397 linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2398 tp->phydev->advertising);
2399 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2400 tp->phydev->advertising);
2401 phy_start_aneg(tp->phydev);
2402 }
2403}
2404
2405DECLARE_RTL_COND(rtl_chipcmd_cond)
2406{
2407 return RTL_R8(tp, ChipCmd) & CmdReset;
2408}
2409
2410static void rtl_hw_reset(struct rtl8169_private *tp)
2411{
2412 RTL_W8(tp, ChipCmd, CmdReset);
2413
2414 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2415}
2416
2417static void rtl_request_firmware(struct rtl8169_private *tp)
2418{
2419 struct rtl_fw *rtl_fw;
2420
2421
2422 if (tp->rtl_fw || !tp->fw_name)
2423 return;
2424
2425 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2426 if (!rtl_fw)
2427 return;
2428
2429 rtl_fw->phy_write = rtl_writephy;
2430 rtl_fw->phy_read = rtl_readphy;
2431 rtl_fw->mac_mcu_write = mac_mcu_write;
2432 rtl_fw->mac_mcu_read = mac_mcu_read;
2433 rtl_fw->fw_name = tp->fw_name;
2434 rtl_fw->dev = tp_to_dev(tp);
2435
2436 if (rtl_fw_request_firmware(rtl_fw))
2437 kfree(rtl_fw);
2438 else
2439 tp->rtl_fw = rtl_fw;
2440}
2441
2442static void rtl_rx_close(struct rtl8169_private *tp)
2443{
2444 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2445}
2446
2447DECLARE_RTL_COND(rtl_npq_cond)
2448{
2449 return RTL_R8(tp, TxPoll) & NPQ;
2450}
2451
2452DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2453{
2454 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2455}
2456
2457DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2458{
2459 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2460}
2461
2462DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2463{
2464
2465 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2466}
2467
2468static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2469{
2470 switch (tp->mac_version) {
2471 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2472 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2473 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2474 break;
2475 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2476 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2477 break;
2478 case RTL_GIGA_MAC_VER_63:
2479 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2480 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2481 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2482 break;
2483 default:
2484 break;
2485 }
2486}
2487
2488static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2489{
2490 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2491 fsleep(2000);
2492 rtl_wait_txrx_fifo_empty(tp);
2493}
2494
2495static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2496{
2497 u32 val = TX_DMA_BURST << TxDMAShift |
2498 InterFrameGap << TxInterFrameGapShift;
2499
2500 if (rtl_is_8168evl_up(tp))
2501 val |= TXCFG_AUTO_FIFO;
2502
2503 RTL_W32(tp, TxConfig, val);
2504}
2505
2506static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2507{
2508
2509 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2510}
2511
2512static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2513{
2514
2515
2516
2517
2518
2519 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2520 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2521 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2522 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2523}
2524
2525static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2526{
2527 u32 val;
2528
2529 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2530 val = 0x000fff00;
2531 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2532 val = 0x00ffff00;
2533 else
2534 return;
2535
2536 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2537 val |= 0xff;
2538
2539 RTL_W32(tp, 0x7c, val);
2540}
2541
2542static void rtl_set_rx_mode(struct net_device *dev)
2543{
2544 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2545
2546 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2547 struct rtl8169_private *tp = netdev_priv(dev);
2548 u32 tmp;
2549
2550 if (dev->flags & IFF_PROMISC) {
2551 rx_mode |= AcceptAllPhys;
2552 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2553 dev->flags & IFF_ALLMULTI ||
2554 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2555
2556 } else if (netdev_mc_empty(dev)) {
2557 rx_mode &= ~AcceptMulticast;
2558 } else {
2559 struct netdev_hw_addr *ha;
2560
2561 mc_filter[1] = mc_filter[0] = 0;
2562 netdev_for_each_mc_addr(ha, dev) {
2563 u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2564 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2565 }
2566
2567 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2568 tmp = mc_filter[0];
2569 mc_filter[0] = swab32(mc_filter[1]);
2570 mc_filter[1] = swab32(tmp);
2571 }
2572 }
2573
2574 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2575 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2576
2577 tmp = RTL_R32(tp, RxConfig);
2578 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2579}
2580
2581DECLARE_RTL_COND(rtl_csiar_cond)
2582{
2583 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2584}
2585
2586static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2587{
2588 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2589
2590 RTL_W32(tp, CSIDR, value);
2591 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2592 CSIAR_BYTE_ENABLE | func << 16);
2593
2594 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2595}
2596
2597static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2598{
2599 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2600
2601 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2602 CSIAR_BYTE_ENABLE);
2603
2604 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2605 RTL_R32(tp, CSIDR) : ~0;
2606}
2607
2608static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2609{
2610 struct pci_dev *pdev = tp->pci_dev;
2611 u32 csi;
2612
2613
2614
2615
2616
2617
2618
2619 if (pdev->cfg_size > 0x070f &&
2620 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2621 return;
2622
2623 netdev_notice_once(tp->dev,
2624 "No native access to PCI extended config space, falling back to CSI\n");
2625 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2626 rtl_csi_write(tp, 0x070c, csi | val << 24);
2627}
2628
2629static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2630{
2631
2632 rtl_set_aspm_entry_latency(tp, 0x27);
2633}
2634
2635struct ephy_info {
2636 unsigned int offset;
2637 u16 mask;
2638 u16 bits;
2639};
2640
2641static void __rtl_ephy_init(struct rtl8169_private *tp,
2642 const struct ephy_info *e, int len)
2643{
2644 u16 w;
2645
2646 while (len-- > 0) {
2647 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2648 rtl_ephy_write(tp, e->offset, w);
2649 e++;
2650 }
2651}
2652
2653#define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2654
2655static void rtl_disable_clock_request(struct rtl8169_private *tp)
2656{
2657 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2658 PCI_EXP_LNKCTL_CLKREQ_EN);
2659}
2660
2661static void rtl_enable_clock_request(struct rtl8169_private *tp)
2662{
2663 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2664 PCI_EXP_LNKCTL_CLKREQ_EN);
2665}
2666
2667static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2668{
2669
2670 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2671}
2672
2673static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2674{
2675
2676
2677
2678
2679
2680
2681
2682
2683 switch (tp->mac_version) {
2684 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2685 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2686 break;
2687 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2688 rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2689 break;
2690 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2691 rtl_eri_set_bits(tp, 0xd4, 0x1f80);
2692 break;
2693 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
2694 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2695 break;
2696 default:
2697 break;
2698 }
2699}
2700
2701static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2702{
2703
2704 if (enable && tp->aspm_manageable) {
2705 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2706 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2707 } else {
2708 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2709 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2710 }
2711
2712 udelay(10);
2713}
2714
2715static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2716 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2717{
2718
2719
2720
2721 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2722 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2723}
2724
2725static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2726 u8 low, u8 high)
2727{
2728
2729 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2730 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2731}
2732
2733static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2734{
2735 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2736}
2737
2738static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2739{
2740 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2741
2742 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2743
2744 rtl_disable_clock_request(tp);
2745}
2746
2747static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2748{
2749 static const struct ephy_info e_info_8168cp[] = {
2750 { 0x01, 0, 0x0001 },
2751 { 0x02, 0x0800, 0x1000 },
2752 { 0x03, 0, 0x0042 },
2753 { 0x06, 0x0080, 0x0000 },
2754 { 0x07, 0, 0x2000 }
2755 };
2756
2757 rtl_set_def_aspm_entry_latency(tp);
2758
2759 rtl_ephy_init(tp, e_info_8168cp);
2760
2761 __rtl_hw_start_8168cp(tp);
2762}
2763
2764static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2765{
2766 rtl_set_def_aspm_entry_latency(tp);
2767
2768 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2769}
2770
2771static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2772{
2773 rtl_set_def_aspm_entry_latency(tp);
2774
2775 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2776
2777
2778 RTL_W8(tp, DBG_REG, 0x20);
2779}
2780
2781static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2782{
2783 static const struct ephy_info e_info_8168c_1[] = {
2784 { 0x02, 0x0800, 0x1000 },
2785 { 0x03, 0, 0x0002 },
2786 { 0x06, 0x0080, 0x0000 }
2787 };
2788
2789 rtl_set_def_aspm_entry_latency(tp);
2790
2791 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2792
2793 rtl_ephy_init(tp, e_info_8168c_1);
2794
2795 __rtl_hw_start_8168cp(tp);
2796}
2797
2798static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2799{
2800 static const struct ephy_info e_info_8168c_2[] = {
2801 { 0x01, 0, 0x0001 },
2802 { 0x03, 0x0400, 0x0020 }
2803 };
2804
2805 rtl_set_def_aspm_entry_latency(tp);
2806
2807 rtl_ephy_init(tp, e_info_8168c_2);
2808
2809 __rtl_hw_start_8168cp(tp);
2810}
2811
2812static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2813{
2814 rtl_set_def_aspm_entry_latency(tp);
2815
2816 __rtl_hw_start_8168cp(tp);
2817}
2818
2819static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2820{
2821 rtl_set_def_aspm_entry_latency(tp);
2822
2823 rtl_disable_clock_request(tp);
2824}
2825
2826static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2827{
2828 static const struct ephy_info e_info_8168d_4[] = {
2829 { 0x0b, 0x0000, 0x0048 },
2830 { 0x19, 0x0020, 0x0050 },
2831 { 0x0c, 0x0100, 0x0020 },
2832 { 0x10, 0x0004, 0x0000 },
2833 };
2834
2835 rtl_set_def_aspm_entry_latency(tp);
2836
2837 rtl_ephy_init(tp, e_info_8168d_4);
2838
2839 rtl_enable_clock_request(tp);
2840}
2841
2842static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2843{
2844 static const struct ephy_info e_info_8168e_1[] = {
2845 { 0x00, 0x0200, 0x0100 },
2846 { 0x00, 0x0000, 0x0004 },
2847 { 0x06, 0x0002, 0x0001 },
2848 { 0x06, 0x0000, 0x0030 },
2849 { 0x07, 0x0000, 0x2000 },
2850 { 0x00, 0x0000, 0x0020 },
2851 { 0x03, 0x5800, 0x2000 },
2852 { 0x03, 0x0000, 0x0001 },
2853 { 0x01, 0x0800, 0x1000 },
2854 { 0x07, 0x0000, 0x4000 },
2855 { 0x1e, 0x0000, 0x2000 },
2856 { 0x19, 0xffff, 0xfe6c },
2857 { 0x0a, 0x0000, 0x0040 }
2858 };
2859
2860 rtl_set_def_aspm_entry_latency(tp);
2861
2862 rtl_ephy_init(tp, e_info_8168e_1);
2863
2864 rtl_disable_clock_request(tp);
2865
2866
2867 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2868 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2869
2870 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2871}
2872
2873static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2874{
2875 static const struct ephy_info e_info_8168e_2[] = {
2876 { 0x09, 0x0000, 0x0080 },
2877 { 0x19, 0x0000, 0x0224 },
2878 { 0x00, 0x0000, 0x0004 },
2879 { 0x0c, 0x3df0, 0x0200 },
2880 };
2881
2882 rtl_set_def_aspm_entry_latency(tp);
2883
2884 rtl_ephy_init(tp, e_info_8168e_2);
2885
2886 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2887 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2888 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2889 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2890 rtl_reset_packet_filter(tp);
2891 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2892 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2893 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2894
2895 rtl_disable_clock_request(tp);
2896
2897 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2898
2899 rtl8168_config_eee_mac(tp);
2900
2901 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2902 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2903 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2904
2905 rtl_hw_aspm_clkreq_enable(tp, true);
2906}
2907
2908static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2909{
2910 rtl_set_def_aspm_entry_latency(tp);
2911
2912 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2913 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2914 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2915 rtl_reset_packet_filter(tp);
2916 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2917 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2918 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2919 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2920
2921 rtl_disable_clock_request(tp);
2922
2923 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2924 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2925 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2926 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2927
2928 rtl8168_config_eee_mac(tp);
2929}
2930
2931static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2932{
2933 static const struct ephy_info e_info_8168f_1[] = {
2934 { 0x06, 0x00c0, 0x0020 },
2935 { 0x08, 0x0001, 0x0002 },
2936 { 0x09, 0x0000, 0x0080 },
2937 { 0x19, 0x0000, 0x0224 },
2938 { 0x00, 0x0000, 0x0008 },
2939 { 0x0c, 0x3df0, 0x0200 },
2940 };
2941
2942 rtl_hw_start_8168f(tp);
2943
2944 rtl_ephy_init(tp, e_info_8168f_1);
2945}
2946
2947static void rtl_hw_start_8411(struct rtl8169_private *tp)
2948{
2949 static const struct ephy_info e_info_8168f_1[] = {
2950 { 0x06, 0x00c0, 0x0020 },
2951 { 0x0f, 0xffff, 0x5200 },
2952 { 0x19, 0x0000, 0x0224 },
2953 { 0x00, 0x0000, 0x0008 },
2954 { 0x0c, 0x3df0, 0x0200 },
2955 };
2956
2957 rtl_hw_start_8168f(tp);
2958 rtl_pcie_state_l2l3_disable(tp);
2959
2960 rtl_ephy_init(tp, e_info_8168f_1);
2961}
2962
2963static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2964{
2965 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2966 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2967
2968 rtl_set_def_aspm_entry_latency(tp);
2969
2970 rtl_reset_packet_filter(tp);
2971 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2972
2973 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2974
2975 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2976 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2977
2978 rtl8168_config_eee_mac(tp);
2979
2980 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2981 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
2982
2983 rtl_pcie_state_l2l3_disable(tp);
2984}
2985
2986static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
2987{
2988 static const struct ephy_info e_info_8168g_1[] = {
2989 { 0x00, 0x0008, 0x0000 },
2990 { 0x0c, 0x3ff0, 0x0820 },
2991 { 0x1e, 0x0000, 0x0001 },
2992 { 0x19, 0x8000, 0x0000 }
2993 };
2994
2995 rtl_hw_start_8168g(tp);
2996
2997
2998 rtl_hw_aspm_clkreq_enable(tp, false);
2999 rtl_ephy_init(tp, e_info_8168g_1);
3000 rtl_hw_aspm_clkreq_enable(tp, true);
3001}
3002
3003static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3004{
3005 static const struct ephy_info e_info_8168g_2[] = {
3006 { 0x00, 0x0008, 0x0000 },
3007 { 0x0c, 0x3ff0, 0x0820 },
3008 { 0x19, 0xffff, 0x7c00 },
3009 { 0x1e, 0xffff, 0x20eb },
3010 { 0x0d, 0xffff, 0x1666 },
3011 { 0x00, 0xffff, 0x10a3 },
3012 { 0x06, 0xffff, 0xf050 },
3013 { 0x04, 0x0000, 0x0010 },
3014 { 0x1d, 0x4000, 0x0000 },
3015 };
3016
3017 rtl_hw_start_8168g(tp);
3018
3019
3020 rtl_hw_aspm_clkreq_enable(tp, false);
3021 rtl_ephy_init(tp, e_info_8168g_2);
3022}
3023
3024static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3025{
3026 static const struct ephy_info e_info_8411_2[] = {
3027 { 0x00, 0x0008, 0x0000 },
3028 { 0x0c, 0x37d0, 0x0820 },
3029 { 0x1e, 0x0000, 0x0001 },
3030 { 0x19, 0x8021, 0x0000 },
3031 { 0x1e, 0x0000, 0x2000 },
3032 { 0x0d, 0x0100, 0x0200 },
3033 { 0x00, 0x0000, 0x0080 },
3034 { 0x06, 0x0000, 0x0010 },
3035 { 0x04, 0x0000, 0x0010 },
3036 { 0x1d, 0x0000, 0x4000 },
3037 };
3038
3039 rtl_hw_start_8168g(tp);
3040
3041
3042 rtl_hw_aspm_clkreq_enable(tp, false);
3043 rtl_ephy_init(tp, e_info_8411_2);
3044
3045
3046
3047
3048 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3049 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3050 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3051 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3052 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3053 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3054 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3055 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3056 mdelay(3);
3057 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3058
3059 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3060 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3061 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3062 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3063 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3064 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3065 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3066 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3067 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3068 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3069 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3070 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3071 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3072 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3073 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3074 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3075 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3076 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3077 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3078 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3079 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3080 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3081 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3082 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3083 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3084 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3085 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3086 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3087 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3088 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3089 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3090 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3091 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3092 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3093 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3094 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3095 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3096 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3097 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3098 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3099 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3100 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3101 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3102 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3103 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3104 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3105 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3106 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3107 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3108 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3109 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3110 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3111 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3112 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3113 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3114 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3115 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3116 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3117 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3118 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3119 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3120 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3121 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3122 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3123 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3124 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3125 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3126 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3127 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3128 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3129 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3130 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3131 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3132 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3133 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3134 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3135 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3136 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3137 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3138 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3139 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3140 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3141 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3142 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3143 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3144 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3145 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3146 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3147 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3148 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3149 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3150 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3151 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3152 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3153 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3154 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3155 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3156 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3157 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3158 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3159 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3160 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3161 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3162 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3163 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3164 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3165 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3166 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3167 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3168 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3169 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3170
3171 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3172
3173 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3174 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3175 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3176 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3177 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3178 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3179 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3180
3181 rtl_hw_aspm_clkreq_enable(tp, true);
3182}
3183
3184static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3185{
3186 static const struct ephy_info e_info_8168h_1[] = {
3187 { 0x1e, 0x0800, 0x0001 },
3188 { 0x1d, 0x0000, 0x0800 },
3189 { 0x05, 0xffff, 0x2089 },
3190 { 0x06, 0xffff, 0x5881 },
3191 { 0x04, 0xffff, 0x854a },
3192 { 0x01, 0xffff, 0x068b }
3193 };
3194 int rg_saw_cnt;
3195
3196
3197 rtl_hw_aspm_clkreq_enable(tp, false);
3198 rtl_ephy_init(tp, e_info_8168h_1);
3199
3200 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3201 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3202
3203 rtl_set_def_aspm_entry_latency(tp);
3204
3205 rtl_reset_packet_filter(tp);
3206
3207 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3208
3209 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3210
3211 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3212
3213 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3214 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3215
3216 rtl8168_config_eee_mac(tp);
3217
3218 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3219 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3220
3221 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3222
3223 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3224
3225 rtl_pcie_state_l2l3_disable(tp);
3226
3227 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3228 if (rg_saw_cnt > 0) {
3229 u16 sw_cnt_1ms_ini;
3230
3231 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3232 sw_cnt_1ms_ini &= 0x0fff;
3233 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3234 }
3235
3236 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3237 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3238 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3239 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3240
3241 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3242 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3243 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3244 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3245
3246 rtl_hw_aspm_clkreq_enable(tp, true);
3247}
3248
3249static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3250{
3251 rtl8168ep_stop_cmac(tp);
3252
3253 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3254 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3255
3256 rtl_set_def_aspm_entry_latency(tp);
3257
3258 rtl_reset_packet_filter(tp);
3259
3260 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3261
3262 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3263
3264 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3265 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3266
3267 rtl8168_config_eee_mac(tp);
3268
3269 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3270
3271 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3272
3273 rtl_pcie_state_l2l3_disable(tp);
3274}
3275
3276static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3277{
3278 static const struct ephy_info e_info_8168ep_1[] = {
3279 { 0x00, 0xffff, 0x10ab },
3280 { 0x06, 0xffff, 0xf030 },
3281 { 0x08, 0xffff, 0x2006 },
3282 { 0x0d, 0xffff, 0x1666 },
3283 { 0x0c, 0x3ff0, 0x0000 }
3284 };
3285
3286
3287 rtl_hw_aspm_clkreq_enable(tp, false);
3288 rtl_ephy_init(tp, e_info_8168ep_1);
3289
3290 rtl_hw_start_8168ep(tp);
3291
3292 rtl_hw_aspm_clkreq_enable(tp, true);
3293}
3294
3295static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3296{
3297 static const struct ephy_info e_info_8168ep_2[] = {
3298 { 0x00, 0xffff, 0x10a3 },
3299 { 0x19, 0xffff, 0xfc00 },
3300 { 0x1e, 0xffff, 0x20ea }
3301 };
3302
3303
3304 rtl_hw_aspm_clkreq_enable(tp, false);
3305 rtl_ephy_init(tp, e_info_8168ep_2);
3306
3307 rtl_hw_start_8168ep(tp);
3308
3309 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3310 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3311
3312 rtl_hw_aspm_clkreq_enable(tp, true);
3313}
3314
3315static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3316{
3317 static const struct ephy_info e_info_8168ep_3[] = {
3318 { 0x00, 0x0000, 0x0080 },
3319 { 0x0d, 0x0100, 0x0200 },
3320 { 0x19, 0x8021, 0x0000 },
3321 { 0x1e, 0x0000, 0x2000 },
3322 };
3323
3324
3325 rtl_hw_aspm_clkreq_enable(tp, false);
3326 rtl_ephy_init(tp, e_info_8168ep_3);
3327
3328 rtl_hw_start_8168ep(tp);
3329
3330 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3331 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3332
3333 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3334 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3335 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3336
3337 rtl_hw_aspm_clkreq_enable(tp, true);
3338}
3339
3340static void rtl_hw_start_8117(struct rtl8169_private *tp)
3341{
3342 static const struct ephy_info e_info_8117[] = {
3343 { 0x19, 0x0040, 0x1100 },
3344 { 0x59, 0x0040, 0x1100 },
3345 };
3346 int rg_saw_cnt;
3347
3348 rtl8168ep_stop_cmac(tp);
3349
3350
3351 rtl_hw_aspm_clkreq_enable(tp, false);
3352 rtl_ephy_init(tp, e_info_8117);
3353
3354 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3355 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3356
3357 rtl_set_def_aspm_entry_latency(tp);
3358
3359 rtl_reset_packet_filter(tp);
3360
3361 rtl_eri_set_bits(tp, 0xd4, 0x0010);
3362
3363 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3364
3365 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3366
3367 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3368 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3369
3370 rtl8168_config_eee_mac(tp);
3371
3372 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3373 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3374
3375 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3376
3377 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3378
3379 rtl_pcie_state_l2l3_disable(tp);
3380
3381 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3382 if (rg_saw_cnt > 0) {
3383 u16 sw_cnt_1ms_ini;
3384
3385 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3386 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3387 }
3388
3389 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3390 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3391 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3392 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3393
3394 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3395 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3396 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3397 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3398
3399
3400 r8169_apply_firmware(tp);
3401
3402 rtl_hw_aspm_clkreq_enable(tp, true);
3403}
3404
3405static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3406{
3407 static const struct ephy_info e_info_8102e_1[] = {
3408 { 0x01, 0, 0x6e65 },
3409 { 0x02, 0, 0x091f },
3410 { 0x03, 0, 0xc2f9 },
3411 { 0x06, 0, 0xafb5 },
3412 { 0x07, 0, 0x0e00 },
3413 { 0x19, 0, 0xec80 },
3414 { 0x01, 0, 0x2e65 },
3415 { 0x01, 0, 0x6e65 }
3416 };
3417 u8 cfg1;
3418
3419 rtl_set_def_aspm_entry_latency(tp);
3420
3421 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3422
3423 RTL_W8(tp, Config1,
3424 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3425 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3426
3427 cfg1 = RTL_R8(tp, Config1);
3428 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3429 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3430
3431 rtl_ephy_init(tp, e_info_8102e_1);
3432}
3433
3434static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3435{
3436 rtl_set_def_aspm_entry_latency(tp);
3437
3438 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3439 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3440}
3441
3442static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3443{
3444 rtl_hw_start_8102e_2(tp);
3445
3446 rtl_ephy_write(tp, 0x03, 0xc2f9);
3447}
3448
3449static void rtl_hw_start_8401(struct rtl8169_private *tp)
3450{
3451 static const struct ephy_info e_info_8401[] = {
3452 { 0x01, 0xffff, 0x6fe5 },
3453 { 0x03, 0xffff, 0x0599 },
3454 { 0x06, 0xffff, 0xaf25 },
3455 { 0x07, 0xffff, 0x8e68 },
3456 };
3457
3458 rtl_ephy_init(tp, e_info_8401);
3459 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3460}
3461
3462static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3463{
3464 static const struct ephy_info e_info_8105e_1[] = {
3465 { 0x07, 0, 0x4000 },
3466 { 0x19, 0, 0x0200 },
3467 { 0x19, 0, 0x0020 },
3468 { 0x1e, 0, 0x2000 },
3469 { 0x03, 0, 0x0001 },
3470 { 0x19, 0, 0x0100 },
3471 { 0x19, 0, 0x0004 },
3472 { 0x0a, 0, 0x0020 }
3473 };
3474
3475
3476 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3477
3478
3479 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3480
3481 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3482 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3483
3484 rtl_ephy_init(tp, e_info_8105e_1);
3485
3486 rtl_pcie_state_l2l3_disable(tp);
3487}
3488
3489static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3490{
3491 rtl_hw_start_8105e_1(tp);
3492 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3493}
3494
3495static void rtl_hw_start_8402(struct rtl8169_private *tp)
3496{
3497 static const struct ephy_info e_info_8402[] = {
3498 { 0x19, 0xffff, 0xff64 },
3499 { 0x1e, 0, 0x4000 }
3500 };
3501
3502 rtl_set_def_aspm_entry_latency(tp);
3503
3504
3505 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3506
3507 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3508
3509 rtl_ephy_init(tp, e_info_8402);
3510
3511 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3512 rtl_reset_packet_filter(tp);
3513 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3514 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3515 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3516
3517
3518 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3519
3520 rtl_pcie_state_l2l3_disable(tp);
3521}
3522
3523static void rtl_hw_start_8106(struct rtl8169_private *tp)
3524{
3525 rtl_hw_aspm_clkreq_enable(tp, false);
3526
3527
3528 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3529
3530 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3531 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3532 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3533
3534
3535 rtl_set_aspm_entry_latency(tp, 0x2f);
3536
3537 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3538
3539
3540 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3541
3542 rtl_pcie_state_l2l3_disable(tp);
3543 rtl_hw_aspm_clkreq_enable(tp, true);
3544}
3545
3546DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3547{
3548 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3549}
3550
3551static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3552{
3553 rtl_pcie_state_l2l3_disable(tp);
3554
3555 RTL_W16(tp, 0x382, 0x221b);
3556 RTL_W8(tp, 0x4500, 0);
3557 RTL_W16(tp, 0x4800, 0);
3558
3559
3560 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3561
3562 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3563
3564 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3565 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3566
3567 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3568 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3569 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3570
3571
3572 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3573
3574 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3575 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3576 else
3577 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3578
3579 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3580 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3581 else
3582 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3583
3584 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3585 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3586 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3587 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3588 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3589 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3590 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3591 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3592 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3593
3594 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3595 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3596 udelay(1);
3597 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3598 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3599
3600 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3601
3602 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3603
3604 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3605 rtl8125b_config_eee_mac(tp);
3606 else
3607 rtl8125a_config_eee_mac(tp);
3608
3609 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3610 udelay(10);
3611}
3612
3613static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3614{
3615 static const struct ephy_info e_info_8125a_1[] = {
3616 { 0x01, 0xffff, 0xa812 },
3617 { 0x09, 0xffff, 0x520c },
3618 { 0x04, 0xffff, 0xd000 },
3619 { 0x0d, 0xffff, 0xf702 },
3620 { 0x0a, 0xffff, 0x8653 },
3621 { 0x06, 0xffff, 0x001e },
3622 { 0x08, 0xffff, 0x3595 },
3623 { 0x20, 0xffff, 0x9455 },
3624 { 0x21, 0xffff, 0x99ff },
3625 { 0x02, 0xffff, 0x6046 },
3626 { 0x29, 0xffff, 0xfe00 },
3627 { 0x23, 0xffff, 0xab62 },
3628
3629 { 0x41, 0xffff, 0xa80c },
3630 { 0x49, 0xffff, 0x520c },
3631 { 0x44, 0xffff, 0xd000 },
3632 { 0x4d, 0xffff, 0xf702 },
3633 { 0x4a, 0xffff, 0x8653 },
3634 { 0x46, 0xffff, 0x001e },
3635 { 0x48, 0xffff, 0x3595 },
3636 { 0x60, 0xffff, 0x9455 },
3637 { 0x61, 0xffff, 0x99ff },
3638 { 0x42, 0xffff, 0x6046 },
3639 { 0x69, 0xffff, 0xfe00 },
3640 { 0x63, 0xffff, 0xab62 },
3641 };
3642
3643 rtl_set_def_aspm_entry_latency(tp);
3644
3645
3646 rtl_hw_aspm_clkreq_enable(tp, false);
3647 rtl_ephy_init(tp, e_info_8125a_1);
3648
3649 rtl_hw_start_8125_common(tp);
3650 rtl_hw_aspm_clkreq_enable(tp, true);
3651}
3652
3653static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3654{
3655 static const struct ephy_info e_info_8125a_2[] = {
3656 { 0x04, 0xffff, 0xd000 },
3657 { 0x0a, 0xffff, 0x8653 },
3658 { 0x23, 0xffff, 0xab66 },
3659 { 0x20, 0xffff, 0x9455 },
3660 { 0x21, 0xffff, 0x99ff },
3661 { 0x29, 0xffff, 0xfe04 },
3662
3663 { 0x44, 0xffff, 0xd000 },
3664 { 0x4a, 0xffff, 0x8653 },
3665 { 0x63, 0xffff, 0xab66 },
3666 { 0x60, 0xffff, 0x9455 },
3667 { 0x61, 0xffff, 0x99ff },
3668 { 0x69, 0xffff, 0xfe04 },
3669 };
3670
3671 rtl_set_def_aspm_entry_latency(tp);
3672
3673
3674 rtl_hw_aspm_clkreq_enable(tp, false);
3675 rtl_ephy_init(tp, e_info_8125a_2);
3676
3677 rtl_hw_start_8125_common(tp);
3678 rtl_hw_aspm_clkreq_enable(tp, true);
3679}
3680
3681static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3682{
3683 static const struct ephy_info e_info_8125b[] = {
3684 { 0x0b, 0xffff, 0xa908 },
3685 { 0x1e, 0xffff, 0x20eb },
3686 { 0x4b, 0xffff, 0xa908 },
3687 { 0x5e, 0xffff, 0x20eb },
3688 { 0x22, 0x0030, 0x0020 },
3689 { 0x62, 0x0030, 0x0020 },
3690 };
3691
3692 rtl_set_def_aspm_entry_latency(tp);
3693 rtl_hw_aspm_clkreq_enable(tp, false);
3694
3695 rtl_ephy_init(tp, e_info_8125b);
3696 rtl_hw_start_8125_common(tp);
3697
3698 rtl_hw_aspm_clkreq_enable(tp, true);
3699}
3700
3701static void rtl_hw_config(struct rtl8169_private *tp)
3702{
3703 static const rtl_generic_fct hw_configs[] = {
3704 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3705 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3706 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3707 [RTL_GIGA_MAC_VER_10] = NULL,
3708 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3709 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3710 [RTL_GIGA_MAC_VER_13] = NULL,
3711 [RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3712 [RTL_GIGA_MAC_VER_16] = NULL,
3713 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3714 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3715 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3716 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3717 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3718 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3719 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3720 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3721 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3722 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3723 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3724 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3725 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3726 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3727 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3728 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3729 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3730 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3731 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3732 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3733 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3734 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3735 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3736 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3737 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3738 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3739 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3740 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3741 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3742 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3743 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3744 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3745 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3746 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3747 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3748 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3749 [RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3750 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125a_1,
3751 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3752 [RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3753 };
3754
3755 if (hw_configs[tp->mac_version])
3756 hw_configs[tp->mac_version](tp);
3757}
3758
3759static void rtl_hw_start_8125(struct rtl8169_private *tp)
3760{
3761 int i;
3762
3763
3764 for (i = 0xa00; i < 0xb00; i += 4)
3765 RTL_W32(tp, i, 0);
3766
3767 rtl_hw_config(tp);
3768}
3769
3770static void rtl_hw_start_8168(struct rtl8169_private *tp)
3771{
3772 if (rtl_is_8168evl_up(tp))
3773 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3774 else
3775 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3776
3777 rtl_hw_config(tp);
3778
3779
3780 RTL_W16(tp, IntrMitigate, 0x0000);
3781}
3782
3783static void rtl_hw_start_8169(struct rtl8169_private *tp)
3784{
3785 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3786
3787 tp->cp_cmd |= PCIMulRW;
3788
3789 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3790 tp->mac_version == RTL_GIGA_MAC_VER_03)
3791 tp->cp_cmd |= EnAnaPLL;
3792
3793 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3794
3795 rtl8169_set_magic_reg(tp);
3796
3797
3798 RTL_W16(tp, IntrMitigate, 0x0000);
3799}
3800
3801static void rtl_hw_start(struct rtl8169_private *tp)
3802{
3803 rtl_unlock_config_regs(tp);
3804
3805 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3806
3807 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3808 rtl_hw_start_8169(tp);
3809 else if (rtl_is_8125(tp))
3810 rtl_hw_start_8125(tp);
3811 else
3812 rtl_hw_start_8168(tp);
3813
3814 rtl_enable_exit_l1(tp);
3815 rtl_set_rx_max_size(tp);
3816 rtl_set_rx_tx_desc_registers(tp);
3817 rtl_lock_config_regs(tp);
3818
3819 rtl_jumbo_config(tp);
3820
3821
3822 rtl_pci_commit(tp);
3823
3824 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3825 rtl_init_rxcfg(tp);
3826 rtl_set_tx_config_registers(tp);
3827 rtl_set_rx_config_features(tp, tp->dev->features);
3828 rtl_set_rx_mode(tp->dev);
3829 rtl_irq_enable(tp);
3830}
3831
3832static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3833{
3834 struct rtl8169_private *tp = netdev_priv(dev);
3835
3836 dev->mtu = new_mtu;
3837 netdev_update_features(dev);
3838 rtl_jumbo_config(tp);
3839
3840 switch (tp->mac_version) {
3841 case RTL_GIGA_MAC_VER_61:
3842 case RTL_GIGA_MAC_VER_63:
3843 rtl8125_set_eee_txidle_timer(tp);
3844 break;
3845 default:
3846 break;
3847 }
3848
3849 return 0;
3850}
3851
3852static void rtl8169_mark_to_asic(struct RxDesc *desc)
3853{
3854 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3855
3856 desc->opts2 = 0;
3857
3858 dma_wmb();
3859 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3860}
3861
3862static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3863 struct RxDesc *desc)
3864{
3865 struct device *d = tp_to_dev(tp);
3866 int node = dev_to_node(d);
3867 dma_addr_t mapping;
3868 struct page *data;
3869
3870 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3871 if (!data)
3872 return NULL;
3873
3874 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3875 if (unlikely(dma_mapping_error(d, mapping))) {
3876 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3877 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3878 return NULL;
3879 }
3880
3881 desc->addr = cpu_to_le64(mapping);
3882 rtl8169_mark_to_asic(desc);
3883
3884 return data;
3885}
3886
3887static void rtl8169_rx_clear(struct rtl8169_private *tp)
3888{
3889 int i;
3890
3891 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3892 dma_unmap_page(tp_to_dev(tp),
3893 le64_to_cpu(tp->RxDescArray[i].addr),
3894 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3895 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3896 tp->Rx_databuff[i] = NULL;
3897 tp->RxDescArray[i].addr = 0;
3898 tp->RxDescArray[i].opts1 = 0;
3899 }
3900}
3901
3902static int rtl8169_rx_fill(struct rtl8169_private *tp)
3903{
3904 int i;
3905
3906 for (i = 0; i < NUM_RX_DESC; i++) {
3907 struct page *data;
3908
3909 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3910 if (!data) {
3911 rtl8169_rx_clear(tp);
3912 return -ENOMEM;
3913 }
3914 tp->Rx_databuff[i] = data;
3915 }
3916
3917
3918 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3919
3920 return 0;
3921}
3922
3923static int rtl8169_init_ring(struct rtl8169_private *tp)
3924{
3925 rtl8169_init_ring_indexes(tp);
3926
3927 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3928 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3929
3930 return rtl8169_rx_fill(tp);
3931}
3932
3933static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3934{
3935 struct ring_info *tx_skb = tp->tx_skb + entry;
3936 struct TxDesc *desc = tp->TxDescArray + entry;
3937
3938 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3939 DMA_TO_DEVICE);
3940 memset(desc, 0, sizeof(*desc));
3941 memset(tx_skb, 0, sizeof(*tx_skb));
3942}
3943
3944static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3945 unsigned int n)
3946{
3947 unsigned int i;
3948
3949 for (i = 0; i < n; i++) {
3950 unsigned int entry = (start + i) % NUM_TX_DESC;
3951 struct ring_info *tx_skb = tp->tx_skb + entry;
3952 unsigned int len = tx_skb->len;
3953
3954 if (len) {
3955 struct sk_buff *skb = tx_skb->skb;
3956
3957 rtl8169_unmap_tx_skb(tp, entry);
3958 if (skb)
3959 dev_consume_skb_any(skb);
3960 }
3961 }
3962}
3963
3964static void rtl8169_tx_clear(struct rtl8169_private *tp)
3965{
3966 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3967 netdev_reset_queue(tp->dev);
3968}
3969
3970static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3971{
3972 napi_disable(&tp->napi);
3973
3974
3975 synchronize_net();
3976
3977
3978 rtl8169_irq_mask_and_ack(tp);
3979
3980 rtl_rx_close(tp);
3981
3982 if (going_down && tp->dev->wol_enabled)
3983 goto no_reset;
3984
3985 switch (tp->mac_version) {
3986 case RTL_GIGA_MAC_VER_27:
3987 case RTL_GIGA_MAC_VER_28:
3988 case RTL_GIGA_MAC_VER_31:
3989 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
3990 break;
3991 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
3992 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
3993 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
3994 break;
3995 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_63:
3996 rtl_enable_rxdvgate(tp);
3997 fsleep(2000);
3998 break;
3999 default:
4000 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4001 fsleep(100);
4002 break;
4003 }
4004
4005 rtl_hw_reset(tp);
4006no_reset:
4007 rtl8169_tx_clear(tp);
4008 rtl8169_init_ring_indexes(tp);
4009}
4010
4011static void rtl_reset_work(struct rtl8169_private *tp)
4012{
4013 int i;
4014
4015 netif_stop_queue(tp->dev);
4016
4017 rtl8169_cleanup(tp, false);
4018
4019 for (i = 0; i < NUM_RX_DESC; i++)
4020 rtl8169_mark_to_asic(tp->RxDescArray + i);
4021
4022 napi_enable(&tp->napi);
4023 rtl_hw_start(tp);
4024}
4025
4026static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4027{
4028 struct rtl8169_private *tp = netdev_priv(dev);
4029
4030 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4031}
4032
4033static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4034 void *addr, unsigned int entry, bool desc_own)
4035{
4036 struct TxDesc *txd = tp->TxDescArray + entry;
4037 struct device *d = tp_to_dev(tp);
4038 dma_addr_t mapping;
4039 u32 opts1;
4040 int ret;
4041
4042 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4043 ret = dma_mapping_error(d, mapping);
4044 if (unlikely(ret)) {
4045 if (net_ratelimit())
4046 netdev_err(tp->dev, "Failed to map TX data!\n");
4047 return ret;
4048 }
4049
4050 txd->addr = cpu_to_le64(mapping);
4051 txd->opts2 = cpu_to_le32(opts[1]);
4052
4053 opts1 = opts[0] | len;
4054 if (entry == NUM_TX_DESC - 1)
4055 opts1 |= RingEnd;
4056 if (desc_own)
4057 opts1 |= DescOwn;
4058 txd->opts1 = cpu_to_le32(opts1);
4059
4060 tp->tx_skb[entry].len = len;
4061
4062 return 0;
4063}
4064
4065static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4066 const u32 *opts, unsigned int entry)
4067{
4068 struct skb_shared_info *info = skb_shinfo(skb);
4069 unsigned int cur_frag;
4070
4071 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4072 const skb_frag_t *frag = info->frags + cur_frag;
4073 void *addr = skb_frag_address(frag);
4074 u32 len = skb_frag_size(frag);
4075
4076 entry = (entry + 1) % NUM_TX_DESC;
4077
4078 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4079 goto err_out;
4080 }
4081
4082 return 0;
4083
4084err_out:
4085 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4086 return -EIO;
4087}
4088
4089static bool rtl_skb_is_udp(struct sk_buff *skb)
4090{
4091 int no = skb_network_offset(skb);
4092 struct ipv6hdr *i6h, _i6h;
4093 struct iphdr *ih, _ih;
4094
4095 switch (vlan_get_protocol(skb)) {
4096 case htons(ETH_P_IP):
4097 ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4098 return ih && ih->protocol == IPPROTO_UDP;
4099 case htons(ETH_P_IPV6):
4100 i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4101 return i6h && i6h->nexthdr == IPPROTO_UDP;
4102 default:
4103 return false;
4104 }
4105}
4106
4107#define RTL_MIN_PATCH_LEN 47
4108
4109
4110static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4111 struct sk_buff *skb)
4112{
4113 unsigned int padto = 0, len = skb->len;
4114
4115 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4116 rtl_skb_is_udp(skb) && skb_transport_header_was_set(skb)) {
4117 unsigned int trans_data_len = skb_tail_pointer(skb) -
4118 skb_transport_header(skb);
4119
4120 if (trans_data_len >= offsetof(struct udphdr, len) &&
4121 trans_data_len < RTL_MIN_PATCH_LEN) {
4122 u16 dest = ntohs(udp_hdr(skb)->dest);
4123
4124
4125 if (dest == 319 || dest == 320)
4126 padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4127 }
4128
4129 if (trans_data_len < sizeof(struct udphdr))
4130 padto = max_t(unsigned int, padto,
4131 len + sizeof(struct udphdr) - trans_data_len);
4132 }
4133
4134 return padto;
4135}
4136
4137static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4138 struct sk_buff *skb)
4139{
4140 unsigned int padto;
4141
4142 padto = rtl8125_quirk_udp_padto(tp, skb);
4143
4144 switch (tp->mac_version) {
4145 case RTL_GIGA_MAC_VER_34:
4146 case RTL_GIGA_MAC_VER_60:
4147 case RTL_GIGA_MAC_VER_61:
4148 case RTL_GIGA_MAC_VER_63:
4149 padto = max_t(unsigned int, padto, ETH_ZLEN);
4150 break;
4151 default:
4152 break;
4153 }
4154
4155 return padto;
4156}
4157
4158static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4159{
4160 u32 mss = skb_shinfo(skb)->gso_size;
4161
4162 if (mss) {
4163 opts[0] |= TD_LSO;
4164 opts[0] |= mss << TD0_MSS_SHIFT;
4165 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4166 const struct iphdr *ip = ip_hdr(skb);
4167
4168 if (ip->protocol == IPPROTO_TCP)
4169 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4170 else if (ip->protocol == IPPROTO_UDP)
4171 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4172 else
4173 WARN_ON_ONCE(1);
4174 }
4175}
4176
4177static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4178 struct sk_buff *skb, u32 *opts)
4179{
4180 u32 transport_offset = (u32)skb_transport_offset(skb);
4181 struct skb_shared_info *shinfo = skb_shinfo(skb);
4182 u32 mss = shinfo->gso_size;
4183
4184 if (mss) {
4185 if (shinfo->gso_type & SKB_GSO_TCPV4) {
4186 opts[0] |= TD1_GTSENV4;
4187 } else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4188 if (skb_cow_head(skb, 0))
4189 return false;
4190
4191 tcp_v6_gso_csum_prep(skb);
4192 opts[0] |= TD1_GTSENV6;
4193 } else {
4194 WARN_ON_ONCE(1);
4195 }
4196
4197 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4198 opts[1] |= mss << TD1_MSS_SHIFT;
4199 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4200 u8 ip_protocol;
4201
4202 switch (vlan_get_protocol(skb)) {
4203 case htons(ETH_P_IP):
4204 opts[1] |= TD1_IPv4_CS;
4205 ip_protocol = ip_hdr(skb)->protocol;
4206 break;
4207
4208 case htons(ETH_P_IPV6):
4209 opts[1] |= TD1_IPv6_CS;
4210 ip_protocol = ipv6_hdr(skb)->nexthdr;
4211 break;
4212
4213 default:
4214 ip_protocol = IPPROTO_RAW;
4215 break;
4216 }
4217
4218 if (ip_protocol == IPPROTO_TCP)
4219 opts[1] |= TD1_TCP_CS;
4220 else if (ip_protocol == IPPROTO_UDP)
4221 opts[1] |= TD1_UDP_CS;
4222 else
4223 WARN_ON_ONCE(1);
4224
4225 opts[1] |= transport_offset << TCPHO_SHIFT;
4226 } else {
4227 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4228
4229
4230 return !__skb_put_padto(skb, padto, false);
4231 }
4232
4233 return true;
4234}
4235
4236static bool rtl_tx_slots_avail(struct rtl8169_private *tp)
4237{
4238 unsigned int slots_avail = READ_ONCE(tp->dirty_tx) + NUM_TX_DESC
4239 - READ_ONCE(tp->cur_tx);
4240
4241
4242 return slots_avail > MAX_SKB_FRAGS;
4243}
4244
4245
4246static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4247{
4248 switch (tp->mac_version) {
4249 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4250 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4251 return false;
4252 default:
4253 return true;
4254 }
4255}
4256
4257static void rtl8169_doorbell(struct rtl8169_private *tp)
4258{
4259 if (rtl_is_8125(tp))
4260 RTL_W16(tp, TxPoll_8125, BIT(0));
4261 else
4262 RTL_W8(tp, TxPoll, NPQ);
4263}
4264
4265static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4266 struct net_device *dev)
4267{
4268 unsigned int frags = skb_shinfo(skb)->nr_frags;
4269 struct rtl8169_private *tp = netdev_priv(dev);
4270 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4271 struct TxDesc *txd_first, *txd_last;
4272 bool stop_queue, door_bell;
4273 u32 opts[2];
4274
4275 if (unlikely(!rtl_tx_slots_avail(tp))) {
4276 if (net_ratelimit())
4277 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4278 goto err_stop_0;
4279 }
4280
4281 opts[1] = rtl8169_tx_vlan_tag(skb);
4282 opts[0] = 0;
4283
4284 if (!rtl_chip_supports_csum_v2(tp))
4285 rtl8169_tso_csum_v1(skb, opts);
4286 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4287 goto err_dma_0;
4288
4289 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4290 entry, false)))
4291 goto err_dma_0;
4292
4293 txd_first = tp->TxDescArray + entry;
4294
4295 if (frags) {
4296 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4297 goto err_dma_1;
4298 entry = (entry + frags) % NUM_TX_DESC;
4299 }
4300
4301 txd_last = tp->TxDescArray + entry;
4302 txd_last->opts1 |= cpu_to_le32(LastFrag);
4303 tp->tx_skb[entry].skb = skb;
4304
4305 skb_tx_timestamp(skb);
4306
4307
4308 dma_wmb();
4309
4310 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4311
4312 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4313
4314
4315 smp_wmb();
4316
4317 WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4318
4319 stop_queue = !rtl_tx_slots_avail(tp);
4320 if (unlikely(stop_queue)) {
4321
4322
4323
4324 smp_wmb();
4325 netif_stop_queue(dev);
4326
4327
4328
4329
4330
4331
4332
4333 smp_mb__after_atomic();
4334 if (rtl_tx_slots_avail(tp))
4335 netif_start_queue(dev);
4336 door_bell = true;
4337 }
4338
4339 if (door_bell)
4340 rtl8169_doorbell(tp);
4341
4342 return NETDEV_TX_OK;
4343
4344err_dma_1:
4345 rtl8169_unmap_tx_skb(tp, entry);
4346err_dma_0:
4347 dev_kfree_skb_any(skb);
4348 dev->stats.tx_dropped++;
4349 return NETDEV_TX_OK;
4350
4351err_stop_0:
4352 netif_stop_queue(dev);
4353 dev->stats.tx_dropped++;
4354 return NETDEV_TX_BUSY;
4355}
4356
4357static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4358{
4359 struct skb_shared_info *info = skb_shinfo(skb);
4360 unsigned int nr_frags = info->nr_frags;
4361
4362 if (!nr_frags)
4363 return UINT_MAX;
4364
4365 return skb_frag_size(info->frags + nr_frags - 1);
4366}
4367
4368
4369static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4370 netdev_features_t features)
4371{
4372
4373 if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4374 ip_hdrlen(skb) > sizeof(struct iphdr))
4375 features &= ~NETIF_F_ALL_TSO;
4376
4377
4378 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4379 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4380 features &= ~NETIF_F_ALL_TSO;
4381
4382 else if (rtl_last_frag_len(skb) <= 6)
4383 features &= ~NETIF_F_ALL_TSO;
4384
4385 return features;
4386}
4387
4388static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4389 struct net_device *dev,
4390 netdev_features_t features)
4391{
4392 int transport_offset = skb_transport_offset(skb);
4393 struct rtl8169_private *tp = netdev_priv(dev);
4394
4395 if (skb_is_gso(skb)) {
4396 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4397 features = rtl8168evl_fix_tso(skb, features);
4398
4399 if (transport_offset > GTTCPHO_MAX &&
4400 rtl_chip_supports_csum_v2(tp))
4401 features &= ~NETIF_F_ALL_TSO;
4402 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4403
4404 if (skb->len < ETH_ZLEN)
4405 features &= ~NETIF_F_CSUM_MASK;
4406
4407 if (rtl_quirk_packet_padto(tp, skb))
4408 features &= ~NETIF_F_CSUM_MASK;
4409
4410 if (transport_offset > TCPHO_MAX &&
4411 rtl_chip_supports_csum_v2(tp))
4412 features &= ~NETIF_F_CSUM_MASK;
4413 }
4414
4415 return vlan_features_check(skb, features);
4416}
4417
4418static void rtl8169_pcierr_interrupt(struct net_device *dev)
4419{
4420 struct rtl8169_private *tp = netdev_priv(dev);
4421 struct pci_dev *pdev = tp->pci_dev;
4422 int pci_status_errs;
4423 u16 pci_cmd;
4424
4425 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4426
4427 pci_status_errs = pci_status_get_and_clear_errors(pdev);
4428
4429 if (net_ratelimit())
4430 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4431 pci_cmd, pci_status_errs);
4432
4433 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4434}
4435
4436static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4437 int budget)
4438{
4439 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4440 struct sk_buff *skb;
4441
4442 dirty_tx = tp->dirty_tx;
4443
4444 while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4445 unsigned int entry = dirty_tx % NUM_TX_DESC;
4446 u32 status;
4447
4448 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4449 if (status & DescOwn)
4450 break;
4451
4452 skb = tp->tx_skb[entry].skb;
4453 rtl8169_unmap_tx_skb(tp, entry);
4454
4455 if (skb) {
4456 pkts_compl++;
4457 bytes_compl += skb->len;
4458 napi_consume_skb(skb, budget);
4459 }
4460 dirty_tx++;
4461 }
4462
4463 if (tp->dirty_tx != dirty_tx) {
4464 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4465 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4466
4467
4468
4469
4470
4471
4472
4473
4474 smp_store_mb(tp->dirty_tx, dirty_tx);
4475 if (netif_queue_stopped(dev) && rtl_tx_slots_avail(tp))
4476 netif_wake_queue(dev);
4477
4478
4479
4480
4481
4482
4483
4484
4485 if (tp->cur_tx != dirty_tx && skb)
4486 rtl8169_doorbell(tp);
4487 }
4488}
4489
4490static inline int rtl8169_fragmented_frame(u32 status)
4491{
4492 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4493}
4494
4495static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4496{
4497 u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4498
4499 if (status == RxProtoTCP || status == RxProtoUDP)
4500 skb->ip_summed = CHECKSUM_UNNECESSARY;
4501 else
4502 skb_checksum_none_assert(skb);
4503}
4504
4505static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4506{
4507 struct device *d = tp_to_dev(tp);
4508 int count;
4509
4510 for (count = 0; count < budget; count++, tp->cur_rx++) {
4511 unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4512 struct RxDesc *desc = tp->RxDescArray + entry;
4513 struct sk_buff *skb;
4514 const void *rx_buf;
4515 dma_addr_t addr;
4516 u32 status;
4517
4518 status = le32_to_cpu(desc->opts1);
4519 if (status & DescOwn)
4520 break;
4521
4522
4523
4524
4525
4526 dma_rmb();
4527
4528 if (unlikely(status & RxRES)) {
4529 if (net_ratelimit())
4530 netdev_warn(dev, "Rx ERROR. status = %08x\n",
4531 status);
4532 dev->stats.rx_errors++;
4533 if (status & (RxRWT | RxRUNT))
4534 dev->stats.rx_length_errors++;
4535 if (status & RxCRC)
4536 dev->stats.rx_crc_errors++;
4537
4538 if (!(dev->features & NETIF_F_RXALL))
4539 goto release_descriptor;
4540 else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4541 goto release_descriptor;
4542 }
4543
4544 pkt_size = status & GENMASK(13, 0);
4545 if (likely(!(dev->features & NETIF_F_RXFCS)))
4546 pkt_size -= ETH_FCS_LEN;
4547
4548
4549
4550
4551 if (unlikely(rtl8169_fragmented_frame(status))) {
4552 dev->stats.rx_dropped++;
4553 dev->stats.rx_length_errors++;
4554 goto release_descriptor;
4555 }
4556
4557 skb = napi_alloc_skb(&tp->napi, pkt_size);
4558 if (unlikely(!skb)) {
4559 dev->stats.rx_dropped++;
4560 goto release_descriptor;
4561 }
4562
4563 addr = le64_to_cpu(desc->addr);
4564 rx_buf = page_address(tp->Rx_databuff[entry]);
4565
4566 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4567 prefetch(rx_buf);
4568 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4569 skb->tail += pkt_size;
4570 skb->len = pkt_size;
4571 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4572
4573 rtl8169_rx_csum(skb, status);
4574 skb->protocol = eth_type_trans(skb, dev);
4575
4576 rtl8169_rx_vlan_tag(desc, skb);
4577
4578 if (skb->pkt_type == PACKET_MULTICAST)
4579 dev->stats.multicast++;
4580
4581 napi_gro_receive(&tp->napi, skb);
4582
4583 dev_sw_netstats_rx_add(dev, pkt_size);
4584release_descriptor:
4585 rtl8169_mark_to_asic(desc);
4586 }
4587
4588 return count;
4589}
4590
4591static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4592{
4593 struct rtl8169_private *tp = dev_instance;
4594 u32 status = rtl_get_events(tp);
4595
4596 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4597 return IRQ_NONE;
4598
4599 if (unlikely(status & SYSErr)) {
4600 rtl8169_pcierr_interrupt(tp->dev);
4601 goto out;
4602 }
4603
4604 if (status & LinkChg)
4605 phy_mac_interrupt(tp->phydev);
4606
4607 if (unlikely(status & RxFIFOOver &&
4608 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4609 netif_stop_queue(tp->dev);
4610 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4611 }
4612
4613 if (napi_schedule_prep(&tp->napi)) {
4614 rtl_irq_disable(tp);
4615 __napi_schedule(&tp->napi);
4616 }
4617out:
4618 rtl_ack_events(tp, status);
4619
4620 return IRQ_HANDLED;
4621}
4622
4623static void rtl_task(struct work_struct *work)
4624{
4625 struct rtl8169_private *tp =
4626 container_of(work, struct rtl8169_private, wk.work);
4627
4628 rtnl_lock();
4629
4630 if (!netif_running(tp->dev) ||
4631 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4632 goto out_unlock;
4633
4634 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4635 rtl_reset_work(tp);
4636 netif_wake_queue(tp->dev);
4637 }
4638out_unlock:
4639 rtnl_unlock();
4640}
4641
4642static int rtl8169_poll(struct napi_struct *napi, int budget)
4643{
4644 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4645 struct net_device *dev = tp->dev;
4646 int work_done;
4647
4648 rtl_tx(dev, tp, budget);
4649
4650 work_done = rtl_rx(dev, tp, budget);
4651
4652 if (work_done < budget && napi_complete_done(napi, work_done))
4653 rtl_irq_enable(tp);
4654
4655 return work_done;
4656}
4657
4658static void r8169_phylink_handler(struct net_device *ndev)
4659{
4660 struct rtl8169_private *tp = netdev_priv(ndev);
4661
4662 if (netif_carrier_ok(ndev)) {
4663 rtl_link_chg_patch(tp);
4664 pm_request_resume(&tp->pci_dev->dev);
4665 } else {
4666 pm_runtime_idle(&tp->pci_dev->dev);
4667 }
4668
4669 if (net_ratelimit())
4670 phy_print_status(tp->phydev);
4671}
4672
4673static int r8169_phy_connect(struct rtl8169_private *tp)
4674{
4675 struct phy_device *phydev = tp->phydev;
4676 phy_interface_t phy_mode;
4677 int ret;
4678
4679 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4680 PHY_INTERFACE_MODE_MII;
4681
4682 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4683 phy_mode);
4684 if (ret)
4685 return ret;
4686
4687 if (!tp->supports_gmii)
4688 phy_set_max_speed(phydev, SPEED_100);
4689
4690 phy_attached_info(phydev);
4691
4692 return 0;
4693}
4694
4695static void rtl8169_down(struct rtl8169_private *tp)
4696{
4697
4698 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4699
4700 phy_stop(tp->phydev);
4701
4702 rtl8169_update_counters(tp);
4703
4704 pci_clear_master(tp->pci_dev);
4705 rtl_pci_commit(tp);
4706
4707 rtl8169_cleanup(tp, true);
4708
4709 rtl_prepare_power_down(tp);
4710}
4711
4712static void rtl8169_up(struct rtl8169_private *tp)
4713{
4714 pci_set_master(tp->pci_dev);
4715 phy_init_hw(tp->phydev);
4716 phy_resume(tp->phydev);
4717 rtl8169_init_phy(tp);
4718 napi_enable(&tp->napi);
4719 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4720 rtl_reset_work(tp);
4721
4722 phy_start(tp->phydev);
4723}
4724
4725static int rtl8169_close(struct net_device *dev)
4726{
4727 struct rtl8169_private *tp = netdev_priv(dev);
4728 struct pci_dev *pdev = tp->pci_dev;
4729
4730 pm_runtime_get_sync(&pdev->dev);
4731
4732 netif_stop_queue(dev);
4733 rtl8169_down(tp);
4734 rtl8169_rx_clear(tp);
4735
4736 cancel_work_sync(&tp->wk.work);
4737
4738 free_irq(pci_irq_vector(pdev, 0), tp);
4739
4740 phy_disconnect(tp->phydev);
4741
4742 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4743 tp->RxPhyAddr);
4744 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4745 tp->TxPhyAddr);
4746 tp->TxDescArray = NULL;
4747 tp->RxDescArray = NULL;
4748
4749 pm_runtime_put_sync(&pdev->dev);
4750
4751 return 0;
4752}
4753
4754#ifdef CONFIG_NET_POLL_CONTROLLER
4755static void rtl8169_netpoll(struct net_device *dev)
4756{
4757 struct rtl8169_private *tp = netdev_priv(dev);
4758
4759 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4760}
4761#endif
4762
4763static int rtl_open(struct net_device *dev)
4764{
4765 struct rtl8169_private *tp = netdev_priv(dev);
4766 struct pci_dev *pdev = tp->pci_dev;
4767 unsigned long irqflags;
4768 int retval = -ENOMEM;
4769
4770 pm_runtime_get_sync(&pdev->dev);
4771
4772
4773
4774
4775
4776 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4777 &tp->TxPhyAddr, GFP_KERNEL);
4778 if (!tp->TxDescArray)
4779 goto out;
4780
4781 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4782 &tp->RxPhyAddr, GFP_KERNEL);
4783 if (!tp->RxDescArray)
4784 goto err_free_tx_0;
4785
4786 retval = rtl8169_init_ring(tp);
4787 if (retval < 0)
4788 goto err_free_rx_1;
4789
4790 rtl_request_firmware(tp);
4791
4792 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4793 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
4794 irqflags, dev->name, tp);
4795 if (retval < 0)
4796 goto err_release_fw_2;
4797
4798 retval = r8169_phy_connect(tp);
4799 if (retval)
4800 goto err_free_irq;
4801
4802 rtl8169_up(tp);
4803 rtl8169_init_counter_offsets(tp);
4804 netif_start_queue(dev);
4805out:
4806 pm_runtime_put_sync(&pdev->dev);
4807
4808 return retval;
4809
4810err_free_irq:
4811 free_irq(pci_irq_vector(pdev, 0), tp);
4812err_release_fw_2:
4813 rtl_release_firmware(tp);
4814 rtl8169_rx_clear(tp);
4815err_free_rx_1:
4816 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4817 tp->RxPhyAddr);
4818 tp->RxDescArray = NULL;
4819err_free_tx_0:
4820 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4821 tp->TxPhyAddr);
4822 tp->TxDescArray = NULL;
4823 goto out;
4824}
4825
4826static void
4827rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4828{
4829 struct rtl8169_private *tp = netdev_priv(dev);
4830 struct pci_dev *pdev = tp->pci_dev;
4831 struct rtl8169_counters *counters = tp->counters;
4832
4833 pm_runtime_get_noresume(&pdev->dev);
4834
4835 netdev_stats_to_stats64(stats, &dev->stats);
4836 dev_fetch_sw_netstats(stats, dev->tstats);
4837
4838
4839
4840
4841
4842 if (pm_runtime_active(&pdev->dev))
4843 rtl8169_update_counters(tp);
4844
4845
4846
4847
4848
4849 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4850 le64_to_cpu(tp->tc_offset.tx_errors);
4851 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4852 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4853 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4854 le16_to_cpu(tp->tc_offset.tx_aborted);
4855 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4856 le16_to_cpu(tp->tc_offset.rx_missed);
4857
4858 pm_runtime_put_noidle(&pdev->dev);
4859}
4860
4861static void rtl8169_net_suspend(struct rtl8169_private *tp)
4862{
4863 netif_device_detach(tp->dev);
4864
4865 if (netif_running(tp->dev))
4866 rtl8169_down(tp);
4867}
4868
4869#ifdef CONFIG_PM
4870
4871static int rtl8169_runtime_resume(struct device *dev)
4872{
4873 struct rtl8169_private *tp = dev_get_drvdata(dev);
4874
4875 rtl_rar_set(tp, tp->dev->dev_addr);
4876 __rtl8169_set_wol(tp, tp->saved_wolopts);
4877
4878 if (tp->TxDescArray)
4879 rtl8169_up(tp);
4880
4881 netif_device_attach(tp->dev);
4882
4883 return 0;
4884}
4885
4886static int __maybe_unused rtl8169_suspend(struct device *device)
4887{
4888 struct rtl8169_private *tp = dev_get_drvdata(device);
4889
4890 rtnl_lock();
4891 rtl8169_net_suspend(tp);
4892 if (!device_may_wakeup(tp_to_dev(tp)))
4893 clk_disable_unprepare(tp->clk);
4894 rtnl_unlock();
4895
4896 return 0;
4897}
4898
4899static int __maybe_unused rtl8169_resume(struct device *device)
4900{
4901 struct rtl8169_private *tp = dev_get_drvdata(device);
4902
4903 if (!device_may_wakeup(tp_to_dev(tp)))
4904 clk_prepare_enable(tp->clk);
4905
4906
4907 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4908 rtl_init_rxcfg(tp);
4909
4910 return rtl8169_runtime_resume(device);
4911}
4912
4913static int rtl8169_runtime_suspend(struct device *device)
4914{
4915 struct rtl8169_private *tp = dev_get_drvdata(device);
4916
4917 if (!tp->TxDescArray) {
4918 netif_device_detach(tp->dev);
4919 return 0;
4920 }
4921
4922 rtnl_lock();
4923 __rtl8169_set_wol(tp, WAKE_PHY);
4924 rtl8169_net_suspend(tp);
4925 rtnl_unlock();
4926
4927 return 0;
4928}
4929
4930static int rtl8169_runtime_idle(struct device *device)
4931{
4932 struct rtl8169_private *tp = dev_get_drvdata(device);
4933
4934 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
4935 pm_schedule_suspend(device, 10000);
4936
4937 return -EBUSY;
4938}
4939
4940static const struct dev_pm_ops rtl8169_pm_ops = {
4941 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
4942 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
4943 rtl8169_runtime_idle)
4944};
4945
4946#endif
4947
4948static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
4949{
4950
4951 switch (tp->mac_version) {
4952 case RTL_GIGA_MAC_VER_11:
4953 case RTL_GIGA_MAC_VER_12:
4954 case RTL_GIGA_MAC_VER_17:
4955 pci_clear_master(tp->pci_dev);
4956
4957 RTL_W8(tp, ChipCmd, CmdRxEnb);
4958 rtl_pci_commit(tp);
4959 break;
4960 default:
4961 break;
4962 }
4963}
4964
4965static void rtl_shutdown(struct pci_dev *pdev)
4966{
4967 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4968
4969 rtnl_lock();
4970 rtl8169_net_suspend(tp);
4971 rtnl_unlock();
4972
4973
4974 rtl_rar_set(tp, tp->dev->perm_addr);
4975
4976 if (system_state == SYSTEM_POWER_OFF) {
4977 if (tp->saved_wolopts)
4978 rtl_wol_shutdown_quirk(tp);
4979
4980 pci_wake_from_d3(pdev, tp->saved_wolopts);
4981 pci_set_power_state(pdev, PCI_D3hot);
4982 }
4983}
4984
4985static void rtl_remove_one(struct pci_dev *pdev)
4986{
4987 struct rtl8169_private *tp = pci_get_drvdata(pdev);
4988
4989 if (pci_dev_run_wake(pdev))
4990 pm_runtime_get_noresume(&pdev->dev);
4991
4992 unregister_netdev(tp->dev);
4993
4994 if (tp->dash_type != RTL_DASH_NONE)
4995 rtl8168_driver_stop(tp);
4996
4997 rtl_release_firmware(tp);
4998
4999
5000 rtl_rar_set(tp, tp->dev->perm_addr);
5001}
5002
5003static const struct net_device_ops rtl_netdev_ops = {
5004 .ndo_open = rtl_open,
5005 .ndo_stop = rtl8169_close,
5006 .ndo_get_stats64 = rtl8169_get_stats64,
5007 .ndo_start_xmit = rtl8169_start_xmit,
5008 .ndo_features_check = rtl8169_features_check,
5009 .ndo_tx_timeout = rtl8169_tx_timeout,
5010 .ndo_validate_addr = eth_validate_addr,
5011 .ndo_change_mtu = rtl8169_change_mtu,
5012 .ndo_fix_features = rtl8169_fix_features,
5013 .ndo_set_features = rtl8169_set_features,
5014 .ndo_set_mac_address = rtl_set_mac_address,
5015 .ndo_eth_ioctl = phy_do_ioctl_running,
5016 .ndo_set_rx_mode = rtl_set_rx_mode,
5017#ifdef CONFIG_NET_POLL_CONTROLLER
5018 .ndo_poll_controller = rtl8169_netpoll,
5019#endif
5020
5021};
5022
5023static void rtl_set_irq_mask(struct rtl8169_private *tp)
5024{
5025 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5026
5027 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5028 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5029 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5030
5031 tp->irq_mask |= RxFIFOOver;
5032 else
5033 tp->irq_mask |= RxOverflow;
5034}
5035
5036static int rtl_alloc_irq(struct rtl8169_private *tp)
5037{
5038 unsigned int flags;
5039
5040 switch (tp->mac_version) {
5041 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5042 rtl_unlock_config_regs(tp);
5043 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5044 rtl_lock_config_regs(tp);
5045 fallthrough;
5046 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5047 flags = PCI_IRQ_LEGACY;
5048 break;
5049 default:
5050 flags = PCI_IRQ_ALL_TYPES;
5051 break;
5052 }
5053
5054 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5055}
5056
5057static void rtl_read_mac_address(struct rtl8169_private *tp,
5058 u8 mac_addr[ETH_ALEN])
5059{
5060
5061 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5062 u32 value;
5063
5064 value = rtl_eri_read(tp, 0xe0);
5065 put_unaligned_le32(value, mac_addr);
5066 value = rtl_eri_read(tp, 0xe4);
5067 put_unaligned_le16(value, mac_addr + 4);
5068 } else if (rtl_is_8125(tp)) {
5069 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5070 }
5071}
5072
5073DECLARE_RTL_COND(rtl_link_list_ready_cond)
5074{
5075 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5076}
5077
5078static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5079{
5080 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5081}
5082
5083static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5084{
5085 struct rtl8169_private *tp = mii_bus->priv;
5086
5087 if (phyaddr > 0)
5088 return -ENODEV;
5089
5090 return rtl_readphy(tp, phyreg);
5091}
5092
5093static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5094 int phyreg, u16 val)
5095{
5096 struct rtl8169_private *tp = mii_bus->priv;
5097
5098 if (phyaddr > 0)
5099 return -ENODEV;
5100
5101 rtl_writephy(tp, phyreg, val);
5102
5103 return 0;
5104}
5105
5106static int r8169_mdio_register(struct rtl8169_private *tp)
5107{
5108 struct pci_dev *pdev = tp->pci_dev;
5109 struct mii_bus *new_bus;
5110 int ret;
5111
5112 new_bus = devm_mdiobus_alloc(&pdev->dev);
5113 if (!new_bus)
5114 return -ENOMEM;
5115
5116 new_bus->name = "r8169";
5117 new_bus->priv = tp;
5118 new_bus->parent = &pdev->dev;
5119 new_bus->irq[0] = PHY_MAC_INTERRUPT;
5120 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5121 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5122
5123 new_bus->read = r8169_mdio_read_reg;
5124 new_bus->write = r8169_mdio_write_reg;
5125
5126 ret = devm_mdiobus_register(&pdev->dev, new_bus);
5127 if (ret)
5128 return ret;
5129
5130 tp->phydev = mdiobus_get_phy(new_bus, 0);
5131 if (!tp->phydev) {
5132 return -ENODEV;
5133 } else if (!tp->phydev->drv) {
5134
5135
5136
5137 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5138 tp->phydev->phy_id);
5139 return -EUNATCH;
5140 }
5141
5142 tp->phydev->mac_managed_pm = 1;
5143
5144 phy_support_asym_pause(tp->phydev);
5145
5146
5147 phy_suspend(tp->phydev);
5148
5149 return 0;
5150}
5151
5152static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5153{
5154 rtl_enable_rxdvgate(tp);
5155
5156 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5157 msleep(1);
5158 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5159
5160 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5161 r8168g_wait_ll_share_fifo_ready(tp);
5162
5163 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5164 r8168g_wait_ll_share_fifo_ready(tp);
5165}
5166
5167static void rtl_hw_init_8125(struct rtl8169_private *tp)
5168{
5169 rtl_enable_rxdvgate(tp);
5170
5171 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5172 msleep(1);
5173 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5174
5175 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5176 r8168g_wait_ll_share_fifo_ready(tp);
5177
5178 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5179 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5180 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5181 r8168g_wait_ll_share_fifo_ready(tp);
5182}
5183
5184static void rtl_hw_initialize(struct rtl8169_private *tp)
5185{
5186 switch (tp->mac_version) {
5187 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_53:
5188 rtl8168ep_stop_cmac(tp);
5189 fallthrough;
5190 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5191 rtl_hw_init_8168g(tp);
5192 break;
5193 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
5194 rtl_hw_init_8125(tp);
5195 break;
5196 default:
5197 break;
5198 }
5199}
5200
5201static int rtl_jumbo_max(struct rtl8169_private *tp)
5202{
5203
5204 if (!tp->supports_gmii)
5205 return 0;
5206
5207 switch (tp->mac_version) {
5208
5209 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5210 return JUMBO_7K;
5211
5212 case RTL_GIGA_MAC_VER_11:
5213 case RTL_GIGA_MAC_VER_12:
5214 case RTL_GIGA_MAC_VER_17:
5215 return JUMBO_4K;
5216
5217 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5218 return JUMBO_6K;
5219 default:
5220 return JUMBO_9K;
5221 }
5222}
5223
5224static void rtl_disable_clk(void *data)
5225{
5226 clk_disable_unprepare(data);
5227}
5228
5229static int rtl_get_ether_clk(struct rtl8169_private *tp)
5230{
5231 struct device *d = tp_to_dev(tp);
5232 struct clk *clk;
5233 int rc;
5234
5235 clk = devm_clk_get(d, "ether_clk");
5236 if (IS_ERR(clk)) {
5237 rc = PTR_ERR(clk);
5238 if (rc == -ENOENT)
5239
5240 rc = 0;
5241 else
5242 dev_err_probe(d, rc, "failed to get clk\n");
5243 } else {
5244 tp->clk = clk;
5245 rc = clk_prepare_enable(clk);
5246 if (rc)
5247 dev_err(d, "failed to enable clk: %d\n", rc);
5248 else
5249 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5250 }
5251
5252 return rc;
5253}
5254
5255static void rtl_init_mac_address(struct rtl8169_private *tp)
5256{
5257 struct net_device *dev = tp->dev;
5258 u8 *mac_addr = dev->dev_addr;
5259 int rc;
5260
5261 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5262 if (!rc)
5263 goto done;
5264
5265 rtl_read_mac_address(tp, mac_addr);
5266 if (is_valid_ether_addr(mac_addr))
5267 goto done;
5268
5269 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5270 if (is_valid_ether_addr(mac_addr))
5271 goto done;
5272
5273 eth_hw_addr_random(dev);
5274 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5275done:
5276 rtl_rar_set(tp, mac_addr);
5277}
5278
5279static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5280{
5281 struct rtl8169_private *tp;
5282 int jumbo_max, region, rc;
5283 enum mac_version chipset;
5284 struct net_device *dev;
5285 u16 xid;
5286
5287 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5288 if (!dev)
5289 return -ENOMEM;
5290
5291 SET_NETDEV_DEV(dev, &pdev->dev);
5292 dev->netdev_ops = &rtl_netdev_ops;
5293 tp = netdev_priv(dev);
5294 tp->dev = dev;
5295 tp->pci_dev = pdev;
5296 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5297 tp->eee_adv = -1;
5298 tp->ocp_base = OCP_STD_PHY_BASE;
5299
5300 dev->tstats = devm_netdev_alloc_pcpu_stats(&pdev->dev,
5301 struct pcpu_sw_netstats);
5302 if (!dev->tstats)
5303 return -ENOMEM;
5304
5305
5306 rc = rtl_get_ether_clk(tp);
5307 if (rc)
5308 return rc;
5309
5310
5311
5312
5313 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5314 tp->aspm_manageable = !rc;
5315
5316
5317 rc = pcim_enable_device(pdev);
5318 if (rc < 0) {
5319 dev_err(&pdev->dev, "enable failure\n");
5320 return rc;
5321 }
5322
5323 if (pcim_set_mwi(pdev) < 0)
5324 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5325
5326
5327 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5328 if (region < 0) {
5329 dev_err(&pdev->dev, "no MMIO resource found\n");
5330 return -ENODEV;
5331 }
5332
5333
5334 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5335 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5336 return -ENODEV;
5337 }
5338
5339 rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5340 if (rc < 0) {
5341 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5342 return rc;
5343 }
5344
5345 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5346
5347 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5348
5349
5350 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5351 if (chipset == RTL_GIGA_MAC_NONE) {
5352 dev_err(&pdev->dev, "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n", xid);
5353 return -ENODEV;
5354 }
5355
5356 tp->mac_version = chipset;
5357
5358 tp->dash_type = rtl_check_dash(tp);
5359
5360 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5361
5362 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5363 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5364 dev->features |= NETIF_F_HIGHDMA;
5365
5366 rtl_init_rxcfg(tp);
5367
5368 rtl8169_irq_mask_and_ack(tp);
5369
5370 rtl_hw_initialize(tp);
5371
5372 rtl_hw_reset(tp);
5373
5374 rc = rtl_alloc_irq(tp);
5375 if (rc < 0) {
5376 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5377 return rc;
5378 }
5379
5380 INIT_WORK(&tp->wk.work, rtl_task);
5381
5382 rtl_init_mac_address(tp);
5383
5384 dev->ethtool_ops = &rtl8169_ethtool_ops;
5385
5386 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5387
5388 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5389 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5390 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5391 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5392
5393
5394
5395
5396
5397 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5398
5399 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5400
5401 if (rtl_chip_supports_csum_v2(tp))
5402 dev->hw_features |= NETIF_F_IPV6_CSUM;
5403
5404 dev->features |= dev->hw_features;
5405
5406
5407
5408
5409
5410
5411 if (rtl_chip_supports_csum_v2(tp)) {
5412 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5413 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5414 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5415 } else {
5416 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5417 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5418 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5419 }
5420
5421 dev->hw_features |= NETIF_F_RXALL;
5422 dev->hw_features |= NETIF_F_RXFCS;
5423
5424
5425 rtl8169_set_features(dev, dev->features);
5426
5427 rtl_set_d3_pll_down(tp, true);
5428
5429 jumbo_max = rtl_jumbo_max(tp);
5430 if (jumbo_max)
5431 dev->max_mtu = jumbo_max;
5432
5433 rtl_set_irq_mask(tp);
5434
5435 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5436
5437 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5438 &tp->counters_phys_addr,
5439 GFP_KERNEL);
5440 if (!tp->counters)
5441 return -ENOMEM;
5442
5443 pci_set_drvdata(pdev, tp);
5444
5445 rc = r8169_mdio_register(tp);
5446 if (rc)
5447 return rc;
5448
5449 rc = register_netdev(dev);
5450 if (rc)
5451 return rc;
5452
5453 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5454 rtl_chip_infos[chipset].name, dev->dev_addr, xid,
5455 pci_irq_vector(pdev, 0));
5456
5457 if (jumbo_max)
5458 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5459 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5460 "ok" : "ko");
5461
5462 if (tp->dash_type != RTL_DASH_NONE) {
5463 netdev_info(dev, "DASH enabled\n");
5464 rtl8168_driver_start(tp);
5465 }
5466
5467 if (pci_dev_run_wake(pdev))
5468 pm_runtime_put_sync(&pdev->dev);
5469
5470 return 0;
5471}
5472
5473static struct pci_driver rtl8169_pci_driver = {
5474 .name = KBUILD_MODNAME,
5475 .id_table = rtl8169_pci_tbl,
5476 .probe = rtl_init_one,
5477 .remove = rtl_remove_one,
5478 .shutdown = rtl_shutdown,
5479 .driver.pm = pm_ptr(&rtl8169_pm_ops),
5480};
5481
5482module_pci_driver(rtl8169_pci_driver);
5483